/****************************/
/* THIS IS OPEN SOURCE CODE */
/****************************/

#ifndef __POWER8_EVENTS_H__
#define __POWER8_EVENTS_H__

/*
* File:    power8_events.h
* CVS:
* Author:  Carl Love
*          carll.ibm.com
* Mods:    <your name here>
*          <your email address>
*
* (C) Copyright IBM Corporation, 2013.  All Rights Reserved.
* Contributed by
*
* Note: This code was automatically generated and should not be modified by
* hand.
*
* Documentation on the PMU events will be published at:
*  http://www.power.org/documentation
*/

#define POWER8_PME_PM_1LPAR_CYC 0
#define POWER8_PME_PM_1PLUS_PPC_CMPL 1
#define POWER8_PME_PM_1PLUS_PPC_DISP 2
#define POWER8_PME_PM_2LPAR_CYC 3
#define POWER8_PME_PM_4LPAR_CYC 4
#define POWER8_PME_PM_ALL_CHIP_PUMP_CPRED 5
#define POWER8_PME_PM_ALL_GRP_PUMP_CPRED 6
#define POWER8_PME_PM_ALL_GRP_PUMP_MPRED 7
#define POWER8_PME_PM_ALL_GRP_PUMP_MPRED_RTY 8
#define POWER8_PME_PM_ALL_PUMP_CPRED 9
#define POWER8_PME_PM_ALL_PUMP_MPRED 10
#define POWER8_PME_PM_ALL_SYS_PUMP_CPRED 11
#define POWER8_PME_PM_ALL_SYS_PUMP_MPRED 12
#define POWER8_PME_PM_ALL_SYS_PUMP_MPRED_RTY 13
#define POWER8_PME_PM_ANY_THRD_RUN_CYC 14
#define POWER8_PME_PM_BACK_BR_CMPL 15
#define POWER8_PME_PM_BANK_CONFLICT 16
#define POWER8_PME_PM_BRU_FIN 17
#define POWER8_PME_PM_BR_2PATH 18
#define POWER8_PME_PM_BR_BC_8 19
#define POWER8_PME_PM_BR_BC_8_CONV 20
#define POWER8_PME_PM_BR_CMPL 21
#define POWER8_PME_PM_BR_MPRED_CCACHE 22
#define POWER8_PME_PM_BR_MPRED_CMPL 23
#define POWER8_PME_PM_BR_MPRED_CR 24
#define POWER8_PME_PM_BR_MPRED_LSTACK 25
#define POWER8_PME_PM_BR_MPRED_TA 26
#define POWER8_PME_PM_BR_MRK_2PATH 27
#define POWER8_PME_PM_BR_PRED_BR0 28
#define POWER8_PME_PM_BR_PRED_BR1 29
#define POWER8_PME_PM_BR_PRED_BR_CMPL 30
#define POWER8_PME_PM_BR_PRED_CCACHE_BR0 31
#define POWER8_PME_PM_BR_PRED_CCACHE_BR1 32
#define POWER8_PME_PM_BR_PRED_CCACHE_CMPL 33
#define POWER8_PME_PM_BR_PRED_CR_BR0 34
#define POWER8_PME_PM_BR_PRED_CR_BR1 35
#define POWER8_PME_PM_BR_PRED_CR_CMPL 36
#define POWER8_PME_PM_BR_PRED_LSTACK_BR0 37
#define POWER8_PME_PM_BR_PRED_LSTACK_BR1 38
#define POWER8_PME_PM_BR_PRED_LSTACK_CMPL 39
#define POWER8_PME_PM_BR_PRED_TA_BR0 40
#define POWER8_PME_PM_BR_PRED_TA_BR1 41
#define POWER8_PME_PM_BR_PRED_TA_CMPL 42
#define POWER8_PME_PM_BR_TAKEN_CMPL 43
#define POWER8_PME_PM_BR_UNCOND_BR0 44
#define POWER8_PME_PM_BR_UNCOND_BR1 45
#define POWER8_PME_PM_BR_UNCOND_CMPL 46
#define POWER8_PME_PM_CASTOUT_ISSUED 47
#define POWER8_PME_PM_CASTOUT_ISSUED_GPR 48
#define POWER8_PME_PM_CHIP_PUMP_CPRED 49
#define POWER8_PME_PM_CLB_HELD 50
#define POWER8_PME_PM_CMPLU_STALL 51
#define POWER8_PME_PM_CMPLU_STALL_BRU 52
#define POWER8_PME_PM_CMPLU_STALL_BRU_CRU 53
#define POWER8_PME_PM_CMPLU_STALL_COQ_FULL 54
#define POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS 55
#define POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 56
#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 57
#define POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 58
#define POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS 59
#define POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM 60
#define POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE 61
#define POWER8_PME_PM_CMPLU_STALL_ERAT_MISS 62
#define POWER8_PME_PM_CMPLU_STALL_FLUSH 63
#define POWER8_PME_PM_CMPLU_STALL_FXLONG 64
#define POWER8_PME_PM_CMPLU_STALL_FXU 65
#define POWER8_PME_PM_CMPLU_STALL_HWSYNC 66
#define POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH 67
#define POWER8_PME_PM_CMPLU_STALL_LSU 68
#define POWER8_PME_PM_CMPLU_STALL_LWSYNC 69
#define POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY 70
#define POWER8_PME_PM_CMPLU_STALL_NO_NTF 71
#define POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH 72
#define POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL 73
#define POWER8_PME_PM_CMPLU_STALL_REJECT 74
#define POWER8_PME_PM_CMPLU_STALL_REJECT_LHS 75
#define POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL 76
#define POWER8_PME_PM_CMPLU_STALL_SCALAR 77
#define POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG 78
#define POWER8_PME_PM_CMPLU_STALL_STORE 79
#define POWER8_PME_PM_CMPLU_STALL_ST_FWD 80
#define POWER8_PME_PM_CMPLU_STALL_THRD 81
#define POWER8_PME_PM_CMPLU_STALL_VECTOR 82
#define POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG 83
#define POWER8_PME_PM_CMPLU_STALL_VSU 84
#define POWER8_PME_PM_CO0_ALLOC 85
#define POWER8_PME_PM_CO0_BUSY 86
#define POWER8_PME_PM_CO_DISP_FAIL 87
#define POWER8_PME_PM_CO_TM_SC_FOOTPRINT 88
#define POWER8_PME_PM_CO_USAGE 89
#define POWER8_PME_PM_CRU_FIN 90
#define POWER8_PME_PM_CYC 91
#define POWER8_PME_PM_DATA_ALL_CHIP_PUMP_CPRED 92
#define POWER8_PME_PM_DATA_ALL_FROM_DL2L3_MOD 93
#define POWER8_PME_PM_DATA_ALL_FROM_DL2L3_SHR 94
#define POWER8_PME_PM_DATA_ALL_FROM_DL4 95
#define POWER8_PME_PM_DATA_ALL_FROM_DMEM 96
#define POWER8_PME_PM_DATA_ALL_FROM_L2 97
#define POWER8_PME_PM_DATA_ALL_FROM_L21_MOD 98
#define POWER8_PME_PM_DATA_ALL_FROM_L21_SHR 99
#define POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD 100
#define POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST 101
#define POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER 102
#define POWER8_PME_PM_DATA_ALL_FROM_L2_MEPF 103
#define POWER8_PME_PM_DATA_ALL_FROM_L2_NO_CONFLICT 104
#define POWER8_PME_PM_DATA_ALL_FROM_L3 105
#define POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_MOD 106
#define POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_SHR 107
#define POWER8_PME_PM_DATA_ALL_FROM_L31_MOD 108
#define POWER8_PME_PM_DATA_ALL_FROM_L31_SHR 109
#define POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD 110
#define POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT 111
#define POWER8_PME_PM_DATA_ALL_FROM_L3_MEPF 112
#define POWER8_PME_PM_DATA_ALL_FROM_L3_NO_CONFLICT 113
#define POWER8_PME_PM_DATA_ALL_FROM_LL4 114
#define POWER8_PME_PM_DATA_ALL_FROM_LMEM 115
#define POWER8_PME_PM_DATA_ALL_FROM_MEMORY 116
#define POWER8_PME_PM_DATA_ALL_FROM_OFF_CHIP_CACHE 117
#define POWER8_PME_PM_DATA_ALL_FROM_ON_CHIP_CACHE 118
#define POWER8_PME_PM_DATA_ALL_FROM_RL2L3_MOD 119
#define POWER8_PME_PM_DATA_ALL_FROM_RL2L3_SHR 120
#define POWER8_PME_PM_DATA_ALL_FROM_RL4 121
#define POWER8_PME_PM_DATA_ALL_FROM_RMEM 122
#define POWER8_PME_PM_DATA_ALL_GRP_PUMP_CPRED 123
#define POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED 124
#define POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED_RTY 125
#define POWER8_PME_PM_DATA_ALL_PUMP_CPRED 126
#define POWER8_PME_PM_DATA_ALL_PUMP_MPRED 127
#define POWER8_PME_PM_DATA_ALL_SYS_PUMP_CPRED 128
#define POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED 129
#define POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED_RTY 130
#define POWER8_PME_PM_DATA_CHIP_PUMP_CPRED 131
#define POWER8_PME_PM_DATA_FROM_DL2L3_MOD 132
#define POWER8_PME_PM_DATA_FROM_DL2L3_SHR 133
#define POWER8_PME_PM_DATA_FROM_DL4 134
#define POWER8_PME_PM_DATA_FROM_DMEM 135
#define POWER8_PME_PM_DATA_FROM_L2 136
#define POWER8_PME_PM_DATA_FROM_L21_MOD 137
#define POWER8_PME_PM_DATA_FROM_L21_SHR 138
#define POWER8_PME_PM_DATA_FROM_L2MISS 139
#define POWER8_PME_PM_DATA_FROM_L2MISS_MOD 140
#define POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST 141
#define POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER 142
#define POWER8_PME_PM_DATA_FROM_L2_MEPF 143
#define POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT 144
#define POWER8_PME_PM_DATA_FROM_L3 145
#define POWER8_PME_PM_DATA_FROM_L31_ECO_MOD 146
#define POWER8_PME_PM_DATA_FROM_L31_ECO_SHR 147
#define POWER8_PME_PM_DATA_FROM_L31_MOD 148
#define POWER8_PME_PM_DATA_FROM_L31_SHR 149
#define POWER8_PME_PM_DATA_FROM_L3MISS 150
#define POWER8_PME_PM_DATA_FROM_L3MISS_MOD 151
#define POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT 152
#define POWER8_PME_PM_DATA_FROM_L3_MEPF 153
#define POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT 154
#define POWER8_PME_PM_DATA_FROM_LL4 155
#define POWER8_PME_PM_DATA_FROM_LMEM 156
#define POWER8_PME_PM_DATA_FROM_MEM 157
#define POWER8_PME_PM_DATA_FROM_MEMORY 158
#define POWER8_PME_PM_DATA_FROM_OFF_CHIP_CACHE 159
#define POWER8_PME_PM_DATA_FROM_ON_CHIP_CACHE 160
#define POWER8_PME_PM_DATA_FROM_RL2L3_MOD 161
#define POWER8_PME_PM_DATA_FROM_RL2L3_SHR 162
#define POWER8_PME_PM_DATA_FROM_RL4 163
#define POWER8_PME_PM_DATA_FROM_RMEM 164
#define POWER8_PME_PM_DATA_GRP_PUMP_CPRED 165
#define POWER8_PME_PM_DATA_GRP_PUMP_MPRED 166
#define POWER8_PME_PM_DATA_GRP_PUMP_MPRED_RTY 167
#define POWER8_PME_PM_DATA_PUMP_CPRED 168
#define POWER8_PME_PM_DATA_PUMP_MPRED 169
#define POWER8_PME_PM_DATA_SYS_PUMP_CPRED 170
#define POWER8_PME_PM_DATA_SYS_PUMP_MPRED 171
#define POWER8_PME_PM_DATA_SYS_PUMP_MPRED_RTY 172
#define POWER8_PME_PM_DATA_TABLEWALK_CYC 173
#define POWER8_PME_PM_DC_COLLISIONS 174
#define POWER8_PME_PM_DC_PREF_STREAM_ALLOC 175
#define POWER8_PME_PM_DC_PREF_STREAM_CONF 176
#define POWER8_PME_PM_DC_PREF_STREAM_FUZZY_CONF 177
#define POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF 178
#define POWER8_PME_PM_DERAT_MISS_16G 179
#define POWER8_PME_PM_DERAT_MISS_16M 180
#define POWER8_PME_PM_DERAT_MISS_4K 181
#define POWER8_PME_PM_DERAT_MISS_64K 182
#define POWER8_PME_PM_DFU 183
#define POWER8_PME_PM_DFU_DCFFIX 184
#define POWER8_PME_PM_DFU_DENBCD 185
#define POWER8_PME_PM_DFU_MC 186
#define POWER8_PME_PM_DISP_CLB_HELD_BAL 187
#define POWER8_PME_PM_DISP_CLB_HELD_RES 188
#define POWER8_PME_PM_DISP_CLB_HELD_SB 189
#define POWER8_PME_PM_DISP_CLB_HELD_SYNC 190
#define POWER8_PME_PM_DISP_CLB_HELD_TLBIE 191
#define POWER8_PME_PM_DISP_HELD 192
#define POWER8_PME_PM_DISP_HELD_IQ_FULL 193
#define POWER8_PME_PM_DISP_HELD_MAP_FULL 194
#define POWER8_PME_PM_DISP_HELD_SRQ_FULL 195
#define POWER8_PME_PM_DISP_HELD_SYNC_HOLD 196
#define POWER8_PME_PM_DISP_HOLD_GCT_FULL 197
#define POWER8_PME_PM_DISP_WT 198
#define POWER8_PME_PM_DPTEG_FROM_DL2L3_MOD 199
#define POWER8_PME_PM_DPTEG_FROM_DL2L3_SHR 200
#define POWER8_PME_PM_DPTEG_FROM_DL4 201
#define POWER8_PME_PM_DPTEG_FROM_DMEM 202
#define POWER8_PME_PM_DPTEG_FROM_L2 203
#define POWER8_PME_PM_DPTEG_FROM_L21_MOD 204
#define POWER8_PME_PM_DPTEG_FROM_L21_SHR 205
#define POWER8_PME_PM_DPTEG_FROM_L2MISS 206
#define POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST 207
#define POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER 208
#define POWER8_PME_PM_DPTEG_FROM_L2_MEPF 209
#define POWER8_PME_PM_DPTEG_FROM_L2_NO_CONFLICT 210
#define POWER8_PME_PM_DPTEG_FROM_L3 211
#define POWER8_PME_PM_DPTEG_FROM_L31_ECO_MOD 212
#define POWER8_PME_PM_DPTEG_FROM_L31_ECO_SHR 213
#define POWER8_PME_PM_DPTEG_FROM_L31_MOD 214
#define POWER8_PME_PM_DPTEG_FROM_L31_SHR 215
#define POWER8_PME_PM_DPTEG_FROM_L3MISS 216
#define POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT 217
#define POWER8_PME_PM_DPTEG_FROM_L3_MEPF 218
#define POWER8_PME_PM_DPTEG_FROM_L3_NO_CONFLICT 219
#define POWER8_PME_PM_DPTEG_FROM_LL4 220
#define POWER8_PME_PM_DPTEG_FROM_LMEM 221
#define POWER8_PME_PM_DPTEG_FROM_MEMORY 222
#define POWER8_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE 223
#define POWER8_PME_PM_DPTEG_FROM_ON_CHIP_CACHE 224
#define POWER8_PME_PM_DPTEG_FROM_RL2L3_MOD 225
#define POWER8_PME_PM_DPTEG_FROM_RL2L3_SHR 226
#define POWER8_PME_PM_DPTEG_FROM_RL4 227
#define POWER8_PME_PM_DPTEG_FROM_RMEM 228
#define POWER8_PME_PM_DSLB_MISS 229
#define POWER8_PME_PM_DTLB_MISS 230
#define POWER8_PME_PM_DTLB_MISS_16G 231
#define POWER8_PME_PM_DTLB_MISS_16M 232
#define POWER8_PME_PM_DTLB_MISS_4K 233
#define POWER8_PME_PM_DTLB_MISS_64K 234
#define POWER8_PME_PM_EAT_FORCE_MISPRED 235
#define POWER8_PME_PM_EAT_FULL_CYC 236
#define POWER8_PME_PM_EE_OFF_EXT_INT 237
#define POWER8_PME_PM_EXT_INT 238
#define POWER8_PME_PM_FAV_TBEGIN 239
#define POWER8_PME_PM_FLOP 240
#define POWER8_PME_PM_FLOP_SUM_SCALAR 241
#define POWER8_PME_PM_FLOP_SUM_VEC 242
#define POWER8_PME_PM_FLUSH 243
#define POWER8_PME_PM_FLUSH_BR_MPRED 244
#define POWER8_PME_PM_FLUSH_COMPLETION 245
#define POWER8_PME_PM_FLUSH_DISP 246
#define POWER8_PME_PM_FLUSH_DISP_SB 247
#define POWER8_PME_PM_FLUSH_DISP_SYNC 248
#define POWER8_PME_PM_FLUSH_DISP_TLBIE 249
#define POWER8_PME_PM_FLUSH_LSU 250
#define POWER8_PME_PM_FLUSH_PARTIAL 251
#define POWER8_PME_PM_FPU0_FCONV 252
#define POWER8_PME_PM_FPU0_FEST 253
#define POWER8_PME_PM_FPU0_FRSP 254
#define POWER8_PME_PM_FPU1_FCONV 255
#define POWER8_PME_PM_FPU1_FEST 256
#define POWER8_PME_PM_FPU1_FRSP 257
#define POWER8_PME_PM_FREQ_DOWN 258
#define POWER8_PME_PM_FREQ_UP 259
#define POWER8_PME_PM_FUSION_TOC_GRP0_1 260
#define POWER8_PME_PM_FUSION_TOC_GRP0_2 261
#define POWER8_PME_PM_FUSION_TOC_GRP0_3 262
#define POWER8_PME_PM_FUSION_TOC_GRP1_1 263
#define POWER8_PME_PM_FUSION_VSX_GRP0_1 264
#define POWER8_PME_PM_FUSION_VSX_GRP0_2 265
#define POWER8_PME_PM_FUSION_VSX_GRP0_3 266
#define POWER8_PME_PM_FUSION_VSX_GRP1_1 267
#define POWER8_PME_PM_FXU0_BUSY_FXU1_IDLE 268
#define POWER8_PME_PM_FXU0_FIN 269
#define POWER8_PME_PM_FXU1_BUSY_FXU0_IDLE 270
#define POWER8_PME_PM_FXU1_FIN 271
#define POWER8_PME_PM_FXU_BUSY 272
#define POWER8_PME_PM_FXU_IDLE 273
#define POWER8_PME_PM_GCT_EMPTY_CYC 274
#define POWER8_PME_PM_GCT_MERGE 275
#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED 276
#define POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS 277
#define POWER8_PME_PM_GCT_NOSLOT_CYC 278
#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ 279
#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_MAP 280
#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER 281
#define POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ 282
#define POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS 283
#define POWER8_PME_PM_GCT_NOSLOT_IC_MISS 284
#define POWER8_PME_PM_GCT_UTIL_11_14_ENTRIES 285
#define POWER8_PME_PM_GCT_UTIL_15_17_ENTRIES 286
#define POWER8_PME_PM_GCT_UTIL_18_ENTRIES 287
#define POWER8_PME_PM_GCT_UTIL_1_2_ENTRIES 288
#define POWER8_PME_PM_GCT_UTIL_3_6_ENTRIES 289
#define POWER8_PME_PM_GCT_UTIL_7_10_ENTRIES 290
#define POWER8_PME_PM_GRP_BR_MPRED_NONSPEC 291
#define POWER8_PME_PM_GRP_CMPL 292
#define POWER8_PME_PM_GRP_DISP 293
#define POWER8_PME_PM_GRP_IC_MISS_NONSPEC 294
#define POWER8_PME_PM_GRP_MRK 295
#define POWER8_PME_PM_GRP_NON_FULL_GROUP 296
#define POWER8_PME_PM_GRP_PUMP_CPRED 297
#define POWER8_PME_PM_GRP_PUMP_MPRED 298
#define POWER8_PME_PM_GRP_PUMP_MPRED_RTY 299
#define POWER8_PME_PM_GRP_TERM_2ND_BRANCH 300
#define POWER8_PME_PM_GRP_TERM_FPU_AFTER_BR 301
#define POWER8_PME_PM_GRP_TERM_NOINST 302
#define POWER8_PME_PM_GRP_TERM_OTHER 303
#define POWER8_PME_PM_GRP_TERM_SLOT_LIMIT 304
#define POWER8_PME_PM_HV_CYC 305
#define POWER8_PME_PM_IBUF_FULL_CYC 306
#define POWER8_PME_PM_IC_DEMAND_CYC 307
#define POWER8_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 308
#define POWER8_PME_PM_IC_DEMAND_L2_BR_REDIRECT 309
#define POWER8_PME_PM_IC_DEMAND_REQ 310
#define POWER8_PME_PM_IC_INVALIDATE 311
#define POWER8_PME_PM_IC_PREF_CANCEL_HIT 312
#define POWER8_PME_PM_IC_PREF_CANCEL_L2 313
#define POWER8_PME_PM_IC_PREF_CANCEL_PAGE 314
#define POWER8_PME_PM_IC_PREF_REQ 315
#define POWER8_PME_PM_IC_PREF_WRITE 316
#define POWER8_PME_PM_IC_RELOAD_PRIVATE 317
#define POWER8_PME_PM_IERAT_RELOAD 318
#define POWER8_PME_PM_IERAT_RELOAD_16M 319
#define POWER8_PME_PM_IERAT_RELOAD_4K 320
#define POWER8_PME_PM_IERAT_RELOAD_64K 321
#define POWER8_PME_PM_IFETCH_THROTTLE 322
#define POWER8_PME_PM_IFU_L2_TOUCH 323
#define POWER8_PME_PM_INST_ALL_CHIP_PUMP_CPRED 324
#define POWER8_PME_PM_INST_ALL_FROM_DL2L3_MOD 325
#define POWER8_PME_PM_INST_ALL_FROM_DL2L3_SHR 326
#define POWER8_PME_PM_INST_ALL_FROM_DL4 327
#define POWER8_PME_PM_INST_ALL_FROM_DMEM 328
#define POWER8_PME_PM_INST_ALL_FROM_L2 329
#define POWER8_PME_PM_INST_ALL_FROM_L21_MOD 330
#define POWER8_PME_PM_INST_ALL_FROM_L21_SHR 331
#define POWER8_PME_PM_INST_ALL_FROM_L2MISS 332
#define POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST 333
#define POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER 334
#define POWER8_PME_PM_INST_ALL_FROM_L2_MEPF 335
#define POWER8_PME_PM_INST_ALL_FROM_L2_NO_CONFLICT 336
#define POWER8_PME_PM_INST_ALL_FROM_L3 337
#define POWER8_PME_PM_INST_ALL_FROM_L31_ECO_MOD 338
#define POWER8_PME_PM_INST_ALL_FROM_L31_ECO_SHR 339
#define POWER8_PME_PM_INST_ALL_FROM_L31_MOD 340
#define POWER8_PME_PM_INST_ALL_FROM_L31_SHR 341
#define POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD 342
#define POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT 343
#define POWER8_PME_PM_INST_ALL_FROM_L3_MEPF 344
#define POWER8_PME_PM_INST_ALL_FROM_L3_NO_CONFLICT 345
#define POWER8_PME_PM_INST_ALL_FROM_LL4 346
#define POWER8_PME_PM_INST_ALL_FROM_LMEM 347
#define POWER8_PME_PM_INST_ALL_FROM_MEMORY 348
#define POWER8_PME_PM_INST_ALL_FROM_OFF_CHIP_CACHE 349
#define POWER8_PME_PM_INST_ALL_FROM_ON_CHIP_CACHE 350
#define POWER8_PME_PM_INST_ALL_FROM_RL2L3_MOD 351
#define POWER8_PME_PM_INST_ALL_FROM_RL2L3_SHR 352
#define POWER8_PME_PM_INST_ALL_FROM_RL4 353
#define POWER8_PME_PM_INST_ALL_FROM_RMEM 354
#define POWER8_PME_PM_INST_ALL_GRP_PUMP_CPRED 355
#define POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED 356
#define POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED_RTY 357
#define POWER8_PME_PM_INST_ALL_PUMP_CPRED 358
#define POWER8_PME_PM_INST_ALL_PUMP_MPRED 359
#define POWER8_PME_PM_INST_ALL_SYS_PUMP_CPRED 360
#define POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED 361
#define POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED_RTY 362
#define POWER8_PME_PM_INST_CHIP_PUMP_CPRED 363
#define POWER8_PME_PM_INST_CMPL 364
#define POWER8_PME_PM_INST_DISP 365
#define POWER8_PME_PM_INST_FROM_DL2L3_MOD 366
#define POWER8_PME_PM_INST_FROM_DL2L3_SHR 367
#define POWER8_PME_PM_INST_FROM_DL4 368
#define POWER8_PME_PM_INST_FROM_DMEM 369
#define POWER8_PME_PM_INST_FROM_L1 370
#define POWER8_PME_PM_INST_FROM_L2 371
#define POWER8_PME_PM_INST_FROM_L21_MOD 372
#define POWER8_PME_PM_INST_FROM_L21_SHR 373
#define POWER8_PME_PM_INST_FROM_L2MISS 374
#define POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST 375
#define POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER 376
#define POWER8_PME_PM_INST_FROM_L2_MEPF 377
#define POWER8_PME_PM_INST_FROM_L2_NO_CONFLICT 378
#define POWER8_PME_PM_INST_FROM_L3 379
#define POWER8_PME_PM_INST_FROM_L31_ECO_MOD 380
#define POWER8_PME_PM_INST_FROM_L31_ECO_SHR 381
#define POWER8_PME_PM_INST_FROM_L31_MOD 382
#define POWER8_PME_PM_INST_FROM_L31_SHR 383
#define POWER8_PME_PM_INST_FROM_L3MISS 384
#define POWER8_PME_PM_INST_FROM_L3MISS_MOD 385
#define POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT 386
#define POWER8_PME_PM_INST_FROM_L3_MEPF 387
#define POWER8_PME_PM_INST_FROM_L3_NO_CONFLICT 388
#define POWER8_PME_PM_INST_FROM_LL4 389
#define POWER8_PME_PM_INST_FROM_LMEM 390
#define POWER8_PME_PM_INST_FROM_MEMORY 391
#define POWER8_PME_PM_INST_FROM_OFF_CHIP_CACHE 392
#define POWER8_PME_PM_INST_FROM_ON_CHIP_CACHE 393
#define POWER8_PME_PM_INST_FROM_RL2L3_MOD 394
#define POWER8_PME_PM_INST_FROM_RL2L3_SHR 395
#define POWER8_PME_PM_INST_FROM_RL4 396
#define POWER8_PME_PM_INST_FROM_RMEM 397
#define POWER8_PME_PM_INST_GRP_PUMP_CPRED 398
#define POWER8_PME_PM_INST_GRP_PUMP_MPRED 399
#define POWER8_PME_PM_INST_GRP_PUMP_MPRED_RTY 400
#define POWER8_PME_PM_INST_IMC_MATCH_CMPL 401
#define POWER8_PME_PM_INST_IMC_MATCH_DISP 402
#define POWER8_PME_PM_INST_PUMP_CPRED 403
#define POWER8_PME_PM_INST_PUMP_MPRED 404
#define POWER8_PME_PM_INST_SYS_PUMP_CPRED 405
#define POWER8_PME_PM_INST_SYS_PUMP_MPRED 406
#define POWER8_PME_PM_INST_SYS_PUMP_MPRED_RTY 407
#define POWER8_PME_PM_IOPS_CMPL 408
#define POWER8_PME_PM_IOPS_DISP 409
#define POWER8_PME_PM_IPTEG_FROM_DL2L3_MOD 410
#define POWER8_PME_PM_IPTEG_FROM_DL2L3_SHR 411
#define POWER8_PME_PM_IPTEG_FROM_DL4 412
#define POWER8_PME_PM_IPTEG_FROM_DMEM 413
#define POWER8_PME_PM_IPTEG_FROM_L2 414
#define POWER8_PME_PM_IPTEG_FROM_L21_MOD 415
#define POWER8_PME_PM_IPTEG_FROM_L21_SHR 416
#define POWER8_PME_PM_IPTEG_FROM_L2MISS 417
#define POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST 418
#define POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER 419
#define POWER8_PME_PM_IPTEG_FROM_L2_MEPF 420
#define POWER8_PME_PM_IPTEG_FROM_L2_NO_CONFLICT 421
#define POWER8_PME_PM_IPTEG_FROM_L3 422
#define POWER8_PME_PM_IPTEG_FROM_L31_ECO_MOD 423
#define POWER8_PME_PM_IPTEG_FROM_L31_ECO_SHR 424
#define POWER8_PME_PM_IPTEG_FROM_L31_MOD 425
#define POWER8_PME_PM_IPTEG_FROM_L31_SHR 426
#define POWER8_PME_PM_IPTEG_FROM_L3MISS 427
#define POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT 428
#define POWER8_PME_PM_IPTEG_FROM_L3_MEPF 429
#define POWER8_PME_PM_IPTEG_FROM_L3_NO_CONFLICT 430
#define POWER8_PME_PM_IPTEG_FROM_LL4 431
#define POWER8_PME_PM_IPTEG_FROM_LMEM 432
#define POWER8_PME_PM_IPTEG_FROM_MEMORY 433
#define POWER8_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE 434
#define POWER8_PME_PM_IPTEG_FROM_ON_CHIP_CACHE 435
#define POWER8_PME_PM_IPTEG_FROM_RL2L3_MOD 436
#define POWER8_PME_PM_IPTEG_FROM_RL2L3_SHR 437
#define POWER8_PME_PM_IPTEG_FROM_RL4 438
#define POWER8_PME_PM_IPTEG_FROM_RMEM 439
#define POWER8_PME_PM_ISIDE_DISP 440
#define POWER8_PME_PM_ISIDE_DISP_FAIL 441
#define POWER8_PME_PM_ISIDE_DISP_FAIL_OTHER 442
#define POWER8_PME_PM_ISIDE_L2MEMACC 443
#define POWER8_PME_PM_ISIDE_MRU_TOUCH 444
#define POWER8_PME_PM_ISLB_MISS 445
#define POWER8_PME_PM_ISU_REF_FX0 446
#define POWER8_PME_PM_ISU_REF_FX1 447
#define POWER8_PME_PM_ISU_REF_FXU 448
#define POWER8_PME_PM_ISU_REF_LS0 449
#define POWER8_PME_PM_ISU_REF_LS1 450
#define POWER8_PME_PM_ISU_REF_LS2 451
#define POWER8_PME_PM_ISU_REF_LS3 452
#define POWER8_PME_PM_ISU_REJECTS_ALL 453
#define POWER8_PME_PM_ISU_REJECT_RES_NA 454
#define POWER8_PME_PM_ISU_REJECT_SAR_BYPASS 455
#define POWER8_PME_PM_ISU_REJECT_SRC_NA 456
#define POWER8_PME_PM_ISU_REJ_VS0 457
#define POWER8_PME_PM_ISU_REJ_VS1 458
#define POWER8_PME_PM_ISU_REJ_VSU 459
#define POWER8_PME_PM_ISYNC 460
#define POWER8_PME_PM_ITLB_MISS 461
#define POWER8_PME_PM_L1MISS_LAT_EXC_1024 462
#define POWER8_PME_PM_L1MISS_LAT_EXC_2048 463
#define POWER8_PME_PM_L1MISS_LAT_EXC_256 464
#define POWER8_PME_PM_L1MISS_LAT_EXC_32 465
#define POWER8_PME_PM_L1PF_L2MEMACC 466
#define POWER8_PME_PM_L1_DCACHE_RELOADED_ALL 467
#define POWER8_PME_PM_L1_DCACHE_RELOAD_VALID 468
#define POWER8_PME_PM_L1_DEMAND_WRITE 469
#define POWER8_PME_PM_L1_ICACHE_MISS 470
#define POWER8_PME_PM_L1_ICACHE_RELOADED_ALL 471
#define POWER8_PME_PM_L1_ICACHE_RELOADED_PREF 472
#define POWER8_PME_PM_L2_CASTOUT_MOD 473
#define POWER8_PME_PM_L2_CASTOUT_SHR 474
#define POWER8_PME_PM_L2_CHIP_PUMP 475
#define POWER8_PME_PM_L2_DC_INV 476
#define POWER8_PME_PM_L2_DISP_ALL_L2MISS 477
#define POWER8_PME_PM_L2_GROUP_PUMP 478
#define POWER8_PME_PM_L2_GRP_GUESS_CORRECT 479
#define POWER8_PME_PM_L2_GRP_GUESS_WRONG 480
#define POWER8_PME_PM_L2_IC_INV 481
#define POWER8_PME_PM_L2_INST 482
#define POWER8_PME_PM_L2_INST_MISS 483
#define POWER8_PME_PM_L2_LD 484
#define POWER8_PME_PM_L2_LD_DISP 485
#define POWER8_PME_PM_L2_LD_HIT 486
#define POWER8_PME_PM_L2_LD_MISS 487
#define POWER8_PME_PM_L2_LOC_GUESS_CORRECT 488
#define POWER8_PME_PM_L2_LOC_GUESS_WRONG 489
#define POWER8_PME_PM_L2_RCLD_DISP 490
#define POWER8_PME_PM_L2_RCLD_DISP_FAIL_ADDR 491
#define POWER8_PME_PM_L2_RCLD_DISP_FAIL_OTHER 492
#define POWER8_PME_PM_L2_RCST_DISP 493
#define POWER8_PME_PM_L2_RCST_DISP_FAIL_ADDR 494
#define POWER8_PME_PM_L2_RCST_DISP_FAIL_OTHER 495
#define POWER8_PME_PM_L2_RC_ST_DONE 496
#define POWER8_PME_PM_L2_RTY_LD 497
#define POWER8_PME_PM_L2_RTY_ST 498
#define POWER8_PME_PM_L2_SN_M_RD_DONE 499
#define POWER8_PME_PM_L2_SN_M_WR_DONE 500
#define POWER8_PME_PM_L2_SN_SX_I_DONE 501
#define POWER8_PME_PM_L2_ST 502
#define POWER8_PME_PM_L2_ST_DISP 503
#define POWER8_PME_PM_L2_ST_HIT 504
#define POWER8_PME_PM_L2_ST_MISS 505
#define POWER8_PME_PM_L2_SYS_GUESS_CORRECT 506
#define POWER8_PME_PM_L2_SYS_GUESS_WRONG 507
#define POWER8_PME_PM_L2_SYS_PUMP 508
#define POWER8_PME_PM_L2_TM_REQ_ABORT 509
#define POWER8_PME_PM_L2_TM_ST_ABORT_SISTER 510
#define POWER8_PME_PM_L3_CINJ 511
#define POWER8_PME_PM_L3_CI_HIT 512
#define POWER8_PME_PM_L3_CI_MISS 513
#define POWER8_PME_PM_L3_CI_USAGE 514
#define POWER8_PME_PM_L3_CO 515
#define POWER8_PME_PM_L3_CO0_ALLOC 516
#define POWER8_PME_PM_L3_CO0_BUSY 517
#define POWER8_PME_PM_L3_CO_L31 518
#define POWER8_PME_PM_L3_CO_LCO 519
#define POWER8_PME_PM_L3_CO_MEM 520
#define POWER8_PME_PM_L3_CO_MEPF 521
#define POWER8_PME_PM_L3_GRP_GUESS_CORRECT 522
#define POWER8_PME_PM_L3_GRP_GUESS_WRONG_HIGH 523
#define POWER8_PME_PM_L3_GRP_GUESS_WRONG_LOW 524
#define POWER8_PME_PM_L3_HIT 525
#define POWER8_PME_PM_L3_L2_CO_HIT 526
#define POWER8_PME_PM_L3_L2_CO_MISS 527
#define POWER8_PME_PM_L3_LAT_CI_HIT 528
#define POWER8_PME_PM_L3_LAT_CI_MISS 529
#define POWER8_PME_PM_L3_LD_HIT 530
#define POWER8_PME_PM_L3_LD_MISS 531
#define POWER8_PME_PM_L3_LD_PREF 532
#define POWER8_PME_PM_L3_LOC_GUESS_CORRECT 533
#define POWER8_PME_PM_L3_LOC_GUESS_WRONG 534
#define POWER8_PME_PM_L3_MISS 535
#define POWER8_PME_PM_L3_P0_CO_L31 536
#define POWER8_PME_PM_L3_P0_CO_MEM 537
#define POWER8_PME_PM_L3_P0_CO_RTY 538
#define POWER8_PME_PM_L3_P0_GRP_PUMP 539
#define POWER8_PME_PM_L3_P0_LCO_DATA 540
#define POWER8_PME_PM_L3_P0_LCO_NO_DATA 541
#define POWER8_PME_PM_L3_P0_LCO_RTY 542
#define POWER8_PME_PM_L3_P0_NODE_PUMP 543
#define POWER8_PME_PM_L3_P0_PF_RTY 544
#define POWER8_PME_PM_L3_P0_SN_HIT 545
#define POWER8_PME_PM_L3_P0_SN_INV 546
#define POWER8_PME_PM_L3_P0_SN_MISS 547
#define POWER8_PME_PM_L3_P0_SYS_PUMP 548
#define POWER8_PME_PM_L3_P1_CO_L31 549
#define POWER8_PME_PM_L3_P1_CO_MEM 550
#define POWER8_PME_PM_L3_P1_CO_RTY 551
#define POWER8_PME_PM_L3_P1_GRP_PUMP 552
#define POWER8_PME_PM_L3_P1_LCO_DATA 553
#define POWER8_PME_PM_L3_P1_LCO_NO_DATA 554
#define POWER8_PME_PM_L3_P1_LCO_RTY 555
#define POWER8_PME_PM_L3_P1_NODE_PUMP 556
#define POWER8_PME_PM_L3_P1_PF_RTY 557
#define POWER8_PME_PM_L3_P1_SN_HIT 558
#define POWER8_PME_PM_L3_P1_SN_INV 559
#define POWER8_PME_PM_L3_P1_SN_MISS 560
#define POWER8_PME_PM_L3_P1_SYS_PUMP 561
#define POWER8_PME_PM_L3_PF0_ALLOC 562
#define POWER8_PME_PM_L3_PF0_BUSY 563
#define POWER8_PME_PM_L3_PF_HIT_L3 564
#define POWER8_PME_PM_L3_PF_MISS_L3 565
#define POWER8_PME_PM_L3_PF_OFF_CHIP_CACHE 566
#define POWER8_PME_PM_L3_PF_OFF_CHIP_MEM 567
#define POWER8_PME_PM_L3_PF_ON_CHIP_CACHE 568
#define POWER8_PME_PM_L3_PF_ON_CHIP_MEM 569
#define POWER8_PME_PM_L3_PF_USAGE 570
#define POWER8_PME_PM_L3_PREF_ALL 571
#define POWER8_PME_PM_L3_RD0_ALLOC 572
#define POWER8_PME_PM_L3_RD0_BUSY 573
#define POWER8_PME_PM_L3_RD_USAGE 574
#define POWER8_PME_PM_L3_SN0_ALLOC 575
#define POWER8_PME_PM_L3_SN0_BUSY 576
#define POWER8_PME_PM_L3_SN_USAGE 577
#define POWER8_PME_PM_L3_ST_PREF 578
#define POWER8_PME_PM_L3_SW_PREF 579
#define POWER8_PME_PM_L3_SYS_GUESS_CORRECT 580
#define POWER8_PME_PM_L3_SYS_GUESS_WRONG 581
#define POWER8_PME_PM_L3_TRANS_PF 582
#define POWER8_PME_PM_L3_WI0_ALLOC 583
#define POWER8_PME_PM_L3_WI0_BUSY 584
#define POWER8_PME_PM_L3_WI_USAGE 585
#define POWER8_PME_PM_LARX_FIN 586
#define POWER8_PME_PM_LD_CMPL 587
#define POWER8_PME_PM_LD_L3MISS_PEND_CYC 588
#define POWER8_PME_PM_LD_MISS_L1 589
#define POWER8_PME_PM_LD_REF_L1 590
#define POWER8_PME_PM_LD_REF_L1_LSU0 591
#define POWER8_PME_PM_LD_REF_L1_LSU1 592
#define POWER8_PME_PM_LD_REF_L1_LSU2 593
#define POWER8_PME_PM_LD_REF_L1_LSU3 594
#define POWER8_PME_PM_LINK_STACK_INVALID_PTR 595
#define POWER8_PME_PM_LINK_STACK_WRONG_ADD_PRED 596
#define POWER8_PME_PM_LS0_ERAT_MISS_PREF 597
#define POWER8_PME_PM_LS0_L1_PREF 598
#define POWER8_PME_PM_LS0_L1_SW_PREF 599
#define POWER8_PME_PM_LS1_ERAT_MISS_PREF 600
#define POWER8_PME_PM_LS1_L1_PREF 601
#define POWER8_PME_PM_LS1_L1_SW_PREF 602
#define POWER8_PME_PM_LSU0_FLUSH_LRQ 603
#define POWER8_PME_PM_LSU0_FLUSH_SRQ 604
#define POWER8_PME_PM_LSU0_FLUSH_ULD 605
#define POWER8_PME_PM_LSU0_FLUSH_UST 606
#define POWER8_PME_PM_LSU0_L1_CAM_CANCEL 607
#define POWER8_PME_PM_LSU0_LARX_FIN 608
#define POWER8_PME_PM_LSU0_LMQ_LHR_MERGE 609
#define POWER8_PME_PM_LSU0_NCLD 610
#define POWER8_PME_PM_LSU0_PRIMARY_ERAT_HIT 611
#define POWER8_PME_PM_LSU0_REJECT 612
#define POWER8_PME_PM_LSU0_SRQ_STFWD 613
#define POWER8_PME_PM_LSU0_STORE_REJECT 614
#define POWER8_PME_PM_LSU0_TMA_REQ_L2 615
#define POWER8_PME_PM_LSU0_TM_L1_HIT 616
#define POWER8_PME_PM_LSU0_TM_L1_MISS 617
#define POWER8_PME_PM_LSU1_FLUSH_LRQ 618
#define POWER8_PME_PM_LSU1_FLUSH_SRQ 619
#define POWER8_PME_PM_LSU1_FLUSH_ULD 620
#define POWER8_PME_PM_LSU1_FLUSH_UST 621
#define POWER8_PME_PM_LSU1_L1_CAM_CANCEL 622
#define POWER8_PME_PM_LSU1_LARX_FIN 623
#define POWER8_PME_PM_LSU1_LMQ_LHR_MERGE 624
#define POWER8_PME_PM_LSU1_NCLD 625
#define POWER8_PME_PM_LSU1_PRIMARY_ERAT_HIT 626
#define POWER8_PME_PM_LSU1_REJECT 627
#define POWER8_PME_PM_LSU1_SRQ_STFWD 628
#define POWER8_PME_PM_LSU1_STORE_REJECT 629
#define POWER8_PME_PM_LSU1_TMA_REQ_L2 630
#define POWER8_PME_PM_LSU1_TM_L1_HIT 631
#define POWER8_PME_PM_LSU1_TM_L1_MISS 632
#define POWER8_PME_PM_LSU2_FLUSH_LRQ 633
#define POWER8_PME_PM_LSU2_FLUSH_SRQ 634
#define POWER8_PME_PM_LSU2_FLUSH_ULD 635
#define POWER8_PME_PM_LSU2_L1_CAM_CANCEL 636
#define POWER8_PME_PM_LSU2_LARX_FIN 637
#define POWER8_PME_PM_LSU2_LDF 638
#define POWER8_PME_PM_LSU2_LDX 639
#define POWER8_PME_PM_LSU2_LMQ_LHR_MERGE 640
#define POWER8_PME_PM_LSU2_PRIMARY_ERAT_HIT 641
#define POWER8_PME_PM_LSU2_REJECT 642
#define POWER8_PME_PM_LSU2_SRQ_STFWD 643
#define POWER8_PME_PM_LSU2_TMA_REQ_L2 644
#define POWER8_PME_PM_LSU2_TM_L1_HIT 645
#define POWER8_PME_PM_LSU2_TM_L1_MISS 646
#define POWER8_PME_PM_LSU3_FLUSH_LRQ 647
#define POWER8_PME_PM_LSU3_FLUSH_SRQ 648
#define POWER8_PME_PM_LSU3_FLUSH_ULD 649
#define POWER8_PME_PM_LSU3_L1_CAM_CANCEL 650
#define POWER8_PME_PM_LSU3_LARX_FIN 651
#define POWER8_PME_PM_LSU3_LDF 652
#define POWER8_PME_PM_LSU3_LDX 653
#define POWER8_PME_PM_LSU3_LMQ_LHR_MERGE 654
#define POWER8_PME_PM_LSU3_PRIMARY_ERAT_HIT 655
#define POWER8_PME_PM_LSU3_REJECT 656
#define POWER8_PME_PM_LSU3_SRQ_STFWD 657
#define POWER8_PME_PM_LSU3_TMA_REQ_L2 658
#define POWER8_PME_PM_LSU3_TM_L1_HIT 659
#define POWER8_PME_PM_LSU3_TM_L1_MISS 660
#define POWER8_PME_PM_LSU_DERAT_MISS 661
#define POWER8_PME_PM_LSU_ERAT_MISS_PREF 662
#define POWER8_PME_PM_LSU_FIN 663
#define POWER8_PME_PM_LSU_FLUSH_UST 664
#define POWER8_PME_PM_LSU_FOUR_TABLEWALK_CYC 665
#define POWER8_PME_PM_LSU_FX_FIN 666
#define POWER8_PME_PM_LSU_L1_PREF 667
#define POWER8_PME_PM_LSU_L1_SW_PREF 668
#define POWER8_PME_PM_LSU_LDF 669
#define POWER8_PME_PM_LSU_LDX 670
#define POWER8_PME_PM_LSU_LMQ_FULL_CYC 671
#define POWER8_PME_PM_LSU_LMQ_S0_ALLOC 672
#define POWER8_PME_PM_LSU_LMQ_S0_VALID 673
#define POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC 674
#define POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 675
#define POWER8_PME_PM_LSU_LRQ_S0_ALLOC 676
#define POWER8_PME_PM_LSU_LRQ_S0_VALID 677
#define POWER8_PME_PM_LSU_LRQ_S43_ALLOC 678
#define POWER8_PME_PM_LSU_LRQ_S43_VALID 679
#define POWER8_PME_PM_LSU_MRK_DERAT_MISS 680
#define POWER8_PME_PM_LSU_NCLD 681
#define POWER8_PME_PM_LSU_NCST 682
#define POWER8_PME_PM_LSU_REJECT 683
#define POWER8_PME_PM_LSU_REJECT_ERAT_MISS 684
#define POWER8_PME_PM_LSU_REJECT_LHS 685
#define POWER8_PME_PM_LSU_REJECT_LMQ_FULL 686
#define POWER8_PME_PM_LSU_SET_MPRED 687
#define POWER8_PME_PM_LSU_SRQ_EMPTY_CYC 688
#define POWER8_PME_PM_LSU_SRQ_FULL_CYC 689
#define POWER8_PME_PM_LSU_SRQ_S0_ALLOC 690
#define POWER8_PME_PM_LSU_SRQ_S0_VALID 691
#define POWER8_PME_PM_LSU_SRQ_S39_ALLOC 692
#define POWER8_PME_PM_LSU_SRQ_S39_VALID 693
#define POWER8_PME_PM_LSU_SRQ_SYNC 694
#define POWER8_PME_PM_LSU_SRQ_SYNC_CYC 695
#define POWER8_PME_PM_LSU_STORE_REJECT 696
#define POWER8_PME_PM_LSU_TWO_TABLEWALK_CYC 697
#define POWER8_PME_PM_LWSYNC 698
#define POWER8_PME_PM_LWSYNC_HELD 699
#define POWER8_PME_PM_MEM_CO 700
#define POWER8_PME_PM_MEM_LOC_THRESH_IFU 701
#define POWER8_PME_PM_MEM_LOC_THRESH_LSU_HIGH 702
#define POWER8_PME_PM_MEM_LOC_THRESH_LSU_MED 703
#define POWER8_PME_PM_MEM_PREF 704
#define POWER8_PME_PM_MEM_READ 705
#define POWER8_PME_PM_MEM_RWITM 706
#define POWER8_PME_PM_MRK_BACK_BR_CMPL 707
#define POWER8_PME_PM_MRK_BRU_FIN 708
#define POWER8_PME_PM_MRK_BR_CMPL 709
#define POWER8_PME_PM_MRK_BR_MPRED_CMPL 710
#define POWER8_PME_PM_MRK_BR_TAKEN_CMPL 711
#define POWER8_PME_PM_MRK_CRU_FIN 712
#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD 713
#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 714
#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR 715
#define POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 716
#define POWER8_PME_PM_MRK_DATA_FROM_DL4 717
#define POWER8_PME_PM_MRK_DATA_FROM_DL4_CYC 718
#define POWER8_PME_PM_MRK_DATA_FROM_DMEM 719
#define POWER8_PME_PM_MRK_DATA_FROM_DMEM_CYC 720
#define POWER8_PME_PM_MRK_DATA_FROM_L2 721
#define POWER8_PME_PM_MRK_DATA_FROM_L21_MOD 722
#define POWER8_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 723
#define POWER8_PME_PM_MRK_DATA_FROM_L21_SHR 724
#define POWER8_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 725
#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS 726
#define POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC 727
#define POWER8_PME_PM_MRK_DATA_FROM_L2_CYC 728
#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST 729
#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC 730
#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER 731
#define POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC 732
#define POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF 733
#define POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC 734
#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 735
#define POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 736
#define POWER8_PME_PM_MRK_DATA_FROM_L3 737
#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD 738
#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC 739
#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR 740
#define POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC 741
#define POWER8_PME_PM_MRK_DATA_FROM_L31_MOD 742
#define POWER8_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 743
#define POWER8_PME_PM_MRK_DATA_FROM_L31_SHR 744
#define POWER8_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 745
#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS 746
#define POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC 747
#define POWER8_PME_PM_MRK_DATA_FROM_L3_CYC 748
#define POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT 749
#define POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC 750
#define POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF 751
#define POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC 752
#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 753
#define POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 754
#define POWER8_PME_PM_MRK_DATA_FROM_LL4 755
#define POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC 756
#define POWER8_PME_PM_MRK_DATA_FROM_LMEM 757
#define POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC 758
#define POWER8_PME_PM_MRK_DATA_FROM_MEM 759
#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY 760
#define POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC 761
#define POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE 762
#define POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC 763
#define POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE 764
#define POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC 765
#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD 766
#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 767
#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR 768
#define POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 769
#define POWER8_PME_PM_MRK_DATA_FROM_RL4 770
#define POWER8_PME_PM_MRK_DATA_FROM_RL4_CYC 771
#define POWER8_PME_PM_MRK_DATA_FROM_RMEM 772
#define POWER8_PME_PM_MRK_DATA_FROM_RMEM_CYC 773
#define POWER8_PME_PM_MRK_DCACHE_RELOAD_INTV 774
#define POWER8_PME_PM_MRK_DERAT_MISS 775
#define POWER8_PME_PM_MRK_DERAT_MISS_16G 776
#define POWER8_PME_PM_MRK_DERAT_MISS_16M 777
#define POWER8_PME_PM_MRK_DERAT_MISS_4K 778
#define POWER8_PME_PM_MRK_DERAT_MISS_64K 779
#define POWER8_PME_PM_MRK_DFU_FIN 780
#define POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD 781
#define POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR 782
#define POWER8_PME_PM_MRK_DPTEG_FROM_DL4 783
#define POWER8_PME_PM_MRK_DPTEG_FROM_DMEM 784
#define POWER8_PME_PM_MRK_DPTEG_FROM_L2 785
#define POWER8_PME_PM_MRK_DPTEG_FROM_L21_MOD 786
#define POWER8_PME_PM_MRK_DPTEG_FROM_L21_SHR 787
#define POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS 788
#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST 789
#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER 790
#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_MEPF 791
#define POWER8_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT 792
#define POWER8_PME_PM_MRK_DPTEG_FROM_L3 793
#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD 794
#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR 795
#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_MOD 796
#define POWER8_PME_PM_MRK_DPTEG_FROM_L31_SHR 797
#define POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS 798
#define POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT 799
#define POWER8_PME_PM_MRK_DPTEG_FROM_L3_MEPF 800
#define POWER8_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT 801
#define POWER8_PME_PM_MRK_DPTEG_FROM_LL4 802
#define POWER8_PME_PM_MRK_DPTEG_FROM_LMEM 803
#define POWER8_PME_PM_MRK_DPTEG_FROM_MEMORY 804
#define POWER8_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE 805
#define POWER8_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE 806
#define POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD 807
#define POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR 808
#define POWER8_PME_PM_MRK_DPTEG_FROM_RL4 809
#define POWER8_PME_PM_MRK_DPTEG_FROM_RMEM 810
#define POWER8_PME_PM_MRK_DTLB_MISS 811
#define POWER8_PME_PM_MRK_DTLB_MISS_16G 812
#define POWER8_PME_PM_MRK_DTLB_MISS_16M 813
#define POWER8_PME_PM_MRK_DTLB_MISS_4K 814
#define POWER8_PME_PM_MRK_DTLB_MISS_64K 815
#define POWER8_PME_PM_MRK_FAB_RSP_BKILL 816
#define POWER8_PME_PM_MRK_FAB_RSP_BKILL_CYC 817
#define POWER8_PME_PM_MRK_FAB_RSP_CLAIM_RTY 818
#define POWER8_PME_PM_MRK_FAB_RSP_DCLAIM 819
#define POWER8_PME_PM_MRK_FAB_RSP_DCLAIM_CYC 820
#define POWER8_PME_PM_MRK_FAB_RSP_MATCH 821
#define POWER8_PME_PM_MRK_FAB_RSP_MATCH_CYC 822
#define POWER8_PME_PM_MRK_FAB_RSP_RD_RTY 823
#define POWER8_PME_PM_MRK_FAB_RSP_RD_T_INTV 824
#define POWER8_PME_PM_MRK_FAB_RSP_RWITM_CYC 825
#define POWER8_PME_PM_MRK_FAB_RSP_RWITM_RTY 826
#define POWER8_PME_PM_MRK_FILT_MATCH 827
#define POWER8_PME_PM_MRK_FIN_STALL_CYC 828
#define POWER8_PME_PM_MRK_FXU_FIN 829
#define POWER8_PME_PM_MRK_GRP_CMPL 830
#define POWER8_PME_PM_MRK_GRP_IC_MISS 831
#define POWER8_PME_PM_MRK_GRP_NTC 832
#define POWER8_PME_PM_MRK_INST_CMPL 833
#define POWER8_PME_PM_MRK_INST_DECODED 834
#define POWER8_PME_PM_MRK_INST_DISP 835
#define POWER8_PME_PM_MRK_INST_FIN 836
#define POWER8_PME_PM_MRK_INST_FROM_L3MISS 837
#define POWER8_PME_PM_MRK_INST_ISSUED 838
#define POWER8_PME_PM_MRK_INST_TIMEO 839
#define POWER8_PME_PM_MRK_L1_ICACHE_MISS 840
#define POWER8_PME_PM_MRK_L1_RELOAD_VALID 841
#define POWER8_PME_PM_MRK_L2_RC_DISP 842
#define POWER8_PME_PM_MRK_L2_RC_DONE 843
#define POWER8_PME_PM_MRK_LARX_FIN 844
#define POWER8_PME_PM_MRK_LD_MISS_EXPOSED 845
#define POWER8_PME_PM_MRK_LD_MISS_EXPOSED_CYC 846
#define POWER8_PME_PM_MRK_LD_MISS_L1 847
#define POWER8_PME_PM_MRK_LD_MISS_L1_CYC 848
#define POWER8_PME_PM_MRK_LSU_FIN 849
#define POWER8_PME_PM_MRK_LSU_FLUSH 850
#define POWER8_PME_PM_MRK_LSU_FLUSH_LRQ 851
#define POWER8_PME_PM_MRK_LSU_FLUSH_SRQ 852
#define POWER8_PME_PM_MRK_LSU_FLUSH_ULD 853
#define POWER8_PME_PM_MRK_LSU_FLUSH_UST 854
#define POWER8_PME_PM_MRK_LSU_REJECT 855
#define POWER8_PME_PM_MRK_LSU_REJECT_ERAT_MISS 856
#define POWER8_PME_PM_MRK_NTF_FIN 857
#define POWER8_PME_PM_MRK_RUN_CYC 858
#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_EFF 859
#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_INEFF 860
#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD 861
#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L2 862
#define POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L3 863
#define POWER8_PME_PM_MRK_STALL_CMPLU_CYC 864
#define POWER8_PME_PM_MRK_STCX_FAIL 865
#define POWER8_PME_PM_MRK_ST_CMPL 866
#define POWER8_PME_PM_MRK_ST_CMPL_INT 867
#define POWER8_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC 868
#define POWER8_PME_PM_MRK_ST_FWD 869
#define POWER8_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC 870
#define POWER8_PME_PM_MRK_ST_NEST 871
#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_EFF 872
#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_INEFF 873
#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD 874
#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L2 875
#define POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L3 876
#define POWER8_PME_PM_MRK_VSU_FIN 877
#define POWER8_PME_PM_MULT_MRK 878
#define POWER8_PME_PM_NESTED_TEND 879
#define POWER8_PME_PM_NEST_REF_CLK 880
#define POWER8_PME_PM_NON_FAV_TBEGIN 881
#define POWER8_PME_PM_NON_TM_RST_SC 882
#define POWER8_PME_PM_NTCG_ALL_FIN 883
#define POWER8_PME_PM_OUTER_TBEGIN 884
#define POWER8_PME_PM_OUTER_TEND 885
#define POWER8_PME_PM_PMC1_OVERFLOW 886
#define POWER8_PME_PM_PMC2_OVERFLOW 887
#define POWER8_PME_PM_PMC2_REWIND 888
#define POWER8_PME_PM_PMC2_SAVED 889
#define POWER8_PME_PM_PMC3_OVERFLOW 890
#define POWER8_PME_PM_PMC4_OVERFLOW 891
#define POWER8_PME_PM_PMC4_REWIND 892
#define POWER8_PME_PM_PMC4_SAVED 893
#define POWER8_PME_PM_PMC5_OVERFLOW 894
#define POWER8_PME_PM_PMC6_OVERFLOW 895
#define POWER8_PME_PM_PREF_TRACKED 896
#define POWER8_PME_PM_PREF_TRACK_EFF 897
#define POWER8_PME_PM_PREF_TRACK_INEFF 898
#define POWER8_PME_PM_PREF_TRACK_MOD 899
#define POWER8_PME_PM_PREF_TRACK_MOD_L2 900
#define POWER8_PME_PM_PREF_TRACK_MOD_L3 901
#define POWER8_PME_PM_PROBE_NOP_DISP 902
#define POWER8_PME_PM_PTE_PREFETCH 903
#define POWER8_PME_PM_PUMP_CPRED 904
#define POWER8_PME_PM_PUMP_MPRED 905
#define POWER8_PME_PM_RC0_ALLOC 906
#define POWER8_PME_PM_RC0_BUSY 907
#define POWER8_PME_PM_RC_LIFETIME_EXC_1024 908
#define POWER8_PME_PM_RC_LIFETIME_EXC_2048 909
#define POWER8_PME_PM_RC_LIFETIME_EXC_256 910
#define POWER8_PME_PM_RC_LIFETIME_EXC_32 911
#define POWER8_PME_PM_RC_USAGE 912
#define POWER8_PME_PM_RD_CLEARING_SC 913
#define POWER8_PME_PM_RD_FORMING_SC 914
#define POWER8_PME_PM_RD_HIT_PF 915
#define POWER8_PME_PM_REAL_SRQ_FULL 916
#define POWER8_PME_PM_RUN_CYC 917
#define POWER8_PME_PM_RUN_CYC_SMT2_MODE 918
#define POWER8_PME_PM_RUN_CYC_SMT2_SHRD_MODE 919
#define POWER8_PME_PM_RUN_CYC_SMT2_SPLIT_MODE 920
#define POWER8_PME_PM_RUN_CYC_SMT4_MODE 921
#define POWER8_PME_PM_RUN_CYC_SMT8_MODE 922
#define POWER8_PME_PM_RUN_CYC_ST_MODE 923
#define POWER8_PME_PM_RUN_INST_CMPL 924
#define POWER8_PME_PM_RUN_PURR 925
#define POWER8_PME_PM_RUN_SPURR 926
#define POWER8_PME_PM_SEC_ERAT_HIT 927
#define POWER8_PME_PM_SHL_CREATED 928
#define POWER8_PME_PM_SHL_ST_CONVERT 929
#define POWER8_PME_PM_SHL_ST_DISABLE 930
#define POWER8_PME_PM_SN0_ALLOC 931
#define POWER8_PME_PM_SN0_BUSY 932
#define POWER8_PME_PM_SNOOP_TLBIE 933
#define POWER8_PME_PM_SNP_TM_HIT_M 934
#define POWER8_PME_PM_SNP_TM_HIT_T 935
#define POWER8_PME_PM_SN_USAGE 936
#define POWER8_PME_PM_STALL_END_GCT_EMPTY 937
#define POWER8_PME_PM_STCX_FAIL 938
#define POWER8_PME_PM_STCX_LSU 939
#define POWER8_PME_PM_ST_CAUSED_FAIL 940
#define POWER8_PME_PM_ST_CMPL 941
#define POWER8_PME_PM_ST_FIN 942
#define POWER8_PME_PM_ST_FWD 943
#define POWER8_PME_PM_ST_MISS_L1 944
#define POWER8_PME_PM_SUSPENDED 945
#define POWER8_PME_PM_SWAP_CANCEL 946
#define POWER8_PME_PM_SWAP_CANCEL_GPR 947
#define POWER8_PME_PM_SWAP_COMPLETE 948
#define POWER8_PME_PM_SWAP_COMPLETE_GPR 949
#define POWER8_PME_PM_SYNC_MRK_BR_LINK 950
#define POWER8_PME_PM_SYNC_MRK_BR_MPRED 951
#define POWER8_PME_PM_SYNC_MRK_FX_DIVIDE 952
#define POWER8_PME_PM_SYNC_MRK_L2HIT 953
#define POWER8_PME_PM_SYNC_MRK_L2MISS 954
#define POWER8_PME_PM_SYNC_MRK_L3MISS 955
#define POWER8_PME_PM_SYNC_MRK_PROBE_NOP 956
#define POWER8_PME_PM_SYS_PUMP_CPRED 957
#define POWER8_PME_PM_SYS_PUMP_MPRED 958
#define POWER8_PME_PM_SYS_PUMP_MPRED_RTY 959
#define POWER8_PME_PM_TABLEWALK_CYC 960
#define POWER8_PME_PM_TABLEWALK_CYC_PREF 961
#define POWER8_PME_PM_TABORT_TRECLAIM 962
#define POWER8_PME_PM_TB_BIT_TRANS 963
#define POWER8_PME_PM_TEND_PEND_CYC 964
#define POWER8_PME_PM_THRD_ALL_RUN_CYC 965
#define POWER8_PME_PM_THRD_CONC_RUN_INST 966
#define POWER8_PME_PM_THRD_GRP_CMPL_BOTH_CYC 967
#define POWER8_PME_PM_THRD_PRIO_0_1_CYC 968
#define POWER8_PME_PM_THRD_PRIO_2_3_CYC 969
#define POWER8_PME_PM_THRD_PRIO_4_5_CYC 970
#define POWER8_PME_PM_THRD_PRIO_6_7_CYC 971
#define POWER8_PME_PM_THRD_REBAL_CYC 972
#define POWER8_PME_PM_THRESH_EXC_1024 973
#define POWER8_PME_PM_THRESH_EXC_128 974
#define POWER8_PME_PM_THRESH_EXC_2048 975
#define POWER8_PME_PM_THRESH_EXC_256 976
#define POWER8_PME_PM_THRESH_EXC_32 977
#define POWER8_PME_PM_THRESH_EXC_4096 978
#define POWER8_PME_PM_THRESH_EXC_512 979
#define POWER8_PME_PM_THRESH_EXC_64 980
#define POWER8_PME_PM_THRESH_MET 981
#define POWER8_PME_PM_THRESH_NOT_MET 982
#define POWER8_PME_PM_TLBIE_FIN 983
#define POWER8_PME_PM_TLB_MISS 984
#define POWER8_PME_PM_TM_BEGIN_ALL 985
#define POWER8_PME_PM_TM_CAM_OVERFLOW 986
#define POWER8_PME_PM_TM_CAP_OVERFLOW 987
#define POWER8_PME_PM_TM_END_ALL 988
#define POWER8_PME_PM_TM_FAIL_CONF_NON_TM 989
#define POWER8_PME_PM_TM_FAIL_CON_TM 990
#define POWER8_PME_PM_TM_FAIL_DISALLOW 991
#define POWER8_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW 992
#define POWER8_PME_PM_TM_FAIL_NON_TX_CONFLICT 993
#define POWER8_PME_PM_TM_FAIL_SELF 994
#define POWER8_PME_PM_TM_FAIL_TLBIE 995
#define POWER8_PME_PM_TM_FAIL_TX_CONFLICT 996
#define POWER8_PME_PM_TM_FAV_CAUSED_FAIL 997
#define POWER8_PME_PM_TM_LD_CAUSED_FAIL 998
#define POWER8_PME_PM_TM_LD_CONF 999
#define POWER8_PME_PM_TM_RST_SC 1000
#define POWER8_PME_PM_TM_SC_CO 1001
#define POWER8_PME_PM_TM_ST_CAUSED_FAIL 1002
#define POWER8_PME_PM_TM_ST_CONF 1003
#define POWER8_PME_PM_TM_TBEGIN 1004
#define POWER8_PME_PM_TM_TRANS_RUN_CYC 1005
#define POWER8_PME_PM_TM_TRANS_RUN_INST 1006
#define POWER8_PME_PM_TM_TRESUME 1007
#define POWER8_PME_PM_TM_TSUSPEND 1008
#define POWER8_PME_PM_TM_TX_PASS_RUN_CYC 1009
#define POWER8_PME_PM_TM_TX_PASS_RUN_INST 1010
#define POWER8_PME_PM_UP_PREF_L3 1011
#define POWER8_PME_PM_UP_PREF_POINTER 1012
#define POWER8_PME_PM_VSU0_16FLOP 1013
#define POWER8_PME_PM_VSU0_1FLOP 1014
#define POWER8_PME_PM_VSU0_2FLOP 1015
#define POWER8_PME_PM_VSU0_4FLOP 1016
#define POWER8_PME_PM_VSU0_8FLOP 1017
#define POWER8_PME_PM_VSU0_COMPLEX_ISSUED 1018
#define POWER8_PME_PM_VSU0_CY_ISSUED 1019
#define POWER8_PME_PM_VSU0_DD_ISSUED 1020
#define POWER8_PME_PM_VSU0_DP_2FLOP 1021
#define POWER8_PME_PM_VSU0_DP_FMA 1022
#define POWER8_PME_PM_VSU0_DP_FSQRT_FDIV 1023
#define POWER8_PME_PM_VSU0_DQ_ISSUED 1024
#define POWER8_PME_PM_VSU0_EX_ISSUED 1025
#define POWER8_PME_PM_VSU0_FIN 1026
#define POWER8_PME_PM_VSU0_FMA 1027
#define POWER8_PME_PM_VSU0_FPSCR 1028
#define POWER8_PME_PM_VSU0_FSQRT_FDIV 1029
#define POWER8_PME_PM_VSU0_PERMUTE_ISSUED 1030
#define POWER8_PME_PM_VSU0_SCALAR_DP_ISSUED 1031
#define POWER8_PME_PM_VSU0_SIMPLE_ISSUED 1032
#define POWER8_PME_PM_VSU0_SINGLE 1033
#define POWER8_PME_PM_VSU0_SQ 1034
#define POWER8_PME_PM_VSU0_STF 1035
#define POWER8_PME_PM_VSU0_VECTOR_DP_ISSUED 1036
#define POWER8_PME_PM_VSU0_VECTOR_SP_ISSUED 1037
#define POWER8_PME_PM_VSU1_16FLOP 1038
#define POWER8_PME_PM_VSU1_1FLOP 1039
#define POWER8_PME_PM_VSU1_2FLOP 1040
#define POWER8_PME_PM_VSU1_4FLOP 1041
#define POWER8_PME_PM_VSU1_8FLOP 1042
#define POWER8_PME_PM_VSU1_COMPLEX_ISSUED 1043
#define POWER8_PME_PM_VSU1_CY_ISSUED 1044
#define POWER8_PME_PM_VSU1_DD_ISSUED 1045
#define POWER8_PME_PM_VSU1_DP_2FLOP 1046
#define POWER8_PME_PM_VSU1_DP_FMA 1047
#define POWER8_PME_PM_VSU1_DP_FSQRT_FDIV 1048
#define POWER8_PME_PM_VSU1_DQ_ISSUED 1049
#define POWER8_PME_PM_VSU1_EX_ISSUED 1050
#define POWER8_PME_PM_VSU1_FIN 1051
#define POWER8_PME_PM_VSU1_FMA 1052
#define POWER8_PME_PM_VSU1_FPSCR 1053
#define POWER8_PME_PM_VSU1_FSQRT_FDIV 1054
#define POWER8_PME_PM_VSU1_PERMUTE_ISSUED 1055
#define POWER8_PME_PM_VSU1_SCALAR_DP_ISSUED 1056
#define POWER8_PME_PM_VSU1_SIMPLE_ISSUED 1057
#define POWER8_PME_PM_VSU1_SINGLE 1058
#define POWER8_PME_PM_VSU1_SQ 1059
#define POWER8_PME_PM_VSU1_STF 1060
#define POWER8_PME_PM_VSU1_VECTOR_DP_ISSUED 1061
#define POWER8_PME_PM_VSU1_VECTOR_SP_ISSUED 1062

static const pme_power_entry_t power8_pe[] = {
[ POWER8_PME_PM_1LPAR_CYC ] = {
	.pme_name = "PM_1LPAR_CYC",
	.pme_code = 0x1f05e,
	.pme_short_desc = "Number of cycles in single lpar mode. All threads in the core are assigned to the same lpar",
	.pme_long_desc = "Number of cycles in single lpar mode.",
},
[ POWER8_PME_PM_1PLUS_PPC_CMPL ] = {
	.pme_name = "PM_1PLUS_PPC_CMPL",
	.pme_code = 0x100f2,
	.pme_short_desc = "1 or more ppc insts finished",
	.pme_long_desc = "1 or more ppc insts finished (completed).",
},
[ POWER8_PME_PM_1PLUS_PPC_DISP ] = {
	.pme_name = "PM_1PLUS_PPC_DISP",
	.pme_code = 0x400f2,
	.pme_short_desc = "Cycles at least one Instr Dispatched",
	.pme_long_desc = "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521",
},
[ POWER8_PME_PM_2LPAR_CYC ] = {
	.pme_name = "PM_2LPAR_CYC",
	.pme_code = 0x2006e,
	.pme_short_desc = "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to Lpar1",
	.pme_long_desc = "Number of cycles in 2 lpar mode.",
},
[ POWER8_PME_PM_4LPAR_CYC ] = {
	.pme_name = "PM_4LPAR_CYC",
	.pme_code = 0x4e05e,
	.pme_short_desc = "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong to lpar2, and threads 6-7 belong to lpar3",
	.pme_long_desc = "Number of cycles in 4 LPAR mode.",
},
[ POWER8_PME_PM_ALL_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_ALL_CHIP_PUMP_CPRED",
	.pme_code = 0x610050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types (demand load,data,inst prefetch,inst fetch,xlate (I or d)",
},
[ POWER8_PME_PM_ALL_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_ALL_GRP_PUMP_CPRED",
	.pme_code = 0x520050,
	.pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER8_PME_PM_ALL_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_ALL_GRP_PUMP_MPRED",
	.pme_code = 0x620052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro",
},
[ POWER8_PME_PM_ALL_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_ALL_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x610052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER8_PME_PM_ALL_PUMP_CPRED ] = {
	.pme_name = "PM_ALL_PUMP_CPRED",
	.pme_code = 0x610054,
	.pme_short_desc = "Pump prediction correct. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER8_PME_PM_ALL_PUMP_MPRED ] = {
	.pme_name = "PM_ALL_PUMP_MPRED",
	.pme_code = 0x640052,
	.pme_short_desc = "Pump misprediction. Counts across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER8_PME_PM_ALL_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_ALL_SYS_PUMP_CPRED",
	.pme_code = 0x630050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER8_PME_PM_ALL_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_ALL_SYS_PUMP_MPRED",
	.pme_code = 0x630052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or",
},
[ POWER8_PME_PM_ALL_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_ALL_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x640050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types (demand load,data prefetch,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER8_PME_PM_ANY_THRD_RUN_CYC ] = {
	.pme_name = "PM_ANY_THRD_RUN_CYC",
	.pme_code = 0x100fa,
	.pme_short_desc = "One of threads in run_cycles",
	.pme_long_desc = "Any thread in run_cycles (was one thread in run_cycles).",
},
[ POWER8_PME_PM_BACK_BR_CMPL ] = {
	.pme_name = "PM_BACK_BR_CMPL",
	.pme_code = 0x2505e,
	.pme_short_desc = "Branch instruction completed with a target address less than current instruction address",
	.pme_long_desc = "Branch instruction completed with a target address less than current instruction address.",
},
[ POWER8_PME_PM_BANK_CONFLICT ] = {
	.pme_name = "PM_BANK_CONFLICT",
	.pme_code = 0x4082,
	.pme_short_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.",
	.pme_long_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.",
},
[ POWER8_PME_PM_BRU_FIN ] = {
	.pme_name = "PM_BRU_FIN",
	.pme_code = 0x10068,
	.pme_short_desc = "Branch Instruction Finished",
	.pme_long_desc = "Branch Instruction Finished .",
},
[ POWER8_PME_PM_BR_2PATH ] = {
	.pme_name = "PM_BR_2PATH",
	.pme_code = 0x20036,
	.pme_short_desc = "two path branch",
	.pme_long_desc = "two path branch.",
},
[ POWER8_PME_PM_BR_BC_8 ] = {
	.pme_name = "PM_BR_BC_8",
	.pme_code = 0x5086,
	.pme_short_desc = "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline",
	.pme_long_desc = "Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline",
},
[ POWER8_PME_PM_BR_BC_8_CONV ] = {
	.pme_name = "PM_BR_BC_8_CONV",
	.pme_code = 0x5084,
	.pme_short_desc = "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline.",
	.pme_long_desc = "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline.",
},
[ POWER8_PME_PM_BR_CMPL ] = {
	.pme_name = "PM_BR_CMPL",
	.pme_code = 0x40060,
	.pme_short_desc = "Branch Instruction completed",
	.pme_long_desc = "Branch Instruction completed.",
},
[ POWER8_PME_PM_BR_MPRED_CCACHE ] = {
	.pme_name = "PM_BR_MPRED_CCACHE",
	.pme_code = 0x40ac,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction",
},
[ POWER8_PME_PM_BR_MPRED_CMPL ] = {
	.pme_name = "PM_BR_MPRED_CMPL",
	.pme_code = 0x400f6,
	.pme_short_desc = "Number of Branch Mispredicts",
	.pme_long_desc = "Number of Branch Mispredicts.",
},
[ POWER8_PME_PM_BR_MPRED_CR ] = {
	.pme_name = "PM_BR_MPRED_CR",
	.pme_code = 0x40b8,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken).",
},
[ POWER8_PME_PM_BR_MPRED_LSTACK ] = {
	.pme_name = "PM_BR_MPRED_LSTACK",
	.pme_code = 0x40ae,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction",
},
[ POWER8_PME_PM_BR_MPRED_TA ] = {
	.pme_name = "PM_BR_MPRED_TA",
	.pme_code = 0x40ba,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.",
},
[ POWER8_PME_PM_BR_MRK_2PATH ] = {
	.pme_name = "PM_BR_MRK_2PATH",
	.pme_code = 0x10138,
	.pme_short_desc = "marked two path branch",
	.pme_long_desc = "marked two path branch.",
},
[ POWER8_PME_PM_BR_PRED_BR0 ] = {
	.pme_name = "PM_BR_PRED_BR0",
	.pme_code = 0x409c,
	.pme_short_desc = "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target",
	.pme_long_desc = "Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target",
},
[ POWER8_PME_PM_BR_PRED_BR1 ] = {
	.pme_name = "PM_BR_PRED_BR1",
	.pme_code = 0x409e,
	.pme_short_desc = "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused.",
	.pme_long_desc = "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused.",
},
[ POWER8_PME_PM_BR_PRED_BR_CMPL ] = {
	.pme_name = "PM_BR_PRED_BR_CMPL",
	.pme_code = 0x489c,
	.pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) OR if_pc_br0_br_pred(1).",
	.pme_long_desc = "IFU",
},
[ POWER8_PME_PM_BR_PRED_CCACHE_BR0 ] = {
	.pme_name = "PM_BR_PRED_CCACHE_BR0",
	.pme_code = 0x40a4,
	.pme_short_desc = "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction",
	.pme_long_desc = "Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction",
},
[ POWER8_PME_PM_BR_PRED_CCACHE_BR1 ] = {
	.pme_name = "PM_BR_PRED_CCACHE_BR1",
	.pme_code = 0x40a6,
	.pme_short_desc = "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction",
	.pme_long_desc = "Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction",
},
[ POWER8_PME_PM_BR_PRED_CCACHE_CMPL ] = {
	.pme_name = "PM_BR_PRED_CCACHE_CMPL",
	.pme_code = 0x48a4,
	.pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND if_pc_br0_pred_type.",
	.pme_long_desc = "IFU",
},
[ POWER8_PME_PM_BR_PRED_CR_BR0 ] = {
	.pme_name = "PM_BR_PRED_CR_BR0",
	.pme_code = 0x40b0,
	.pme_short_desc = "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches",
	.pme_long_desc = "Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra",
},
[ POWER8_PME_PM_BR_PRED_CR_BR1 ] = {
	.pme_name = "PM_BR_PRED_CR_BR1",
	.pme_code = 0x40b2,
	.pme_short_desc = "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches",
	.pme_long_desc = "Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra",
},
[ POWER8_PME_PM_BR_PRED_CR_CMPL ] = {
	.pme_name = "PM_BR_PRED_CR_CMPL",
	.pme_code = 0x48b0,
	.pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(1)='1'.",
	.pme_long_desc = "IFU",
},
[ POWER8_PME_PM_BR_PRED_LSTACK_BR0 ] = {
	.pme_name = "PM_BR_PRED_LSTACK_BR0",
	.pme_code = 0x40a8,
	.pme_short_desc = "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction",
	.pme_long_desc = "Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction",
},
[ POWER8_PME_PM_BR_PRED_LSTACK_BR1 ] = {
	.pme_name = "PM_BR_PRED_LSTACK_BR1",
	.pme_code = 0x40aa,
	.pme_short_desc = "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction",
	.pme_long_desc = "Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction",
},
[ POWER8_PME_PM_BR_PRED_LSTACK_CMPL ] = {
	.pme_name = "PM_BR_PRED_LSTACK_CMPL",
	.pme_code = 0x48a8,
	.pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0) AND (not if_pc_br0_pred_type).",
	.pme_long_desc = "IFU",
},
[ POWER8_PME_PM_BR_PRED_TA_BR0 ] = {
	.pme_name = "PM_BR_PRED_TA_BR0",
	.pme_code = 0x40b4,
	.pme_short_desc = "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event.",
	.pme_long_desc = "Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event.",
},
[ POWER8_PME_PM_BR_PRED_TA_BR1 ] = {
	.pme_name = "PM_BR_PRED_TA_BR1",
	.pme_code = 0x40b6,
	.pme_short_desc = "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event.",
	.pme_long_desc = "Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event.",
},
[ POWER8_PME_PM_BR_PRED_TA_CMPL ] = {
	.pme_name = "PM_BR_PRED_TA_CMPL",
	.pme_code = 0x48b4,
	.pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred(0)='1'.",
	.pme_long_desc = "IFU",
},
[ POWER8_PME_PM_BR_TAKEN_CMPL ] = {
	.pme_name = "PM_BR_TAKEN_CMPL",
	.pme_code = 0x200fa,
	.pme_short_desc = "New event for Branch Taken",
	.pme_long_desc = "Branch Taken.",
},
[ POWER8_PME_PM_BR_UNCOND_BR0 ] = {
	.pme_name = "PM_BR_UNCOND_BR0",
	.pme_code = 0x40a0,
	.pme_short_desc = "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was converted to a Resolve.",
	.pme_long_desc = "Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was converted to a Resolve.",
},
[ POWER8_PME_PM_BR_UNCOND_BR1 ] = {
	.pme_name = "PM_BR_UNCOND_BR1",
	.pme_code = 0x40a2,
	.pme_short_desc = "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was converted to a Resolve.",
	.pme_long_desc = "Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was converted to a Resolve.",
},
[ POWER8_PME_PM_BR_UNCOND_CMPL ] = {
	.pme_name = "PM_BR_UNCOND_CMPL",
	.pme_code = 0x48a0,
	.pme_short_desc = "Completion Time Event. This event can also be calculated from the direct bus as follows: if_pc_br0_br_pred=00 AND if_pc_br0_completed.",
	.pme_long_desc = "IFU",
},
[ POWER8_PME_PM_CASTOUT_ISSUED ] = {
	.pme_name = "PM_CASTOUT_ISSUED",
	.pme_code = 0x3094,
	.pme_short_desc = "Castouts issued",
	.pme_long_desc = "Castouts issued",
},
[ POWER8_PME_PM_CASTOUT_ISSUED_GPR ] = {
	.pme_name = "PM_CASTOUT_ISSUED_GPR",
	.pme_code = 0x3096,
	.pme_short_desc = "Castouts issued GPR",
	.pme_long_desc = "Castouts issued GPR",
},
[ POWER8_PME_PM_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_CHIP_PUMP_CPRED",
	.pme_code = 0x10050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types (demand load,data,inst prefetch,inst fetch,xlate (I or d).",
},
[ POWER8_PME_PM_CLB_HELD ] = {
	.pme_name = "PM_CLB_HELD",
	.pme_code = 0x2090,
	.pme_short_desc = "CLB Hold: Any Reason",
	.pme_long_desc = "CLB Hold: Any Reason",
},
[ POWER8_PME_PM_CMPLU_STALL ] = {
	.pme_name = "PM_CMPLU_STALL",
	.pme_code = 0x4000a,
	.pme_short_desc = "Completion stall",
	.pme_long_desc = "Completion stall.",
},
[ POWER8_PME_PM_CMPLU_STALL_BRU ] = {
	.pme_name = "PM_CMPLU_STALL_BRU",
	.pme_code = 0x4d018,
	.pme_short_desc = "Completion stall due to a Branch Unit",
	.pme_long_desc = "Completion stall due to a Branch Unit.",
},
[ POWER8_PME_PM_CMPLU_STALL_BRU_CRU ] = {
	.pme_name = "PM_CMPLU_STALL_BRU_CRU",
	.pme_code = 0x2d018,
	.pme_short_desc = "Completion stall due to IFU",
	.pme_long_desc = "Completion stall due to IFU.",
},
[ POWER8_PME_PM_CMPLU_STALL_COQ_FULL ] = {
	.pme_name = "PM_CMPLU_STALL_COQ_FULL",
	.pme_code = 0x30026,
	.pme_short_desc = "Completion stall due to CO q full",
	.pme_long_desc = "Completion stall due to CO q full.",
},
[ POWER8_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
	.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
	.pme_code = 0x2c012,
	.pme_short_desc = "Completion stall by Dcache miss",
	.pme_long_desc = "Completion stall by Dcache miss.",
},
[ POWER8_PME_PM_CMPLU_STALL_DMISS_L21_L31 ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L21_L31",
	.pme_code = 0x2c018,
	.pme_short_desc = "Completion stall by Dcache miss which resolved on chip (excluding local L2/L3)",
	.pme_long_desc = "Completion stall by Dcache miss which resolved on chip (excluding local L2/L3).",
},
[ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3 ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L2L3",
	.pme_code = 0x2c016,
	.pme_short_desc = "Completion stall by Dcache miss which resolved in L2/L3",
	.pme_long_desc = "Completion stall by Dcache miss which resolved in L2/L3.",
},
[ POWER8_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
	.pme_code = 0x4c016,
	.pme_short_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
	.pme_long_desc = "Completion stall due to cache miss resolving in core's L2/L3 with a conflict.",
},
[ POWER8_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L3MISS",
	.pme_code = 0x4c01a,
	.pme_short_desc = "Completion stall due to cache miss resolving missed the L3",
	.pme_long_desc = "Completion stall due to cache miss resolving missed the L3.",
},
[ POWER8_PME_PM_CMPLU_STALL_DMISS_LMEM ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_LMEM",
	.pme_code = 0x4c018,
	.pme_short_desc = "Completion stall due to cache miss that resolves in local memory",
	.pme_long_desc = "Completion stall due to cache miss resolving in core's Local Memory.",
},
[ POWER8_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_REMOTE",
	.pme_code = 0x2c01c,
	.pme_short_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
	.pme_long_desc = "Completion stall by Dcache miss which resolved on chip (excluding local L2/L3).",
},
[ POWER8_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
	.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
	.pme_code = 0x4c012,
	.pme_short_desc = "Completion stall due to LSU reject ERAT miss",
	.pme_long_desc = "Completion stall due to LSU reject ERAT miss.",
},
[ POWER8_PME_PM_CMPLU_STALL_FLUSH ] = {
	.pme_name = "PM_CMPLU_STALL_FLUSH",
	.pme_code = 0x30038,
	.pme_short_desc = "completion stall due to flush by own thread",
	.pme_long_desc = "completion stall due to flush by own thread.",
},
[ POWER8_PME_PM_CMPLU_STALL_FXLONG ] = {
	.pme_name = "PM_CMPLU_STALL_FXLONG",
	.pme_code = 0x4d016,
	.pme_short_desc = "Completion stall due to a long latency fixed point instruction",
	.pme_long_desc = "Completion stall due to a long latency fixed point instruction.",
},
[ POWER8_PME_PM_CMPLU_STALL_FXU ] = {
	.pme_name = "PM_CMPLU_STALL_FXU",
	.pme_code = 0x2d016,
	.pme_short_desc = "Completion stall due to FXU",
	.pme_long_desc = "Completion stall due to FXU.",
},
[ POWER8_PME_PM_CMPLU_STALL_HWSYNC ] = {
	.pme_name = "PM_CMPLU_STALL_HWSYNC",
	.pme_code = 0x30036,
	.pme_short_desc = "completion stall due to hwsync",
	.pme_long_desc = "completion stall due to hwsync.",
},
[ POWER8_PME_PM_CMPLU_STALL_LOAD_FINISH ] = {
	.pme_name = "PM_CMPLU_STALL_LOAD_FINISH",
	.pme_code = 0x4d014,
	.pme_short_desc = "Completion stall due to a Load finish",
	.pme_long_desc = "Completion stall due to a Load finish.",
},
[ POWER8_PME_PM_CMPLU_STALL_LSU ] = {
	.pme_name = "PM_CMPLU_STALL_LSU",
	.pme_code = 0x2c010,
	.pme_short_desc = "Completion stall by LSU instruction",
	.pme_long_desc = "Completion stall by LSU instruction.",
},
[ POWER8_PME_PM_CMPLU_STALL_LWSYNC ] = {
	.pme_name = "PM_CMPLU_STALL_LWSYNC",
	.pme_code = 0x10036,
	.pme_short_desc = "completion stall due to isync/lwsync",
	.pme_long_desc = "completion stall due to isync/lwsync.",
},
[ POWER8_PME_PM_CMPLU_STALL_MEM_ECC_DELAY ] = {
	.pme_name = "PM_CMPLU_STALL_MEM_ECC_DELAY",
	.pme_code = 0x30028,
	.pme_short_desc = "Completion stall due to mem ECC delay",
	.pme_long_desc = "Completion stall due to mem ECC delay.",
},
[ POWER8_PME_PM_CMPLU_STALL_NO_NTF ] = {
	.pme_name = "PM_CMPLU_STALL_NO_NTF",
	.pme_code = 0x2e01c,
	.pme_short_desc = "Completion stall due to nop",
	.pme_long_desc = "Completion stall due to nop.",
},
[ POWER8_PME_PM_CMPLU_STALL_NTCG_FLUSH ] = {
	.pme_name = "PM_CMPLU_STALL_NTCG_FLUSH",
	.pme_code = 0x2e01e,
	.pme_short_desc = "Completion stall due to ntcg flush",
	.pme_long_desc = "Completion stall due to reject (load hit store).",
},
[ POWER8_PME_PM_CMPLU_STALL_OTHER_CMPL ] = {
	.pme_name = "PM_CMPLU_STALL_OTHER_CMPL",
	.pme_code = 0x30006,
	.pme_short_desc = "Instructions core completed while this tread was stalled",
	.pme_long_desc = "Instructions core completed while this thread was stalled.",
},
[ POWER8_PME_PM_CMPLU_STALL_REJECT ] = {
	.pme_name = "PM_CMPLU_STALL_REJECT",
	.pme_code = 0x4c010,
	.pme_short_desc = "Completion stall due to LSU reject",
	.pme_long_desc = "Completion stall due to LSU reject.",
},
[ POWER8_PME_PM_CMPLU_STALL_REJECT_LHS ] = {
	.pme_name = "PM_CMPLU_STALL_REJECT_LHS",
	.pme_code = 0x2c01a,
	.pme_short_desc = "Completion stall due to reject (load hit store)",
	.pme_long_desc = "Completion stall due to reject (load hit store).",
},
[ POWER8_PME_PM_CMPLU_STALL_REJ_LMQ_FULL ] = {
	.pme_name = "PM_CMPLU_STALL_REJ_LMQ_FULL",
	.pme_code = 0x4c014,
	.pme_short_desc = "Completion stall due to LSU reject LMQ full",
	.pme_long_desc = "Completion stall due to LSU reject LMQ full.",
},
[ POWER8_PME_PM_CMPLU_STALL_SCALAR ] = {
	.pme_name = "PM_CMPLU_STALL_SCALAR",
	.pme_code = 0x4d010,
	.pme_short_desc = "Completion stall due to VSU scalar instruction",
	.pme_long_desc = "Completion stall due to VSU scalar instruction.",
},
[ POWER8_PME_PM_CMPLU_STALL_SCALAR_LONG ] = {
	.pme_name = "PM_CMPLU_STALL_SCALAR_LONG",
	.pme_code = 0x2d010,
	.pme_short_desc = "Completion stall due to VSU scalar long latency instruction",
	.pme_long_desc = "Completion stall due to VSU scalar long latency instruction.",
},
[ POWER8_PME_PM_CMPLU_STALL_STORE ] = {
	.pme_name = "PM_CMPLU_STALL_STORE",
	.pme_code = 0x2c014,
	.pme_short_desc = "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data finishes in LS2/LS3",
	.pme_long_desc = "Completion stall by stores.",
},
[ POWER8_PME_PM_CMPLU_STALL_ST_FWD ] = {
	.pme_name = "PM_CMPLU_STALL_ST_FWD",
	.pme_code = 0x4c01c,
	.pme_short_desc = "Completion stall due to store forward",
	.pme_long_desc = "Completion stall due to store forward.",
},
[ POWER8_PME_PM_CMPLU_STALL_THRD ] = {
	.pme_name = "PM_CMPLU_STALL_THRD",
	.pme_code = 0x1001c,
	.pme_short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
	.pme_long_desc = "Completion stall due to thread conflict.",
},
[ POWER8_PME_PM_CMPLU_STALL_VECTOR ] = {
	.pme_name = "PM_CMPLU_STALL_VECTOR",
	.pme_code = 0x2d014,
	.pme_short_desc = "Completion stall due to VSU vector instruction",
	.pme_long_desc = "Completion stall due to VSU vector instruction.",
},
[ POWER8_PME_PM_CMPLU_STALL_VECTOR_LONG ] = {
	.pme_name = "PM_CMPLU_STALL_VECTOR_LONG",
	.pme_code = 0x4d012,
	.pme_short_desc = "Completion stall due to VSU vector long instruction",
	.pme_long_desc = "Completion stall due to VSU vector long instruction.",
},
[ POWER8_PME_PM_CMPLU_STALL_VSU ] = {
	.pme_name = "PM_CMPLU_STALL_VSU",
	.pme_code = 0x2d012,
	.pme_short_desc = "Completion stall due to VSU instruction",
	.pme_long_desc = "Completion stall due to VSU instruction.",
},
[ POWER8_PME_PM_CO0_ALLOC ] = {
	.pme_name = "PM_CO0_ALLOC",
	.pme_code = 0x16083,
	.pme_short_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_CO0_BUSY ] = {
	.pme_name = "PM_CO0_BUSY",
	.pme_code = 0x16082,
	.pme_short_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
	.pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
},
[ POWER8_PME_PM_CO_DISP_FAIL ] = {
	.pme_name = "PM_CO_DISP_FAIL",
	.pme_code = 0x517082,
	.pme_short_desc = "CO dispatch failed due to all CO machines being busy",
	.pme_long_desc = "CO dispatch failed due to all CO machines being busy",
},
[ POWER8_PME_PM_CO_TM_SC_FOOTPRINT ] = {
	.pme_name = "PM_CO_TM_SC_FOOTPRINT",
	.pme_code = 0x527084,
	.pme_short_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)",
	.pme_long_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3)",
},
[ POWER8_PME_PM_CO_USAGE ] = {
	.pme_name = "PM_CO_USAGE",
	.pme_code = 0x3608a,
	.pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
	.pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
},
[ POWER8_PME_PM_CRU_FIN ] = {
	.pme_name = "PM_CRU_FIN",
	.pme_code = 0x40066,
	.pme_short_desc = "IFU Finished a (non-branch) instruction",
	.pme_long_desc = "IFU Finished a (non-branch) instruction.",
},
[ POWER8_PME_PM_CYC ] = {
	.pme_name = "PM_CYC",
	.pme_code = 0x1e,
	.pme_short_desc = "Cycles",
	.pme_long_desc = "Cycles .",
},
[ POWER8_PME_PM_DATA_ALL_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_ALL_CHIP_PUMP_CPRED",
	.pme_code = 0x61c050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load",
},
[ POWER8_PME_PM_DATA_ALL_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_DL2L3_MOD",
	.pme_code = 0x64c048,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_DATA_ALL_FROM_DL2L3_SHR",
	.pme_code = 0x63c048,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_DL4 ] = {
	.pme_name = "PM_DATA_ALL_FROM_DL4",
	.pme_code = 0x63c04c,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_DMEM ] = {
	.pme_name = "PM_DATA_ALL_FROM_DMEM",
	.pme_code = 0x64c04c,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L2 ] = {
	.pme_name = "PM_DATA_ALL_FROM_L2",
	.pme_code = 0x61c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L21_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_L21_MOD",
	.pme_code = 0x64c046,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L21_SHR ] = {
	.pme_name = "PM_DATA_ALL_FROM_L21_SHR",
	.pme_code = 0x63c046,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L2MISS_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_L2MISS_MOD",
	.pme_code = 0x61c04e,
	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x63c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x64c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L2_MEPF ] = {
	.pme_name = "PM_DATA_ALL_FROM_L2_MEPF",
	.pme_code = 0x62c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_DATA_ALL_FROM_L2_NO_CONFLICT",
	.pme_code = 0x61c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L3 ] = {
	.pme_name = "PM_DATA_ALL_FROM_L3",
	.pme_code = 0x64c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_L31_ECO_MOD",
	.pme_code = 0x64c044,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_DATA_ALL_FROM_L31_ECO_SHR",
	.pme_code = 0x63c044,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L31_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_L31_MOD",
	.pme_code = 0x62c044,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L31_SHR ] = {
	.pme_name = "PM_DATA_ALL_FROM_L31_SHR",
	.pme_code = 0x61c046,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L3MISS_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_L3MISS_MOD",
	.pme_code = 0x64c04e,
	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_DATA_ALL_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x63c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L3_MEPF ] = {
	.pme_name = "PM_DATA_ALL_FROM_L3_MEPF",
	.pme_code = 0x62c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_DATA_ALL_FROM_L3_NO_CONFLICT",
	.pme_code = 0x61c044,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_LL4 ] = {
	.pme_name = "PM_DATA_ALL_FROM_LL4",
	.pme_code = 0x61c04c,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_LMEM ] = {
	.pme_name = "PM_DATA_ALL_FROM_LMEM",
	.pme_code = 0x62c048,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_MEMORY ] = {
	.pme_name = "PM_DATA_ALL_FROM_MEMORY",
	.pme_code = 0x62c04c,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_DATA_ALL_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x64c04a,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_DATA_ALL_FROM_ON_CHIP_CACHE",
	.pme_code = 0x61c048,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_DATA_ALL_FROM_RL2L3_MOD",
	.pme_code = 0x62c046,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_DATA_ALL_FROM_RL2L3_SHR",
	.pme_code = 0x61c04a,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_RL4 ] = {
	.pme_name = "PM_DATA_ALL_FROM_RL4",
	.pme_code = 0x62c04a,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_FROM_RMEM ] = {
	.pme_name = "PM_DATA_ALL_FROM_RMEM",
	.pme_code = 0x63c04a,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Remote) due to either demand loads or data prefetch",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1",
},
[ POWER8_PME_PM_DATA_ALL_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_ALL_GRP_PUMP_CPRED",
	.pme_code = 0x62c050,
	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for either demand loads or data prefetch",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load",
},
[ POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_ALL_GRP_PUMP_MPRED",
	.pme_code = 0x62c052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for either demand loads or data prefetch",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro",
},
[ POWER8_PME_PM_DATA_ALL_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_DATA_ALL_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x61c052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for either demand loads or data prefetch",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load",
},
[ POWER8_PME_PM_DATA_ALL_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_ALL_PUMP_CPRED",
	.pme_code = 0x61c054,
	.pme_short_desc = "Pump prediction correct. Counts across all types of pumps for either demand loads or data prefetch",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load",
},
[ POWER8_PME_PM_DATA_ALL_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_ALL_PUMP_MPRED",
	.pme_code = 0x64c052,
	.pme_short_desc = "Pump misprediction. Counts across all types of pumps for either demand loads or data prefetch",
	.pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor a demand load",
},
[ POWER8_PME_PM_DATA_ALL_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_ALL_SYS_PUMP_CPRED",
	.pme_code = 0x63c050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for either demand loads or data prefetch",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load",
},
[ POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_ALL_SYS_PUMP_MPRED",
	.pme_code = 0x63c052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for either demand loads or data prefetch",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or",
},
[ POWER8_PME_PM_DATA_ALL_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_DATA_ALL_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x64c050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for either demand loads or data prefetch",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load",
},
[ POWER8_PME_PM_DATA_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_CHIP_PUMP_CPRED",
	.pme_code = 0x1c050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load.",
},
[ POWER8_PME_PM_DATA_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_DATA_FROM_DL2L3_MOD",
	.pme_code = 0x4c048,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_DATA_FROM_DL2L3_SHR",
	.pme_code = 0x3c048,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_DL4 ] = {
	.pme_name = "PM_DATA_FROM_DL4",
	.pme_code = 0x3c04c,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_DMEM ] = {
	.pme_name = "PM_DATA_FROM_DMEM",
	.pme_code = 0x4c04c,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L2 ] = {
	.pme_name = "PM_DATA_FROM_L2",
	.pme_code = 0x1c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L21_MOD ] = {
	.pme_name = "PM_DATA_FROM_L21_MOD",
	.pme_code = 0x4c046,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L21_SHR ] = {
	.pme_name = "PM_DATA_FROM_L21_SHR",
	.pme_code = 0x3c046,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L2MISS ] = {
	.pme_name = "PM_DATA_FROM_L2MISS",
	.pme_code = 0x200fe,
	.pme_short_desc = "Demand LD - L2 Miss (not L2 hit)",
	.pme_long_desc = "Demand LD - L2 Miss (not L2 hit).",
},
[ POWER8_PME_PM_DATA_FROM_L2MISS_MOD ] = {
	.pme_name = "PM_DATA_FROM_L2MISS_MOD",
	.pme_code = 0x1c04e,
	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x3c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x4c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L2_MEPF ] = {
	.pme_name = "PM_DATA_FROM_L2_MEPF",
	.pme_code = 0x2c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_DATA_FROM_L2_NO_CONFLICT",
	.pme_code = 0x1c040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 .",
},
[ POWER8_PME_PM_DATA_FROM_L3 ] = {
	.pme_name = "PM_DATA_FROM_L3",
	.pme_code = 0x4c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_DATA_FROM_L31_ECO_MOD",
	.pme_code = 0x4c044,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_DATA_FROM_L31_ECO_SHR",
	.pme_code = 0x3c044,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L31_MOD ] = {
	.pme_name = "PM_DATA_FROM_L31_MOD",
	.pme_code = 0x2c044,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L31_SHR ] = {
	.pme_name = "PM_DATA_FROM_L31_SHR",
	.pme_code = 0x1c046,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L3MISS ] = {
	.pme_name = "PM_DATA_FROM_L3MISS",
	.pme_code = 0x300fe,
	.pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
	.pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit).",
},
[ POWER8_PME_PM_DATA_FROM_L3MISS_MOD ] = {
	.pme_name = "PM_DATA_FROM_L3MISS_MOD",
	.pme_code = 0x4c04e,
	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x3c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L3_MEPF ] = {
	.pme_name = "PM_DATA_FROM_L3_MEPF",
	.pme_code = 0x2c042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_DATA_FROM_L3_NO_CONFLICT",
	.pme_code = 0x1c044,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_LL4 ] = {
	.pme_name = "PM_DATA_FROM_LL4",
	.pme_code = 0x1c04c,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_LMEM ] = {
	.pme_name = "PM_DATA_FROM_LMEM",
	.pme_code = 0x2c048,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_MEM ] = {
	.pme_name = "PM_DATA_FROM_MEM",
	.pme_code = 0x400fe,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
	.pme_long_desc = "Data cache reload from memory (including L4).",
},
[ POWER8_PME_PM_DATA_FROM_MEMORY ] = {
	.pme_name = "PM_DATA_FROM_MEMORY",
	.pme_code = 0x2c04c,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_DATA_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x4c04a,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_DATA_FROM_ON_CHIP_CACHE",
	.pme_code = 0x1c048,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_DATA_FROM_RL2L3_MOD",
	.pme_code = 0x2c046,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_DATA_FROM_RL2L3_SHR",
	.pme_code = 0x1c04a,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_RL4 ] = {
	.pme_name = "PM_DATA_FROM_RL4",
	.pme_code = 0x2c04a,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_FROM_RMEM ] = {
	.pme_name = "PM_DATA_FROM_RMEM",
	.pme_code = 0x3c04a,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Remote) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1.",
},
[ POWER8_PME_PM_DATA_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_GRP_PUMP_CPRED",
	.pme_code = 0x2c050,
	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load.",
},
[ POWER8_PME_PM_DATA_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_GRP_PUMP_MPRED",
	.pme_code = 0x2c052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro",
},
[ POWER8_PME_PM_DATA_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_DATA_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x1c052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load.",
},
[ POWER8_PME_PM_DATA_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_PUMP_CPRED",
	.pme_code = 0x1c054,
	.pme_short_desc = "Pump prediction correct. Counts across all types of pumps for a demand load",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load.",
},
[ POWER8_PME_PM_DATA_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_PUMP_MPRED",
	.pme_code = 0x4c052,
	.pme_short_desc = "Pump misprediction. Counts across all types of pumps for a demand load",
	.pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor a demand load.",
},
[ POWER8_PME_PM_DATA_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_SYS_PUMP_CPRED",
	.pme_code = 0x3c050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load.",
},
[ POWER8_PME_PM_DATA_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_SYS_PUMP_MPRED",
	.pme_code = 0x3c052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or",
},
[ POWER8_PME_PM_DATA_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_DATA_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x4c050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load.",
},
[ POWER8_PME_PM_DATA_TABLEWALK_CYC ] = {
	.pme_name = "PM_DATA_TABLEWALK_CYC",
	.pme_code = 0x3001a,
	.pme_short_desc = "Tablwalk Cycles (could be 1 or 2 active)",
	.pme_long_desc = "Data Tablewalk Active.",
},
[ POWER8_PME_PM_DC_COLLISIONS ] = {
	.pme_name = "PM_DC_COLLISIONS",
	.pme_code = 0xe0bc,
	.pme_short_desc = "DATA Cache collisions",
	.pme_long_desc = "DATA Cache collisions42",
},
[ POWER8_PME_PM_DC_PREF_STREAM_ALLOC ] = {
	.pme_name = "PM_DC_PREF_STREAM_ALLOC",
	.pme_code = 0x1e050,
	.pme_short_desc = "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1",
	.pme_long_desc = "Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1.",
},
[ POWER8_PME_PM_DC_PREF_STREAM_CONF ] = {
	.pme_name = "PM_DC_PREF_STREAM_CONF",
	.pme_code = 0x2e050,
	.pme_short_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down",
	.pme_long_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down.",
},
[ POWER8_PME_PM_DC_PREF_STREAM_FUZZY_CONF ] = {
	.pme_name = "PM_DC_PREF_STREAM_FUZZY_CONF",
	.pme_code = 0x4e050,
	.pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)",
	.pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up).",
},
[ POWER8_PME_PM_DC_PREF_STREAM_STRIDED_CONF ] = {
	.pme_name = "PM_DC_PREF_STREAM_STRIDED_CONF",
	.pme_code = 0x3e050,
	.pme_short_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.",
	.pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software..",
},
[ POWER8_PME_PM_DERAT_MISS_16G ] = {
	.pme_name = "PM_DERAT_MISS_16G",
	.pme_code = 0x4c054,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16G",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16G.",
},
[ POWER8_PME_PM_DERAT_MISS_16M ] = {
	.pme_name = "PM_DERAT_MISS_16M",
	.pme_code = 0x3c054,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16M",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16M.",
},
[ POWER8_PME_PM_DERAT_MISS_4K ] = {
	.pme_name = "PM_DERAT_MISS_4K",
	.pme_code = 0x1c056,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 4K",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 4K.",
},
[ POWER8_PME_PM_DERAT_MISS_64K ] = {
	.pme_name = "PM_DERAT_MISS_64K",
	.pme_code = 0x2c054,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 64K",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 64K.",
},
[ POWER8_PME_PM_DFU ] = {
	.pme_name = "PM_DFU",
	.pme_code = 0xb0ba,
	.pme_short_desc = "Finish DFU (all finish)",
	.pme_long_desc = "Finish DFU (all finish)",
},
[ POWER8_PME_PM_DFU_DCFFIX ] = {
	.pme_name = "PM_DFU_DCFFIX",
	.pme_code = 0xb0be,
	.pme_short_desc = "Convert from fixed opcode finish (dcffix,dcffixq)",
	.pme_long_desc = "Convert from fixed opcode finish (dcffix,dcffixq)",
},
[ POWER8_PME_PM_DFU_DENBCD ] = {
	.pme_name = "PM_DFU_DENBCD",
	.pme_code = 0xb0bc,
	.pme_short_desc = "BCD->DPD opcode finish (denbcd, denbcdq)",
	.pme_long_desc = "BCD->DPD opcode finish (denbcd, denbcdq)",
},
[ POWER8_PME_PM_DFU_MC ] = {
	.pme_name = "PM_DFU_MC",
	.pme_code = 0xb0b8,
	.pme_short_desc = "Finish DFU multicycle",
	.pme_long_desc = "Finish DFU multicycle",
},
[ POWER8_PME_PM_DISP_CLB_HELD_BAL ] = {
	.pme_name = "PM_DISP_CLB_HELD_BAL",
	.pme_code = 0x2092,
	.pme_short_desc = "Dispatch/CLB Hold: Balance",
	.pme_long_desc = "Dispatch/CLB Hold: Balance",
},
[ POWER8_PME_PM_DISP_CLB_HELD_RES ] = {
	.pme_name = "PM_DISP_CLB_HELD_RES",
	.pme_code = 0x2094,
	.pme_short_desc = "Dispatch/CLB Hold: Resource",
	.pme_long_desc = "Dispatch/CLB Hold: Resource",
},
[ POWER8_PME_PM_DISP_CLB_HELD_SB ] = {
	.pme_name = "PM_DISP_CLB_HELD_SB",
	.pme_code = 0x20a8,
	.pme_short_desc = "Dispatch/CLB Hold: Scoreboard",
	.pme_long_desc = "Dispatch/CLB Hold: Scoreboard",
},
[ POWER8_PME_PM_DISP_CLB_HELD_SYNC ] = {
	.pme_name = "PM_DISP_CLB_HELD_SYNC",
	.pme_code = 0x2098,
	.pme_short_desc = "Dispatch/CLB Hold: Sync type instruction",
	.pme_long_desc = "Dispatch/CLB Hold: Sync type instruction",
},
[ POWER8_PME_PM_DISP_CLB_HELD_TLBIE ] = {
	.pme_name = "PM_DISP_CLB_HELD_TLBIE",
	.pme_code = 0x2096,
	.pme_short_desc = "Dispatch Hold: Due to TLBIE",
	.pme_long_desc = "Dispatch Hold: Due to TLBIE",
},
[ POWER8_PME_PM_DISP_HELD ] = {
	.pme_name = "PM_DISP_HELD",
	.pme_code = 0x10006,
	.pme_short_desc = "Dispatch Held",
	.pme_long_desc = "Dispatch Held.",
},
[ POWER8_PME_PM_DISP_HELD_IQ_FULL ] = {
	.pme_name = "PM_DISP_HELD_IQ_FULL",
	.pme_code = 0x20006,
	.pme_short_desc = "Dispatch held due to Issue q full",
	.pme_long_desc = "Dispatch held due to Issue q full.",
},
[ POWER8_PME_PM_DISP_HELD_MAP_FULL ] = {
	.pme_name = "PM_DISP_HELD_MAP_FULL",
	.pme_code = 0x1002a,
	.pme_short_desc = "Dispatch for this thread was held because the Mappers were full",
	.pme_long_desc = "Dispatch held due to Mapper full.",
},
[ POWER8_PME_PM_DISP_HELD_SRQ_FULL ] = {
	.pme_name = "PM_DISP_HELD_SRQ_FULL",
	.pme_code = 0x30018,
	.pme_short_desc = "Dispatch held due SRQ no room",
	.pme_long_desc = "Dispatch held due SRQ no room.",
},
[ POWER8_PME_PM_DISP_HELD_SYNC_HOLD ] = {
	.pme_name = "PM_DISP_HELD_SYNC_HOLD",
	.pme_code = 0x4003c,
	.pme_short_desc = "Dispatch held due to SYNC hold",
	.pme_long_desc = "Dispatch held due to SYNC hold.",
},
[ POWER8_PME_PM_DISP_HOLD_GCT_FULL ] = {
	.pme_name = "PM_DISP_HOLD_GCT_FULL",
	.pme_code = 0x30a6,
	.pme_short_desc = "Dispatch Hold Due to no space in the GCT",
	.pme_long_desc = "Dispatch Hold Due to no space in the GCT",
},
[ POWER8_PME_PM_DISP_WT ] = {
	.pme_name = "PM_DISP_WT",
	.pme_code = 0x30008,
	.pme_short_desc = "Dispatched Starved",
	.pme_long_desc = "Dispatched Starved (not held, nothing to dispatch).",
},
[ POWER8_PME_PM_DPTEG_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_DL2L3_MOD",
	.pme_code = 0x4e048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_DL2L3_SHR",
	.pme_code = 0x3e048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_DL4 ] = {
	.pme_name = "PM_DPTEG_FROM_DL4",
	.pme_code = 0x3e04c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_DMEM ] = {
	.pme_name = "PM_DPTEG_FROM_DMEM",
	.pme_code = 0x4e04c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L2 ] = {
	.pme_name = "PM_DPTEG_FROM_L2",
	.pme_code = 0x1e042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L21_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_L21_MOD",
	.pme_code = 0x4e046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L21_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_L21_SHR",
	.pme_code = 0x3e046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L2MISS ] = {
	.pme_name = "PM_DPTEG_FROM_L2MISS",
	.pme_code = 0x1e04e,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x3e040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x4e040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L2_MEPF ] = {
	.pme_name = "PM_DPTEG_FROM_L2_MEPF",
	.pme_code = 0x2e040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_DPTEG_FROM_L2_NO_CONFLICT",
	.pme_code = 0x1e040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L3 ] = {
	.pme_name = "PM_DPTEG_FROM_L3",
	.pme_code = 0x4e042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_L31_ECO_MOD",
	.pme_code = 0x4e044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_L31_ECO_SHR",
	.pme_code = 0x3e044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L31_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_L31_MOD",
	.pme_code = 0x2e044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L31_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_L31_SHR",
	.pme_code = 0x1e046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L3MISS ] = {
	.pme_name = "PM_DPTEG_FROM_L3MISS",
	.pme_code = 0x4e04e,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x3e042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L3_MEPF ] = {
	.pme_name = "PM_DPTEG_FROM_L3_MEPF",
	.pme_code = 0x2e042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_DPTEG_FROM_L3_NO_CONFLICT",
	.pme_code = 0x1e044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_LL4 ] = {
	.pme_name = "PM_DPTEG_FROM_LL4",
	.pme_code = 0x1e04c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_LMEM ] = {
	.pme_name = "PM_DPTEG_FROM_LMEM",
	.pme_code = 0x2e048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_MEMORY ] = {
	.pme_name = "PM_DPTEG_FROM_MEMORY",
	.pme_code = 0x2e04c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_DPTEG_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x4e04a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_DPTEG_FROM_ON_CHIP_CACHE",
	.pme_code = 0x1e048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_RL2L3_MOD",
	.pme_code = 0x2e046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_RL2L3_SHR",
	.pme_code = 0x1e04a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_RL4 ] = {
	.pme_name = "PM_DPTEG_FROM_RL4",
	.pme_code = 0x2e04a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group (Remote) due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group (Remote) due to a data side request.",
},
[ POWER8_PME_PM_DPTEG_FROM_RMEM ] = {
	.pme_name = "PM_DPTEG_FROM_RMEM",
	.pme_code = 0x3e04a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Remote) due to a data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Remote) due to a data side request.",
},
[ POWER8_PME_PM_DSLB_MISS ] = {
	.pme_name = "PM_DSLB_MISS",
	.pme_code = 0xd094,
	.pme_short_desc = "Data SLB Miss - Total of all segment sizes",
	.pme_long_desc = "Data SLB Miss - Total of all segment sizesData SLB misses",
},
[ POWER8_PME_PM_DTLB_MISS ] = {
	.pme_name = "PM_DTLB_MISS",
	.pme_code = 0x300fc,
	.pme_short_desc = "Data PTEG reload",
	.pme_long_desc = "Data PTEG Reloaded (DTLB Miss).",
},
[ POWER8_PME_PM_DTLB_MISS_16G ] = {
	.pme_name = "PM_DTLB_MISS_16G",
	.pme_code = 0x1c058,
	.pme_short_desc = "Data TLB Miss page size 16G",
	.pme_long_desc = "Data TLB Miss page size 16G.",
},
[ POWER8_PME_PM_DTLB_MISS_16M ] = {
	.pme_name = "PM_DTLB_MISS_16M",
	.pme_code = 0x4c056,
	.pme_short_desc = "Data TLB Miss page size 16M",
	.pme_long_desc = "Data TLB Miss page size 16M.",
},
[ POWER8_PME_PM_DTLB_MISS_4K ] = {
	.pme_name = "PM_DTLB_MISS_4K",
	.pme_code = 0x2c056,
	.pme_short_desc = "Data TLB Miss page size 4k",
	.pme_long_desc = "Data TLB Miss page size 4k.",
},
[ POWER8_PME_PM_DTLB_MISS_64K ] = {
	.pme_name = "PM_DTLB_MISS_64K",
	.pme_code = 0x3c056,
	.pme_short_desc = "Data TLB Miss page size 64K",
	.pme_long_desc = "Data TLB Miss page size 64K.",
},
[ POWER8_PME_PM_EAT_FORCE_MISPRED ] = {
	.pme_name = "PM_EAT_FORCE_MISPRED",
	.pme_code = 0x50a8,
	.pme_short_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issue",
	.pme_long_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is",
},
[ POWER8_PME_PM_EAT_FULL_CYC ] = {
	.pme_name = "PM_EAT_FULL_CYC",
	.pme_code = 0x4084,
	.pme_short_desc = "Cycles No room in EAT",
	.pme_long_desc = "Cycles No room in EATSet on bank conflict and case where no ibuffers available.",
},
[ POWER8_PME_PM_EE_OFF_EXT_INT ] = {
	.pme_name = "PM_EE_OFF_EXT_INT",
	.pme_code = 0x2080,
	.pme_short_desc = "Ee off and external interrupt",
	.pme_long_desc = "Ee off and external interrupt",
},
[ POWER8_PME_PM_EXT_INT ] = {
	.pme_name = "PM_EXT_INT",
	.pme_code = 0x200f8,
	.pme_short_desc = "external interrupt",
	.pme_long_desc = "external interrupt.",
},
[ POWER8_PME_PM_FAV_TBEGIN ] = {
	.pme_name = "PM_FAV_TBEGIN",
	.pme_code = 0x20b4,
	.pme_short_desc = "Dispatch time Favored tbegin",
	.pme_long_desc = "Dispatch time Favored tbegin",
},
[ POWER8_PME_PM_FLOP ] = {
	.pme_name = "PM_FLOP",
	.pme_code = 0x100f4,
	.pme_short_desc = "Floating Point Operation Finished",
	.pme_long_desc = "Floating Point Operations Finished.",
},
[ POWER8_PME_PM_FLOP_SUM_SCALAR ] = {
	.pme_name = "PM_FLOP_SUM_SCALAR",
	.pme_code = 0xa0ae,
	.pme_short_desc = "flops summary scalar instructions",
	.pme_long_desc = "flops summary scalar instructions",
},
[ POWER8_PME_PM_FLOP_SUM_VEC ] = {
	.pme_name = "PM_FLOP_SUM_VEC",
	.pme_code = 0xa0ac,
	.pme_short_desc = "flops summary vector instructions",
	.pme_long_desc = "flops summary vector instructions",
},
[ POWER8_PME_PM_FLUSH ] = {
	.pme_name = "PM_FLUSH",
	.pme_code = 0x400f8,
	.pme_short_desc = "Flush (any type)",
	.pme_long_desc = "Flush (any type).",
},
[ POWER8_PME_PM_FLUSH_BR_MPRED ] = {
	.pme_name = "PM_FLUSH_BR_MPRED",
	.pme_code = 0x2084,
	.pme_short_desc = "Flush caused by branch mispredict",
	.pme_long_desc = "Flush caused by branch mispredict",
},
[ POWER8_PME_PM_FLUSH_COMPLETION ] = {
	.pme_name = "PM_FLUSH_COMPLETION",
	.pme_code = 0x30012,
	.pme_short_desc = "Completion Flush",
	.pme_long_desc = "Completion Flush.",
},
[ POWER8_PME_PM_FLUSH_DISP ] = {
	.pme_name = "PM_FLUSH_DISP",
	.pme_code = 0x2082,
	.pme_short_desc = "Dispatch flush",
	.pme_long_desc = "Dispatch flush",
},
[ POWER8_PME_PM_FLUSH_DISP_SB ] = {
	.pme_name = "PM_FLUSH_DISP_SB",
	.pme_code = 0x208c,
	.pme_short_desc = "Dispatch Flush: Scoreboard",
	.pme_long_desc = "Dispatch Flush: Scoreboard",
},
[ POWER8_PME_PM_FLUSH_DISP_SYNC ] = {
	.pme_name = "PM_FLUSH_DISP_SYNC",
	.pme_code = 0x2088,
	.pme_short_desc = "Dispatch Flush: Sync",
	.pme_long_desc = "Dispatch Flush: Sync",
},
[ POWER8_PME_PM_FLUSH_DISP_TLBIE ] = {
	.pme_name = "PM_FLUSH_DISP_TLBIE",
	.pme_code = 0x208a,
	.pme_short_desc = "Dispatch Flush: TLBIE",
	.pme_long_desc = "Dispatch Flush: TLBIE",
},
[ POWER8_PME_PM_FLUSH_LSU ] = {
	.pme_name = "PM_FLUSH_LSU",
	.pme_code = 0x208e,
	.pme_short_desc = "Flush initiated by LSU",
	.pme_long_desc = "Flush initiated by LSU",
},
[ POWER8_PME_PM_FLUSH_PARTIAL ] = {
	.pme_name = "PM_FLUSH_PARTIAL",
	.pme_code = 0x2086,
	.pme_short_desc = "Partial flush",
	.pme_long_desc = "Partial flush",
},
[ POWER8_PME_PM_FPU0_FCONV ] = {
	.pme_name = "PM_FPU0_FCONV",
	.pme_code = 0xa0b0,
	.pme_short_desc = "Convert instruction executed",
	.pme_long_desc = "Convert instruction executed",
},
[ POWER8_PME_PM_FPU0_FEST ] = {
	.pme_name = "PM_FPU0_FEST",
	.pme_code = 0xa0b8,
	.pme_short_desc = "Estimate instruction executed",
	.pme_long_desc = "Estimate instruction executed",
},
[ POWER8_PME_PM_FPU0_FRSP ] = {
	.pme_name = "PM_FPU0_FRSP",
	.pme_code = 0xa0b4,
	.pme_short_desc = "Round to single precision instruction executed",
	.pme_long_desc = "Round to single precision instruction executed",
},
[ POWER8_PME_PM_FPU1_FCONV ] = {
	.pme_name = "PM_FPU1_FCONV",
	.pme_code = 0xa0b2,
	.pme_short_desc = "Convert instruction executed",
	.pme_long_desc = "Convert instruction executed",
},
[ POWER8_PME_PM_FPU1_FEST ] = {
	.pme_name = "PM_FPU1_FEST",
	.pme_code = 0xa0ba,
	.pme_short_desc = "Estimate instruction executed",
	.pme_long_desc = "Estimate instruction executed",
},
[ POWER8_PME_PM_FPU1_FRSP ] = {
	.pme_name = "PM_FPU1_FRSP",
	.pme_code = 0xa0b6,
	.pme_short_desc = "Round to single precision instruction executed",
	.pme_long_desc = "Round to single precision instruction executed",
},
[ POWER8_PME_PM_FREQ_DOWN ] = {
	.pme_name = "PM_FREQ_DOWN",
	.pme_code = 0x3000c,
	.pme_short_desc = "Power Management: Below Threshold B",
	.pme_long_desc = "Frequency is being slewed down due to Power Management.",
},
[ POWER8_PME_PM_FREQ_UP ] = {
	.pme_name = "PM_FREQ_UP",
	.pme_code = 0x4000c,
	.pme_short_desc = "Power Management: Above Threshold A",
	.pme_long_desc = "Frequency is being slewed up due to Power Management.",
},
[ POWER8_PME_PM_FUSION_TOC_GRP0_1 ] = {
	.pme_name = "PM_FUSION_TOC_GRP0_1",
	.pme_code = 0x50b0,
	.pme_short_desc = "One pair of instructions fused with TOC in Group0",
	.pme_long_desc = "One pair of instructions fused with TOC in Group0",
},
[ POWER8_PME_PM_FUSION_TOC_GRP0_2 ] = {
	.pme_name = "PM_FUSION_TOC_GRP0_2",
	.pme_code = 0x50ae,
	.pme_short_desc = "Two pairs of instructions fused with TOCin Group0",
	.pme_long_desc = "Two pairs of instructions fused with TOCin Group0",
},
[ POWER8_PME_PM_FUSION_TOC_GRP0_3 ] = {
	.pme_name = "PM_FUSION_TOC_GRP0_3",
	.pme_code = 0x50ac,
	.pme_short_desc = "Three pairs of instructions fused with TOC in Group0",
	.pme_long_desc = "Three pairs of instructions fused with TOC in Group0",
},
[ POWER8_PME_PM_FUSION_TOC_GRP1_1 ] = {
	.pme_name = "PM_FUSION_TOC_GRP1_1",
	.pme_code = 0x50b2,
	.pme_short_desc = "One pair of instructions fused with TOX in Group1",
	.pme_long_desc = "One pair of instructions fused with TOX in Group1",
},
[ POWER8_PME_PM_FUSION_VSX_GRP0_1 ] = {
	.pme_name = "PM_FUSION_VSX_GRP0_1",
	.pme_code = 0x50b8,
	.pme_short_desc = "One pair of instructions fused with VSX in Group0",
	.pme_long_desc = "One pair of instructions fused with VSX in Group0",
},
[ POWER8_PME_PM_FUSION_VSX_GRP0_2 ] = {
	.pme_name = "PM_FUSION_VSX_GRP0_2",
	.pme_code = 0x50b6,
	.pme_short_desc = "Two pairs of instructions fused with VSX in Group0",
	.pme_long_desc = "Two pairs of instructions fused with VSX in Group0",
},
[ POWER8_PME_PM_FUSION_VSX_GRP0_3 ] = {
	.pme_name = "PM_FUSION_VSX_GRP0_3",
	.pme_code = 0x50b4,
	.pme_short_desc = "Three pairs of instructions fused with VSX in Group0",
	.pme_long_desc = "Three pairs of instructions fused with VSX in Group0",
},
[ POWER8_PME_PM_FUSION_VSX_GRP1_1 ] = {
	.pme_name = "PM_FUSION_VSX_GRP1_1",
	.pme_code = 0x50ba,
	.pme_short_desc = "One pair of instructions fused with VSX in Group1",
	.pme_long_desc = "One pair of instructions fused with VSX in Group1",
},
[ POWER8_PME_PM_FXU0_BUSY_FXU1_IDLE ] = {
	.pme_name = "PM_FXU0_BUSY_FXU1_IDLE",
	.pme_code = 0x3000e,
	.pme_short_desc = "fxu0 busy and fxu1 idle",
	.pme_long_desc = "fxu0 busy and fxu1 idle.",
},
[ POWER8_PME_PM_FXU0_FIN ] = {
	.pme_name = "PM_FXU0_FIN",
	.pme_code = 0x10004,
	.pme_short_desc = "The fixed point unit Unit 0 finished an instruction. Instructions that finish may not necessary complete.",
	.pme_long_desc = "FXU0 Finished.",
},
[ POWER8_PME_PM_FXU1_BUSY_FXU0_IDLE ] = {
	.pme_name = "PM_FXU1_BUSY_FXU0_IDLE",
	.pme_code = 0x4000e,
	.pme_short_desc = "fxu0 idle and fxu1 busy.",
	.pme_long_desc = "fxu0 idle and fxu1 busy. .",
},
[ POWER8_PME_PM_FXU1_FIN ] = {
	.pme_name = "PM_FXU1_FIN",
	.pme_code = 0x40004,
	.pme_short_desc = "FXU1 Finished",
	.pme_long_desc = "FXU1 Finished.",
},
[ POWER8_PME_PM_FXU_BUSY ] = {
	.pme_name = "PM_FXU_BUSY",
	.pme_code = 0x2000e,
	.pme_short_desc = "fxu0 busy and fxu1 busy.",
	.pme_long_desc = "fxu0 busy and fxu1 busy..",
},
[ POWER8_PME_PM_FXU_IDLE ] = {
	.pme_name = "PM_FXU_IDLE",
	.pme_code = 0x1000e,
	.pme_short_desc = "fxu0 idle and fxu1 idle",
	.pme_long_desc = "fxu0 idle and fxu1 idle.",
},
[ POWER8_PME_PM_GCT_EMPTY_CYC ] = {
	.pme_name = "PM_GCT_EMPTY_CYC",
	.pme_code = 0x20008,
	.pme_short_desc = "No itags assigned either thread (GCT Empty)",
	.pme_long_desc = "No itags assigned either thread (GCT Empty).",
},
[ POWER8_PME_PM_GCT_MERGE ] = {
	.pme_name = "PM_GCT_MERGE",
	.pme_code = 0x30a4,
	.pme_short_desc = "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread",
	.pme_long_desc = "Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread",
},
[ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED ] = {
	.pme_name = "PM_GCT_NOSLOT_BR_MPRED",
	.pme_code = 0x4d01e,
	.pme_short_desc = "Gct empty for this thread due to branch mispred",
	.pme_long_desc = "Gct empty for this thread due to branch mispred.",
},
[ POWER8_PME_PM_GCT_NOSLOT_BR_MPRED_ICMISS ] = {
	.pme_name = "PM_GCT_NOSLOT_BR_MPRED_ICMISS",
	.pme_code = 0x4d01a,
	.pme_short_desc = "Gct empty for this thread due to Icache Miss and branch mispred",
	.pme_long_desc = "Gct empty for this thread due to Icache Miss and branch mispred.",
},
[ POWER8_PME_PM_GCT_NOSLOT_CYC ] = {
	.pme_name = "PM_GCT_NOSLOT_CYC",
	.pme_code = 0x100f8,
	.pme_short_desc = "No itags assigned",
	.pme_long_desc = "Pipeline empty (No itags assigned , no GCT slots used).",
},
[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_ISSQ ] = {
	.pme_name = "PM_GCT_NOSLOT_DISP_HELD_ISSQ",
	.pme_code = 0x2d01e,
	.pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full",
	.pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Issue q full.",
},
[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_MAP ] = {
	.pme_name = "PM_GCT_NOSLOT_DISP_HELD_MAP",
	.pme_code = 0x4d01c,
	.pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to Mapper full",
	.pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to Mapper full.",
},
[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_OTHER ] = {
	.pme_name = "PM_GCT_NOSLOT_DISP_HELD_OTHER",
	.pme_code = 0x2e010,
	.pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to sync",
	.pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to sync.",
},
[ POWER8_PME_PM_GCT_NOSLOT_DISP_HELD_SRQ ] = {
	.pme_name = "PM_GCT_NOSLOT_DISP_HELD_SRQ",
	.pme_code = 0x2d01c,
	.pme_short_desc = "Gct empty for this thread due to dispatch hold on this thread due to SRQ full",
	.pme_long_desc = "Gct empty for this thread due to dispatch hold on this thread due to SRQ full.",
},
[ POWER8_PME_PM_GCT_NOSLOT_IC_L3MISS ] = {
	.pme_name = "PM_GCT_NOSLOT_IC_L3MISS",
	.pme_code = 0x4e010,
	.pme_short_desc = "Gct empty for this thread due to icach l3 miss",
	.pme_long_desc = "Gct empty for this thread due to icach l3 miss.",
},
[ POWER8_PME_PM_GCT_NOSLOT_IC_MISS ] = {
	.pme_name = "PM_GCT_NOSLOT_IC_MISS",
	.pme_code = 0x2d01a,
	.pme_short_desc = "Gct empty for this thread due to Icache Miss",
	.pme_long_desc = "Gct empty for this thread due to Icache Miss.",
},
[ POWER8_PME_PM_GCT_UTIL_11_14_ENTRIES ] = {
	.pme_name = "PM_GCT_UTIL_11_14_ENTRIES",
	.pme_code = 0x20a2,
	.pme_short_desc = "GCT Utilization 11-14 entries",
	.pme_long_desc = "GCT Utilization 11-14 entries",
},
[ POWER8_PME_PM_GCT_UTIL_15_17_ENTRIES ] = {
	.pme_name = "PM_GCT_UTIL_15_17_ENTRIES",
	.pme_code = 0x20a4,
	.pme_short_desc = "GCT Utilization 15-17 entries",
	.pme_long_desc = "GCT Utilization 15-17 entries",
},
[ POWER8_PME_PM_GCT_UTIL_18_ENTRIES ] = {
	.pme_name = "PM_GCT_UTIL_18_ENTRIES",
	.pme_code = 0x20a6,
	.pme_short_desc = "GCT Utilization 18+ entries",
	.pme_long_desc = "GCT Utilization 18+ entries",
},
[ POWER8_PME_PM_GCT_UTIL_1_2_ENTRIES ] = {
	.pme_name = "PM_GCT_UTIL_1_2_ENTRIES",
	.pme_code = 0x209c,
	.pme_short_desc = "GCT Utilization 1-2 entries",
	.pme_long_desc = "GCT Utilization 1-2 entries",
},
[ POWER8_PME_PM_GCT_UTIL_3_6_ENTRIES ] = {
	.pme_name = "PM_GCT_UTIL_3_6_ENTRIES",
	.pme_code = 0x209e,
	.pme_short_desc = "GCT Utilization 3-6 entries",
	.pme_long_desc = "GCT Utilization 3-6 entries",
},
[ POWER8_PME_PM_GCT_UTIL_7_10_ENTRIES ] = {
	.pme_name = "PM_GCT_UTIL_7_10_ENTRIES",
	.pme_code = 0x20a0,
	.pme_short_desc = "GCT Utilization 7-10 entries",
	.pme_long_desc = "GCT Utilization 7-10 entries",
},
[ POWER8_PME_PM_GRP_BR_MPRED_NONSPEC ] = {
	.pme_name = "PM_GRP_BR_MPRED_NONSPEC",
	.pme_code = 0x1000a,
	.pme_short_desc = "Group experienced non-speculative branch redirect",
	.pme_long_desc = "Group experienced Non-speculative br mispredicct.",
},
[ POWER8_PME_PM_GRP_CMPL ] = {
	.pme_name = "PM_GRP_CMPL",
	.pme_code = 0x30004,
	.pme_short_desc = "group completed",
	.pme_long_desc = "group completed.",
},
[ POWER8_PME_PM_GRP_DISP ] = {
	.pme_name = "PM_GRP_DISP",
	.pme_code = 0x3000a,
	.pme_short_desc = "group dispatch",
	.pme_long_desc = "dispatch_success (Group Dispatched).",
},
[ POWER8_PME_PM_GRP_IC_MISS_NONSPEC ] = {
	.pme_name = "PM_GRP_IC_MISS_NONSPEC",
	.pme_code = 0x1000c,
	.pme_short_desc = "Group experienced non-speculative I cache miss",
	.pme_long_desc = "Group experi enced Non-specu lative I cache miss.",
},
[ POWER8_PME_PM_GRP_MRK ] = {
	.pme_name = "PM_GRP_MRK",
	.pme_code = 0x10130,
	.pme_short_desc = "Instruction Marked",
	.pme_long_desc = "Instruction marked in idu.",
},
[ POWER8_PME_PM_GRP_NON_FULL_GROUP ] = {
	.pme_name = "PM_GRP_NON_FULL_GROUP",
	.pme_code = 0x509c,
	.pme_short_desc = "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches",
	.pme_long_desc = "GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches",
},
[ POWER8_PME_PM_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_GRP_PUMP_CPRED",
	.pme_code = 0x20050,
	.pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).",
},
[ POWER8_PME_PM_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_GRP_PUMP_MPRED",
	.pme_code = 0x20052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro",
},
[ POWER8_PME_PM_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x10052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).",
},
[ POWER8_PME_PM_GRP_TERM_2ND_BRANCH ] = {
	.pme_name = "PM_GRP_TERM_2ND_BRANCH",
	.pme_code = 0x50a4,
	.pme_short_desc = "There were enough instructions in the Ibuffer, but 2nd branch ends group",
	.pme_long_desc = "There were enough instructions in the Ibuffer, but 2nd branch ends group",
},
[ POWER8_PME_PM_GRP_TERM_FPU_AFTER_BR ] = {
	.pme_name = "PM_GRP_TERM_FPU_AFTER_BR",
	.pme_code = 0x50a6,
	.pme_short_desc = "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes",
	.pme_long_desc = "There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes",
},
[ POWER8_PME_PM_GRP_TERM_NOINST ] = {
	.pme_name = "PM_GRP_TERM_NOINST",
	.pme_code = 0x509e,
	.pme_short_desc = "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer).",
	.pme_long_desc = "Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer).",
},
[ POWER8_PME_PM_GRP_TERM_OTHER ] = {
	.pme_name = "PM_GRP_TERM_OTHER",
	.pme_code = 0x50a0,
	.pme_short_desc = "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last.",
	.pme_long_desc = "There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last.",
},
[ POWER8_PME_PM_GRP_TERM_SLOT_LIMIT ] = {
	.pme_name = "PM_GRP_TERM_SLOT_LIMIT",
	.pme_code = 0x50a2,
	.pme_short_desc = "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination",
	.pme_long_desc = "There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination",
},
[ POWER8_PME_PM_HV_CYC ] = {
	.pme_name = "PM_HV_CYC",
	.pme_code = 0x2000a,
	.pme_short_desc = "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
	.pme_long_desc = "cycles in hypervisor mode .",
},
[ POWER8_PME_PM_IBUF_FULL_CYC ] = {
	.pme_name = "PM_IBUF_FULL_CYC",
	.pme_code = 0x4086,
	.pme_short_desc = "Cycles No room in ibuff",
	.pme_long_desc = "Cycles No room in ibufffully qualified transfer (if5 valid).",
},
[ POWER8_PME_PM_IC_DEMAND_CYC ] = {
	.pme_name = "PM_IC_DEMAND_CYC",
	.pme_code = 0x10018,
	.pme_short_desc = "Cycles when a demand ifetch was pending",
	.pme_long_desc = "Demand ifetch pending.",
},
[ POWER8_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
	.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
	.pme_code = 0x4098,
	.pme_short_desc = "L2 I cache demand request due to BHT redirect, branch redirect (2 bubbles 3 cycles)",
	.pme_long_desc = "L2 I cache demand request due to BHT redirect, branch redirect (2 bubbles 3 cycles)",
},
[ POWER8_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
	.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
	.pme_code = 0x409a,
	.pme_short_desc = "L2 I cache demand request due to branch Mispredict (15 cycle path)",
	.pme_long_desc = "L2 I cache demand request due to branch Mispredict (15 cycle path)",
},
[ POWER8_PME_PM_IC_DEMAND_REQ ] = {
	.pme_name = "PM_IC_DEMAND_REQ",
	.pme_code = 0x4088,
	.pme_short_desc = "Demand Instruction fetch request",
	.pme_long_desc = "Demand Instruction fetch request",
},
[ POWER8_PME_PM_IC_INVALIDATE ] = {
	.pme_name = "PM_IC_INVALIDATE",
	.pme_code = 0x508a,
	.pme_short_desc = "Ic line invalidated",
	.pme_long_desc = "Ic line invalidated",
},
[ POWER8_PME_PM_IC_PREF_CANCEL_HIT ] = {
	.pme_name = "PM_IC_PREF_CANCEL_HIT",
	.pme_code = 0x4092,
	.pme_short_desc = "Prefetch Canceled due to icache hit",
	.pme_long_desc = "Prefetch Canceled due to icache hit",
},
[ POWER8_PME_PM_IC_PREF_CANCEL_L2 ] = {
	.pme_name = "PM_IC_PREF_CANCEL_L2",
	.pme_code = 0x4094,
	.pme_short_desc = "L2 Squashed request",
	.pme_long_desc = "L2 Squashed request",
},
[ POWER8_PME_PM_IC_PREF_CANCEL_PAGE ] = {
	.pme_name = "PM_IC_PREF_CANCEL_PAGE",
	.pme_code = 0x4090,
	.pme_short_desc = "Prefetch Canceled due to page boundary",
	.pme_long_desc = "Prefetch Canceled due to page boundary",
},
[ POWER8_PME_PM_IC_PREF_REQ ] = {
	.pme_name = "PM_IC_PREF_REQ",
	.pme_code = 0x408a,
	.pme_short_desc = "Instruction prefetch requests",
	.pme_long_desc = "Instruction prefetch requests",
},
[ POWER8_PME_PM_IC_PREF_WRITE ] = {
	.pme_name = "PM_IC_PREF_WRITE",
	.pme_code = 0x408e,
	.pme_short_desc = "Instruction prefetch written into IL1",
	.pme_long_desc = "Instruction prefetch written into IL1",
},
[ POWER8_PME_PM_IC_RELOAD_PRIVATE ] = {
	.pme_name = "PM_IC_RELOAD_PRIVATE",
	.pme_code = 0x4096,
	.pme_short_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat",
	.pme_long_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv",
},
[ POWER8_PME_PM_IERAT_RELOAD ] = {
	.pme_name = "PM_IERAT_RELOAD",
	.pme_code = 0x100f6,
	.pme_short_desc = "Number of I-ERAT reloads",
	.pme_long_desc = "IERAT Reloaded (Miss).",
},
[ POWER8_PME_PM_IERAT_RELOAD_16M ] = {
	.pme_name = "PM_IERAT_RELOAD_16M",
	.pme_code = 0x4006a,
	.pme_short_desc = "IERAT Reloaded (Miss) for a 16M page",
	.pme_long_desc = "IERAT Reloaded (Miss) for a 16M page.",
},
[ POWER8_PME_PM_IERAT_RELOAD_4K ] = {
	.pme_name = "PM_IERAT_RELOAD_4K",
	.pme_code = 0x20064,
	.pme_short_desc = "IERAT Miss (Not implemented as DI on POWER6)",
	.pme_long_desc = "IERAT Reloaded (Miss) for a 4k page.",
},
[ POWER8_PME_PM_IERAT_RELOAD_64K ] = {
	.pme_name = "PM_IERAT_RELOAD_64K",
	.pme_code = 0x3006a,
	.pme_short_desc = "IERAT Reloaded (Miss) for a 64k page",
	.pme_long_desc = "IERAT Reloaded (Miss) for a 64k page.",
},
[ POWER8_PME_PM_IFETCH_THROTTLE ] = {
	.pme_name = "PM_IFETCH_THROTTLE",
	.pme_code = 0x3405e,
	.pme_short_desc = "Cycles in which Instruction fetch throttle was active",
	.pme_long_desc = "Cycles instruction fecth was throttled in IFU.",
},
[ POWER8_PME_PM_IFU_L2_TOUCH ] = {
	.pme_name = "PM_IFU_L2_TOUCH",
	.pme_code = 0x5088,
	.pme_short_desc = "L2 touch to update MRU on a line",
	.pme_long_desc = "L2 touch to update MRU on a line",
},
[ POWER8_PME_PM_INST_ALL_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_INST_ALL_CHIP_PUMP_CPRED",
	.pme_code = 0x514050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for instruction fetches and prefetches",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch",
},
[ POWER8_PME_PM_INST_ALL_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_INST_ALL_FROM_DL2L3_MOD",
	.pme_code = 0x544048,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_INST_ALL_FROM_DL2L3_SHR",
	.pme_code = 0x534048,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_DL4 ] = {
	.pme_name = "PM_INST_ALL_FROM_DL4",
	.pme_code = 0x53404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_DMEM ] = {
	.pme_name = "PM_INST_ALL_FROM_DMEM",
	.pme_code = 0x54404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L2 ] = {
	.pme_name = "PM_INST_ALL_FROM_L2",
	.pme_code = 0x514042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L21_MOD ] = {
	.pme_name = "PM_INST_ALL_FROM_L21_MOD",
	.pme_code = 0x544046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L21_SHR ] = {
	.pme_name = "PM_INST_ALL_FROM_L21_SHR",
	.pme_code = 0x534046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L2MISS ] = {
	.pme_name = "PM_INST_ALL_FROM_L2MISS",
	.pme_code = 0x51404e,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x534040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x544040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L2_MEPF ] = {
	.pme_name = "PM_INST_ALL_FROM_L2_MEPF",
	.pme_code = 0x524040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_INST_ALL_FROM_L2_NO_CONFLICT",
	.pme_code = 0x514040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L3 ] = {
	.pme_name = "PM_INST_ALL_FROM_L3",
	.pme_code = 0x544042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_INST_ALL_FROM_L31_ECO_MOD",
	.pme_code = 0x544044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_INST_ALL_FROM_L31_ECO_SHR",
	.pme_code = 0x534044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L31_MOD ] = {
	.pme_name = "PM_INST_ALL_FROM_L31_MOD",
	.pme_code = 0x524044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L31_SHR ] = {
	.pme_name = "PM_INST_ALL_FROM_L31_SHR",
	.pme_code = 0x514046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L3MISS_MOD ] = {
	.pme_name = "PM_INST_ALL_FROM_L3MISS_MOD",
	.pme_code = 0x54404e,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_INST_ALL_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x534042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L3_MEPF ] = {
	.pme_name = "PM_INST_ALL_FROM_L3_MEPF",
	.pme_code = 0x524042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_INST_ALL_FROM_L3_NO_CONFLICT",
	.pme_code = 0x514044,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_LL4 ] = {
	.pme_name = "PM_INST_ALL_FROM_LL4",
	.pme_code = 0x51404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_LMEM ] = {
	.pme_name = "PM_INST_ALL_FROM_LMEM",
	.pme_code = 0x524048,
	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_MEMORY ] = {
	.pme_name = "PM_INST_ALL_FROM_MEMORY",
	.pme_code = 0x52404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_INST_ALL_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x54404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_INST_ALL_FROM_ON_CHIP_CACHE",
	.pme_code = 0x514048,
	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_INST_ALL_FROM_RL2L3_MOD",
	.pme_code = 0x524046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_INST_ALL_FROM_RL2L3_SHR",
	.pme_code = 0x51404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_RL4 ] = {
	.pme_name = "PM_INST_ALL_FROM_RL4",
	.pme_code = 0x52404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_FROM_RMEM ] = {
	.pme_name = "PM_INST_ALL_FROM_RMEM",
	.pme_code = 0x53404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Remote) due to instruction fetches and prefetches",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1",
},
[ POWER8_PME_PM_INST_ALL_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_INST_ALL_GRP_PUMP_CPRED",
	.pme_code = 0x524050,
	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for instruction fetches and prefetches",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch",
},
[ POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_INST_ALL_GRP_PUMP_MPRED",
	.pme_code = 0x524052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for instruction fetches and prefetches",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro",
},
[ POWER8_PME_PM_INST_ALL_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_INST_ALL_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x514052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for instruction fetches and prefetches",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch",
},
[ POWER8_PME_PM_INST_ALL_PUMP_CPRED ] = {
	.pme_name = "PM_INST_ALL_PUMP_CPRED",
	.pme_code = 0x514054,
	.pme_short_desc = "Pump prediction correct. Counts across all types of pumps for instruction fetches and prefetches",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch",
},
[ POWER8_PME_PM_INST_ALL_PUMP_MPRED ] = {
	.pme_name = "PM_INST_ALL_PUMP_MPRED",
	.pme_code = 0x544052,
	.pme_short_desc = "Pump misprediction. Counts across all types of pumps for instruction fetches and prefetches",
	.pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch",
},
[ POWER8_PME_PM_INST_ALL_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_INST_ALL_SYS_PUMP_CPRED",
	.pme_code = 0x534050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for instruction fetches and prefetches",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch",
},
[ POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_INST_ALL_SYS_PUMP_MPRED",
	.pme_code = 0x534052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for instruction fetches and prefetches",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or",
},
[ POWER8_PME_PM_INST_ALL_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_INST_ALL_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x544050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for instruction fetches and prefetches",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch",
},
[ POWER8_PME_PM_INST_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_INST_CHIP_PUMP_CPRED",
	.pme_code = 0x14050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch.",
},
[ POWER8_PME_PM_INST_CMPL ] = {
	.pme_name = "PM_INST_CMPL",
	.pme_code = 0x2,
	.pme_short_desc = "Number of PowerPC Instructions that completed.",
	.pme_long_desc = "PPC Instructions Finished (completed).",
},
[ POWER8_PME_PM_INST_DISP ] = {
	.pme_name = "PM_INST_DISP",
	.pme_code = 0x200f2,
	.pme_short_desc = "PPC Dispatched",
	.pme_long_desc = "PPC Dispatched.",
},
[ POWER8_PME_PM_INST_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_INST_FROM_DL2L3_MOD",
	.pme_code = 0x44048,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_INST_FROM_DL2L3_SHR",
	.pme_code = 0x34048,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_DL4 ] = {
	.pme_name = "PM_INST_FROM_DL4",
	.pme_code = 0x3404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_DMEM ] = {
	.pme_name = "PM_INST_FROM_DMEM",
	.pme_code = 0x4404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L1 ] = {
	.pme_name = "PM_INST_FROM_L1",
	.pme_code = 0x4080,
	.pme_short_desc = "Instruction fetches from L1",
	.pme_long_desc = "Instruction fetches from L1",
},
[ POWER8_PME_PM_INST_FROM_L2 ] = {
	.pme_name = "PM_INST_FROM_L2",
	.pme_code = 0x14042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L21_MOD ] = {
	.pme_name = "PM_INST_FROM_L21_MOD",
	.pme_code = 0x44046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L21_SHR ] = {
	.pme_name = "PM_INST_FROM_L21_SHR",
	.pme_code = 0x34046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L2MISS ] = {
	.pme_name = "PM_INST_FROM_L2MISS",
	.pme_code = 0x1404e,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x34040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x44040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L2_MEPF ] = {
	.pme_name = "PM_INST_FROM_L2_MEPF",
	.pme_code = 0x24040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_INST_FROM_L2_NO_CONFLICT",
	.pme_code = 0x14040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L3 ] = {
	.pme_name = "PM_INST_FROM_L3",
	.pme_code = 0x44042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_INST_FROM_L31_ECO_MOD",
	.pme_code = 0x44044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_INST_FROM_L31_ECO_SHR",
	.pme_code = 0x34044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L31_MOD ] = {
	.pme_name = "PM_INST_FROM_L31_MOD",
	.pme_code = 0x24044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L31_SHR ] = {
	.pme_name = "PM_INST_FROM_L31_SHR",
	.pme_code = 0x14046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L3MISS ] = {
	.pme_name = "PM_INST_FROM_L3MISS",
	.pme_code = 0x300fa,
	.pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
	.pme_long_desc = "Inst from L3 miss.",
},
[ POWER8_PME_PM_INST_FROM_L3MISS_MOD ] = {
	.pme_name = "PM_INST_FROM_L3MISS_MOD",
	.pme_code = 0x4404e,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_INST_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x34042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L3_MEPF ] = {
	.pme_name = "PM_INST_FROM_L3_MEPF",
	.pme_code = 0x24042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_INST_FROM_L3_NO_CONFLICT",
	.pme_code = 0x14044,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_LL4 ] = {
	.pme_name = "PM_INST_FROM_LL4",
	.pme_code = 0x1404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_LMEM ] = {
	.pme_name = "PM_INST_FROM_LMEM",
	.pme_code = 0x24048,
	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_MEMORY ] = {
	.pme_name = "PM_INST_FROM_MEMORY",
	.pme_code = 0x2404c,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_INST_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x4404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_INST_FROM_ON_CHIP_CACHE",
	.pme_code = 0x14048,
	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_INST_FROM_RL2L3_MOD",
	.pme_code = 0x24046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_INST_FROM_RL2L3_SHR",
	.pme_code = 0x1404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_RL4 ] = {
	.pme_name = "PM_INST_FROM_RL4",
	.pme_code = 0x2404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_FROM_RMEM ] = {
	.pme_name = "PM_INST_FROM_RMEM",
	.pme_code = 0x3404a,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Remote) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 .",
},
[ POWER8_PME_PM_INST_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_INST_GRP_PUMP_CPRED",
	.pme_code = 0x24050,
	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch.",
},
[ POWER8_PME_PM_INST_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_INST_GRP_PUMP_MPRED",
	.pme_code = 0x24052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro",
},
[ POWER8_PME_PM_INST_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_INST_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x14052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
	.pme_long_desc = "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch.",
},
[ POWER8_PME_PM_INST_IMC_MATCH_CMPL ] = {
	.pme_name = "PM_INST_IMC_MATCH_CMPL",
	.pme_code = 0x1003a,
	.pme_short_desc = "IMC Match Count (Not architected in P8)",
	.pme_long_desc = "IMC Match Count.",
},
[ POWER8_PME_PM_INST_IMC_MATCH_DISP ] = {
	.pme_name = "PM_INST_IMC_MATCH_DISP",
	.pme_code = 0x30016,
	.pme_short_desc = "Matched Instructions Dispatched",
	.pme_long_desc = "IMC Matches dispatched.",
},
[ POWER8_PME_PM_INST_PUMP_CPRED ] = {
	.pme_name = "PM_INST_PUMP_CPRED",
	.pme_code = 0x14054,
	.pme_short_desc = "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch.",
},
[ POWER8_PME_PM_INST_PUMP_MPRED ] = {
	.pme_name = "PM_INST_PUMP_MPRED",
	.pme_code = 0x44052,
	.pme_short_desc = "Pump misprediction. Counts across all types of pumps for an instruction fetch",
	.pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch.",
},
[ POWER8_PME_PM_INST_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_INST_SYS_PUMP_CPRED",
	.pme_code = 0x34050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch.",
},
[ POWER8_PME_PM_INST_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_INST_SYS_PUMP_MPRED",
	.pme_code = 0x34052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or",
},
[ POWER8_PME_PM_INST_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_INST_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x44050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch.",
},
[ POWER8_PME_PM_IOPS_CMPL ] = {
	.pme_name = "PM_IOPS_CMPL",
	.pme_code = 0x10014,
	.pme_short_desc = "Internal Operations completed",
	.pme_long_desc = "IOPS Completed.",
},
[ POWER8_PME_PM_IOPS_DISP ] = {
	.pme_name = "PM_IOPS_DISP",
	.pme_code = 0x30014,
	.pme_short_desc = "Internal Operations dispatched",
	.pme_long_desc = "IOPS dispatched.",
},
[ POWER8_PME_PM_IPTEG_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_DL2L3_MOD",
	.pme_code = 0x45048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_DL2L3_SHR",
	.pme_code = 0x35048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_DL4 ] = {
	.pme_name = "PM_IPTEG_FROM_DL4",
	.pme_code = 0x3504c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_DMEM ] = {
	.pme_name = "PM_IPTEG_FROM_DMEM",
	.pme_code = 0x4504c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L2 ] = {
	.pme_name = "PM_IPTEG_FROM_L2",
	.pme_code = 0x15042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L21_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_L21_MOD",
	.pme_code = 0x45046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L21_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_L21_SHR",
	.pme_code = 0x35046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L2MISS ] = {
	.pme_name = "PM_IPTEG_FROM_L2MISS",
	.pme_code = 0x1504e,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x35040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x45040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L2_MEPF ] = {
	.pme_name = "PM_IPTEG_FROM_L2_MEPF",
	.pme_code = 0x25040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_IPTEG_FROM_L2_NO_CONFLICT",
	.pme_code = 0x15040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L3 ] = {
	.pme_name = "PM_IPTEG_FROM_L3",
	.pme_code = 0x45042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_L31_ECO_MOD",
	.pme_code = 0x45044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_L31_ECO_SHR",
	.pme_code = 0x35044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L31_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_L31_MOD",
	.pme_code = 0x25044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L31_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_L31_SHR",
	.pme_code = 0x15046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L3MISS ] = {
	.pme_name = "PM_IPTEG_FROM_L3MISS",
	.pme_code = 0x4504e,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x35042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L3_MEPF ] = {
	.pme_name = "PM_IPTEG_FROM_L3_MEPF",
	.pme_code = 0x25042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_IPTEG_FROM_L3_NO_CONFLICT",
	.pme_code = 0x15044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_LL4 ] = {
	.pme_name = "PM_IPTEG_FROM_LL4",
	.pme_code = 0x1504c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_LMEM ] = {
	.pme_name = "PM_IPTEG_FROM_LMEM",
	.pme_code = 0x25048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_MEMORY ] = {
	.pme_name = "PM_IPTEG_FROM_MEMORY",
	.pme_code = 0x2504c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_IPTEG_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x4504a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_IPTEG_FROM_ON_CHIP_CACHE",
	.pme_code = 0x15048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_RL2L3_MOD",
	.pme_code = 0x25046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_RL2L3_SHR",
	.pme_code = 0x1504a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_RL4 ] = {
	.pme_name = "PM_IPTEG_FROM_RL4",
	.pme_code = 0x2504a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group (Remote) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group (Remote) due to a instruction side request.",
},
[ POWER8_PME_PM_IPTEG_FROM_RMEM ] = {
	.pme_name = "PM_IPTEG_FROM_RMEM",
	.pme_code = 0x3504a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Remote) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Remote) due to a instruction side request.",
},
[ POWER8_PME_PM_ISIDE_DISP ] = {
	.pme_name = "PM_ISIDE_DISP",
	.pme_code = 0x617082,
	.pme_short_desc = "All i-side dispatch attempts",
	.pme_long_desc = "All i-side dispatch attempts",
},
[ POWER8_PME_PM_ISIDE_DISP_FAIL ] = {
	.pme_name = "PM_ISIDE_DISP_FAIL",
	.pme_code = 0x627084,
	.pme_short_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine",
	.pme_long_desc = "All i-side dispatch attempts that failed due to a addr collision with another machine",
},
[ POWER8_PME_PM_ISIDE_DISP_FAIL_OTHER ] = {
	.pme_name = "PM_ISIDE_DISP_FAIL_OTHER",
	.pme_code = 0x627086,
	.pme_short_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision",
	.pme_long_desc = "All i-side dispatch attempts that failed due to a reason other than addrs collision",
},
[ POWER8_PME_PM_ISIDE_L2MEMACC ] = {
	.pme_name = "PM_ISIDE_L2MEMACC",
	.pme_code = 0x4608e,
	.pme_short_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)",
	.pme_long_desc = "valid when first beat of data comes in for an i-side fetch where data came from mem(or L4)",
},
[ POWER8_PME_PM_ISIDE_MRU_TOUCH ] = {
	.pme_name = "PM_ISIDE_MRU_TOUCH",
	.pme_code = 0x44608e,
	.pme_short_desc = "Iside L2 MRU touch",
	.pme_long_desc = "Iside L2 MRU touch",
},
[ POWER8_PME_PM_ISLB_MISS ] = {
	.pme_name = "PM_ISLB_MISS",
	.pme_code = 0xd096,
	.pme_short_desc = "I SLB Miss.",
	.pme_long_desc = "I SLB Miss.",
},
[ POWER8_PME_PM_ISU_REF_FX0 ] = {
	.pme_name = "PM_ISU_REF_FX0",
	.pme_code = 0x30ac,
	.pme_short_desc = "FX0 ISU reject",
	.pme_long_desc = "FX0 ISU reject",
},
[ POWER8_PME_PM_ISU_REF_FX1 ] = {
	.pme_name = "PM_ISU_REF_FX1",
	.pme_code = 0x30ae,
	.pme_short_desc = "FX1 ISU reject",
	.pme_long_desc = "FX1 ISU reject",
},
[ POWER8_PME_PM_ISU_REF_FXU ] = {
	.pme_name = "PM_ISU_REF_FXU",
	.pme_code = 0x38ac,
	.pme_short_desc = "FXU ISU reject from either pipe",
	.pme_long_desc = "ISU",
},
[ POWER8_PME_PM_ISU_REF_LS0 ] = {
	.pme_name = "PM_ISU_REF_LS0",
	.pme_code = 0x30b0,
	.pme_short_desc = "LS0 ISU reject",
	.pme_long_desc = "LS0 ISU reject",
},
[ POWER8_PME_PM_ISU_REF_LS1 ] = {
	.pme_name = "PM_ISU_REF_LS1",
	.pme_code = 0x30b2,
	.pme_short_desc = "LS1 ISU reject",
	.pme_long_desc = "LS1 ISU reject",
},
[ POWER8_PME_PM_ISU_REF_LS2 ] = {
	.pme_name = "PM_ISU_REF_LS2",
	.pme_code = 0x30b4,
	.pme_short_desc = "LS2 ISU reject",
	.pme_long_desc = "LS2 ISU reject",
},
[ POWER8_PME_PM_ISU_REF_LS3 ] = {
	.pme_name = "PM_ISU_REF_LS3",
	.pme_code = 0x30b6,
	.pme_short_desc = "LS3 ISU reject",
	.pme_long_desc = "LS3 ISU reject",
},
[ POWER8_PME_PM_ISU_REJECTS_ALL ] = {
	.pme_name = "PM_ISU_REJECTS_ALL",
	.pme_code = 0x309c,
	.pme_short_desc = "All isu rejects could be more than 1 per cycle",
	.pme_long_desc = "All isu rejects could be more than 1 per cycle",
},
[ POWER8_PME_PM_ISU_REJECT_RES_NA ] = {
	.pme_name = "PM_ISU_REJECT_RES_NA",
	.pme_code = 0x30a2,
	.pme_short_desc = "ISU reject due to resource not available",
	.pme_long_desc = "ISU reject due to resource not available",
},
[ POWER8_PME_PM_ISU_REJECT_SAR_BYPASS ] = {
	.pme_name = "PM_ISU_REJECT_SAR_BYPASS",
	.pme_code = 0x309e,
	.pme_short_desc = "Reject because of SAR bypass",
	.pme_long_desc = "Reject because of SAR bypass",
},
[ POWER8_PME_PM_ISU_REJECT_SRC_NA ] = {
	.pme_name = "PM_ISU_REJECT_SRC_NA",
	.pme_code = 0x30a0,
	.pme_short_desc = "ISU reject due to source not available",
	.pme_long_desc = "ISU reject due to source not available",
},
[ POWER8_PME_PM_ISU_REJ_VS0 ] = {
	.pme_name = "PM_ISU_REJ_VS0",
	.pme_code = 0x30a8,
	.pme_short_desc = "VS0 ISU reject",
	.pme_long_desc = "VS0 ISU reject",
},
[ POWER8_PME_PM_ISU_REJ_VS1 ] = {
	.pme_name = "PM_ISU_REJ_VS1",
	.pme_code = 0x30aa,
	.pme_short_desc = "VS1 ISU reject",
	.pme_long_desc = "VS1 ISU reject",
},
[ POWER8_PME_PM_ISU_REJ_VSU ] = {
	.pme_name = "PM_ISU_REJ_VSU",
	.pme_code = 0x38a8,
	.pme_short_desc = "VSU ISU reject from either pipe",
	.pme_long_desc = "ISU",
},
[ POWER8_PME_PM_ISYNC ] = {
	.pme_name = "PM_ISYNC",
	.pme_code = 0x30b8,
	.pme_short_desc = "Isync count per thread",
	.pme_long_desc = "Isync count per thread",
},
[ POWER8_PME_PM_ITLB_MISS ] = {
	.pme_name = "PM_ITLB_MISS",
	.pme_code = 0x400fc,
	.pme_short_desc = "ITLB Reloaded (always zero on POWER6)",
	.pme_long_desc = "ITLB Reloaded.",
},
[ POWER8_PME_PM_L1MISS_LAT_EXC_1024 ] = {
	.pme_name = "PM_L1MISS_LAT_EXC_1024",
	.pme_code = 0x67200301eaull,
	.pme_short_desc = "L1 misses that took longer than 1024 cyles to resolve (miss to reload)",
	.pme_long_desc = "Reload latency exceeded 1024 cyc",
},
[ POWER8_PME_PM_L1MISS_LAT_EXC_2048 ] = {
	.pme_name = "PM_L1MISS_LAT_EXC_2048",
	.pme_code = 0x67200401ecull,
	.pme_short_desc = "L1 misses that took longer than 2048 cyles to resolve (miss to reload)",
	.pme_long_desc = "Reload latency exceeded 2048 cyc",
},
[ POWER8_PME_PM_L1MISS_LAT_EXC_256 ] = {
	.pme_name = "PM_L1MISS_LAT_EXC_256",
	.pme_code = 0x67200101e8ull,
	.pme_short_desc = "L1 misses that took longer than 256 cyles to resolve (miss to reload)",
	.pme_long_desc = "Reload latency exceeded 256 cyc",
},
[ POWER8_PME_PM_L1MISS_LAT_EXC_32 ] = {
	.pme_name = "PM_L1MISS_LAT_EXC_32",
	.pme_code = 0x67200201e6ull,
	.pme_short_desc = "L1 misses that took longer than 32 cyles to resolve (miss to reload)",
	.pme_long_desc = "Reload latency exceeded 32 cyc",
},
[ POWER8_PME_PM_L1PF_L2MEMACC ] = {
	.pme_name = "PM_L1PF_L2MEMACC",
	.pme_code = 0x26086,
	.pme_short_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)",
	.pme_long_desc = "valid when first beat of data comes in for an L1pref where data came from mem(or L4)",
},
[ POWER8_PME_PM_L1_DCACHE_RELOADED_ALL ] = {
	.pme_name = "PM_L1_DCACHE_RELOADED_ALL",
	.pme_code = 0x1002c,
	.pme_short_desc = "L1 data cache reloaded for demand or prefetch",
	.pme_long_desc = "L1 data cache reloaded for demand or prefetch .",
},
[ POWER8_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
	.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
	.pme_code = 0x300f6,
	.pme_short_desc = "DL1 reloaded due to Demand Load",
	.pme_long_desc = "DL1 reloaded due to Demand Load .",
},
[ POWER8_PME_PM_L1_DEMAND_WRITE ] = {
	.pme_name = "PM_L1_DEMAND_WRITE",
	.pme_code = 0x408c,
	.pme_short_desc = "Instruction Demand sectors wriittent into IL1",
	.pme_long_desc = "Instruction Demand sectors wriittent into IL1",
},
[ POWER8_PME_PM_L1_ICACHE_MISS ] = {
	.pme_name = "PM_L1_ICACHE_MISS",
	.pme_code = 0x200fd,
	.pme_short_desc = "Demand iCache Miss",
	.pme_long_desc = "Demand iCache Miss.",
},
[ POWER8_PME_PM_L1_ICACHE_RELOADED_ALL ] = {
	.pme_name = "PM_L1_ICACHE_RELOADED_ALL",
	.pme_code = 0x40012,
	.pme_short_desc = "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch",
	.pme_long_desc = "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch.",
},
[ POWER8_PME_PM_L1_ICACHE_RELOADED_PREF ] = {
	.pme_name = "PM_L1_ICACHE_RELOADED_PREF",
	.pme_code = 0x30068,
	.pme_short_desc = "Counts all Icache prefetch reloads (includes demand turned into prefetch)",
	.pme_long_desc = "Counts all Icache prefetch reloads (includes demand turned into prefetch).",
},
[ POWER8_PME_PM_L2_CASTOUT_MOD ] = {
	.pme_name = "PM_L2_CASTOUT_MOD",
	.pme_code = 0x417080,
	.pme_short_desc = "L2 Castouts - Modified (M, Mu, Me)",
	.pme_long_desc = "L2 Castouts - Modified (M, Mu, Me)",
},
[ POWER8_PME_PM_L2_CASTOUT_SHR ] = {
	.pme_name = "PM_L2_CASTOUT_SHR",
	.pme_code = 0x417082,
	.pme_short_desc = "L2 Castouts - Shared (T, Te, Si, S)",
	.pme_long_desc = "L2 Castouts - Shared (T, Te, Si, S)",
},
[ POWER8_PME_PM_L2_CHIP_PUMP ] = {
	.pme_name = "PM_L2_CHIP_PUMP",
	.pme_code = 0x27084,
	.pme_short_desc = "RC requests that were local on chip pump attempts",
	.pme_long_desc = "RC requests that were local on chip pump attempts",
},
[ POWER8_PME_PM_L2_DC_INV ] = {
	.pme_name = "PM_L2_DC_INV",
	.pme_code = 0x427086,
	.pme_short_desc = "Dcache invalidates from L2",
	.pme_long_desc = "Dcache invalidates from L2",
},
[ POWER8_PME_PM_L2_DISP_ALL_L2MISS ] = {
	.pme_name = "PM_L2_DISP_ALL_L2MISS",
	.pme_code = 0x44608c,
	.pme_short_desc = "All successful Ld/St dispatches for this thread that were an L2miss.",
	.pme_long_desc = "All successful Ld/St dispatches for this thread that were an L2miss.",
},
[ POWER8_PME_PM_L2_GROUP_PUMP ] = {
	.pme_name = "PM_L2_GROUP_PUMP",
	.pme_code = 0x27086,
	.pme_short_desc = "RC requests that were on Node Pump attempts",
	.pme_long_desc = "RC requests that were on Node Pump attempts",
},
[ POWER8_PME_PM_L2_GRP_GUESS_CORRECT ] = {
	.pme_name = "PM_L2_GRP_GUESS_CORRECT",
	.pme_code = 0x626084,
	.pme_short_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)",
	.pme_long_desc = "L2 guess grp and guess was correct (data intra-6chip AND ^on-chip)",
},
[ POWER8_PME_PM_L2_GRP_GUESS_WRONG ] = {
	.pme_name = "PM_L2_GRP_GUESS_WRONG",
	.pme_code = 0x626086,
	.pme_short_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)",
	.pme_long_desc = "L2 guess grp and guess was not correct (ie data on-chip OR beyond-6chip)",
},
[ POWER8_PME_PM_L2_IC_INV ] = {
	.pme_name = "PM_L2_IC_INV",
	.pme_code = 0x427084,
	.pme_short_desc = "Icache Invalidates from L2",
	.pme_long_desc = "Icache Invalidates from L2",
},
[ POWER8_PME_PM_L2_INST ] = {
	.pme_name = "PM_L2_INST",
	.pme_code = 0x436088,
	.pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
	.pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
},
[ POWER8_PME_PM_L2_INST_MISS ] = {
	.pme_name = "PM_L2_INST_MISS",
	.pme_code = 0x43608a,
	.pme_short_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)",
	.pme_long_desc = "All successful i-side dispatches that were an L2miss for this thread (excludes i_l2mru_tch reqs)",
},
[ POWER8_PME_PM_L2_LD ] = {
	.pme_name = "PM_L2_LD",
	.pme_code = 0x416080,
	.pme_short_desc = "All successful D-side Load dispatches for this thread",
	.pme_long_desc = "All successful D-side Load dispatches for this thread",
},
[ POWER8_PME_PM_L2_LD_DISP ] = {
	.pme_name = "PM_L2_LD_DISP",
	.pme_code = 0x437088,
	.pme_short_desc = "All successful load dispatches",
	.pme_long_desc = "All successful load dispatches",
},
[ POWER8_PME_PM_L2_LD_HIT ] = {
	.pme_name = "PM_L2_LD_HIT",
	.pme_code = 0x43708a,
	.pme_short_desc = "All successful load dispatches that were L2 hits",
	.pme_long_desc = "All successful load dispatches that were L2 hits",
},
[ POWER8_PME_PM_L2_LD_MISS ] = {
	.pme_name = "PM_L2_LD_MISS",
	.pme_code = 0x426084,
	.pme_short_desc = "All successful D-Side Load dispatches that were an L2miss for this thread",
	.pme_long_desc = "All successful D-Side Load dispatches that were an L2miss for this thread",
},
[ POWER8_PME_PM_L2_LOC_GUESS_CORRECT ] = {
	.pme_name = "PM_L2_LOC_GUESS_CORRECT",
	.pme_code = 0x616080,
	.pme_short_desc = "L2 guess loc and guess was correct (ie data local)",
	.pme_long_desc = "L2 guess loc and guess was correct (ie data local)",
},
[ POWER8_PME_PM_L2_LOC_GUESS_WRONG ] = {
	.pme_name = "PM_L2_LOC_GUESS_WRONG",
	.pme_code = 0x616082,
	.pme_short_desc = "L2 guess loc and guess was not correct (ie data not on chip)",
	.pme_long_desc = "L2 guess loc and guess was not correct (ie data not on chip)",
},
[ POWER8_PME_PM_L2_RCLD_DISP ] = {
	.pme_name = "PM_L2_RCLD_DISP",
	.pme_code = 0x516080,
	.pme_short_desc = "L2 RC load dispatch attempt",
	.pme_long_desc = "L2 RC load dispatch attempt",
},
[ POWER8_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = {
	.pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR",
	.pme_code = 0x516082,
	.pme_short_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
	.pme_long_desc = "L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ",
},
[ POWER8_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = {
	.pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER",
	.pme_code = 0x526084,
	.pme_short_desc = "L2 RC load dispatch attempt failed due to other reasons",
	.pme_long_desc = "L2 RC load dispatch attempt failed due to other reasons",
},
[ POWER8_PME_PM_L2_RCST_DISP ] = {
	.pme_name = "PM_L2_RCST_DISP",
	.pme_code = 0x536088,
	.pme_short_desc = "L2 RC store dispatch attempt",
	.pme_long_desc = "L2 RC store dispatch attempt",
},
[ POWER8_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = {
	.pme_name = "PM_L2_RCST_DISP_FAIL_ADDR",
	.pme_code = 0x53608a,
	.pme_short_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
	.pme_long_desc = "L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ",
},
[ POWER8_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = {
	.pme_name = "PM_L2_RCST_DISP_FAIL_OTHER",
	.pme_code = 0x54608c,
	.pme_short_desc = "L2 RC store dispatch attempt failed due to other reasons",
	.pme_long_desc = "L2 RC store dispatch attempt failed due to other reasons",
},
[ POWER8_PME_PM_L2_RC_ST_DONE ] = {
	.pme_name = "PM_L2_RC_ST_DONE",
	.pme_code = 0x537088,
	.pme_short_desc = "RC did st to line that was Tx or Sx",
	.pme_long_desc = "RC did st to line that was Tx or Sx",
},
[ POWER8_PME_PM_L2_RTY_LD ] = {
	.pme_name = "PM_L2_RTY_LD",
	.pme_code = 0x63708a,
	.pme_short_desc = "RC retries on PB for any load from core",
	.pme_long_desc = "RC retries on PB for any load from core",
},
[ POWER8_PME_PM_L2_RTY_ST ] = {
	.pme_name = "PM_L2_RTY_ST",
	.pme_code = 0x3708a,
	.pme_short_desc = "RC retries on PB for any store from core",
	.pme_long_desc = "RC retries on PB for any store from core",
},
[ POWER8_PME_PM_L2_SN_M_RD_DONE ] = {
	.pme_name = "PM_L2_SN_M_RD_DONE",
	.pme_code = 0x54708c,
	.pme_short_desc = "SNP dispatched for a read and was M",
	.pme_long_desc = "SNP dispatched for a read and was M",
},
[ POWER8_PME_PM_L2_SN_M_WR_DONE ] = {
	.pme_name = "PM_L2_SN_M_WR_DONE",
	.pme_code = 0x54708e,
	.pme_short_desc = "SNP dispatched for a write and was M",
	.pme_long_desc = "SNP dispatched for a write and was M",
},
[ POWER8_PME_PM_L2_SN_SX_I_DONE ] = {
	.pme_name = "PM_L2_SN_SX_I_DONE",
	.pme_code = 0x53708a,
	.pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix",
	.pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix",
},
[ POWER8_PME_PM_L2_ST ] = {
	.pme_name = "PM_L2_ST",
	.pme_code = 0x17080,
	.pme_short_desc = "All successful D-side store dispatches for this thread",
	.pme_long_desc = "All successful D-side store dispatches for this thread",
},
[ POWER8_PME_PM_L2_ST_DISP ] = {
	.pme_name = "PM_L2_ST_DISP",
	.pme_code = 0x44708c,
	.pme_short_desc = "All successful store dispatches",
	.pme_long_desc = "All successful store dispatches",
},
[ POWER8_PME_PM_L2_ST_HIT ] = {
	.pme_name = "PM_L2_ST_HIT",
	.pme_code = 0x44708e,
	.pme_short_desc = "All successful store dispatches that were L2Hits",
	.pme_long_desc = "All successful store dispatches that were L2Hits",
},
[ POWER8_PME_PM_L2_ST_MISS ] = {
	.pme_name = "PM_L2_ST_MISS",
	.pme_code = 0x17082,
	.pme_short_desc = "All successful D-side store dispatches for this thread that were L2 Miss",
	.pme_long_desc = "All successful D-side store dispatches for this thread that were L2 Miss",
},
[ POWER8_PME_PM_L2_SYS_GUESS_CORRECT ] = {
	.pme_name = "PM_L2_SYS_GUESS_CORRECT",
	.pme_code = 0x636088,
	.pme_short_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)",
	.pme_long_desc = "L2 guess sys and guess was correct (ie data beyond-6chip)",
},
[ POWER8_PME_PM_L2_SYS_GUESS_WRONG ] = {
	.pme_name = "PM_L2_SYS_GUESS_WRONG",
	.pme_code = 0x63608a,
	.pme_short_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)",
	.pme_long_desc = "L2 guess sys and guess was not correct (ie data ^beyond-6chip)",
},
[ POWER8_PME_PM_L2_SYS_PUMP ] = {
	.pme_name = "PM_L2_SYS_PUMP",
	.pme_code = 0x617080,
	.pme_short_desc = "RC requests that were system pump attempts",
	.pme_long_desc = "RC requests that were system pump attempts",
},
[ POWER8_PME_PM_L2_TM_REQ_ABORT ] = {
	.pme_name = "PM_L2_TM_REQ_ABORT",
	.pme_code = 0x1e05e,
	.pme_short_desc = "TM abort",
	.pme_long_desc = "TM abort.",
},
[ POWER8_PME_PM_L2_TM_ST_ABORT_SISTER ] = {
	.pme_name = "PM_L2_TM_ST_ABORT_SISTER",
	.pme_code = 0x3e05c,
	.pme_short_desc = "TM marked store abort",
	.pme_long_desc = "TM marked store abort.",
},
[ POWER8_PME_PM_L3_CINJ ] = {
	.pme_name = "PM_L3_CINJ",
	.pme_code = 0x23808a,
	.pme_short_desc = "l3 ci of cache inject",
	.pme_long_desc = "l3 ci of cache inject",
},
[ POWER8_PME_PM_L3_CI_HIT ] = {
	.pme_name = "PM_L3_CI_HIT",
	.pme_code = 0x128084,
	.pme_short_desc = "L3 Castins Hit (total count",
	.pme_long_desc = "L3 Castins Hit (total count",
},
[ POWER8_PME_PM_L3_CI_MISS ] = {
	.pme_name = "PM_L3_CI_MISS",
	.pme_code = 0x128086,
	.pme_short_desc = "L3 castins miss (total count",
	.pme_long_desc = "L3 castins miss (total count",
},
[ POWER8_PME_PM_L3_CI_USAGE ] = {
	.pme_name = "PM_L3_CI_USAGE",
	.pme_code = 0x819082,
	.pme_short_desc = "rotating sample of 16 CI or CO actives",
	.pme_long_desc = "rotating sample of 16 CI or CO actives",
},
[ POWER8_PME_PM_L3_CO ] = {
	.pme_name = "PM_L3_CO",
	.pme_code = 0x438088,
	.pme_short_desc = "l3 castout occurring (does not include casthrough or log writes (cinj/dmaw)",
	.pme_long_desc = "l3 castout occurring (does not include casthrough or log writes (cinj/dmaw)",
},
[ POWER8_PME_PM_L3_CO0_ALLOC ] = {
	.pme_name = "PM_L3_CO0_ALLOC",
	.pme_code = 0x83908b,
	.pme_short_desc = "lifetime, sample of CO machine 0 valid",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_L3_CO0_BUSY ] = {
	.pme_name = "PM_L3_CO0_BUSY",
	.pme_code = 0x83908a,
	.pme_short_desc = "lifetime, sample of CO machine 0 valid",
	.pme_long_desc = "lifetime, sample of CO machine 0 valid",
},
[ POWER8_PME_PM_L3_CO_L31 ] = {
	.pme_name = "PM_L3_CO_L31",
	.pme_code = 0x28086,
	.pme_short_desc = "L3 CO to L3.1 OR of port 0 and 1 (lossy)",
	.pme_long_desc = "L3 CO to L3.1 OR of port 0 and 1 (lossy)",
},
[ POWER8_PME_PM_L3_CO_LCO ] = {
	.pme_name = "PM_L3_CO_LCO",
	.pme_code = 0x238088,
	.pme_short_desc = "Total L3 castouts occurred on LCO",
	.pme_long_desc = "Total L3 castouts occurred on LCO",
},
[ POWER8_PME_PM_L3_CO_MEM ] = {
	.pme_name = "PM_L3_CO_MEM",
	.pme_code = 0x28084,
	.pme_short_desc = "L3 CO to memory OR of port 0 and 1 (lossy)",
	.pme_long_desc = "L3 CO to memory OR of port 0 and 1 (lossy)",
},
[ POWER8_PME_PM_L3_CO_MEPF ] = {
	.pme_name = "PM_L3_CO_MEPF",
	.pme_code = 0x18082,
	.pme_short_desc = "L3 CO of line in Mep state (includes casthrough)",
	.pme_long_desc = "L3 CO of line in Mep state (includes casthrough)",
},
[ POWER8_PME_PM_L3_GRP_GUESS_CORRECT ] = {
	.pme_name = "PM_L3_GRP_GUESS_CORRECT",
	.pme_code = 0xb19082,
	.pme_short_desc = "Initial scope=group and data from same group (near) (pred successful)",
	.pme_long_desc = "Initial scope=group and data from same group (near) (pred successful)",
},
[ POWER8_PME_PM_L3_GRP_GUESS_WRONG_HIGH ] = {
	.pme_name = "PM_L3_GRP_GUESS_WRONG_HIGH",
	.pme_code = 0xb3908a,
	.pme_short_desc = "Initial scope=group but data from local node. Predition too high",
	.pme_long_desc = "Initial scope=group but data from local node. Predition too high",
},
[ POWER8_PME_PM_L3_GRP_GUESS_WRONG_LOW ] = {
	.pme_name = "PM_L3_GRP_GUESS_WRONG_LOW",
	.pme_code = 0xb39088,
	.pme_short_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low",
	.pme_long_desc = "Initial scope=group but data from outside group (far or rem). Prediction too Low",
},
[ POWER8_PME_PM_L3_HIT ] = {
	.pme_name = "PM_L3_HIT",
	.pme_code = 0x218080,
	.pme_short_desc = "L3 Hits",
	.pme_long_desc = "L3 Hits",
},
[ POWER8_PME_PM_L3_L2_CO_HIT ] = {
	.pme_name = "PM_L3_L2_CO_HIT",
	.pme_code = 0x138088,
	.pme_short_desc = "L2 castout hits",
	.pme_long_desc = "L2 castout hits",
},
[ POWER8_PME_PM_L3_L2_CO_MISS ] = {
	.pme_name = "PM_L3_L2_CO_MISS",
	.pme_code = 0x13808a,
	.pme_short_desc = "L2 castout miss",
	.pme_long_desc = "L2 castout miss",
},
[ POWER8_PME_PM_L3_LAT_CI_HIT ] = {
	.pme_name = "PM_L3_LAT_CI_HIT",
	.pme_code = 0x14808c,
	.pme_short_desc = "L3 Lateral Castins Hit",
	.pme_long_desc = "L3 Lateral Castins Hit",
},
[ POWER8_PME_PM_L3_LAT_CI_MISS ] = {
	.pme_name = "PM_L3_LAT_CI_MISS",
	.pme_code = 0x14808e,
	.pme_short_desc = "L3 Lateral Castins Miss",
	.pme_long_desc = "L3 Lateral Castins Miss",
},
[ POWER8_PME_PM_L3_LD_HIT ] = {
	.pme_name = "PM_L3_LD_HIT",
	.pme_code = 0x228084,
	.pme_short_desc = "L3 demand LD Hits",
	.pme_long_desc = "L3 demand LD Hits",
},
[ POWER8_PME_PM_L3_LD_MISS ] = {
	.pme_name = "PM_L3_LD_MISS",
	.pme_code = 0x228086,
	.pme_short_desc = "L3 demand LD Miss",
	.pme_long_desc = "L3 demand LD Miss",
},
[ POWER8_PME_PM_L3_LD_PREF ] = {
	.pme_name = "PM_L3_LD_PREF",
	.pme_code = 0x1e052,
	.pme_short_desc = "L3 Load Prefetches",
	.pme_long_desc = "L3 Load Prefetches.",
},
[ POWER8_PME_PM_L3_LOC_GUESS_CORRECT ] = {
	.pme_name = "PM_L3_LOC_GUESS_CORRECT",
	.pme_code = 0xb19080,
	.pme_short_desc = "initial scope=node/chip and data from local node (local) (pred successful)",
	.pme_long_desc = "initial scope=node/chip and data from local node (local) (pred successful)",
},
[ POWER8_PME_PM_L3_LOC_GUESS_WRONG ] = {
	.pme_name = "PM_L3_LOC_GUESS_WRONG",
	.pme_code = 0xb29086,
	.pme_short_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low",
	.pme_long_desc = "Initial scope=node but data from out side local node (near or far or rem). Prediction too Low",
},
[ POWER8_PME_PM_L3_MISS ] = {
	.pme_name = "PM_L3_MISS",
	.pme_code = 0x218082,
	.pme_short_desc = "L3 Misses",
	.pme_long_desc = "L3 Misses",
},
[ POWER8_PME_PM_L3_P0_CO_L31 ] = {
	.pme_name = "PM_L3_P0_CO_L31",
	.pme_code = 0x54808c,
	.pme_short_desc = "l3 CO to L3.1 (lco) port 0",
	.pme_long_desc = "l3 CO to L3.1 (lco) port 0",
},
[ POWER8_PME_PM_L3_P0_CO_MEM ] = {
	.pme_name = "PM_L3_P0_CO_MEM",
	.pme_code = 0x538088,
	.pme_short_desc = "l3 CO to memory port 0",
	.pme_long_desc = "l3 CO to memory port 0",
},
[ POWER8_PME_PM_L3_P0_CO_RTY ] = {
	.pme_name = "PM_L3_P0_CO_RTY",
	.pme_code = 0x929084,
	.pme_short_desc = "L3 CO received retry port 0",
	.pme_long_desc = "L3 CO received retry port 0",
},
[ POWER8_PME_PM_L3_P0_GRP_PUMP ] = {
	.pme_name = "PM_L3_P0_GRP_PUMP",
	.pme_code = 0xa29084,
	.pme_short_desc = "L3 pf sent with grp scope port 0",
	.pme_long_desc = "L3 pf sent with grp scope port 0",
},
[ POWER8_PME_PM_L3_P0_LCO_DATA ] = {
	.pme_name = "PM_L3_P0_LCO_DATA",
	.pme_code = 0x528084,
	.pme_short_desc = "lco sent with data port 0",
	.pme_long_desc = "lco sent with data port 0",
},
[ POWER8_PME_PM_L3_P0_LCO_NO_DATA ] = {
	.pme_name = "PM_L3_P0_LCO_NO_DATA",
	.pme_code = 0x518080,
	.pme_short_desc = "dataless l3 lco sent port 0",
	.pme_long_desc = "dataless l3 lco sent port 0",
},
[ POWER8_PME_PM_L3_P0_LCO_RTY ] = {
	.pme_name = "PM_L3_P0_LCO_RTY",
	.pme_code = 0xa4908c,
	.pme_short_desc = "L3 LCO received retry port 0",
	.pme_long_desc = "L3 LCO received retry port 0",
},
[ POWER8_PME_PM_L3_P0_NODE_PUMP ] = {
	.pme_name = "PM_L3_P0_NODE_PUMP",
	.pme_code = 0xa19080,
	.pme_short_desc = "L3 pf sent with nodal scope port 0",
	.pme_long_desc = "L3 pf sent with nodal scope port 0",
},
[ POWER8_PME_PM_L3_P0_PF_RTY ] = {
	.pme_name = "PM_L3_P0_PF_RTY",
	.pme_code = 0x919080,
	.pme_short_desc = "L3 PF received retry port 0",
	.pme_long_desc = "L3 PF received retry port 0",
},
[ POWER8_PME_PM_L3_P0_SN_HIT ] = {
	.pme_name = "PM_L3_P0_SN_HIT",
	.pme_code = 0x939088,
	.pme_short_desc = "L3 snoop hit port 0",
	.pme_long_desc = "L3 snoop hit port 0",
},
[ POWER8_PME_PM_L3_P0_SN_INV ] = {
	.pme_name = "PM_L3_P0_SN_INV",
	.pme_code = 0x118080,
	.pme_short_desc = "Port0 snooper detects someone doing a store to a line that is Sx",
	.pme_long_desc = "Port0 snooper detects someone doing a store to a line that is Sx",
},
[ POWER8_PME_PM_L3_P0_SN_MISS ] = {
	.pme_name = "PM_L3_P0_SN_MISS",
	.pme_code = 0x94908c,
	.pme_short_desc = "L3 snoop miss port 0",
	.pme_long_desc = "L3 snoop miss port 0",
},
[ POWER8_PME_PM_L3_P0_SYS_PUMP ] = {
	.pme_name = "PM_L3_P0_SYS_PUMP",
	.pme_code = 0xa39088,
	.pme_short_desc = "L3 pf sent with sys scope port 0",
	.pme_long_desc = "L3 pf sent with sys scope port 0",
},
[ POWER8_PME_PM_L3_P1_CO_L31 ] = {
	.pme_name = "PM_L3_P1_CO_L31",
	.pme_code = 0x54808e,
	.pme_short_desc = "l3 CO to L3.1 (lco) port 1",
	.pme_long_desc = "l3 CO to L3.1 (lco) port 1",
},
[ POWER8_PME_PM_L3_P1_CO_MEM ] = {
	.pme_name = "PM_L3_P1_CO_MEM",
	.pme_code = 0x53808a,
	.pme_short_desc = "l3 CO to memory port 1",
	.pme_long_desc = "l3 CO to memory port 1",
},
[ POWER8_PME_PM_L3_P1_CO_RTY ] = {
	.pme_name = "PM_L3_P1_CO_RTY",
	.pme_code = 0x929086,
	.pme_short_desc = "L3 CO received retry port 1",
	.pme_long_desc = "L3 CO received retry port 1",
},
[ POWER8_PME_PM_L3_P1_GRP_PUMP ] = {
	.pme_name = "PM_L3_P1_GRP_PUMP",
	.pme_code = 0xa29086,
	.pme_short_desc = "L3 pf sent with grp scope port 1",
	.pme_long_desc = "L3 pf sent with grp scope port 1",
},
[ POWER8_PME_PM_L3_P1_LCO_DATA ] = {
	.pme_name = "PM_L3_P1_LCO_DATA",
	.pme_code = 0x528086,
	.pme_short_desc = "lco sent with data port 1",
	.pme_long_desc = "lco sent with data port 1",
},
[ POWER8_PME_PM_L3_P1_LCO_NO_DATA ] = {
	.pme_name = "PM_L3_P1_LCO_NO_DATA",
	.pme_code = 0x518082,
	.pme_short_desc = "dataless l3 lco sent port 1",
	.pme_long_desc = "dataless l3 lco sent port 1",
},
[ POWER8_PME_PM_L3_P1_LCO_RTY ] = {
	.pme_name = "PM_L3_P1_LCO_RTY",
	.pme_code = 0xa4908e,
	.pme_short_desc = "L3 LCO received retry port 1",
	.pme_long_desc = "L3 LCO received retry port 1",
},
[ POWER8_PME_PM_L3_P1_NODE_PUMP ] = {
	.pme_name = "PM_L3_P1_NODE_PUMP",
	.pme_code = 0xa19082,
	.pme_short_desc = "L3 pf sent with nodal scope port 1",
	.pme_long_desc = "L3 pf sent with nodal scope port 1",
},
[ POWER8_PME_PM_L3_P1_PF_RTY ] = {
	.pme_name = "PM_L3_P1_PF_RTY",
	.pme_code = 0x919082,
	.pme_short_desc = "L3 PF received retry port 1",
	.pme_long_desc = "L3 PF received retry port 1",
},
[ POWER8_PME_PM_L3_P1_SN_HIT ] = {
	.pme_name = "PM_L3_P1_SN_HIT",
	.pme_code = 0x93908a,
	.pme_short_desc = "L3 snoop hit port 1",
	.pme_long_desc = "L3 snoop hit port 1",
},
[ POWER8_PME_PM_L3_P1_SN_INV ] = {
	.pme_name = "PM_L3_P1_SN_INV",
	.pme_code = 0x118082,
	.pme_short_desc = "Port1 snooper detects someone doing a store to a line that is Sx",
	.pme_long_desc = "Port1 snooper detects someone doing a store to a line that is Sx",
},
[ POWER8_PME_PM_L3_P1_SN_MISS ] = {
	.pme_name = "PM_L3_P1_SN_MISS",
	.pme_code = 0x94908e,
	.pme_short_desc = "L3 snoop miss port 1",
	.pme_long_desc = "L3 snoop miss port 1",
},
[ POWER8_PME_PM_L3_P1_SYS_PUMP ] = {
	.pme_name = "PM_L3_P1_SYS_PUMP",
	.pme_code = 0xa3908a,
	.pme_short_desc = "L3 pf sent with sys scope port 1",
	.pme_long_desc = "L3 pf sent with sys scope port 1",
},
[ POWER8_PME_PM_L3_PF0_ALLOC ] = {
	.pme_name = "PM_L3_PF0_ALLOC",
	.pme_code = 0x84908d,
	.pme_short_desc = "lifetime, sample of PF machine 0 valid",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_L3_PF0_BUSY ] = {
	.pme_name = "PM_L3_PF0_BUSY",
	.pme_code = 0x84908c,
	.pme_short_desc = "lifetime, sample of PF machine 0 valid",
	.pme_long_desc = "lifetime, sample of PF machine 0 valid",
},
[ POWER8_PME_PM_L3_PF_HIT_L3 ] = {
	.pme_name = "PM_L3_PF_HIT_L3",
	.pme_code = 0x428084,
	.pme_short_desc = "l3 pf hit in l3",
	.pme_long_desc = "l3 pf hit in l3",
},
[ POWER8_PME_PM_L3_PF_MISS_L3 ] = {
	.pme_name = "PM_L3_PF_MISS_L3",
	.pme_code = 0x18080,
	.pme_short_desc = "L3 Prefetch missed in L3",
	.pme_long_desc = "L3 Prefetch missed in L3",
},
[ POWER8_PME_PM_L3_PF_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_L3_PF_OFF_CHIP_CACHE",
	.pme_code = 0x3808a,
	.pme_short_desc = "L3 Prefetch from Off chip cache",
	.pme_long_desc = "L3 Prefetch from Off chip cache",
},
[ POWER8_PME_PM_L3_PF_OFF_CHIP_MEM ] = {
	.pme_name = "PM_L3_PF_OFF_CHIP_MEM",
	.pme_code = 0x4808e,
	.pme_short_desc = "L3 Prefetch from Off chip memory",
	.pme_long_desc = "L3 Prefetch from Off chip memory",
},
[ POWER8_PME_PM_L3_PF_ON_CHIP_CACHE ] = {
	.pme_name = "PM_L3_PF_ON_CHIP_CACHE",
	.pme_code = 0x38088,
	.pme_short_desc = "L3 Prefetch from On chip cache",
	.pme_long_desc = "L3 Prefetch from On chip cache",
},
[ POWER8_PME_PM_L3_PF_ON_CHIP_MEM ] = {
	.pme_name = "PM_L3_PF_ON_CHIP_MEM",
	.pme_code = 0x4808c,
	.pme_short_desc = "L3 Prefetch from On chip memory",
	.pme_long_desc = "L3 Prefetch from On chip memory",
},
[ POWER8_PME_PM_L3_PF_USAGE ] = {
	.pme_name = "PM_L3_PF_USAGE",
	.pme_code = 0x829084,
	.pme_short_desc = "rotating sample of 32 PF actives",
	.pme_long_desc = "rotating sample of 32 PF actives",
},
[ POWER8_PME_PM_L3_PREF_ALL ] = {
	.pme_name = "PM_L3_PREF_ALL",
	.pme_code = 0x4e052,
	.pme_short_desc = "Total HW L3 prefetches(Load+store)",
	.pme_long_desc = "Total HW L3 prefetches(Load+store).",
},
[ POWER8_PME_PM_L3_RD0_ALLOC ] = {
	.pme_name = "PM_L3_RD0_ALLOC",
	.pme_code = 0x84908f,
	.pme_short_desc = "lifetime, sample of RD machine 0 valid",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_L3_RD0_BUSY ] = {
	.pme_name = "PM_L3_RD0_BUSY",
	.pme_code = 0x84908e,
	.pme_short_desc = "lifetime, sample of RD machine 0 valid",
	.pme_long_desc = "lifetime, sample of RD machine 0 valid",
},
[ POWER8_PME_PM_L3_RD_USAGE ] = {
	.pme_name = "PM_L3_RD_USAGE",
	.pme_code = 0x829086,
	.pme_short_desc = "rotating sample of 16 RD actives",
	.pme_long_desc = "rotating sample of 16 RD actives",
},
[ POWER8_PME_PM_L3_SN0_ALLOC ] = {
	.pme_name = "PM_L3_SN0_ALLOC",
	.pme_code = 0x839089,
	.pme_short_desc = "lifetime, sample of snooper machine 0 valid",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_L3_SN0_BUSY ] = {
	.pme_name = "PM_L3_SN0_BUSY",
	.pme_code = 0x839088,
	.pme_short_desc = "lifetime, sample of snooper machine 0 valid",
	.pme_long_desc = "lifetime, sample of snooper machine 0 valid",
},
[ POWER8_PME_PM_L3_SN_USAGE ] = {
	.pme_name = "PM_L3_SN_USAGE",
	.pme_code = 0x819080,
	.pme_short_desc = "rotating sample of 8 snoop valids",
	.pme_long_desc = "rotating sample of 8 snoop valids",
},
[ POWER8_PME_PM_L3_ST_PREF ] = {
	.pme_name = "PM_L3_ST_PREF",
	.pme_code = 0x2e052,
	.pme_short_desc = "L3 store Prefetches",
	.pme_long_desc = "L3 store Prefetches.",
},
[ POWER8_PME_PM_L3_SW_PREF ] = {
	.pme_name = "PM_L3_SW_PREF",
	.pme_code = 0x3e052,
	.pme_short_desc = "Data stream touchto L3",
	.pme_long_desc = "Data stream touchto L3.",
},
[ POWER8_PME_PM_L3_SYS_GUESS_CORRECT ] = {
	.pme_name = "PM_L3_SYS_GUESS_CORRECT",
	.pme_code = 0xb29084,
	.pme_short_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)",
	.pme_long_desc = "Initial scope=system and data from outside group (far or rem)(pred successful)",
},
[ POWER8_PME_PM_L3_SYS_GUESS_WRONG ] = {
	.pme_name = "PM_L3_SYS_GUESS_WRONG",
	.pme_code = 0xb4908c,
	.pme_short_desc = "Initial scope=system but data from local or near. Predction too high",
	.pme_long_desc = "Initial scope=system but data from local or near. Predction too high",
},
[ POWER8_PME_PM_L3_TRANS_PF ] = {
	.pme_name = "PM_L3_TRANS_PF",
	.pme_code = 0x24808e,
	.pme_short_desc = "L3 Transient prefetch",
	.pme_long_desc = "L3 Transient prefetch",
},
[ POWER8_PME_PM_L3_WI0_ALLOC ] = {
	.pme_name = "PM_L3_WI0_ALLOC",
	.pme_code = 0x18081,
	.pme_short_desc = "lifetime, sample of Write Inject machine 0 valid",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_L3_WI0_BUSY ] = {
	.pme_name = "PM_L3_WI0_BUSY",
	.pme_code = 0x418080,
	.pme_short_desc = "lifetime, sample of Write Inject machine 0 valid",
	.pme_long_desc = "lifetime, sample of Write Inject machine 0 valid",
},
[ POWER8_PME_PM_L3_WI_USAGE ] = {
	.pme_name = "PM_L3_WI_USAGE",
	.pme_code = 0x418082,
	.pme_short_desc = "rotating sample of 8 WI actives",
	.pme_long_desc = "rotating sample of 8 WI actives",
},
[ POWER8_PME_PM_LARX_FIN ] = {
	.pme_name = "PM_LARX_FIN",
	.pme_code = 0x3c058,
	.pme_short_desc = "Larx finished",
	.pme_long_desc = "Larx finished .",
},
[ POWER8_PME_PM_LD_CMPL ] = {
	.pme_name = "PM_LD_CMPL",
	.pme_code = 0x1002e,
	.pme_short_desc = "count of Loads completed",
	.pme_long_desc = "count of Loads completed.",
},
[ POWER8_PME_PM_LD_L3MISS_PEND_CYC ] = {
	.pme_name = "PM_LD_L3MISS_PEND_CYC",
	.pme_code = 0x10062,
	.pme_short_desc = "Cycles L3 miss was pending for this thread",
	.pme_long_desc = "Cycles L3 miss was pending for this thread.",
},
[ POWER8_PME_PM_LD_MISS_L1 ] = {
	.pme_name = "PM_LD_MISS_L1",
	.pme_code = 0x3e054,
	.pme_short_desc = "Load Missed L1",
	.pme_long_desc = "Load Missed L1.",
},
[ POWER8_PME_PM_LD_REF_L1 ] = {
	.pme_name = "PM_LD_REF_L1",
	.pme_code = 0x100ee,
	.pme_short_desc = "All L1 D cache load references counted at finish, gated by reject",
	.pme_long_desc = "Load Ref count combined for all units.",
},
[ POWER8_PME_PM_LD_REF_L1_LSU0 ] = {
	.pme_name = "PM_LD_REF_L1_LSU0",
	.pme_code = 0xc080,
	.pme_short_desc = "LS0 L1 D cache load references counted at finish, gated by reject",
	.pme_long_desc = "LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references",
},
[ POWER8_PME_PM_LD_REF_L1_LSU1 ] = {
	.pme_name = "PM_LD_REF_L1_LSU1",
	.pme_code = 0xc082,
	.pme_short_desc = "LS1 L1 D cache load references counted at finish, gated by reject",
	.pme_long_desc = "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references",
},
[ POWER8_PME_PM_LD_REF_L1_LSU2 ] = {
	.pme_name = "PM_LD_REF_L1_LSU2",
	.pme_code = 0xc094,
	.pme_short_desc = "LS2 L1 D cache load references counted at finish, gated by reject",
	.pme_long_desc = "LS2 L1 D cache load references counted at finish, gated by reject42",
},
[ POWER8_PME_PM_LD_REF_L1_LSU3 ] = {
	.pme_name = "PM_LD_REF_L1_LSU3",
	.pme_code = 0xc096,
	.pme_short_desc = "LS3 L1 D cache load references counted at finish, gated by reject",
	.pme_long_desc = "LS3 L1 D cache load references counted at finish, gated by reject42",
},
[ POWER8_PME_PM_LINK_STACK_INVALID_PTR ] = {
	.pme_name = "PM_LINK_STACK_INVALID_PTR",
	.pme_code = 0x509a,
	.pme_short_desc = "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops",
	.pme_long_desc = "A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops",
},
[ POWER8_PME_PM_LINK_STACK_WRONG_ADD_PRED ] = {
	.pme_name = "PM_LINK_STACK_WRONG_ADD_PRED",
	.pme_code = 0x5098,
	.pme_short_desc = "Link stack predicts wrong address, because of link stack design limitation.",
	.pme_long_desc = "Link stack predicts wrong address, because of link stack design limitation.",
},
[ POWER8_PME_PM_LS0_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LS0_ERAT_MISS_PREF",
	.pme_code = 0xe080,
	.pme_short_desc = "LS0 Erat miss due to prefetch",
	.pme_long_desc = "LS0 Erat miss due to prefetch42",
},
[ POWER8_PME_PM_LS0_L1_PREF ] = {
	.pme_name = "PM_LS0_L1_PREF",
	.pme_code = 0xd0b8,
	.pme_short_desc = "LS0 L1 cache data prefetches",
	.pme_long_desc = "LS0 L1 cache data prefetches42",
},
[ POWER8_PME_PM_LS0_L1_SW_PREF ] = {
	.pme_name = "PM_LS0_L1_SW_PREF",
	.pme_code = 0xc098,
	.pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches",
	.pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches42",
},
[ POWER8_PME_PM_LS1_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LS1_ERAT_MISS_PREF",
	.pme_code = 0xe082,
	.pme_short_desc = "LS1 Erat miss due to prefetch",
	.pme_long_desc = "LS1 Erat miss due to prefetch42",
},
[ POWER8_PME_PM_LS1_L1_PREF ] = {
	.pme_name = "PM_LS1_L1_PREF",
	.pme_code = 0xd0ba,
	.pme_short_desc = "LS1 L1 cache data prefetches",
	.pme_long_desc = "LS1 L1 cache data prefetches42",
},
[ POWER8_PME_PM_LS1_L1_SW_PREF ] = {
	.pme_name = "PM_LS1_L1_SW_PREF",
	.pme_code = 0xc09a,
	.pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches",
	.pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches42",
},
[ POWER8_PME_PM_LSU0_FLUSH_LRQ ] = {
	.pme_name = "PM_LSU0_FLUSH_LRQ",
	.pme_code = 0xc0b0,
	.pme_short_desc = "LS0 Flush: LRQ",
	.pme_long_desc = "LS0 Flush: LRQLSU0 LRQ flushes",
},
[ POWER8_PME_PM_LSU0_FLUSH_SRQ ] = {
	.pme_name = "PM_LSU0_FLUSH_SRQ",
	.pme_code = 0xc0b8,
	.pme_short_desc = "LS0 Flush: SRQ",
	.pme_long_desc = "LS0 Flush: SRQLSU0 SRQ lhs flushes",
},
[ POWER8_PME_PM_LSU0_FLUSH_ULD ] = {
	.pme_name = "PM_LSU0_FLUSH_ULD",
	.pme_code = 0xc0a4,
	.pme_short_desc = "LS0 Flush: Unaligned Load",
	.pme_long_desc = "LS0 Flush: Unaligned LoadLSU0 unaligned load flushes",
},
[ POWER8_PME_PM_LSU0_FLUSH_UST ] = {
	.pme_name = "PM_LSU0_FLUSH_UST",
	.pme_code = 0xc0ac,
	.pme_short_desc = "LS0 Flush: Unaligned Store",
	.pme_long_desc = "LS0 Flush: Unaligned StoreLSU0 unaligned store flushes",
},
[ POWER8_PME_PM_LSU0_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU0_L1_CAM_CANCEL",
	.pme_code = 0xf088,
	.pme_short_desc = "ls0 l1 tm cam cancel",
	.pme_long_desc = "ls0 l1 tm cam cancel42",
},
[ POWER8_PME_PM_LSU0_LARX_FIN ] = {
	.pme_name = "PM_LSU0_LARX_FIN",
	.pme_code = 0x1e056,
	.pme_short_desc = "Larx finished in LSU pipe0",
	.pme_long_desc = ".",
},
[ POWER8_PME_PM_LSU0_LMQ_LHR_MERGE ] = {
	.pme_name = "PM_LSU0_LMQ_LHR_MERGE",
	.pme_code = 0xd08c,
	.pme_short_desc = "LS0 Load Merged with another cacheline request",
	.pme_long_desc = "LS0 Load Merged with another cacheline request42",
},
[ POWER8_PME_PM_LSU0_NCLD ] = {
	.pme_name = "PM_LSU0_NCLD",
	.pme_code = 0xc08c,
	.pme_short_desc = "LS0 Non-cachable Loads counted at finish",
	.pme_long_desc = "LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads",
},
[ POWER8_PME_PM_LSU0_PRIMARY_ERAT_HIT ] = {
	.pme_name = "PM_LSU0_PRIMARY_ERAT_HIT",
	.pme_code = 0xe090,
	.pme_short_desc = "Primary ERAT hit",
	.pme_long_desc = "Primary ERAT hit42",
},
[ POWER8_PME_PM_LSU0_REJECT ] = {
	.pme_name = "PM_LSU0_REJECT",
	.pme_code = 0x1e05a,
	.pme_short_desc = "LSU0 reject",
	.pme_long_desc = "LSU0 reject .",
},
[ POWER8_PME_PM_LSU0_SRQ_STFWD ] = {
	.pme_name = "PM_LSU0_SRQ_STFWD",
	.pme_code = 0xc09c,
	.pme_short_desc = "LS0 SRQ forwarded data to a load",
	.pme_long_desc = "LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded",
},
[ POWER8_PME_PM_LSU0_STORE_REJECT ] = {
	.pme_name = "PM_LSU0_STORE_REJECT",
	.pme_code = 0xf084,
	.pme_short_desc = "ls0 store reject",
	.pme_long_desc = "ls0 store reject42",
},
[ POWER8_PME_PM_LSU0_TMA_REQ_L2 ] = {
	.pme_name = "PM_LSU0_TMA_REQ_L2",
	.pme_code = 0xe0a8,
	.pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
	.pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42",
},
[ POWER8_PME_PM_LSU0_TM_L1_HIT ] = {
	.pme_name = "PM_LSU0_TM_L1_HIT",
	.pme_code = 0xe098,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L142",
},
[ POWER8_PME_PM_LSU0_TM_L1_MISS ] = {
	.pme_name = "PM_LSU0_TM_L1_MISS",
	.pme_code = 0xe0a0,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss42",
},
[ POWER8_PME_PM_LSU1_FLUSH_LRQ ] = {
	.pme_name = "PM_LSU1_FLUSH_LRQ",
	.pme_code = 0xc0b2,
	.pme_short_desc = "LS1 Flush: LRQ",
	.pme_long_desc = "LS1 Flush: LRQLSU1 LRQ flushes",
},
[ POWER8_PME_PM_LSU1_FLUSH_SRQ ] = {
	.pme_name = "PM_LSU1_FLUSH_SRQ",
	.pme_code = 0xc0ba,
	.pme_short_desc = "LS1 Flush: SRQ",
	.pme_long_desc = "LS1 Flush: SRQLSU1 SRQ lhs flushes",
},
[ POWER8_PME_PM_LSU1_FLUSH_ULD ] = {
	.pme_name = "PM_LSU1_FLUSH_ULD",
	.pme_code = 0xc0a6,
	.pme_short_desc = "LS 1 Flush: Unaligned Load",
	.pme_long_desc = "LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes",
},
[ POWER8_PME_PM_LSU1_FLUSH_UST ] = {
	.pme_name = "PM_LSU1_FLUSH_UST",
	.pme_code = 0xc0ae,
	.pme_short_desc = "LS1 Flush: Unaligned Store",
	.pme_long_desc = "LS1 Flush: Unaligned StoreLSU1 unaligned store flushes",
},
[ POWER8_PME_PM_LSU1_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU1_L1_CAM_CANCEL",
	.pme_code = 0xf08a,
	.pme_short_desc = "ls1 l1 tm cam cancel",
	.pme_long_desc = "ls1 l1 tm cam cancel42",
},
[ POWER8_PME_PM_LSU1_LARX_FIN ] = {
	.pme_name = "PM_LSU1_LARX_FIN",
	.pme_code = 0x2e056,
	.pme_short_desc = "Larx finished in LSU pipe1",
	.pme_long_desc = "Larx finished in LSU pipe1.",
},
[ POWER8_PME_PM_LSU1_LMQ_LHR_MERGE ] = {
	.pme_name = "PM_LSU1_LMQ_LHR_MERGE",
	.pme_code = 0xd08e,
	.pme_short_desc = "LS1 Load Merge with another cacheline request",
	.pme_long_desc = "LS1 Load Merge with another cacheline request42",
},
[ POWER8_PME_PM_LSU1_NCLD ] = {
	.pme_name = "PM_LSU1_NCLD",
	.pme_code = 0xc08e,
	.pme_short_desc = "LS1 Non-cachable Loads counted at finish",
	.pme_long_desc = "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads",
},
[ POWER8_PME_PM_LSU1_PRIMARY_ERAT_HIT ] = {
	.pme_name = "PM_LSU1_PRIMARY_ERAT_HIT",
	.pme_code = 0xe092,
	.pme_short_desc = "Primary ERAT hit",
	.pme_long_desc = "Primary ERAT hit42",
},
[ POWER8_PME_PM_LSU1_REJECT ] = {
	.pme_name = "PM_LSU1_REJECT",
	.pme_code = 0x2e05a,
	.pme_short_desc = "LSU1 reject",
	.pme_long_desc = "LSU1 reject .",
},
[ POWER8_PME_PM_LSU1_SRQ_STFWD ] = {
	.pme_name = "PM_LSU1_SRQ_STFWD",
	.pme_code = 0xc09e,
	.pme_short_desc = "LS1 SRQ forwarded data to a load",
	.pme_long_desc = "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded",
},
[ POWER8_PME_PM_LSU1_STORE_REJECT ] = {
	.pme_name = "PM_LSU1_STORE_REJECT",
	.pme_code = 0xf086,
	.pme_short_desc = "ls1 store reject",
	.pme_long_desc = "ls1 store reject42",
},
[ POWER8_PME_PM_LSU1_TMA_REQ_L2 ] = {
	.pme_name = "PM_LSU1_TMA_REQ_L2",
	.pme_code = 0xe0aa,
	.pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
	.pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42",
},
[ POWER8_PME_PM_LSU1_TM_L1_HIT ] = {
	.pme_name = "PM_LSU1_TM_L1_HIT",
	.pme_code = 0xe09a,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L142",
},
[ POWER8_PME_PM_LSU1_TM_L1_MISS ] = {
	.pme_name = "PM_LSU1_TM_L1_MISS",
	.pme_code = 0xe0a2,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss42",
},
[ POWER8_PME_PM_LSU2_FLUSH_LRQ ] = {
	.pme_name = "PM_LSU2_FLUSH_LRQ",
	.pme_code = 0xc0b4,
	.pme_short_desc = "LS02Flush: LRQ",
	.pme_long_desc = "LS02Flush: LRQ42",
},
[ POWER8_PME_PM_LSU2_FLUSH_SRQ ] = {
	.pme_name = "PM_LSU2_FLUSH_SRQ",
	.pme_code = 0xc0bc,
	.pme_short_desc = "LS2 Flush: SRQ",
	.pme_long_desc = "LS2 Flush: SRQ42",
},
[ POWER8_PME_PM_LSU2_FLUSH_ULD ] = {
	.pme_name = "PM_LSU2_FLUSH_ULD",
	.pme_code = 0xc0a8,
	.pme_short_desc = "LS3 Flush: Unaligned Load",
	.pme_long_desc = "LS3 Flush: Unaligned Load42",
},
[ POWER8_PME_PM_LSU2_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU2_L1_CAM_CANCEL",
	.pme_code = 0xf08c,
	.pme_short_desc = "ls2 l1 tm cam cancel",
	.pme_long_desc = "ls2 l1 tm cam cancel42",
},
[ POWER8_PME_PM_LSU2_LARX_FIN ] = {
	.pme_name = "PM_LSU2_LARX_FIN",
	.pme_code = 0x3e056,
	.pme_short_desc = "Larx finished in LSU pipe2",
	.pme_long_desc = "Larx finished in LSU pipe2.",
},
[ POWER8_PME_PM_LSU2_LDF ] = {
	.pme_name = "PM_LSU2_LDF",
	.pme_code = 0xc084,
	.pme_short_desc = "LS2 Scalar Loads",
	.pme_long_desc = "LS2 Scalar Loads42",
},
[ POWER8_PME_PM_LSU2_LDX ] = {
	.pme_name = "PM_LSU2_LDX",
	.pme_code = 0xc088,
	.pme_short_desc = "LS0 Vector Loads",
	.pme_long_desc = "LS0 Vector Loads42",
},
[ POWER8_PME_PM_LSU2_LMQ_LHR_MERGE ] = {
	.pme_name = "PM_LSU2_LMQ_LHR_MERGE",
	.pme_code = 0xd090,
	.pme_short_desc = "LS0 Load Merged with another cacheline request",
	.pme_long_desc = "LS0 Load Merged with another cacheline request42",
},
[ POWER8_PME_PM_LSU2_PRIMARY_ERAT_HIT ] = {
	.pme_name = "PM_LSU2_PRIMARY_ERAT_HIT",
	.pme_code = 0xe094,
	.pme_short_desc = "Primary ERAT hit",
	.pme_long_desc = "Primary ERAT hit42",
},
[ POWER8_PME_PM_LSU2_REJECT ] = {
	.pme_name = "PM_LSU2_REJECT",
	.pme_code = 0x3e05a,
	.pme_short_desc = "LSU2 reject",
	.pme_long_desc = "LSU2 reject .",
},
[ POWER8_PME_PM_LSU2_SRQ_STFWD ] = {
	.pme_name = "PM_LSU2_SRQ_STFWD",
	.pme_code = 0xc0a0,
	.pme_short_desc = "LS2 SRQ forwarded data to a load",
	.pme_long_desc = "LS2 SRQ forwarded data to a load42",
},
[ POWER8_PME_PM_LSU2_TMA_REQ_L2 ] = {
	.pme_name = "PM_LSU2_TMA_REQ_L2",
	.pme_code = 0xe0ac,
	.pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
	.pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42",
},
[ POWER8_PME_PM_LSU2_TM_L1_HIT ] = {
	.pme_name = "PM_LSU2_TM_L1_HIT",
	.pme_code = 0xe09c,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L142",
},
[ POWER8_PME_PM_LSU2_TM_L1_MISS ] = {
	.pme_name = "PM_LSU2_TM_L1_MISS",
	.pme_code = 0xe0a4,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss42",
},
[ POWER8_PME_PM_LSU3_FLUSH_LRQ ] = {
	.pme_name = "PM_LSU3_FLUSH_LRQ",
	.pme_code = 0xc0b6,
	.pme_short_desc = "LS3 Flush: LRQ",
	.pme_long_desc = "LS3 Flush: LRQ42",
},
[ POWER8_PME_PM_LSU3_FLUSH_SRQ ] = {
	.pme_name = "PM_LSU3_FLUSH_SRQ",
	.pme_code = 0xc0be,
	.pme_short_desc = "LS13 Flush: SRQ",
	.pme_long_desc = "LS13 Flush: SRQ42",
},
[ POWER8_PME_PM_LSU3_FLUSH_ULD ] = {
	.pme_name = "PM_LSU3_FLUSH_ULD",
	.pme_code = 0xc0aa,
	.pme_short_desc = "LS 14Flush: Unaligned Load",
	.pme_long_desc = "LS 14Flush: Unaligned Load42",
},
[ POWER8_PME_PM_LSU3_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU3_L1_CAM_CANCEL",
	.pme_code = 0xf08e,
	.pme_short_desc = "ls3 l1 tm cam cancel",
	.pme_long_desc = "ls3 l1 tm cam cancel42",
},
[ POWER8_PME_PM_LSU3_LARX_FIN ] = {
	.pme_name = "PM_LSU3_LARX_FIN",
	.pme_code = 0x4e056,
	.pme_short_desc = "Larx finished in LSU pipe3",
	.pme_long_desc = "Larx finished in LSU pipe3.",
},
[ POWER8_PME_PM_LSU3_LDF ] = {
	.pme_name = "PM_LSU3_LDF",
	.pme_code = 0xc086,
	.pme_short_desc = "LS3 Scalar Loads",
	.pme_long_desc = "LS3 Scalar Loads 42",
},
[ POWER8_PME_PM_LSU3_LDX ] = {
	.pme_name = "PM_LSU3_LDX",
	.pme_code = 0xc08a,
	.pme_short_desc = "LS1 Vector Loads",
	.pme_long_desc = "LS1 Vector Loads42",
},
[ POWER8_PME_PM_LSU3_LMQ_LHR_MERGE ] = {
	.pme_name = "PM_LSU3_LMQ_LHR_MERGE",
	.pme_code = 0xd092,
	.pme_short_desc = "LS1 Load Merge with another cacheline request",
	.pme_long_desc = "LS1 Load Merge with another cacheline request42",
},
[ POWER8_PME_PM_LSU3_PRIMARY_ERAT_HIT ] = {
	.pme_name = "PM_LSU3_PRIMARY_ERAT_HIT",
	.pme_code = 0xe096,
	.pme_short_desc = "Primary ERAT hit",
	.pme_long_desc = "Primary ERAT hit42",
},
[ POWER8_PME_PM_LSU3_REJECT ] = {
	.pme_name = "PM_LSU3_REJECT",
	.pme_code = 0x4e05a,
	.pme_short_desc = "LSU3 reject",
	.pme_long_desc = "LSU3 reject .",
},
[ POWER8_PME_PM_LSU3_SRQ_STFWD ] = {
	.pme_name = "PM_LSU3_SRQ_STFWD",
	.pme_code = 0xc0a2,
	.pme_short_desc = "LS3 SRQ forwarded data to a load",
	.pme_long_desc = "LS3 SRQ forwarded data to a load42",
},
[ POWER8_PME_PM_LSU3_TMA_REQ_L2 ] = {
	.pme_name = "PM_LSU3_TMA_REQ_L2",
	.pme_code = 0xe0ae,
	.pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
	.pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42",
},
[ POWER8_PME_PM_LSU3_TM_L1_HIT ] = {
	.pme_name = "PM_LSU3_TM_L1_HIT",
	.pme_code = 0xe09e,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L142",
},
[ POWER8_PME_PM_LSU3_TM_L1_MISS ] = {
	.pme_name = "PM_LSU3_TM_L1_MISS",
	.pme_code = 0xe0a6,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss42",
},
[ POWER8_PME_PM_LSU_DERAT_MISS ] = {
	.pme_name = "PM_LSU_DERAT_MISS",
	.pme_code = 0x200f6,
	.pme_short_desc = "DERAT Reloaded due to a DERAT miss",
	.pme_long_desc = "DERAT Reloaded (Miss).",
},
[ POWER8_PME_PM_LSU_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LSU_ERAT_MISS_PREF",
	.pme_code = 0xe880,
	.pme_short_desc = "Erat miss due to prefetch, on either pipe",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_FIN ] = {
	.pme_name = "PM_LSU_FIN",
	.pme_code = 0x30066,
	.pme_short_desc = "LSU Finished an instruction (up to 2 per cycle)",
	.pme_long_desc = "LSU Finished an instruction (up to 2 per cycle).",
},
[ POWER8_PME_PM_LSU_FLUSH_UST ] = {
	.pme_name = "PM_LSU_FLUSH_UST",
	.pme_code = 0xc8ac,
	.pme_short_desc = "Unaligned Store Flush on either pipe",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_FOUR_TABLEWALK_CYC ] = {
	.pme_name = "PM_LSU_FOUR_TABLEWALK_CYC",
	.pme_code = 0xd0a4,
	.pme_short_desc = "Cycles when four tablewalks pending on this thread",
	.pme_long_desc = "Cycles when four tablewalks pending on this thread42",
},
[ POWER8_PME_PM_LSU_FX_FIN ] = {
	.pme_name = "PM_LSU_FX_FIN",
	.pme_code = 0x10066,
	.pme_short_desc = "LSU Finished a FX operation (up to 2 per cycle",
	.pme_long_desc = "LSU Finished a FX operation (up to 2 per cycle.",
},
[ POWER8_PME_PM_LSU_L1_PREF ] = {
	.pme_name = "PM_LSU_L1_PREF",
	.pme_code = 0xd8b8,
	.pme_short_desc = "hw initiated , include sw streaming forms as well , include sw streams as a separate event",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_L1_SW_PREF ] = {
	.pme_name = "PM_LSU_L1_SW_PREF",
	.pme_code = 0xc898,
	.pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches, on both pipes",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_LDF ] = {
	.pme_name = "PM_LSU_LDF",
	.pme_code = 0xc884,
	.pme_short_desc = "FPU loads only on LS2/LS3 ie LU0/LU1",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_LDX ] = {
	.pme_name = "PM_LSU_LDX",
	.pme_code = 0xc888,
	.pme_short_desc = "Vector loads can issue only on LS2/LS3",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_LMQ_FULL_CYC ] = {
	.pme_name = "PM_LSU_LMQ_FULL_CYC",
	.pme_code = 0xd0a2,
	.pme_short_desc = "LMQ full",
	.pme_long_desc = "LMQ fullCycles LMQ full,",
},
[ POWER8_PME_PM_LSU_LMQ_S0_ALLOC ] = {
	.pme_name = "PM_LSU_LMQ_S0_ALLOC",
	.pme_code = 0xd0a1,
	.pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_LSU_LMQ_S0_VALID ] = {
	.pme_name = "PM_LSU_LMQ_S0_VALID",
	.pme_code = 0xd0a0,
	.pme_short_desc = "Slot 0 of LMQ valid",
	.pme_long_desc = "Slot 0 of LMQ validLMQ slot 0 valid",
},
[ POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = {
	.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC",
	.pme_code = 0x3001c,
	.pme_short_desc = "ALL threads lsu empty (lmq and srq empty)",
	.pme_long_desc = "ALL threads lsu empty (lmq and srq empty). Issue HW016541",
},
[ POWER8_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
	.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
	.pme_code = 0x2003e,
	.pme_short_desc = "LSU empty (lmq and srq empty)",
	.pme_long_desc = "LSU empty (lmq and srq empty).",
},
[ POWER8_PME_PM_LSU_LRQ_S0_ALLOC ] = {
	.pme_name = "PM_LSU_LRQ_S0_ALLOC",
	.pme_code = 0xd09f,
	.pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_LSU_LRQ_S0_VALID ] = {
	.pme_name = "PM_LSU_LRQ_S0_VALID",
	.pme_code = 0xd09e,
	.pme_short_desc = "Slot 0 of LRQ valid",
	.pme_long_desc = "Slot 0 of LRQ validLRQ slot 0 valid",
},
[ POWER8_PME_PM_LSU_LRQ_S43_ALLOC ] = {
	.pme_name = "PM_LSU_LRQ_S43_ALLOC",
	.pme_code = 0xf091,
	.pme_short_desc = "LRQ slot 43 was released",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_LSU_LRQ_S43_VALID ] = {
	.pme_name = "PM_LSU_LRQ_S43_VALID",
	.pme_code = 0xf090,
	.pme_short_desc = "LRQ slot 43 was busy",
	.pme_long_desc = "LRQ slot 43 was busy42",
},
[ POWER8_PME_PM_LSU_MRK_DERAT_MISS ] = {
	.pme_name = "PM_LSU_MRK_DERAT_MISS",
	.pme_code = 0x30162,
	.pme_short_desc = "DERAT Reloaded (Miss)",
	.pme_long_desc = "DERAT Reloaded (Miss).",
},
[ POWER8_PME_PM_LSU_NCLD ] = {
	.pme_name = "PM_LSU_NCLD",
	.pme_code = 0xc88c,
	.pme_short_desc = "count at finish so can return only on ls0 or ls1",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_NCST ] = {
	.pme_name = "PM_LSU_NCST",
	.pme_code = 0xc092,
	.pme_short_desc = "Non-cachable Stores sent to nest",
	.pme_long_desc = "Non-cachable Stores sent to nest42",
},
[ POWER8_PME_PM_LSU_REJECT ] = {
	.pme_name = "PM_LSU_REJECT",
	.pme_code = 0x10064,
	.pme_short_desc = "LSU Reject (up to 4 per cycle)",
	.pme_long_desc = "LSU Reject (up to 4 per cycle).",
},
[ POWER8_PME_PM_LSU_REJECT_ERAT_MISS ] = {
	.pme_name = "PM_LSU_REJECT_ERAT_MISS",
	.pme_code = 0x2e05c,
	.pme_short_desc = "LSU Reject due to ERAT (up to 4 per cycles)",
	.pme_long_desc = "LSU Reject due to ERAT (up to 4 per cycles).",
},
[ POWER8_PME_PM_LSU_REJECT_LHS ] = {
	.pme_name = "PM_LSU_REJECT_LHS",
	.pme_code = 0x4e05c,
	.pme_short_desc = "LSU Reject due to LHS (up to 4 per cycle)",
	.pme_long_desc = "LSU Reject due to LHS (up to 4 per cycle).",
},
[ POWER8_PME_PM_LSU_REJECT_LMQ_FULL ] = {
	.pme_name = "PM_LSU_REJECT_LMQ_FULL",
	.pme_code = 0x1e05c,
	.pme_short_desc = "LSU reject due to LMQ full (4 per cycle)",
	.pme_long_desc = "LSU reject due to LMQ full (4 per cycle).",
},
[ POWER8_PME_PM_LSU_SET_MPRED ] = {
	.pme_name = "PM_LSU_SET_MPRED",
	.pme_code = 0xd082,
	.pme_short_desc = "Line already in cache at reload time",
	.pme_long_desc = "Line already in cache at reload time42",
},
[ POWER8_PME_PM_LSU_SRQ_EMPTY_CYC ] = {
	.pme_name = "PM_LSU_SRQ_EMPTY_CYC",
	.pme_code = 0x40008,
	.pme_short_desc = "ALL threads srq empty",
	.pme_long_desc = "All threads srq empty.",
},
[ POWER8_PME_PM_LSU_SRQ_FULL_CYC ] = {
	.pme_name = "PM_LSU_SRQ_FULL_CYC",
	.pme_code = 0x1001a,
	.pme_short_desc = "Storage Queue is full and is blocking dispatch",
	.pme_long_desc = "SRQ is Full.",
},
[ POWER8_PME_PM_LSU_SRQ_S0_ALLOC ] = {
	.pme_name = "PM_LSU_SRQ_S0_ALLOC",
	.pme_code = 0xd09d,
	.pme_short_desc = "Per thread - use edge detect to count allocates On a per thread basis, level signal indicating Slot 0 is valid. By instrumenting a single slot we can calculate service time for that slot. Previous machines required a separate signal indicating the slot was allocated. Because any signal can be routed to any counter in P8, we can count level in one PMC and edge detect in another PMC using the same signal",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_LSU_SRQ_S0_VALID ] = {
	.pme_name = "PM_LSU_SRQ_S0_VALID",
	.pme_code = 0xd09c,
	.pme_short_desc = "Slot 0 of SRQ valid",
	.pme_long_desc = "Slot 0 of SRQ validSRQ slot 0 valid",
},
[ POWER8_PME_PM_LSU_SRQ_S39_ALLOC ] = {
	.pme_name = "PM_LSU_SRQ_S39_ALLOC",
	.pme_code = 0xf093,
	.pme_short_desc = "SRQ slot 39 was released",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_LSU_SRQ_S39_VALID ] = {
	.pme_name = "PM_LSU_SRQ_S39_VALID",
	.pme_code = 0xf092,
	.pme_short_desc = "SRQ slot 39 was busy",
	.pme_long_desc = "SRQ slot 39 was busy42",
},
[ POWER8_PME_PM_LSU_SRQ_SYNC ] = {
	.pme_name = "PM_LSU_SRQ_SYNC",
	.pme_code = 0xd09b,
	.pme_short_desc = "A sync in the SRQ ended",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_LSU_SRQ_SYNC_CYC ] = {
	.pme_name = "PM_LSU_SRQ_SYNC_CYC",
	.pme_code = 0xd09a,
	.pme_short_desc = "A sync is in the SRQ (edge detect to count)",
	.pme_long_desc = "A sync is in the SRQ (edge detect to count)SRQ sync duration",
},
[ POWER8_PME_PM_LSU_STORE_REJECT ] = {
	.pme_name = "PM_LSU_STORE_REJECT",
	.pme_code = 0xf084,
	.pme_short_desc = "Store reject on either pipe",
	.pme_long_desc = "LSU",
},
[ POWER8_PME_PM_LSU_TWO_TABLEWALK_CYC ] = {
	.pme_name = "PM_LSU_TWO_TABLEWALK_CYC",
	.pme_code = 0xd0a6,
	.pme_short_desc = "Cycles when two tablewalks pending on this thread",
	.pme_long_desc = "Cycles when two tablewalks pending on this thread42",
},
[ POWER8_PME_PM_LWSYNC ] = {
	.pme_name = "PM_LWSYNC",
	.pme_code = 0x5094,
	.pme_short_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out",
	.pme_long_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out",
},
[ POWER8_PME_PM_LWSYNC_HELD ] = {
	.pme_name = "PM_LWSYNC_HELD",
	.pme_code = 0x209a,
	.pme_short_desc = "LWSYNC held at dispatch",
	.pme_long_desc = "LWSYNC held at dispatch",
},
[ POWER8_PME_PM_MEM_CO ] = {
	.pme_name = "PM_MEM_CO",
	.pme_code = 0x4c058,
	.pme_short_desc = "Memory castouts from this lpar",
	.pme_long_desc = "Memory castouts from this lpar.",
},
[ POWER8_PME_PM_MEM_LOC_THRESH_IFU ] = {
	.pme_name = "PM_MEM_LOC_THRESH_IFU",
	.pme_code = 0x10058,
	.pme_short_desc = "Local Memory above threshold for IFU speculation control",
	.pme_long_desc = "Local Memory above threshold for IFU speculation control.",
},
[ POWER8_PME_PM_MEM_LOC_THRESH_LSU_HIGH ] = {
	.pme_name = "PM_MEM_LOC_THRESH_LSU_HIGH",
	.pme_code = 0x40056,
	.pme_short_desc = "Local memory above threshold for LSU medium",
	.pme_long_desc = "Local memory above threshold for LSU medium.",
},
[ POWER8_PME_PM_MEM_LOC_THRESH_LSU_MED ] = {
	.pme_name = "PM_MEM_LOC_THRESH_LSU_MED",
	.pme_code = 0x1c05e,
	.pme_short_desc = "Local memory above theshold for data prefetch",
	.pme_long_desc = "Local memory above theshold for data prefetch.",
},
[ POWER8_PME_PM_MEM_PREF ] = {
	.pme_name = "PM_MEM_PREF",
	.pme_code = 0x2c058,
	.pme_short_desc = "Memory prefetch for this lpar. Includes L4",
	.pme_long_desc = "Memory prefetch for this lpar.",
},
[ POWER8_PME_PM_MEM_READ ] = {
	.pme_name = "PM_MEM_READ",
	.pme_code = 0x10056,
	.pme_short_desc = "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
	.pme_long_desc = "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch).",
},
[ POWER8_PME_PM_MEM_RWITM ] = {
	.pme_name = "PM_MEM_RWITM",
	.pme_code = 0x3c05e,
	.pme_short_desc = "Memory rwitm for this lpar",
	.pme_long_desc = "Memory rwitm for this lpar.",
},
[ POWER8_PME_PM_MRK_BACK_BR_CMPL ] = {
	.pme_name = "PM_MRK_BACK_BR_CMPL",
	.pme_code = 0x3515e,
	.pme_short_desc = "Marked branch instruction completed with a target address less than current instruction address",
	.pme_long_desc = "Marked branch instruction completed with a target address less than current instruction address.",
},
[ POWER8_PME_PM_MRK_BRU_FIN ] = {
	.pme_name = "PM_MRK_BRU_FIN",
	.pme_code = 0x2013a,
	.pme_short_desc = "bru marked instr finish",
	.pme_long_desc = "bru marked instr finish.",
},
[ POWER8_PME_PM_MRK_BR_CMPL ] = {
	.pme_name = "PM_MRK_BR_CMPL",
	.pme_code = 0x1016e,
	.pme_short_desc = "Branch Instruction completed",
	.pme_long_desc = "Branch Instruction completed.",
},
[ POWER8_PME_PM_MRK_BR_MPRED_CMPL ] = {
	.pme_name = "PM_MRK_BR_MPRED_CMPL",
	.pme_code = 0x301e4,
	.pme_short_desc = "Marked Branch Mispredicted",
	.pme_long_desc = "Marked Branch Mispredicted.",
},
[ POWER8_PME_PM_MRK_BR_TAKEN_CMPL ] = {
	.pme_name = "PM_MRK_BR_TAKEN_CMPL",
	.pme_code = 0x101e2,
	.pme_short_desc = "Marked Branch Taken completed",
	.pme_long_desc = "Marked Branch Taken.",
},
[ POWER8_PME_PM_MRK_CRU_FIN ] = {
	.pme_name = "PM_MRK_CRU_FIN",
	.pme_code = 0x3013a,
	.pme_short_desc = "IFU non-branch finished",
	.pme_long_desc = "IFU non-branch marked instruction finished.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD",
	.pme_code = 0x4d148,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
	.pme_code = 0x2d128,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR",
	.pme_code = 0x3d148,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
	.pme_code = 0x2c128,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DL4 ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL4",
	.pme_code = 0x3d14c,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DL4_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL4_CYC",
	.pme_code = 0x2c12c,
	.pme_short_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DMEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_DMEM",
	.pme_code = 0x4d14c,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DMEM_CYC",
	.pme_code = 0x2d12c,
	.pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2 ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2",
	.pme_code = 0x1d142,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L21_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_MOD",
	.pme_code = 0x4d146,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC",
	.pme_code = 0x2d126,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L21_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_SHR",
	.pme_code = 0x3d146,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC",
	.pme_code = 0x2c126,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2MISS ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2MISS",
	.pme_code = 0x1d14e,
	.pme_short_desc = "Data cache reload L2 miss",
	.pme_long_desc = "Data cache reload L2 miss.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC",
	.pme_code = 0x4c12e,
	.pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_CYC",
	.pme_code = 0x4c122,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x3d140,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
	.pme_code = 0x2c120,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x4d140,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
	.pme_code = 0x2d120,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_MEPF",
	.pme_code = 0x2d140,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_MEPF_CYC",
	.pme_code = 0x4d120,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
	.pme_code = 0x1d140,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
	.pme_code = 0x4c120,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3 ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3",
	.pme_code = 0x4d142,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD",
	.pme_code = 0x4d144,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC",
	.pme_code = 0x2d124,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR",
	.pme_code = 0x3d144,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
	.pme_code = 0x2c124,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_MOD",
	.pme_code = 0x2d144,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC",
	.pme_code = 0x4d124,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_SHR",
	.pme_code = 0x1d146,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC",
	.pme_code = 0x4c126,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3MISS ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3MISS",
	.pme_code = 0x201e4,
	.pme_short_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC",
	.pme_code = 0x2d12e,
	.pme_short_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_CYC",
	.pme_code = 0x2d122,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x3d142,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
	.pme_code = 0x2c122,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_MEPF",
	.pme_code = 0x2d142,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_MEPF_CYC",
	.pme_code = 0x4d122,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
	.pme_code = 0x1d144,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
	.pme_code = 0x4c124,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_LL4 ] = {
	.pme_name = "PM_MRK_DATA_FROM_LL4",
	.pme_code = 0x1d14c,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_LL4_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_LL4_CYC",
	.pme_code = 0x4c12c,
	.pme_short_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_LMEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_LMEM",
	.pme_code = 0x2d148,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
	.pme_code = 0x4d128,
	.pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_MEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_MEM",
	.pme_code = 0x201e0,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_MEMORY ] = {
	.pme_name = "PM_MRK_DATA_FROM_MEMORY",
	.pme_code = 0x2d14c,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_MEMORY_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_MEMORY_CYC",
	.pme_code = 0x4d12c,
	.pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x4d14a,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
	.pme_code = 0x2d12a,
	.pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
	.pme_code = 0x1d148,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
	.pme_code = 0x4c128,
	.pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD",
	.pme_code = 0x2d146,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
	.pme_code = 0x4d126,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR",
	.pme_code = 0x1d14a,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
	.pme_code = 0x4c12a,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RL4 ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL4",
	.pme_code = 0x2d14a,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group (Remote) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RL4_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL4_CYC",
	.pme_code = 0x4d12a,
	.pme_short_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group (Remote) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group (Remote) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RMEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_RMEM",
	.pme_code = 0x3d14a,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Remote) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Remote) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RMEM_CYC",
	.pme_code = 0x2c12a,
	.pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Remote) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Remote) due to a marked load.",
},
[ POWER8_PME_PM_MRK_DCACHE_RELOAD_INTV ] = {
	.pme_name = "PM_MRK_DCACHE_RELOAD_INTV",
	.pme_code = 0x40118,
	.pme_short_desc = "Combined Intervention event",
	.pme_long_desc = "Combined Intervention event.",
},
[ POWER8_PME_PM_MRK_DERAT_MISS ] = {
	.pme_name = "PM_MRK_DERAT_MISS",
	.pme_code = 0x301e6,
	.pme_short_desc = "Erat Miss (TLB Access) All page sizes",
	.pme_long_desc = "Erat Miss (TLB Access) All page sizes.",
},
[ POWER8_PME_PM_MRK_DERAT_MISS_16G ] = {
	.pme_name = "PM_MRK_DERAT_MISS_16G",
	.pme_code = 0x4d154,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G.",
},
[ POWER8_PME_PM_MRK_DERAT_MISS_16M ] = {
	.pme_name = "PM_MRK_DERAT_MISS_16M",
	.pme_code = 0x3d154,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M.",
},
[ POWER8_PME_PM_MRK_DERAT_MISS_4K ] = {
	.pme_name = "PM_MRK_DERAT_MISS_4K",
	.pme_code = 0x1d156,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K.",
},
[ POWER8_PME_PM_MRK_DERAT_MISS_64K ] = {
	.pme_name = "PM_MRK_DERAT_MISS_64K",
	.pme_code = 0x2d154,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K.",
},
[ POWER8_PME_PM_MRK_DFU_FIN ] = {
	.pme_name = "PM_MRK_DFU_FIN",
	.pme_code = 0x20132,
	.pme_short_desc = "Decimal Unit marked Instruction Finish",
	.pme_long_desc = "Decimal Unit marked Instruction Finish.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DL2L3_MOD",
	.pme_code = 0x4f148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DL2L3_SHR",
	.pme_code = 0x3f148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_DL4 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DL4",
	.pme_code = 0x3f14c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_DMEM ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DMEM",
	.pme_code = 0x4f14c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L2 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2",
	.pme_code = 0x1f142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L21_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L21_MOD",
	.pme_code = 0x4f146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L21_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L21_SHR",
	.pme_code = 0x3f146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L2MISS ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2MISS",
	.pme_code = 0x1f14e,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x3f140,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x4f140,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_MEPF ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2_MEPF",
	.pme_code = 0x2f140,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
	.pme_code = 0x1f140,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L3 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3",
	.pme_code = 0x4f142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_MOD",
	.pme_code = 0x4f144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_SHR",
	.pme_code = 0x3f144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_MOD",
	.pme_code = 0x2f144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L31_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_SHR",
	.pme_code = 0x1f146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L3MISS ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3MISS",
	.pme_code = 0x4f14e,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x3f142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L3_MEPF ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3_MEPF",
	.pme_code = 0x2f142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
	.pme_code = 0x1f144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_LL4 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_LL4",
	.pme_code = 0x1f14c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_LMEM ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_LMEM",
	.pme_code = 0x2f148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_MEMORY ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_MEMORY",
	.pme_code = 0x2f14c,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x4f14a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
	.pme_code = 0x1f148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RL2L3_MOD",
	.pme_code = 0x2f146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RL2L3_SHR",
	.pme_code = 0x1f14a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_RL4 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RL4",
	.pme_code = 0x2f14a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group (Remote) due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group (Remote) due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DPTEG_FROM_RMEM ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RMEM",
	.pme_code = 0x3f14a,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Remote) due to a marked data side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Remote) due to a marked data side request.",
},
[ POWER8_PME_PM_MRK_DTLB_MISS ] = {
	.pme_name = "PM_MRK_DTLB_MISS",
	.pme_code = 0x401e4,
	.pme_short_desc = "Marked dtlb miss",
	.pme_long_desc = "Marked dtlb miss.",
},
[ POWER8_PME_PM_MRK_DTLB_MISS_16G ] = {
	.pme_name = "PM_MRK_DTLB_MISS_16G",
	.pme_code = 0x1d158,
	.pme_short_desc = "Marked Data TLB Miss page size 16G",
	.pme_long_desc = "Marked Data TLB Miss page size 16G.",
},
[ POWER8_PME_PM_MRK_DTLB_MISS_16M ] = {
	.pme_name = "PM_MRK_DTLB_MISS_16M",
	.pme_code = 0x4d156,
	.pme_short_desc = "Marked Data TLB Miss page size 16M",
	.pme_long_desc = "Marked Data TLB Miss page size 16M.",
},
[ POWER8_PME_PM_MRK_DTLB_MISS_4K ] = {
	.pme_name = "PM_MRK_DTLB_MISS_4K",
	.pme_code = 0x2d156,
	.pme_short_desc = "Marked Data TLB Miss page size 4k",
	.pme_long_desc = "Marked Data TLB Miss page size 4k.",
},
[ POWER8_PME_PM_MRK_DTLB_MISS_64K ] = {
	.pme_name = "PM_MRK_DTLB_MISS_64K",
	.pme_code = 0x3d156,
	.pme_short_desc = "Marked Data TLB Miss page size 64K",
	.pme_long_desc = "Marked Data TLB Miss page size 64K.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_BKILL ] = {
	.pme_name = "PM_MRK_FAB_RSP_BKILL",
	.pme_code = 0x40154,
	.pme_short_desc = "Marked store had to do a bkill",
	.pme_long_desc = "Marked store had to do a bkill.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_BKILL_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_BKILL_CYC",
	.pme_code = 0x2f150,
	.pme_short_desc = "cycles L2 RC took for a bkill",
	.pme_long_desc = "cycles L2 RC took for a bkill.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_CLAIM_RTY ] = {
	.pme_name = "PM_MRK_FAB_RSP_CLAIM_RTY",
	.pme_code = 0x3015e,
	.pme_short_desc = "Sampled store did a rwitm and got a rty",
	.pme_long_desc = "Sampled store did a rwitm and got a rty.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_DCLAIM ] = {
	.pme_name = "PM_MRK_FAB_RSP_DCLAIM",
	.pme_code = 0x30154,
	.pme_short_desc = "Marked store had to do a dclaim",
	.pme_long_desc = "Marked store had to do a dclaim.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_DCLAIM_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_DCLAIM_CYC",
	.pme_code = 0x2f152,
	.pme_short_desc = "cycles L2 RC took for a dclaim",
	.pme_long_desc = "cycles L2 RC took for a dclaim.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_MATCH ] = {
	.pme_name = "PM_MRK_FAB_RSP_MATCH",
	.pme_code = 0x30156,
	.pme_short_desc = "ttype and cresp matched as specified in MMCR1",
	.pme_long_desc = "ttype and cresp matched as specified in MMCR1.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_MATCH_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_MATCH_CYC",
	.pme_code = 0x4f152,
	.pme_short_desc = "cresp/ttype match cycles",
	.pme_long_desc = "cresp/ttype match cycles.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_RD_RTY ] = {
	.pme_name = "PM_MRK_FAB_RSP_RD_RTY",
	.pme_code = 0x4015e,
	.pme_short_desc = "Sampled L2 reads retry count",
	.pme_long_desc = "Sampled L2 reads retry count.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_RD_T_INTV ] = {
	.pme_name = "PM_MRK_FAB_RSP_RD_T_INTV",
	.pme_code = 0x1015e,
	.pme_short_desc = "Sampled Read got a T intervention",
	.pme_long_desc = "Sampled Read got a T intervention.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_RWITM_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_RWITM_CYC",
	.pme_code = 0x4f150,
	.pme_short_desc = "cycles L2 RC took for a rwitm",
	.pme_long_desc = "cycles L2 RC took for a rwitm.",
},
[ POWER8_PME_PM_MRK_FAB_RSP_RWITM_RTY ] = {
	.pme_name = "PM_MRK_FAB_RSP_RWITM_RTY",
	.pme_code = 0x2015e,
	.pme_short_desc = "Sampled store did a rwitm and got a rty",
	.pme_long_desc = "Sampled store did a rwitm and got a rty.",
},
[ POWER8_PME_PM_MRK_FILT_MATCH ] = {
	.pme_name = "PM_MRK_FILT_MATCH",
	.pme_code = 0x2013c,
	.pme_short_desc = "Marked filter Match",
	.pme_long_desc = "Marked filter Match.",
},
[ POWER8_PME_PM_MRK_FIN_STALL_CYC ] = {
	.pme_name = "PM_MRK_FIN_STALL_CYC",
	.pme_code = 0x1013c,
	.pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count )",
	.pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #).",
},
[ POWER8_PME_PM_MRK_FXU_FIN ] = {
	.pme_name = "PM_MRK_FXU_FIN",
	.pme_code = 0x20134,
	.pme_short_desc = "fxu marked instr finish",
	.pme_long_desc = "fxu marked instr finish.",
},
[ POWER8_PME_PM_MRK_GRP_CMPL ] = {
	.pme_name = "PM_MRK_GRP_CMPL",
	.pme_code = 0x40130,
	.pme_short_desc = "marked instruction finished (completed)",
	.pme_long_desc = "marked instruction finished (completed).",
},
[ POWER8_PME_PM_MRK_GRP_IC_MISS ] = {
	.pme_name = "PM_MRK_GRP_IC_MISS",
	.pme_code = 0x4013a,
	.pme_short_desc = "Marked Group experienced I cache miss",
	.pme_long_desc = "Marked Group experienced I cache miss.",
},
[ POWER8_PME_PM_MRK_GRP_NTC ] = {
	.pme_name = "PM_MRK_GRP_NTC",
	.pme_code = 0x3013c,
	.pme_short_desc = "Marked group ntc cycles.",
	.pme_long_desc = "Marked group ntc cycles.",
},
[ POWER8_PME_PM_MRK_INST_CMPL ] = {
	.pme_name = "PM_MRK_INST_CMPL",
	.pme_code = 0x401e0,
	.pme_short_desc = "marked instruction completed",
	.pme_long_desc = "marked instruction completed.",
},
[ POWER8_PME_PM_MRK_INST_DECODED ] = {
	.pme_name = "PM_MRK_INST_DECODED",
	.pme_code = 0x20130,
	.pme_short_desc = "marked instruction decoded",
	.pme_long_desc = "marked instruction decoded. Name from ISU?",
},
[ POWER8_PME_PM_MRK_INST_DISP ] = {
	.pme_name = "PM_MRK_INST_DISP",
	.pme_code = 0x101e0,
	.pme_short_desc = "The thread has dispatched a randomly sampled marked instruction",
	.pme_long_desc = "Marked Instruction dispatched.",
},
[ POWER8_PME_PM_MRK_INST_FIN ] = {
	.pme_name = "PM_MRK_INST_FIN",
	.pme_code = 0x30130,
	.pme_short_desc = "marked instruction finished",
	.pme_long_desc = "marked instr finish any unit .",
},
[ POWER8_PME_PM_MRK_INST_FROM_L3MISS ] = {
	.pme_name = "PM_MRK_INST_FROM_L3MISS",
	.pme_code = 0x401e6,
	.pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
	.pme_long_desc = "n/a",
},
[ POWER8_PME_PM_MRK_INST_ISSUED ] = {
	.pme_name = "PM_MRK_INST_ISSUED",
	.pme_code = 0x10132,
	.pme_short_desc = "Marked instruction issued",
	.pme_long_desc = "Marked instruction issued.",
},
[ POWER8_PME_PM_MRK_INST_TIMEO ] = {
	.pme_name = "PM_MRK_INST_TIMEO",
	.pme_code = 0x40134,
	.pme_short_desc = "marked Instruction finish timeout (instruction lost)",
	.pme_long_desc = "marked Instruction finish timeout (instruction lost).",
},
[ POWER8_PME_PM_MRK_L1_ICACHE_MISS ] = {
	.pme_name = "PM_MRK_L1_ICACHE_MISS",
	.pme_code = 0x101e4,
	.pme_short_desc = "sampled Instruction suffered an icache Miss",
	.pme_long_desc = "Marked L1 Icache Miss.",
},
[ POWER8_PME_PM_MRK_L1_RELOAD_VALID ] = {
	.pme_name = "PM_MRK_L1_RELOAD_VALID",
	.pme_code = 0x101ea,
	.pme_short_desc = "Marked demand reload",
	.pme_long_desc = "Marked demand reload.",
},
[ POWER8_PME_PM_MRK_L2_RC_DISP ] = {
	.pme_name = "PM_MRK_L2_RC_DISP",
	.pme_code = 0x20114,
	.pme_short_desc = "Marked Instruction RC dispatched in L2",
	.pme_long_desc = "Marked Instruction RC dispatched in L2.",
},
[ POWER8_PME_PM_MRK_L2_RC_DONE ] = {
	.pme_name = "PM_MRK_L2_RC_DONE",
	.pme_code = 0x3012a,
	.pme_short_desc = "Marked RC done",
	.pme_long_desc = "Marked RC done.",
},
[ POWER8_PME_PM_MRK_LARX_FIN ] = {
	.pme_name = "PM_MRK_LARX_FIN",
	.pme_code = 0x40116,
	.pme_short_desc = "Larx finished",
	.pme_long_desc = "Larx finished .",
},
[ POWER8_PME_PM_MRK_LD_MISS_EXPOSED ] = {
	.pme_name = "PM_MRK_LD_MISS_EXPOSED",
	.pme_code = 0x1013f,
	.pme_short_desc = "Marked Load exposed Miss (exposed period ended)",
	.pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)",
},
[ POWER8_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = {
	.pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC",
	.pme_code = 0x1013e,
	.pme_short_desc = "Marked Load exposed Miss cycles",
	.pme_long_desc = "Marked Load exposed Miss (use edge detect to count #).",
},
[ POWER8_PME_PM_MRK_LD_MISS_L1 ] = {
	.pme_name = "PM_MRK_LD_MISS_L1",
	.pme_code = 0x201e2,
	.pme_short_desc = "Marked DL1 Demand Miss counted at exec time",
	.pme_long_desc = "Marked DL1 Demand Miss counted at exec time.",
},
[ POWER8_PME_PM_MRK_LD_MISS_L1_CYC ] = {
	.pme_name = "PM_MRK_LD_MISS_L1_CYC",
	.pme_code = 0x4013e,
	.pme_short_desc = "Marked ld latency",
	.pme_long_desc = "Marked ld latency.",
},
[ POWER8_PME_PM_MRK_LSU_FIN ] = {
	.pme_name = "PM_MRK_LSU_FIN",
	.pme_code = 0x40132,
	.pme_short_desc = "lsu marked instr finish",
	.pme_long_desc = "lsu marked instr finish.",
},
[ POWER8_PME_PM_MRK_LSU_FLUSH ] = {
	.pme_name = "PM_MRK_LSU_FLUSH",
	.pme_code = 0xd180,
	.pme_short_desc = "Flush: (marked) : All Cases",
	.pme_long_desc = "Flush: (marked) : All Cases42",
},
[ POWER8_PME_PM_MRK_LSU_FLUSH_LRQ ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_LRQ",
	.pme_code = 0xd188,
	.pme_short_desc = "Flush: (marked) LRQ",
	.pme_long_desc = "Flush: (marked) LRQMarked LRQ flushes",
},
[ POWER8_PME_PM_MRK_LSU_FLUSH_SRQ ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_SRQ",
	.pme_code = 0xd18a,
	.pme_short_desc = "Flush: (marked) SRQ",
	.pme_long_desc = "Flush: (marked) SRQMarked SRQ lhs flushes",
},
[ POWER8_PME_PM_MRK_LSU_FLUSH_ULD ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_ULD",
	.pme_code = 0xd184,
	.pme_short_desc = "Flush: (marked) Unaligned Load",
	.pme_long_desc = "Flush: (marked) Unaligned LoadMarked unaligned load flushes",
},
[ POWER8_PME_PM_MRK_LSU_FLUSH_UST ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_UST",
	.pme_code = 0xd186,
	.pme_short_desc = "Flush: (marked) Unaligned Store",
	.pme_long_desc = "Flush: (marked) Unaligned StoreMarked unaligned store flushes",
},
[ POWER8_PME_PM_MRK_LSU_REJECT ] = {
	.pme_name = "PM_MRK_LSU_REJECT",
	.pme_code = 0x40164,
	.pme_short_desc = "LSU marked reject (up to 2 per cycle)",
	.pme_long_desc = "LSU marked reject (up to 2 per cycle).",
},
[ POWER8_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = {
	.pme_name = "PM_MRK_LSU_REJECT_ERAT_MISS",
	.pme_code = 0x30164,
	.pme_short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)",
	.pme_long_desc = "LSU marked reject due to ERAT (up to 2 per cycle).",
},
[ POWER8_PME_PM_MRK_NTF_FIN ] = {
	.pme_name = "PM_MRK_NTF_FIN",
	.pme_code = 0x20112,
	.pme_short_desc = "Marked next to finish instruction finished",
	.pme_long_desc = "Marked next to finish instruction finished.",
},
[ POWER8_PME_PM_MRK_RUN_CYC ] = {
	.pme_name = "PM_MRK_RUN_CYC",
	.pme_code = 0x1d15e,
	.pme_short_desc = "Marked run cycles",
	.pme_long_desc = "Marked run cycles.",
},
[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_EFF ] = {
	.pme_name = "PM_MRK_SRC_PREF_TRACK_EFF",
	.pme_code = 0x1d15a,
	.pme_short_desc = "Marked src pref track was effective",
	.pme_long_desc = "Marked src pref track was effective.",
},
[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_INEFF ] = {
	.pme_name = "PM_MRK_SRC_PREF_TRACK_INEFF",
	.pme_code = 0x3d15a,
	.pme_short_desc = "Prefetch tracked was ineffective for marked src",
	.pme_long_desc = "Prefetch tracked was ineffective for marked src.",
},
[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD ] = {
	.pme_name = "PM_MRK_SRC_PREF_TRACK_MOD",
	.pme_code = 0x4d15c,
	.pme_short_desc = "Prefetch tracked was moderate for marked src",
	.pme_long_desc = "Prefetch tracked was moderate for marked src.",
},
[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L2 ] = {
	.pme_name = "PM_MRK_SRC_PREF_TRACK_MOD_L2",
	.pme_code = 0x1d15c,
	.pme_short_desc = "Marked src Prefetch Tracked was moderate (source L2)",
	.pme_long_desc = "Marked src Prefetch Tracked was moderate (source L2).",
},
[ POWER8_PME_PM_MRK_SRC_PREF_TRACK_MOD_L3 ] = {
	.pme_name = "PM_MRK_SRC_PREF_TRACK_MOD_L3",
	.pme_code = 0x3d15c,
	.pme_short_desc = "Prefetch tracked was moderate (L3 hit) for marked src",
	.pme_long_desc = "Prefetch tracked was moderate (L3 hit) for marked src.",
},
[ POWER8_PME_PM_MRK_STALL_CMPLU_CYC ] = {
	.pme_name = "PM_MRK_STALL_CMPLU_CYC",
	.pme_code = 0x3013e,
	.pme_short_desc = "Marked Group completion Stall",
	.pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count #).",
},
[ POWER8_PME_PM_MRK_STCX_FAIL ] = {
	.pme_name = "PM_MRK_STCX_FAIL",
	.pme_code = 0x3e158,
	.pme_short_desc = "marked stcx failed",
	.pme_long_desc = "marked stcx failed.",
},
[ POWER8_PME_PM_MRK_ST_CMPL ] = {
	.pme_name = "PM_MRK_ST_CMPL",
	.pme_code = 0x10134,
	.pme_short_desc = "marked store completed and sent to nest",
	.pme_long_desc = "Marked store completed.",
},
[ POWER8_PME_PM_MRK_ST_CMPL_INT ] = {
	.pme_name = "PM_MRK_ST_CMPL_INT",
	.pme_code = 0x30134,
	.pme_short_desc = "marked store finished with intervention",
	.pme_long_desc = "marked store complete (data home) with intervention.",
},
[ POWER8_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC ] = {
	.pme_name = "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
	.pme_code = 0x3f150,
	.pme_short_desc = "cycles to drain st from core to L2",
	.pme_long_desc = "cycles to drain st from core to L2.",
},
[ POWER8_PME_PM_MRK_ST_FWD ] = {
	.pme_name = "PM_MRK_ST_FWD",
	.pme_code = 0x3012c,
	.pme_short_desc = "Marked st forwards",
	.pme_long_desc = "Marked st forwards.",
},
[ POWER8_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC ] = {
	.pme_name = "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
	.pme_code = 0x1f150,
	.pme_short_desc = "cycles from L2 rc disp to l2 rc completion",
	.pme_long_desc = "cycles from L2 rc disp to l2 rc completion.",
},
[ POWER8_PME_PM_MRK_ST_NEST ] = {
	.pme_name = "PM_MRK_ST_NEST",
	.pme_code = 0x20138,
	.pme_short_desc = "Marked store sent to nest",
	.pme_long_desc = "Marked store sent to nest.",
},
[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_EFF ] = {
	.pme_name = "PM_MRK_TGT_PREF_TRACK_EFF",
	.pme_code = 0x1c15a,
	.pme_short_desc = "Marked target pref track was effective",
	.pme_long_desc = "Marked target pref track was effective.",
},
[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_INEFF ] = {
	.pme_name = "PM_MRK_TGT_PREF_TRACK_INEFF",
	.pme_code = 0x3c15a,
	.pme_short_desc = "Prefetch tracked was ineffective for marked target",
	.pme_long_desc = "Prefetch tracked was ineffective for marked target.",
},
[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD ] = {
	.pme_name = "PM_MRK_TGT_PREF_TRACK_MOD",
	.pme_code = 0x4c15c,
	.pme_short_desc = "Prefetch tracked was moderate for marked target",
	.pme_long_desc = "Prefetch tracked was moderate for marked target.",
},
[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L2 ] = {
	.pme_name = "PM_MRK_TGT_PREF_TRACK_MOD_L2",
	.pme_code = 0x1c15c,
	.pme_short_desc = "Marked target Prefetch Tracked was moderate (source L2)",
	.pme_long_desc = "Marked target Prefetch Tracked was moderate (source L2).",
},
[ POWER8_PME_PM_MRK_TGT_PREF_TRACK_MOD_L3 ] = {
	.pme_name = "PM_MRK_TGT_PREF_TRACK_MOD_L3",
	.pme_code = 0x3c15c,
	.pme_short_desc = "Prefetch tracked was moderate (L3 hit) for marked target",
	.pme_long_desc = "Prefetch tracked was moderate (L3 hit) for marked target.",
},
[ POWER8_PME_PM_MRK_VSU_FIN ] = {
	.pme_name = "PM_MRK_VSU_FIN",
	.pme_code = 0x30132,
	.pme_short_desc = "VSU marked instr finish",
	.pme_long_desc = "vsu (fpu) marked instr finish.",
},
[ POWER8_PME_PM_MULT_MRK ] = {
	.pme_name = "PM_MULT_MRK",
	.pme_code = 0x3d15e,
	.pme_short_desc = "mult marked instr",
	.pme_long_desc = "mult marked instr.",
},
[ POWER8_PME_PM_NESTED_TEND ] = {
	.pme_name = "PM_NESTED_TEND",
	.pme_code = 0x20b0,
	.pme_short_desc = "Completion time nested tend",
	.pme_long_desc = "Completion time nested tend",
},
[ POWER8_PME_PM_NEST_REF_CLK ] = {
	.pme_name = "PM_NEST_REF_CLK",
	.pme_code = 0x3006e,
	.pme_short_desc = "Multiply by 4 to obtain the number of PB cycles",
	.pme_long_desc = "Nest reference clocks.",
},
[ POWER8_PME_PM_NON_FAV_TBEGIN ] = {
	.pme_name = "PM_NON_FAV_TBEGIN",
	.pme_code = 0x20b6,
	.pme_short_desc = "Dispatch time non favored tbegin",
	.pme_long_desc = "Dispatch time non favored tbegin",
},
[ POWER8_PME_PM_NON_TM_RST_SC ] = {
	.pme_name = "PM_NON_TM_RST_SC",
	.pme_code = 0x328084,
	.pme_short_desc = "non tm snp rst tm sc",
	.pme_long_desc = "non tm snp rst tm sc",
},
[ POWER8_PME_PM_NTCG_ALL_FIN ] = {
	.pme_name = "PM_NTCG_ALL_FIN",
	.pme_code = 0x2001a,
	.pme_short_desc = "Cycles after all instructions have finished to group completed",
	.pme_long_desc = "Ccycles after all instructions have finished to group completed.",
},
[ POWER8_PME_PM_OUTER_TBEGIN ] = {
	.pme_name = "PM_OUTER_TBEGIN",
	.pme_code = 0x20ac,
	.pme_short_desc = "Completion time outer tbegin",
	.pme_long_desc = "Completion time outer tbegin",
},
[ POWER8_PME_PM_OUTER_TEND ] = {
	.pme_name = "PM_OUTER_TEND",
	.pme_code = 0x20ae,
	.pme_short_desc = "Completion time outer tend",
	.pme_long_desc = "Completion time outer tend",
},
[ POWER8_PME_PM_PMC1_OVERFLOW ] = {
	.pme_name = "PM_PMC1_OVERFLOW",
	.pme_code = 0x20010,
	.pme_short_desc = "Overflow from counter 1",
	.pme_long_desc = "Overflow from counter 1.",
},
[ POWER8_PME_PM_PMC2_OVERFLOW ] = {
	.pme_name = "PM_PMC2_OVERFLOW",
	.pme_code = 0x30010,
	.pme_short_desc = "Overflow from counter 2",
	.pme_long_desc = "Overflow from counter 2.",
},
[ POWER8_PME_PM_PMC2_REWIND ] = {
	.pme_name = "PM_PMC2_REWIND",
	.pme_code = 0x30020,
	.pme_short_desc = "PMC2 Rewind Event (did not match condition)",
	.pme_long_desc = "PMC2 Rewind Event (did not match condition).",
},
[ POWER8_PME_PM_PMC2_SAVED ] = {
	.pme_name = "PM_PMC2_SAVED",
	.pme_code = 0x10022,
	.pme_short_desc = "PMC2 Rewind Value saved",
	.pme_long_desc = "PMC2 Rewind Value saved (matched condition).",
},
[ POWER8_PME_PM_PMC3_OVERFLOW ] = {
	.pme_name = "PM_PMC3_OVERFLOW",
	.pme_code = 0x40010,
	.pme_short_desc = "Overflow from counter 3",
	.pme_long_desc = "Overflow from counter 3.",
},
[ POWER8_PME_PM_PMC4_OVERFLOW ] = {
	.pme_name = "PM_PMC4_OVERFLOW",
	.pme_code = 0x10010,
	.pme_short_desc = "Overflow from counter 4",
	.pme_long_desc = "Overflow from counter 4.",
},
[ POWER8_PME_PM_PMC4_REWIND ] = {
	.pme_name = "PM_PMC4_REWIND",
	.pme_code = 0x10020,
	.pme_short_desc = "PMC4 Rewind Event",
	.pme_long_desc = "PMC4 Rewind Event (did not match condition).",
},
[ POWER8_PME_PM_PMC4_SAVED ] = {
	.pme_name = "PM_PMC4_SAVED",
	.pme_code = 0x30022,
	.pme_short_desc = "PMC4 Rewind Value saved (matched condition)",
	.pme_long_desc = "PMC4 Rewind Value saved (matched condition).",
},
[ POWER8_PME_PM_PMC5_OVERFLOW ] = {
	.pme_name = "PM_PMC5_OVERFLOW",
	.pme_code = 0x10024,
	.pme_short_desc = "Overflow from counter 5",
	.pme_long_desc = "Overflow from counter 5.",
},
[ POWER8_PME_PM_PMC6_OVERFLOW ] = {
	.pme_name = "PM_PMC6_OVERFLOW",
	.pme_code = 0x30024,
	.pme_short_desc = "Overflow from counter 6",
	.pme_long_desc = "Overflow from counter 6.",
},
[ POWER8_PME_PM_PREF_TRACKED ] = {
	.pme_name = "PM_PREF_TRACKED",
	.pme_code = 0x2005a,
	.pme_short_desc = "Total number of Prefetch Operations that were tracked",
	.pme_long_desc = "Total number of Prefetch Operations that were tracked.",
},
[ POWER8_PME_PM_PREF_TRACK_EFF ] = {
	.pme_name = "PM_PREF_TRACK_EFF",
	.pme_code = 0x1005a,
	.pme_short_desc = "Prefetch Tracked was effective",
	.pme_long_desc = "Prefetch Tracked was effective.",
},
[ POWER8_PME_PM_PREF_TRACK_INEFF ] = {
	.pme_name = "PM_PREF_TRACK_INEFF",
	.pme_code = 0x3005a,
	.pme_short_desc = "Prefetch tracked was ineffective",
	.pme_long_desc = "Prefetch tracked was ineffective.",
},
[ POWER8_PME_PM_PREF_TRACK_MOD ] = {
	.pme_name = "PM_PREF_TRACK_MOD",
	.pme_code = 0x4005a,
	.pme_short_desc = "Prefetch tracked was moderate",
	.pme_long_desc = "Prefetch tracked was moderate.",
},
[ POWER8_PME_PM_PREF_TRACK_MOD_L2 ] = {
	.pme_name = "PM_PREF_TRACK_MOD_L2",
	.pme_code = 0x1005c,
	.pme_short_desc = "Prefetch Tracked was moderate (source L2)",
	.pme_long_desc = "Prefetch Tracked was moderate (source L2).",
},
[ POWER8_PME_PM_PREF_TRACK_MOD_L3 ] = {
	.pme_name = "PM_PREF_TRACK_MOD_L3",
	.pme_code = 0x3005c,
	.pme_short_desc = "Prefetch tracked was moderate (L3)",
	.pme_long_desc = "Prefetch tracked was moderate (L3).",
},
[ POWER8_PME_PM_PROBE_NOP_DISP ] = {
	.pme_name = "PM_PROBE_NOP_DISP",
	.pme_code = 0x40014,
	.pme_short_desc = "ProbeNops dispatched",
	.pme_long_desc = "ProbeNops dispatched.",
},
[ POWER8_PME_PM_PTE_PREFETCH ] = {
	.pme_name = "PM_PTE_PREFETCH",
	.pme_code = 0xe084,
	.pme_short_desc = "PTE prefetches",
	.pme_long_desc = "PTE prefetches42",
},
[ POWER8_PME_PM_PUMP_CPRED ] = {
	.pme_name = "PM_PUMP_CPRED",
	.pme_code = 0x10054,
	.pme_short_desc = "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).",
},
[ POWER8_PME_PM_PUMP_MPRED ] = {
	.pme_name = "PM_PUMP_MPRED",
	.pme_code = 0x40052,
	.pme_short_desc = "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).",
},
[ POWER8_PME_PM_RC0_ALLOC ] = {
	.pme_name = "PM_RC0_ALLOC",
	.pme_code = 0x16081,
	.pme_short_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_RC0_BUSY ] = {
	.pme_name = "PM_RC0_BUSY",
	.pme_code = 0x16080,
	.pme_short_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
	.pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
},
[ POWER8_PME_PM_RC_LIFETIME_EXC_1024 ] = {
	.pme_name = "PM_RC_LIFETIME_EXC_1024",
	.pme_code = 0xde200301eaull,
	.pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 1024 cycles",
	.pme_long_desc = "Reload latency exceeded 1024 cyc",
},
[ POWER8_PME_PM_RC_LIFETIME_EXC_2048 ] = {
	.pme_name = "PM_RC_LIFETIME_EXC_2048",
	.pme_code = 0xde200401ecull,
	.pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 2048 cycles",
	.pme_long_desc = "Threshold counter exceeded a value of 2048",
},
[ POWER8_PME_PM_RC_LIFETIME_EXC_256 ] = {
	.pme_name = "PM_RC_LIFETIME_EXC_256",
	.pme_code = 0xde200101e8ull,
	.pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 256 cycles",
	.pme_long_desc = "Threshold counter exceed a count of 256",
},
[ POWER8_PME_PM_RC_LIFETIME_EXC_32 ] = {
	.pme_name = "PM_RC_LIFETIME_EXC_32",
	.pme_code = 0xde200201e6ull,
	.pme_short_desc = "Number of times the RC machine for a sampled instruction was active for more than 32 cycles",
	.pme_long_desc = "Reload latency exceeded 32 cyc",
},
[ POWER8_PME_PM_RC_USAGE ] = {
	.pme_name = "PM_RC_USAGE",
	.pme_code = 0x36088,
	.pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
	.pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
},
[ POWER8_PME_PM_RD_CLEARING_SC ] = {
	.pme_name = "PM_RD_CLEARING_SC",
	.pme_code = 0x34808e,
	.pme_short_desc = "rd clearing sc",
	.pme_long_desc = "rd clearing sc",
},
[ POWER8_PME_PM_RD_FORMING_SC ] = {
	.pme_name = "PM_RD_FORMING_SC",
	.pme_code = 0x34808c,
	.pme_short_desc = "rd forming sc",
	.pme_long_desc = "rd forming sc",
},
[ POWER8_PME_PM_RD_HIT_PF ] = {
	.pme_name = "PM_RD_HIT_PF",
	.pme_code = 0x428086,
	.pme_short_desc = "rd machine hit l3 pf machine",
	.pme_long_desc = "rd machine hit l3 pf machine",
},
[ POWER8_PME_PM_REAL_SRQ_FULL ] = {
	.pme_name = "PM_REAL_SRQ_FULL",
	.pme_code = 0x20004,
	.pme_short_desc = "Out of real srq entries",
	.pme_long_desc = "Out of real srq entries.",
},
[ POWER8_PME_PM_RUN_CYC ] = {
	.pme_name = "PM_RUN_CYC",
	.pme_code = 0x600f4,
	.pme_short_desc = "Run_cycles",
	.pme_long_desc = "Run_cycles.",
},
[ POWER8_PME_PM_RUN_CYC_SMT2_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT2_MODE",
	.pme_code = 0x3006c,
	.pme_short_desc = "Cycles run latch is set and core is in SMT2 mode",
	.pme_long_desc = "Cycles run latch is set and core is in SMT2 mode.",
},
[ POWER8_PME_PM_RUN_CYC_SMT2_SHRD_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT2_SHRD_MODE",
	.pme_code = 0x2006a,
	.pme_short_desc = "cycles this threads run latch is set and the core is in SMT2 shared mode",
	.pme_long_desc = "Cycles run latch is set and core is in SMT2-shared mode.",
},
[ POWER8_PME_PM_RUN_CYC_SMT2_SPLIT_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT2_SPLIT_MODE",
	.pme_code = 0x1006a,
	.pme_short_desc = "Cycles run latch is set and core is in SMT2-split mode",
	.pme_long_desc = "Cycles run latch is set and core is in SMT2-split mode.",
},
[ POWER8_PME_PM_RUN_CYC_SMT4_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT4_MODE",
	.pme_code = 0x2006c,
	.pme_short_desc = "cycles this threads run latch is set and the core is in SMT4 mode",
	.pme_long_desc = "Cycles run latch is set and core is in SMT4 mode.",
},
[ POWER8_PME_PM_RUN_CYC_SMT8_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT8_MODE",
	.pme_code = 0x4006c,
	.pme_short_desc = "Cycles run latch is set and core is in SMT8 mode",
	.pme_long_desc = "Cycles run latch is set and core is in SMT8 mode.",
},
[ POWER8_PME_PM_RUN_CYC_ST_MODE ] = {
	.pme_name = "PM_RUN_CYC_ST_MODE",
	.pme_code = 0x1006c,
	.pme_short_desc = "Cycles run latch is set and core is in ST mode",
	.pme_long_desc = "Cycles run latch is set and core is in ST mode.",
},
[ POWER8_PME_PM_RUN_INST_CMPL ] = {
	.pme_name = "PM_RUN_INST_CMPL",
	.pme_code = 0x500fa,
	.pme_short_desc = "Run_Instructions",
	.pme_long_desc = "Run_Instructions.",
},
[ POWER8_PME_PM_RUN_PURR ] = {
	.pme_name = "PM_RUN_PURR",
	.pme_code = 0x400f4,
	.pme_short_desc = "Run_PURR",
	.pme_long_desc = "Run_PURR.",
},
[ POWER8_PME_PM_RUN_SPURR ] = {
	.pme_name = "PM_RUN_SPURR",
	.pme_code = 0x10008,
	.pme_short_desc = "Run SPURR",
	.pme_long_desc = "Run SPURR.",
},
[ POWER8_PME_PM_SEC_ERAT_HIT ] = {
	.pme_name = "PM_SEC_ERAT_HIT",
	.pme_code = 0xf082,
	.pme_short_desc = "secondary ERAT Hit",
	.pme_long_desc = "secondary ERAT Hit42",
},
[ POWER8_PME_PM_SHL_CREATED ] = {
	.pme_name = "PM_SHL_CREATED",
	.pme_code = 0x508c,
	.pme_short_desc = "Store-Hit-Load Table Entry Created",
	.pme_long_desc = "Store-Hit-Load Table Entry Created",
},
[ POWER8_PME_PM_SHL_ST_CONVERT ] = {
	.pme_name = "PM_SHL_ST_CONVERT",
	.pme_code = 0x508e,
	.pme_short_desc = "Store-Hit-Load Table Read Hit with entry Enabled",
	.pme_long_desc = "Store-Hit-Load Table Read Hit with entry Enabled",
},
[ POWER8_PME_PM_SHL_ST_DISABLE ] = {
	.pme_name = "PM_SHL_ST_DISABLE",
	.pme_code = 0x5090,
	.pme_short_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)",
	.pme_long_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)",
},
[ POWER8_PME_PM_SN0_ALLOC ] = {
	.pme_name = "PM_SN0_ALLOC",
	.pme_code = 0x26085,
	.pme_short_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
	.pme_long_desc = "0.0",
},
[ POWER8_PME_PM_SN0_BUSY ] = {
	.pme_name = "PM_SN0_BUSY",
	.pme_code = 0x26084,
	.pme_short_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
	.pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point)",
},
[ POWER8_PME_PM_SNOOP_TLBIE ] = {
	.pme_name = "PM_SNOOP_TLBIE",
	.pme_code = 0xd0b2,
	.pme_short_desc = "TLBIE snoop",
	.pme_long_desc = "TLBIE snoopSnoop TLBIE",
},
[ POWER8_PME_PM_SNP_TM_HIT_M ] = {
	.pme_name = "PM_SNP_TM_HIT_M",
	.pme_code = 0x338088,
	.pme_short_desc = "snp tm st hit m mu",
	.pme_long_desc = "snp tm st hit m mu",
},
[ POWER8_PME_PM_SNP_TM_HIT_T ] = {
	.pme_name = "PM_SNP_TM_HIT_T",
	.pme_code = 0x33808a,
	.pme_short_desc = "snp tm_st_hit t tn te",
	.pme_long_desc = "snp tm_st_hit t tn te",
},
[ POWER8_PME_PM_SN_USAGE ] = {
	.pme_name = "PM_SN_USAGE",
	.pme_code = 0x4608c,
	.pme_short_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
	.pme_long_desc = "Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
},
[ POWER8_PME_PM_STALL_END_GCT_EMPTY ] = {
	.pme_name = "PM_STALL_END_GCT_EMPTY",
	.pme_code = 0x10028,
	.pme_short_desc = "Count ended because GCT went empty",
	.pme_long_desc = "Count ended because GCT went empty.",
},
[ POWER8_PME_PM_STCX_FAIL ] = {
	.pme_name = "PM_STCX_FAIL",
	.pme_code = 0x1e058,
	.pme_short_desc = "stcx failed",
	.pme_long_desc = "stcx failed .",
},
[ POWER8_PME_PM_STCX_LSU ] = {
	.pme_name = "PM_STCX_LSU",
	.pme_code = 0xc090,
	.pme_short_desc = "STCX executed reported at sent to nest",
	.pme_long_desc = "STCX executed reported at sent to nest42",
},
[ POWER8_PME_PM_ST_CAUSED_FAIL ] = {
	.pme_name = "PM_ST_CAUSED_FAIL",
	.pme_code = 0x717080,
	.pme_short_desc = "Non TM St caused any thread to fail",
	.pme_long_desc = "Non TM St caused any thread to fail",
},
[ POWER8_PME_PM_ST_CMPL ] = {
	.pme_name = "PM_ST_CMPL",
	.pme_code = 0x20016,
	.pme_short_desc = "Store completion count",
	.pme_long_desc = "Store completion count.",
},
[ POWER8_PME_PM_ST_FIN ] = {
	.pme_name = "PM_ST_FIN",
	.pme_code = 0x200f0,
	.pme_short_desc = "Store Instructions Finished",
	.pme_long_desc = "Store Instructions Finished (store sent to nest).",
},
[ POWER8_PME_PM_ST_FWD ] = {
	.pme_name = "PM_ST_FWD",
	.pme_code = 0x20018,
	.pme_short_desc = "Store forwards that finished",
	.pme_long_desc = "Store forwards that finished.",
},
[ POWER8_PME_PM_ST_MISS_L1 ] = {
	.pme_name = "PM_ST_MISS_L1",
	.pme_code = 0x300f0,
	.pme_short_desc = "Store Missed L1",
	.pme_long_desc = "Store Missed L1.",
},
[ POWER8_PME_PM_SUSPENDED ] = {
	.pme_name = "PM_SUSPENDED",
	.pme_code = 0x0,
	.pme_short_desc = "Counter OFF",
	.pme_long_desc = "Counter OFF.",
},
[ POWER8_PME_PM_SWAP_CANCEL ] = {
	.pme_name = "PM_SWAP_CANCEL",
	.pme_code = 0x3090,
	.pme_short_desc = "SWAP cancel , rtag not available",
	.pme_long_desc = "SWAP cancel , rtag not available",
},
[ POWER8_PME_PM_SWAP_CANCEL_GPR ] = {
	.pme_name = "PM_SWAP_CANCEL_GPR",
	.pme_code = 0x3092,
	.pme_short_desc = "SWAP cancel , rtag not available for gpr",
	.pme_long_desc = "SWAP cancel , rtag not available for gpr",
},
[ POWER8_PME_PM_SWAP_COMPLETE ] = {
	.pme_name = "PM_SWAP_COMPLETE",
	.pme_code = 0x308c,
	.pme_short_desc = "swap cast in completed",
	.pme_long_desc = "swap cast in completed",
},
[ POWER8_PME_PM_SWAP_COMPLETE_GPR ] = {
	.pme_name = "PM_SWAP_COMPLETE_GPR",
	.pme_code = 0x308e,
	.pme_short_desc = "swap cast in completed fpr gpr",
	.pme_long_desc = "swap cast in completed fpr gpr",
},
[ POWER8_PME_PM_SYNC_MRK_BR_LINK ] = {
	.pme_name = "PM_SYNC_MRK_BR_LINK",
	.pme_code = 0x15152,
	.pme_short_desc = "Marked Branch and link branch that can cause a synchronous interrupt",
	.pme_long_desc = "Marked Branch and link branch that can cause a synchronous interrupt.",
},
[ POWER8_PME_PM_SYNC_MRK_BR_MPRED ] = {
	.pme_name = "PM_SYNC_MRK_BR_MPRED",
	.pme_code = 0x1515c,
	.pme_short_desc = "Marked Branch mispredict that can cause a synchronous interrupt",
	.pme_long_desc = "Marked Branch mispredict that can cause a synchronous interrupt.",
},
[ POWER8_PME_PM_SYNC_MRK_FX_DIVIDE ] = {
	.pme_name = "PM_SYNC_MRK_FX_DIVIDE",
	.pme_code = 0x15156,
	.pme_short_desc = "Marked fixed point divide that can cause a synchronous interrupt",
	.pme_long_desc = "Marked fixed point divide that can cause a synchronous interrupt.",
},
[ POWER8_PME_PM_SYNC_MRK_L2HIT ] = {
	.pme_name = "PM_SYNC_MRK_L2HIT",
	.pme_code = 0x15158,
	.pme_short_desc = "Marked L2 Hits that can throw a synchronous interrupt",
	.pme_long_desc = "Marked L2 Hits that can throw a synchronous interrupt.",
},
[ POWER8_PME_PM_SYNC_MRK_L2MISS ] = {
	.pme_name = "PM_SYNC_MRK_L2MISS",
	.pme_code = 0x1515a,
	.pme_short_desc = "Marked L2 Miss that can throw a synchronous interrupt",
	.pme_long_desc = "Marked L2 Miss that can throw a synchronous interrupt.",
},
[ POWER8_PME_PM_SYNC_MRK_L3MISS ] = {
	.pme_name = "PM_SYNC_MRK_L3MISS",
	.pme_code = 0x15154,
	.pme_short_desc = "Marked L3 misses that can throw a synchronous interrupt",
	.pme_long_desc = "Marked L3 misses that can throw a synchronous interrupt.",
},
[ POWER8_PME_PM_SYNC_MRK_PROBE_NOP ] = {
	.pme_name = "PM_SYNC_MRK_PROBE_NOP",
	.pme_code = 0x15150,
	.pme_short_desc = "Marked probeNops which can cause synchronous interrupts",
	.pme_long_desc = "Marked probeNops which can cause synchronous interrupts.",
},
[ POWER8_PME_PM_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_SYS_PUMP_CPRED",
	.pme_code = 0x30050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).",
},
[ POWER8_PME_PM_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_SYS_PUMP_MPRED",
	.pme_code = 0x30052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or",
},
[ POWER8_PME_PM_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x40050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate).",
},
[ POWER8_PME_PM_TABLEWALK_CYC ] = {
	.pme_name = "PM_TABLEWALK_CYC",
	.pme_code = 0x10026,
	.pme_short_desc = "Cycles when a tablewalk (I or D) is active",
	.pme_long_desc = "Tablewalk Active.",
},
[ POWER8_PME_PM_TABLEWALK_CYC_PREF ] = {
	.pme_name = "PM_TABLEWALK_CYC_PREF",
	.pme_code = 0xe086,
	.pme_short_desc = "tablewalk qualified for pte prefetches",
	.pme_long_desc = "tablewalk qualified for pte prefetches42",
},
[ POWER8_PME_PM_TABORT_TRECLAIM ] = {
	.pme_name = "PM_TABORT_TRECLAIM",
	.pme_code = 0x20b2,
	.pme_short_desc = "Completion time tabortnoncd, tabortcd, treclaim",
	.pme_long_desc = "Completion time tabortnoncd, tabortcd, treclaim",
},
[ POWER8_PME_PM_TB_BIT_TRANS ] = {
	.pme_name = "PM_TB_BIT_TRANS",
	.pme_code = 0x300f8,
	.pme_short_desc = "timebase event",
	.pme_long_desc = "timebase event.",
},
[ POWER8_PME_PM_TEND_PEND_CYC ] = {
	.pme_name = "PM_TEND_PEND_CYC",
	.pme_code = 0xe0ba,
	.pme_short_desc = "TEND latency per thread",
	.pme_long_desc = "TEND latency per thread42",
},
[ POWER8_PME_PM_THRD_ALL_RUN_CYC ] = {
	.pme_name = "PM_THRD_ALL_RUN_CYC",
	.pme_code = 0x2000c,
	.pme_short_desc = "All Threads in Run_cycles (was both threads in run_cycles)",
	.pme_long_desc = "All Threads in Run_cycles (was both threads in run_cycles).",
},
[ POWER8_PME_PM_THRD_CONC_RUN_INST ] = {
	.pme_name = "PM_THRD_CONC_RUN_INST",
	.pme_code = 0x300f4,
	.pme_short_desc = "PPC Instructions Finished when both threads in run_cycles",
	.pme_long_desc = "Concurrent Run Instructions.",
},
[ POWER8_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = {
	.pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC",
	.pme_code = 0x10012,
	.pme_short_desc = "Cycles group completed on both completion slots by any thread",
	.pme_long_desc = "Two threads finished same cycle (gated by run latch).",
},
[ POWER8_PME_PM_THRD_PRIO_0_1_CYC ] = {
	.pme_name = "PM_THRD_PRIO_0_1_CYC",
	.pme_code = 0x40bc,
	.pme_short_desc = "Cycles thread running at priority level 0 or 1",
	.pme_long_desc = "Cycles thread running at priority level 0 or 1",
},
[ POWER8_PME_PM_THRD_PRIO_2_3_CYC ] = {
	.pme_name = "PM_THRD_PRIO_2_3_CYC",
	.pme_code = 0x40be,
	.pme_short_desc = "Cycles thread running at priority level 2 or 3",
	.pme_long_desc = "Cycles thread running at priority level 2 or 3",
},
[ POWER8_PME_PM_THRD_PRIO_4_5_CYC ] = {
	.pme_name = "PM_THRD_PRIO_4_5_CYC",
	.pme_code = 0x5080,
	.pme_short_desc = "Cycles thread running at priority level 4 or 5",
	.pme_long_desc = "Cycles thread running at priority level 4 or 5",
},
[ POWER8_PME_PM_THRD_PRIO_6_7_CYC ] = {
	.pme_name = "PM_THRD_PRIO_6_7_CYC",
	.pme_code = 0x5082,
	.pme_short_desc = "Cycles thread running at priority level 6 or 7",
	.pme_long_desc = "Cycles thread running at priority level 6 or 7",
},
[ POWER8_PME_PM_THRD_REBAL_CYC ] = {
	.pme_name = "PM_THRD_REBAL_CYC",
	.pme_code = 0x3098,
	.pme_short_desc = "cycles rebalance was active",
	.pme_long_desc = "cycles rebalance was active",
},
[ POWER8_PME_PM_THRESH_EXC_1024 ] = {
	.pme_name = "PM_THRESH_EXC_1024",
	.pme_code = 0x301ea,
	.pme_short_desc = "Threshold counter exceeded a value of 1024",
	.pme_long_desc = "Threshold counter exceeded a value of 1024.",
},
[ POWER8_PME_PM_THRESH_EXC_128 ] = {
	.pme_name = "PM_THRESH_EXC_128",
	.pme_code = 0x401ea,
	.pme_short_desc = "Threshold counter exceeded a value of 128",
	.pme_long_desc = "Threshold counter exceeded a value of 128.",
},
[ POWER8_PME_PM_THRESH_EXC_2048 ] = {
	.pme_name = "PM_THRESH_EXC_2048",
	.pme_code = 0x401ec,
	.pme_short_desc = "Threshold counter exceeded a value of 2048",
	.pme_long_desc = "Threshold counter exceeded a value of 2048.",
},
[ POWER8_PME_PM_THRESH_EXC_256 ] = {
	.pme_name = "PM_THRESH_EXC_256",
	.pme_code = 0x101e8,
	.pme_short_desc = "Threshold counter exceed a count of 256",
	.pme_long_desc = "Threshold counter exceed a count of 256.",
},
[ POWER8_PME_PM_THRESH_EXC_32 ] = {
	.pme_name = "PM_THRESH_EXC_32",
	.pme_code = 0x201e6,
	.pme_short_desc = "Threshold counter exceeded a value of 32",
	.pme_long_desc = "Threshold counter exceeded a value of 32.",
},
[ POWER8_PME_PM_THRESH_EXC_4096 ] = {
	.pme_name = "PM_THRESH_EXC_4096",
	.pme_code = 0x101e6,
	.pme_short_desc = "Threshold counter exceed a count of 4096",
	.pme_long_desc = "Threshold counter exceed a count of 4096.",
},
[ POWER8_PME_PM_THRESH_EXC_512 ] = {
	.pme_name = "PM_THRESH_EXC_512",
	.pme_code = 0x201e8,
	.pme_short_desc = "Threshold counter exceeded a value of 512",
	.pme_long_desc = "Threshold counter exceeded a value of 512.",
},
[ POWER8_PME_PM_THRESH_EXC_64 ] = {
	.pme_name = "PM_THRESH_EXC_64",
	.pme_code = 0x301e8,
	.pme_short_desc = "IFU non-branch finished",
	.pme_long_desc = "Threshold counter exceeded a value of 64.",
},
[ POWER8_PME_PM_THRESH_MET ] = {
	.pme_name = "PM_THRESH_MET",
	.pme_code = 0x101ec,
	.pme_short_desc = "threshold exceeded",
	.pme_long_desc = "threshold exceeded.",
},
[ POWER8_PME_PM_THRESH_NOT_MET ] = {
	.pme_name = "PM_THRESH_NOT_MET",
	.pme_code = 0x4016e,
	.pme_short_desc = "Threshold counter did not meet threshold",
	.pme_long_desc = "Threshold counter did not meet threshold.",
},
[ POWER8_PME_PM_TLBIE_FIN ] = {
	.pme_name = "PM_TLBIE_FIN",
	.pme_code = 0x30058,
	.pme_short_desc = "tlbie finished",
	.pme_long_desc = "tlbie finished.",
},
[ POWER8_PME_PM_TLB_MISS ] = {
	.pme_name = "PM_TLB_MISS",
	.pme_code = 0x20066,
	.pme_short_desc = "TLB Miss (I + D)",
	.pme_long_desc = "TLB Miss (I + D).",
},
[ POWER8_PME_PM_TM_BEGIN_ALL ] = {
	.pme_name = "PM_TM_BEGIN_ALL",
	.pme_code = 0x20b8,
	.pme_short_desc = "Tm any tbegin",
	.pme_long_desc = "Tm any tbegin",
},
[ POWER8_PME_PM_TM_CAM_OVERFLOW ] = {
	.pme_name = "PM_TM_CAM_OVERFLOW",
	.pme_code = 0x318082,
	.pme_short_desc = "l3 tm cam overflow during L2 co of SC",
	.pme_long_desc = "l3 tm cam overflow during L2 co of SC",
},
[ POWER8_PME_PM_TM_CAP_OVERFLOW ] = {
	.pme_name = "PM_TM_CAP_OVERFLOW",
	.pme_code = 0x74708c,
	.pme_short_desc = "TM Footprint Capactiy Overflow",
	.pme_long_desc = "TM Footprint Capactiy Overflow",
},
[ POWER8_PME_PM_TM_END_ALL ] = {
	.pme_name = "PM_TM_END_ALL",
	.pme_code = 0x20ba,
	.pme_short_desc = "Tm any tend",
	.pme_long_desc = "Tm any tend",
},
[ POWER8_PME_PM_TM_FAIL_CONF_NON_TM ] = {
	.pme_name = "PM_TM_FAIL_CONF_NON_TM",
	.pme_code = 0x3086,
	.pme_short_desc = "TEXAS fail reason @ completion",
	.pme_long_desc = "TEXAS fail reason @ completion",
},
[ POWER8_PME_PM_TM_FAIL_CON_TM ] = {
	.pme_name = "PM_TM_FAIL_CON_TM",
	.pme_code = 0x3088,
	.pme_short_desc = "TEXAS fail reason @ completion",
	.pme_long_desc = "TEXAS fail reason @ completion",
},
[ POWER8_PME_PM_TM_FAIL_DISALLOW ] = {
	.pme_name = "PM_TM_FAIL_DISALLOW",
	.pme_code = 0xe0b2,
	.pme_short_desc = "TM fail disallow",
	.pme_long_desc = "TM fail disallow42",
},
[ POWER8_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW ] = {
	.pme_name = "PM_TM_FAIL_FOOTPRINT_OVERFLOW",
	.pme_code = 0x3084,
	.pme_short_desc = "TEXAS fail reason @ completion",
	.pme_long_desc = "TEXAS fail reason @ completion",
},
[ POWER8_PME_PM_TM_FAIL_NON_TX_CONFLICT ] = {
	.pme_name = "PM_TM_FAIL_NON_TX_CONFLICT",
	.pme_code = 0xe0b8,
	.pme_short_desc = "Non transactional conflict from LSU whtver gets repoted to texas",
	.pme_long_desc = "Non transactional conflict from LSU whtver gets repoted to texas42",
},
[ POWER8_PME_PM_TM_FAIL_SELF ] = {
	.pme_name = "PM_TM_FAIL_SELF",
	.pme_code = 0x308a,
	.pme_short_desc = "TEXAS fail reason @ completion",
	.pme_long_desc = "TEXAS fail reason @ completion",
},
[ POWER8_PME_PM_TM_FAIL_TLBIE ] = {
	.pme_name = "PM_TM_FAIL_TLBIE",
	.pme_code = 0xe0b4,
	.pme_short_desc = "TLBIE hit bloom filter",
	.pme_long_desc = "TLBIE hit bloom filter42",
},
[ POWER8_PME_PM_TM_FAIL_TX_CONFLICT ] = {
	.pme_name = "PM_TM_FAIL_TX_CONFLICT",
	.pme_code = 0xe0b6,
	.pme_short_desc = "Transactional conflict from LSU, whatever gets reported to texas",
	.pme_long_desc = "Transactional conflict from LSU, whatever gets reported to texas 42",
},
[ POWER8_PME_PM_TM_FAV_CAUSED_FAIL ] = {
	.pme_name = "PM_TM_FAV_CAUSED_FAIL",
	.pme_code = 0x727086,
	.pme_short_desc = "TM Load (fav) caused another thread to fail",
	.pme_long_desc = "TM Load (fav) caused another thread to fail",
},
[ POWER8_PME_PM_TM_LD_CAUSED_FAIL ] = {
	.pme_name = "PM_TM_LD_CAUSED_FAIL",
	.pme_code = 0x717082,
	.pme_short_desc = "Non TM Ld caused any thread to fail",
	.pme_long_desc = "Non TM Ld caused any thread to fail",
},
[ POWER8_PME_PM_TM_LD_CONF ] = {
	.pme_name = "PM_TM_LD_CONF",
	.pme_code = 0x727084,
	.pme_short_desc = "TM Load (fav or non-fav) ran into conflict (failed)",
	.pme_long_desc = "TM Load (fav or non-fav) ran into conflict (failed)",
},
[ POWER8_PME_PM_TM_RST_SC ] = {
	.pme_name = "PM_TM_RST_SC",
	.pme_code = 0x328086,
	.pme_short_desc = "tm snp rst tm sc",
	.pme_long_desc = "tm snp rst tm sc",
},
[ POWER8_PME_PM_TM_SC_CO ] = {
	.pme_name = "PM_TM_SC_CO",
	.pme_code = 0x318080,
	.pme_short_desc = "l3 castout tm Sc line",
	.pme_long_desc = "l3 castout tm Sc line",
},
[ POWER8_PME_PM_TM_ST_CAUSED_FAIL ] = {
	.pme_name = "PM_TM_ST_CAUSED_FAIL",
	.pme_code = 0x73708a,
	.pme_short_desc = "TM Store (fav or non-fav) caused another thread to fail",
	.pme_long_desc = "TM Store (fav or non-fav) caused another thread to fail",
},
[ POWER8_PME_PM_TM_ST_CONF ] = {
	.pme_name = "PM_TM_ST_CONF",
	.pme_code = 0x737088,
	.pme_short_desc = "TM Store (fav or non-fav) ran into conflict (failed)",
	.pme_long_desc = "TM Store (fav or non-fav) ran into conflict (failed)",
},
[ POWER8_PME_PM_TM_TBEGIN ] = {
	.pme_name = "PM_TM_TBEGIN",
	.pme_code = 0x20bc,
	.pme_short_desc = "Tm nested tbegin",
	.pme_long_desc = "Tm nested tbegin",
},
[ POWER8_PME_PM_TM_TRANS_RUN_CYC ] = {
	.pme_name = "PM_TM_TRANS_RUN_CYC",
	.pme_code = 0x10060,
	.pme_short_desc = "run cycles in transactional state",
	.pme_long_desc = "run cycles in transactional state.",
},
[ POWER8_PME_PM_TM_TRANS_RUN_INST ] = {
	.pme_name = "PM_TM_TRANS_RUN_INST",
	.pme_code = 0x30060,
	.pme_short_desc = "Instructions completed in transactional state",
	.pme_long_desc = "Instructions completed in transactional state.",
},
[ POWER8_PME_PM_TM_TRESUME ] = {
	.pme_name = "PM_TM_TRESUME",
	.pme_code = 0x3080,
	.pme_short_desc = "Tm resume",
	.pme_long_desc = "Tm resume",
},
[ POWER8_PME_PM_TM_TSUSPEND ] = {
	.pme_name = "PM_TM_TSUSPEND",
	.pme_code = 0x20be,
	.pme_short_desc = "Tm suspend",
	.pme_long_desc = "Tm suspend",
},
[ POWER8_PME_PM_TM_TX_PASS_RUN_CYC ] = {
	.pme_name = "PM_TM_TX_PASS_RUN_CYC",
	.pme_code = 0x2e012,
	.pme_short_desc = "cycles spent in successful transactions",
	.pme_long_desc = "run cycles spent in successful transactions.",
},
[ POWER8_PME_PM_TM_TX_PASS_RUN_INST ] = {
	.pme_name = "PM_TM_TX_PASS_RUN_INST",
	.pme_code = 0x4e014,
	.pme_short_desc = "run instructions spent in successful transactions.",
	.pme_long_desc = "run instructions spent in successful transactions.",
},
[ POWER8_PME_PM_UP_PREF_L3 ] = {
	.pme_name = "PM_UP_PREF_L3",
	.pme_code = 0xe08c,
	.pme_short_desc = "Micropartition prefetch",
	.pme_long_desc = "Micropartition prefetch42",
},
[ POWER8_PME_PM_UP_PREF_POINTER ] = {
	.pme_name = "PM_UP_PREF_POINTER",
	.pme_code = 0xe08e,
	.pme_short_desc = "Micrpartition pointer prefetches",
	.pme_long_desc = "Micrpartition pointer prefetches42",
},
[ POWER8_PME_PM_VSU0_16FLOP ] = {
	.pme_name = "PM_VSU0_16FLOP",
	.pme_code = 0xa0a4,
	.pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)",
	.pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)",
},
[ POWER8_PME_PM_VSU0_1FLOP ] = {
	.pme_name = "PM_VSU0_1FLOP",
	.pme_code = 0xa080,
	.pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished",
	.pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route(eg x1, x2, x4) Only if instr sends finish to ISU",
},
[ POWER8_PME_PM_VSU0_2FLOP ] = {
	.pme_name = "PM_VSU0_2FLOP",
	.pme_code = 0xa098,
	.pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
	.pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
},
[ POWER8_PME_PM_VSU0_4FLOP ] = {
	.pme_name = "PM_VSU0_4FLOP",
	.pme_code = 0xa09c,
	.pme_short_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)",
	.pme_long_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)",
},
[ POWER8_PME_PM_VSU0_8FLOP ] = {
	.pme_name = "PM_VSU0_8FLOP",
	.pme_code = 0xa0a0,
	.pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)",
	.pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)",
},
[ POWER8_PME_PM_VSU0_COMPLEX_ISSUED ] = {
	.pme_name = "PM_VSU0_COMPLEX_ISSUED",
	.pme_code = 0xb0a4,
	.pme_short_desc = "Complex VMX instruction issued",
	.pme_long_desc = "Complex VMX instruction issued",
},
[ POWER8_PME_PM_VSU0_CY_ISSUED ] = {
	.pme_name = "PM_VSU0_CY_ISSUED",
	.pme_code = 0xb0b4,
	.pme_short_desc = "Cryptographic instruction RFC02196 Issued",
	.pme_long_desc = "Cryptographic instruction RFC02196 Issued",
},
[ POWER8_PME_PM_VSU0_DD_ISSUED ] = {
	.pme_name = "PM_VSU0_DD_ISSUED",
	.pme_code = 0xb0a8,
	.pme_short_desc = "64BIT Decimal Issued",
	.pme_long_desc = "64BIT Decimal Issued",
},
[ POWER8_PME_PM_VSU0_DP_2FLOP ] = {
	.pme_name = "PM_VSU0_DP_2FLOP",
	.pme_code = 0xa08c,
	.pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg",
	.pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg",
},
[ POWER8_PME_PM_VSU0_DP_FMA ] = {
	.pme_name = "PM_VSU0_DP_FMA",
	.pme_code = 0xa090,
	.pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub",
	.pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub",
},
[ POWER8_PME_PM_VSU0_DP_FSQRT_FDIV ] = {
	.pme_name = "PM_VSU0_DP_FSQRT_FDIV",
	.pme_code = 0xa094,
	.pme_short_desc = "DP vector versions of fdiv,fsqrt",
	.pme_long_desc = "DP vector versions of fdiv,fsqrt",
},
[ POWER8_PME_PM_VSU0_DQ_ISSUED ] = {
	.pme_name = "PM_VSU0_DQ_ISSUED",
	.pme_code = 0xb0ac,
	.pme_short_desc = "128BIT Decimal Issued",
	.pme_long_desc = "128BIT Decimal Issued",
},
[ POWER8_PME_PM_VSU0_EX_ISSUED ] = {
	.pme_name = "PM_VSU0_EX_ISSUED",
	.pme_code = 0xb0b0,
	.pme_short_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued",
	.pme_long_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued",
},
[ POWER8_PME_PM_VSU0_FIN ] = {
	.pme_name = "PM_VSU0_FIN",
	.pme_code = 0xa0bc,
	.pme_short_desc = "VSU0 Finished an instruction",
	.pme_long_desc = "VSU0 Finished an instruction",
},
[ POWER8_PME_PM_VSU0_FMA ] = {
	.pme_name = "PM_VSU0_FMA",
	.pme_code = 0xa084,
	.pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
	.pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
},
[ POWER8_PME_PM_VSU0_FPSCR ] = {
	.pme_name = "PM_VSU0_FPSCR",
	.pme_code = 0xb098,
	.pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
	.pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
},
[ POWER8_PME_PM_VSU0_FSQRT_FDIV ] = {
	.pme_name = "PM_VSU0_FSQRT_FDIV",
	.pme_code = 0xa088,
	.pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
	.pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
},
[ POWER8_PME_PM_VSU0_PERMUTE_ISSUED ] = {
	.pme_name = "PM_VSU0_PERMUTE_ISSUED",
	.pme_code = 0xb090,
	.pme_short_desc = "Permute VMX Instruction Issued",
	.pme_long_desc = "Permute VMX Instruction Issued",
},
[ POWER8_PME_PM_VSU0_SCALAR_DP_ISSUED ] = {
	.pme_name = "PM_VSU0_SCALAR_DP_ISSUED",
	.pme_code = 0xb088,
	.pme_short_desc = "Double Precision scalar instruction issued on Pipe0",
	.pme_long_desc = "Double Precision scalar instruction issued on Pipe0",
},
[ POWER8_PME_PM_VSU0_SIMPLE_ISSUED ] = {
	.pme_name = "PM_VSU0_SIMPLE_ISSUED",
	.pme_code = 0xb094,
	.pme_short_desc = "Simple VMX instruction issued",
	.pme_long_desc = "Simple VMX instruction issued",
},
[ POWER8_PME_PM_VSU0_SINGLE ] = {
	.pme_name = "PM_VSU0_SINGLE",
	.pme_code = 0xa0a8,
	.pme_short_desc = "FPU single precision",
	.pme_long_desc = "FPU single precision",
},
[ POWER8_PME_PM_VSU0_SQ ] = {
	.pme_name = "PM_VSU0_SQ",
	.pme_code = 0xb09c,
	.pme_short_desc = "Store Vector Issued",
	.pme_long_desc = "Store Vector Issued",
},
[ POWER8_PME_PM_VSU0_STF ] = {
	.pme_name = "PM_VSU0_STF",
	.pme_code = 0xb08c,
	.pme_short_desc = "FPU store (SP or DP) issued on Pipe0",
	.pme_long_desc = "FPU store (SP or DP) issued on Pipe0",
},
[ POWER8_PME_PM_VSU0_VECTOR_DP_ISSUED ] = {
	.pme_name = "PM_VSU0_VECTOR_DP_ISSUED",
	.pme_code = 0xb080,
	.pme_short_desc = "Double Precision vector instruction issued on Pipe0",
	.pme_long_desc = "Double Precision vector instruction issued on Pipe0",
},
[ POWER8_PME_PM_VSU0_VECTOR_SP_ISSUED ] = {
	.pme_name = "PM_VSU0_VECTOR_SP_ISSUED",
	.pme_code = 0xb084,
	.pme_short_desc = "Single Precision vector instruction issued (executed)",
	.pme_long_desc = "Single Precision vector instruction issued (executed)",
},
[ POWER8_PME_PM_VSU1_16FLOP ] = {
	.pme_name = "PM_VSU1_16FLOP",
	.pme_code = 0xa0a6,
	.pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)",
	.pme_long_desc = "Sixteen flops operation (SP vector versions of fdiv,fsqrt)",
},
[ POWER8_PME_PM_VSU1_1FLOP ] = {
	.pme_name = "PM_VSU1_1FLOP",
	.pme_code = 0xa082,
	.pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished",
	.pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished",
},
[ POWER8_PME_PM_VSU1_2FLOP ] = {
	.pme_name = "PM_VSU1_2FLOP",
	.pme_code = 0xa09a,
	.pme_short_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
	.pme_long_desc = "two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)",
},
[ POWER8_PME_PM_VSU1_4FLOP ] = {
	.pme_name = "PM_VSU1_4FLOP",
	.pme_code = 0xa09e,
	.pme_short_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)",
	.pme_long_desc = "four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions)",
},
[ POWER8_PME_PM_VSU1_8FLOP ] = {
	.pme_name = "PM_VSU1_8FLOP",
	.pme_code = 0xa0a2,
	.pme_short_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)",
	.pme_long_desc = "eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)",
},
[ POWER8_PME_PM_VSU1_COMPLEX_ISSUED ] = {
	.pme_name = "PM_VSU1_COMPLEX_ISSUED",
	.pme_code = 0xb0a6,
	.pme_short_desc = "Complex VMX instruction issued",
	.pme_long_desc = "Complex VMX instruction issued",
},
[ POWER8_PME_PM_VSU1_CY_ISSUED ] = {
	.pme_name = "PM_VSU1_CY_ISSUED",
	.pme_code = 0xb0b6,
	.pme_short_desc = "Cryptographic instruction RFC02196 Issued",
	.pme_long_desc = "Cryptographic instruction RFC02196 Issued",
},
[ POWER8_PME_PM_VSU1_DD_ISSUED ] = {
	.pme_name = "PM_VSU1_DD_ISSUED",
	.pme_code = 0xb0aa,
	.pme_short_desc = "64BIT Decimal Issued",
	.pme_long_desc = "64BIT Decimal Issued",
},
[ POWER8_PME_PM_VSU1_DP_2FLOP ] = {
	.pme_name = "PM_VSU1_DP_2FLOP",
	.pme_code = 0xa08e,
	.pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg",
	.pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg",
},
[ POWER8_PME_PM_VSU1_DP_FMA ] = {
	.pme_name = "PM_VSU1_DP_FMA",
	.pme_code = 0xa092,
	.pme_short_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub",
	.pme_long_desc = "DP vector version of fmadd,fnmadd,fmsub,fnmsub",
},
[ POWER8_PME_PM_VSU1_DP_FSQRT_FDIV ] = {
	.pme_name = "PM_VSU1_DP_FSQRT_FDIV",
	.pme_code = 0xa096,
	.pme_short_desc = "DP vector versions of fdiv,fsqrt",
	.pme_long_desc = "DP vector versions of fdiv,fsqrt",
},
[ POWER8_PME_PM_VSU1_DQ_ISSUED ] = {
	.pme_name = "PM_VSU1_DQ_ISSUED",
	.pme_code = 0xb0ae,
	.pme_short_desc = "128BIT Decimal Issued",
	.pme_long_desc = "128BIT Decimal Issued",
},
[ POWER8_PME_PM_VSU1_EX_ISSUED ] = {
	.pme_name = "PM_VSU1_EX_ISSUED",
	.pme_code = 0xb0b2,
	.pme_short_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued",
	.pme_long_desc = "Direct move 32/64b VRFtoGPR RFC02206 Issued",
},
[ POWER8_PME_PM_VSU1_FIN ] = {
	.pme_name = "PM_VSU1_FIN",
	.pme_code = 0xa0be,
	.pme_short_desc = "VSU1 Finished an instruction",
	.pme_long_desc = "VSU1 Finished an instruction",
},
[ POWER8_PME_PM_VSU1_FMA ] = {
	.pme_name = "PM_VSU1_FMA",
	.pme_code = 0xa086,
	.pme_short_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
	.pme_long_desc = "two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!",
},
[ POWER8_PME_PM_VSU1_FPSCR ] = {
	.pme_name = "PM_VSU1_FPSCR",
	.pme_code = 0xb09a,
	.pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
	.pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0",
},
[ POWER8_PME_PM_VSU1_FSQRT_FDIV ] = {
	.pme_name = "PM_VSU1_FSQRT_FDIV",
	.pme_code = 0xa08a,
	.pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
	.pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only!",
},
[ POWER8_PME_PM_VSU1_PERMUTE_ISSUED ] = {
	.pme_name = "PM_VSU1_PERMUTE_ISSUED",
	.pme_code = 0xb092,
	.pme_short_desc = "Permute VMX Instruction Issued",
	.pme_long_desc = "Permute VMX Instruction Issued",
},
[ POWER8_PME_PM_VSU1_SCALAR_DP_ISSUED ] = {
	.pme_name = "PM_VSU1_SCALAR_DP_ISSUED",
	.pme_code = 0xb08a,
	.pme_short_desc = "Double Precision scalar instruction issued on Pipe1",
	.pme_long_desc = "Double Precision scalar instruction issued on Pipe1",
},
[ POWER8_PME_PM_VSU1_SIMPLE_ISSUED ] = {
	.pme_name = "PM_VSU1_SIMPLE_ISSUED",
	.pme_code = 0xb096,
	.pme_short_desc = "Simple VMX instruction issued",
	.pme_long_desc = "Simple VMX instruction issued",
},
[ POWER8_PME_PM_VSU1_SINGLE ] = {
	.pme_name = "PM_VSU1_SINGLE",
	.pme_code = 0xa0aa,
	.pme_short_desc = "FPU single precision",
	.pme_long_desc = "FPU single precision",
},
[ POWER8_PME_PM_VSU1_SQ ] = {
	.pme_name = "PM_VSU1_SQ",
	.pme_code = 0xb09e,
	.pme_short_desc = "Store Vector Issued",
	.pme_long_desc = "Store Vector Issued",
},
[ POWER8_PME_PM_VSU1_STF ] = {
	.pme_name = "PM_VSU1_STF",
	.pme_code = 0xb08e,
	.pme_short_desc = "FPU store (SP or DP) issued on Pipe1",
	.pme_long_desc = "FPU store (SP or DP) issued on Pipe1",
},
[ POWER8_PME_PM_VSU1_VECTOR_DP_ISSUED ] = {
	.pme_name = "PM_VSU1_VECTOR_DP_ISSUED",
	.pme_code = 0xb082,
	.pme_short_desc = "Double Precision vector instruction issued on Pipe1",
	.pme_long_desc = "Double Precision vector instruction issued on Pipe1",
},
[ POWER8_PME_PM_VSU1_VECTOR_SP_ISSUED ] = {
	.pme_name = "PM_VSU1_VECTOR_SP_ISSUED",
	.pme_code = 0xb086,
	.pme_short_desc = "Single Precision vector instruction issued (executed)",
	.pme_long_desc = "Single Precision vector instruction issued (executed)",
},
};
#endif