//-------------------------------------------------------------------------------- // Auto-generated by Migen (811d135) & LiteX (5da0bcbd) on 2019-12-29 19:13:39 //-------------------------------------------------------------------------------- module dut( input sys_clk, output serial_source_valid, input serial_source_ready, output [7:0] serial_source_data, input serial_sink_valid, output serial_sink_ready, input [7:0] serial_sink_data ); wire main_soclinux_ctrl_reset_reset_re; wire main_soclinux_ctrl_reset_reset_r; wire main_soclinux_ctrl_reset_reset_we; reg main_soclinux_ctrl_reset_reset_w = 1'd0; reg [31:0] main_soclinux_ctrl_storage = 32'd305419896; reg main_soclinux_ctrl_re = 1'd0; wire [31:0] main_soclinux_ctrl_bus_errors_status; wire main_soclinux_ctrl_bus_errors_we; wire main_soclinux_ctrl_reset; wire main_soclinux_ctrl_bus_error; reg [31:0] main_soclinux_ctrl_bus_errors = 32'd0; wire main_soclinux_cpu_reset; wire [29:0] main_soclinux_cpu_ibus_adr; wire [31:0] main_soclinux_cpu_ibus_dat_w; wire [31:0] main_soclinux_cpu_ibus_dat_r; wire [3:0] main_soclinux_cpu_ibus_sel; wire main_soclinux_cpu_ibus_cyc; wire main_soclinux_cpu_ibus_stb; wire main_soclinux_cpu_ibus_ack; wire main_soclinux_cpu_ibus_we; wire [2:0] main_soclinux_cpu_ibus_cti; wire [1:0] main_soclinux_cpu_ibus_bte; wire main_soclinux_cpu_ibus_err; wire [29:0] main_soclinux_cpu_dbus_adr; wire [31:0] main_soclinux_cpu_dbus_dat_w; wire [31:0] main_soclinux_cpu_dbus_dat_r; wire [3:0] main_soclinux_cpu_dbus_sel; wire main_soclinux_cpu_dbus_cyc; wire main_soclinux_cpu_dbus_stb; wire main_soclinux_cpu_dbus_ack; wire main_soclinux_cpu_dbus_we; wire [2:0] main_soclinux_cpu_dbus_cti; wire [1:0] main_soclinux_cpu_dbus_bte; wire main_soclinux_cpu_dbus_err; reg [31:0] main_soclinux_cpu_interrupt0 = 32'd0; wire main_soclinux_cpu_latch_re; wire main_soclinux_cpu_latch_r; wire main_soclinux_cpu_latch_we; reg main_soclinux_cpu_latch_w = 1'd0; reg [63:0] main_soclinux_cpu_time_status = 64'd0; wire main_soclinux_cpu_time_we; reg [63:0] main_soclinux_cpu_time_cmp_storage = 64'd18446744073709551615; reg main_soclinux_cpu_time_cmp_re = 1'd0; wire main_soclinux_cpu_interrupt1; reg [63:0] main_soclinux_cpu_time = 64'd0; reg [63:0] main_soclinux_cpu_time_cmp = 64'd18446744073709551615; wire [29:0] main_soclinux_interface0_soc_bus_adr; wire [31:0] main_soclinux_interface0_soc_bus_dat_w; wire [31:0] main_soclinux_interface0_soc_bus_dat_r; wire [3:0] main_soclinux_interface0_soc_bus_sel; wire main_soclinux_interface0_soc_bus_cyc; wire main_soclinux_interface0_soc_bus_stb; wire main_soclinux_interface0_soc_bus_ack; wire main_soclinux_interface0_soc_bus_we; wire [2:0] main_soclinux_interface0_soc_bus_cti; wire [1:0] main_soclinux_interface0_soc_bus_bte; wire main_soclinux_interface0_soc_bus_err; wire [29:0] main_soclinux_interface1_soc_bus_adr; wire [31:0] main_soclinux_interface1_soc_bus_dat_w; wire [31:0] main_soclinux_interface1_soc_bus_dat_r; wire [3:0] main_soclinux_interface1_soc_bus_sel; wire main_soclinux_interface1_soc_bus_cyc; wire main_soclinux_interface1_soc_bus_stb; wire main_soclinux_interface1_soc_bus_ack; wire main_soclinux_interface1_soc_bus_we; wire [2:0] main_soclinux_interface1_soc_bus_cti; wire [1:0] main_soclinux_interface1_soc_bus_bte; wire main_soclinux_interface1_soc_bus_err; wire [29:0] main_soclinux_rom_bus_adr; wire [31:0] main_soclinux_rom_bus_dat_w; wire [31:0] main_soclinux_rom_bus_dat_r; wire [3:0] main_soclinux_rom_bus_sel; wire main_soclinux_rom_bus_cyc; wire main_soclinux_rom_bus_stb; reg main_soclinux_rom_bus_ack = 1'd0; wire main_soclinux_rom_bus_we; wire [2:0] main_soclinux_rom_bus_cti; wire [1:0] main_soclinux_rom_bus_bte; reg main_soclinux_rom_bus_err = 1'd0; wire [12:0] main_soclinux_rom_adr; wire [31:0] main_soclinux_rom_dat_r; wire [29:0] main_soclinux_sram_bus_adr; wire [31:0] main_soclinux_sram_bus_dat_w; wire [31:0] main_soclinux_sram_bus_dat_r; wire [3:0] main_soclinux_sram_bus_sel; wire main_soclinux_sram_bus_cyc; wire main_soclinux_sram_bus_stb; reg main_soclinux_sram_bus_ack = 1'd0; wire main_soclinux_sram_bus_we; wire [2:0] main_soclinux_sram_bus_cti; wire [1:0] main_soclinux_sram_bus_bte; reg main_soclinux_sram_bus_err = 1'd0; wire [9:0] main_soclinux_sram_adr; wire [31:0] main_soclinux_sram_dat_r; reg [3:0] main_soclinux_sram_we = 4'd0; wire [31:0] main_soclinux_sram_dat_w; wire [29:0] main_soclinux_main_ram_bus_adr; wire [31:0] main_soclinux_main_ram_bus_dat_w; wire [31:0] main_soclinux_main_ram_bus_dat_r; wire [3:0] main_soclinux_main_ram_bus_sel; wire main_soclinux_main_ram_bus_cyc; wire main_soclinux_main_ram_bus_stb; reg main_soclinux_main_ram_bus_ack = 1'd0; wire main_soclinux_main_ram_bus_we; wire [2:0] main_soclinux_main_ram_bus_cti; wire [1:0] main_soclinux_main_ram_bus_bte; reg main_soclinux_main_ram_bus_err = 1'd0; wire [22:0] main_soclinux_main_ram_adr; wire [31:0] main_soclinux_main_ram_dat_r; reg [3:0] main_soclinux_main_ram_we = 4'd0; wire [31:0] main_soclinux_main_ram_dat_w; reg [31:0] main_soclinux_load_storage = 32'd0; reg main_soclinux_load_re = 1'd0; reg [31:0] main_soclinux_reload_storage = 32'd0; reg main_soclinux_reload_re = 1'd0; reg main_soclinux_en_storage = 1'd0; reg main_soclinux_en_re = 1'd0; reg main_soclinux_update_value_storage = 1'd0; reg main_soclinux_update_value_re = 1'd0; reg [31:0] main_soclinux_value_status = 32'd0; wire main_soclinux_value_we; wire main_soclinux_irq; wire main_soclinux_zero_status; reg main_soclinux_zero_pending = 1'd0; wire main_soclinux_zero_trigger; reg main_soclinux_zero_clear = 1'd0; reg main_soclinux_zero_old_trigger = 1'd0; wire main_soclinux_eventmanager_status_re; wire main_soclinux_eventmanager_status_r; wire main_soclinux_eventmanager_status_we; wire main_soclinux_eventmanager_status_w; wire main_soclinux_eventmanager_pending_re; wire main_soclinux_eventmanager_pending_r; wire main_soclinux_eventmanager_pending_we; wire main_soclinux_eventmanager_pending_w; reg main_soclinux_eventmanager_storage = 1'd0; reg main_soclinux_eventmanager_re = 1'd0; reg [31:0] main_soclinux_value = 32'd0; reg [13:0] main_soclinux_interface_adr = 14'd0; reg main_soclinux_interface_we = 1'd0; wire [7:0] main_soclinux_interface_dat_w; wire [7:0] main_soclinux_interface_dat_r; wire [29:0] main_soclinux_bus_wishbone_adr; wire [31:0] main_soclinux_bus_wishbone_dat_w; wire [31:0] main_soclinux_bus_wishbone_dat_r; wire [3:0] main_soclinux_bus_wishbone_sel; wire main_soclinux_bus_wishbone_cyc; wire main_soclinux_bus_wishbone_stb; reg main_soclinux_bus_wishbone_ack = 1'd0; wire main_soclinux_bus_wishbone_we; wire [2:0] main_soclinux_bus_wishbone_cti; wire [1:0] main_soclinux_bus_wishbone_bte; reg main_soclinux_bus_wishbone_err = 1'd0; wire main_finish_finish_re; wire main_finish_finish_r; wire main_finish_finish_we; reg main_finish_finish_w = 1'd0; reg main_finish = 1'd0; wire sys_clk_1; wire sys_rst; wire por_clk; reg main_int_rst = 1'd1; wire [29:0] main_bus_adr; wire [31:0] main_bus_dat_w; wire [31:0] main_bus_dat_r; wire [3:0] main_bus_sel; wire main_bus_cyc; wire main_bus_stb; reg main_bus_ack = 1'd0; wire main_bus_we; wire [2:0] main_bus_cti; wire [1:0] main_bus_bte; reg main_bus_err = 1'd0; wire [11:0] main_adr; wire [31:0] main_dat_r; reg [3:0] main_we = 4'd0; wire [31:0] main_dat_w; wire main_sink_valid; wire main_sink_ready; wire main_sink_first; wire main_sink_last; wire [7:0] main_sink_payload_data; wire main_source_valid; wire main_source_ready; reg main_source_first = 1'd0; reg main_source_last = 1'd0; wire [7:0] main_source_payload_data; wire main_uart_rxtx_re; wire [7:0] main_uart_rxtx_r; wire main_uart_rxtx_we; wire [7:0] main_uart_rxtx_w; wire main_uart_txfull_status; wire main_uart_txfull_we; wire main_uart_rxempty_status; wire main_uart_rxempty_we; wire main_uart_irq; wire main_uart_tx_status; reg main_uart_tx_pending = 1'd0; wire main_uart_tx_trigger; reg main_uart_tx_clear = 1'd0; reg main_uart_tx_old_trigger = 1'd0; wire main_uart_rx_status; reg main_uart_rx_pending = 1'd0; wire main_uart_rx_trigger; reg main_uart_rx_clear = 1'd0; reg main_uart_rx_old_trigger = 1'd0; wire main_uart_eventmanager_status_re; wire [1:0] main_uart_eventmanager_status_r; wire main_uart_eventmanager_status_we; reg [1:0] main_uart_eventmanager_status_w = 2'd0; wire main_uart_eventmanager_pending_re; wire [1:0] main_uart_eventmanager_pending_r; wire main_uart_eventmanager_pending_we; reg [1:0] main_uart_eventmanager_pending_w = 2'd0; reg [1:0] main_uart_eventmanager_storage = 2'd0; reg main_uart_eventmanager_re = 1'd0; wire main_uart_tx_fifo_sink_valid; wire main_uart_tx_fifo_sink_ready; reg main_uart_tx_fifo_sink_first = 1'd0; reg main_uart_tx_fifo_sink_last = 1'd0; wire [7:0] main_uart_tx_fifo_sink_payload_data; wire main_uart_tx_fifo_source_valid; wire main_uart_tx_fifo_source_ready; wire main_uart_tx_fifo_source_first; wire main_uart_tx_fifo_source_last; wire [7:0] main_uart_tx_fifo_source_payload_data; wire main_uart_tx_fifo_re; reg main_uart_tx_fifo_readable = 1'd0; wire main_uart_tx_fifo_syncfifo_we; wire main_uart_tx_fifo_syncfifo_writable; wire main_uart_tx_fifo_syncfifo_re; wire main_uart_tx_fifo_syncfifo_readable; wire [9:0] main_uart_tx_fifo_syncfifo_din; wire [9:0] main_uart_tx_fifo_syncfifo_dout; reg [4:0] main_uart_tx_fifo_level0 = 5'd0; reg main_uart_tx_fifo_replace = 1'd0; reg [3:0] main_uart_tx_fifo_produce = 4'd0; reg [3:0] main_uart_tx_fifo_consume = 4'd0; reg [3:0] main_uart_tx_fifo_wrport_adr = 4'd0; wire [9:0] main_uart_tx_fifo_wrport_dat_r; wire main_uart_tx_fifo_wrport_we; wire [9:0] main_uart_tx_fifo_wrport_dat_w; wire main_uart_tx_fifo_do_read; wire [3:0] main_uart_tx_fifo_rdport_adr; wire [9:0] main_uart_tx_fifo_rdport_dat_r; wire main_uart_tx_fifo_rdport_re; wire [4:0] main_uart_tx_fifo_level1; wire [7:0] main_uart_tx_fifo_fifo_in_payload_data; wire main_uart_tx_fifo_fifo_in_first; wire main_uart_tx_fifo_fifo_in_last; wire [7:0] main_uart_tx_fifo_fifo_out_payload_data; wire main_uart_tx_fifo_fifo_out_first; wire main_uart_tx_fifo_fifo_out_last; wire main_uart_rx_fifo_sink_valid; wire main_uart_rx_fifo_sink_ready; wire main_uart_rx_fifo_sink_first; wire main_uart_rx_fifo_sink_last; wire [7:0] main_uart_rx_fifo_sink_payload_data; wire main_uart_rx_fifo_source_valid; wire main_uart_rx_fifo_source_ready; wire main_uart_rx_fifo_source_first; wire main_uart_rx_fifo_source_last; wire [7:0] main_uart_rx_fifo_source_payload_data; wire main_uart_rx_fifo_re; reg main_uart_rx_fifo_readable = 1'd0; wire main_uart_rx_fifo_syncfifo_we; wire main_uart_rx_fifo_syncfifo_writable; wire main_uart_rx_fifo_syncfifo_re; wire main_uart_rx_fifo_syncfifo_readable; wire [9:0] main_uart_rx_fifo_syncfifo_din; wire [9:0] main_uart_rx_fifo_syncfifo_dout; reg [4:0] main_uart_rx_fifo_level0 = 5'd0; reg main_uart_rx_fifo_replace = 1'd0; reg [3:0] main_uart_rx_fifo_produce = 4'd0; reg [3:0] main_uart_rx_fifo_consume = 4'd0; reg [3:0] main_uart_rx_fifo_wrport_adr = 4'd0; wire [9:0] main_uart_rx_fifo_wrport_dat_r; wire main_uart_rx_fifo_wrport_we; wire [9:0] main_uart_rx_fifo_wrport_dat_w; wire main_uart_rx_fifo_do_read; wire [3:0] main_uart_rx_fifo_rdport_adr; wire [9:0] main_uart_rx_fifo_rdport_dat_r; wire main_uart_rx_fifo_rdport_re; wire [4:0] main_uart_rx_fifo_level1; wire [7:0] main_uart_rx_fifo_fifo_in_payload_data; wire main_uart_rx_fifo_fifo_in_first; wire main_uart_rx_fifo_fifo_in_last; wire [7:0] main_uart_rx_fifo_fifo_out_payload_data; wire main_uart_rx_fifo_fifo_out_first; wire main_uart_rx_fifo_fifo_out_last; reg builder_state = 1'd0; reg builder_next_state = 1'd0; wire [29:0] builder_shared_adr; wire [31:0] builder_shared_dat_w; reg [31:0] builder_shared_dat_r = 32'd0; wire [3:0] builder_shared_sel; wire builder_shared_cyc; wire builder_shared_stb; reg builder_shared_ack = 1'd0; wire builder_shared_we; wire [2:0] builder_shared_cti; wire [1:0] builder_shared_bte; wire builder_shared_err; wire [1:0] builder_request; reg builder_grant = 1'd0; reg [4:0] builder_slave_sel = 5'd0; reg [4:0] builder_slave_sel_r = 5'd0; reg builder_error = 1'd0; wire builder_wait; wire builder_done; reg [19:0] builder_count = 20'd1000000; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; wire [7:0] builder_interface0_bank_bus_dat_w; reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; wire builder_csrbank0_timer_time7_re; wire [7:0] builder_csrbank0_timer_time7_r; wire builder_csrbank0_timer_time7_we; wire [7:0] builder_csrbank0_timer_time7_w; wire builder_csrbank0_timer_time6_re; wire [7:0] builder_csrbank0_timer_time6_r; wire builder_csrbank0_timer_time6_we; wire [7:0] builder_csrbank0_timer_time6_w; wire builder_csrbank0_timer_time5_re; wire [7:0] builder_csrbank0_timer_time5_r; wire builder_csrbank0_timer_time5_we; wire [7:0] builder_csrbank0_timer_time5_w; wire builder_csrbank0_timer_time4_re; wire [7:0] builder_csrbank0_timer_time4_r; wire builder_csrbank0_timer_time4_we; wire [7:0] builder_csrbank0_timer_time4_w; wire builder_csrbank0_timer_time3_re; wire [7:0] builder_csrbank0_timer_time3_r; wire builder_csrbank0_timer_time3_we; wire [7:0] builder_csrbank0_timer_time3_w; wire builder_csrbank0_timer_time2_re; wire [7:0] builder_csrbank0_timer_time2_r; wire builder_csrbank0_timer_time2_we; wire [7:0] builder_csrbank0_timer_time2_w; wire builder_csrbank0_timer_time1_re; wire [7:0] builder_csrbank0_timer_time1_r; wire builder_csrbank0_timer_time1_we; wire [7:0] builder_csrbank0_timer_time1_w; wire builder_csrbank0_timer_time0_re; wire [7:0] builder_csrbank0_timer_time0_r; wire builder_csrbank0_timer_time0_we; wire [7:0] builder_csrbank0_timer_time0_w; wire builder_csrbank0_timer_time_cmp7_re; wire [7:0] builder_csrbank0_timer_time_cmp7_r; wire builder_csrbank0_timer_time_cmp7_we; wire [7:0] builder_csrbank0_timer_time_cmp7_w; wire builder_csrbank0_timer_time_cmp6_re; wire [7:0] builder_csrbank0_timer_time_cmp6_r; wire builder_csrbank0_timer_time_cmp6_we; wire [7:0] builder_csrbank0_timer_time_cmp6_w; wire builder_csrbank0_timer_time_cmp5_re; wire [7:0] builder_csrbank0_timer_time_cmp5_r; wire builder_csrbank0_timer_time_cmp5_we; wire [7:0] builder_csrbank0_timer_time_cmp5_w; wire builder_csrbank0_timer_time_cmp4_re; wire [7:0] builder_csrbank0_timer_time_cmp4_r; wire builder_csrbank0_timer_time_cmp4_we; wire [7:0] builder_csrbank0_timer_time_cmp4_w; wire builder_csrbank0_timer_time_cmp3_re; wire [7:0] builder_csrbank0_timer_time_cmp3_r; wire builder_csrbank0_timer_time_cmp3_we; wire [7:0] builder_csrbank0_timer_time_cmp3_w; wire builder_csrbank0_timer_time_cmp2_re; wire [7:0] builder_csrbank0_timer_time_cmp2_r; wire builder_csrbank0_timer_time_cmp2_we; wire [7:0] builder_csrbank0_timer_time_cmp2_w; wire builder_csrbank0_timer_time_cmp1_re; wire [7:0] builder_csrbank0_timer_time_cmp1_r; wire builder_csrbank0_timer_time_cmp1_we; wire [7:0] builder_csrbank0_timer_time_cmp1_w; wire builder_csrbank0_timer_time_cmp0_re; wire [7:0] builder_csrbank0_timer_time_cmp0_r; wire builder_csrbank0_timer_time_cmp0_we; wire [7:0] builder_csrbank0_timer_time_cmp0_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; wire [7:0] builder_interface1_bank_bus_dat_w; reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; wire builder_csrbank1_scratch3_re; wire [7:0] builder_csrbank1_scratch3_r; wire builder_csrbank1_scratch3_we; wire [7:0] builder_csrbank1_scratch3_w; wire builder_csrbank1_scratch2_re; wire [7:0] builder_csrbank1_scratch2_r; wire builder_csrbank1_scratch2_we; wire [7:0] builder_csrbank1_scratch2_w; wire builder_csrbank1_scratch1_re; wire [7:0] builder_csrbank1_scratch1_r; wire builder_csrbank1_scratch1_we; wire [7:0] builder_csrbank1_scratch1_w; wire builder_csrbank1_scratch0_re; wire [7:0] builder_csrbank1_scratch0_r; wire builder_csrbank1_scratch0_we; wire [7:0] builder_csrbank1_scratch0_w; wire builder_csrbank1_bus_errors3_re; wire [7:0] builder_csrbank1_bus_errors3_r; wire builder_csrbank1_bus_errors3_we; wire [7:0] builder_csrbank1_bus_errors3_w; wire builder_csrbank1_bus_errors2_re; wire [7:0] builder_csrbank1_bus_errors2_r; wire builder_csrbank1_bus_errors2_we; wire [7:0] builder_csrbank1_bus_errors2_w; wire builder_csrbank1_bus_errors1_re; wire [7:0] builder_csrbank1_bus_errors1_r; wire builder_csrbank1_bus_errors1_we; wire [7:0] builder_csrbank1_bus_errors1_w; wire builder_csrbank1_bus_errors0_re; wire [7:0] builder_csrbank1_bus_errors0_r; wire builder_csrbank1_bus_errors0_we; wire [7:0] builder_csrbank1_bus_errors0_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; wire [7:0] builder_interface2_bank_bus_dat_w; reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; wire builder_csrbank2_sel; wire [13:0] builder_interface3_bank_bus_adr; wire builder_interface3_bank_bus_we; wire [7:0] builder_interface3_bank_bus_dat_w; reg [7:0] builder_interface3_bank_bus_dat_r = 8'd0; wire builder_csrbank3_load3_re; wire [7:0] builder_csrbank3_load3_r; wire builder_csrbank3_load3_we; wire [7:0] builder_csrbank3_load3_w; wire builder_csrbank3_load2_re; wire [7:0] builder_csrbank3_load2_r; wire builder_csrbank3_load2_we; wire [7:0] builder_csrbank3_load2_w; wire builder_csrbank3_load1_re; wire [7:0] builder_csrbank3_load1_r; wire builder_csrbank3_load1_we; wire [7:0] builder_csrbank3_load1_w; wire builder_csrbank3_load0_re; wire [7:0] builder_csrbank3_load0_r; wire builder_csrbank3_load0_we; wire [7:0] builder_csrbank3_load0_w; wire builder_csrbank3_reload3_re; wire [7:0] builder_csrbank3_reload3_r; wire builder_csrbank3_reload3_we; wire [7:0] builder_csrbank3_reload3_w; wire builder_csrbank3_reload2_re; wire [7:0] builder_csrbank3_reload2_r; wire builder_csrbank3_reload2_we; wire [7:0] builder_csrbank3_reload2_w; wire builder_csrbank3_reload1_re; wire [7:0] builder_csrbank3_reload1_r; wire builder_csrbank3_reload1_we; wire [7:0] builder_csrbank3_reload1_w; wire builder_csrbank3_reload0_re; wire [7:0] builder_csrbank3_reload0_r; wire builder_csrbank3_reload0_we; wire [7:0] builder_csrbank3_reload0_w; wire builder_csrbank3_en0_re; wire builder_csrbank3_en0_r; wire builder_csrbank3_en0_we; wire builder_csrbank3_en0_w; wire builder_csrbank3_update_value0_re; wire builder_csrbank3_update_value0_r; wire builder_csrbank3_update_value0_we; wire builder_csrbank3_update_value0_w; wire builder_csrbank3_value3_re; wire [7:0] builder_csrbank3_value3_r; wire builder_csrbank3_value3_we; wire [7:0] builder_csrbank3_value3_w; wire builder_csrbank3_value2_re; wire [7:0] builder_csrbank3_value2_r; wire builder_csrbank3_value2_we; wire [7:0] builder_csrbank3_value2_w; wire builder_csrbank3_value1_re; wire [7:0] builder_csrbank3_value1_r; wire builder_csrbank3_value1_we; wire [7:0] builder_csrbank3_value1_w; wire builder_csrbank3_value0_re; wire [7:0] builder_csrbank3_value0_r; wire builder_csrbank3_value0_we; wire [7:0] builder_csrbank3_value0_w; wire builder_csrbank3_ev_enable0_re; wire builder_csrbank3_ev_enable0_r; wire builder_csrbank3_ev_enable0_we; wire builder_csrbank3_ev_enable0_w; wire builder_csrbank3_sel; wire [13:0] builder_interface4_bank_bus_adr; wire builder_interface4_bank_bus_we; wire [7:0] builder_interface4_bank_bus_dat_w; reg [7:0] builder_interface4_bank_bus_dat_r = 8'd0; wire builder_csrbank4_txfull_re; wire builder_csrbank4_txfull_r; wire builder_csrbank4_txfull_we; wire builder_csrbank4_txfull_w; wire builder_csrbank4_rxempty_re; wire builder_csrbank4_rxempty_r; wire builder_csrbank4_rxempty_we; wire builder_csrbank4_rxempty_w; wire builder_csrbank4_ev_enable0_re; wire [1:0] builder_csrbank4_ev_enable0_r; wire builder_csrbank4_ev_enable0_we; wire [1:0] builder_csrbank4_ev_enable0_w; wire builder_csrbank4_sel; wire [13:0] builder_adr; wire builder_we; wire [7:0] builder_dat_w; wire [7:0] builder_dat_r; reg [29:0] builder_array_muxed0 = 30'd0; reg [31:0] builder_array_muxed1 = 32'd0; reg [3:0] builder_array_muxed2 = 4'd0; reg builder_array_muxed3 = 1'd0; reg builder_array_muxed4 = 1'd0; reg builder_array_muxed5 = 1'd0; reg [2:0] builder_array_muxed6 = 3'd0; reg [1:0] builder_array_muxed7 = 2'd0; assign main_soclinux_cpu_reset = main_soclinux_ctrl_reset; assign main_soclinux_ctrl_bus_error = builder_error; always @(*) begin main_soclinux_cpu_interrupt0 = 32'd0; main_soclinux_cpu_interrupt0[1] = main_soclinux_irq; main_soclinux_cpu_interrupt0[0] = main_uart_irq; end assign main_soclinux_ctrl_reset = main_soclinux_ctrl_reset_reset_re; assign main_soclinux_ctrl_bus_errors_status = main_soclinux_ctrl_bus_errors; assign main_soclinux_cpu_interrupt1 = (main_soclinux_cpu_time >= main_soclinux_cpu_time_cmp); assign main_soclinux_interface0_soc_bus_adr = main_soclinux_cpu_ibus_adr; assign main_soclinux_interface0_soc_bus_dat_w = main_soclinux_cpu_ibus_dat_w; assign main_soclinux_cpu_ibus_dat_r = main_soclinux_interface0_soc_bus_dat_r; assign main_soclinux_interface0_soc_bus_sel = main_soclinux_cpu_ibus_sel; assign main_soclinux_interface0_soc_bus_cyc = main_soclinux_cpu_ibus_cyc; assign main_soclinux_interface0_soc_bus_stb = main_soclinux_cpu_ibus_stb; assign main_soclinux_cpu_ibus_ack = main_soclinux_interface0_soc_bus_ack; assign main_soclinux_interface0_soc_bus_we = main_soclinux_cpu_ibus_we; assign main_soclinux_interface0_soc_bus_cti = main_soclinux_cpu_ibus_cti; assign main_soclinux_interface0_soc_bus_bte = main_soclinux_cpu_ibus_bte; assign main_soclinux_cpu_ibus_err = main_soclinux_interface0_soc_bus_err; assign main_soclinux_interface1_soc_bus_adr = main_soclinux_cpu_dbus_adr; assign main_soclinux_interface1_soc_bus_dat_w = main_soclinux_cpu_dbus_dat_w; assign main_soclinux_cpu_dbus_dat_r = main_soclinux_interface1_soc_bus_dat_r; assign main_soclinux_interface1_soc_bus_sel = main_soclinux_cpu_dbus_sel; assign main_soclinux_interface1_soc_bus_cyc = main_soclinux_cpu_dbus_cyc; assign main_soclinux_interface1_soc_bus_stb = main_soclinux_cpu_dbus_stb; assign main_soclinux_cpu_dbus_ack = main_soclinux_interface1_soc_bus_ack; assign main_soclinux_interface1_soc_bus_we = main_soclinux_cpu_dbus_we; assign main_soclinux_interface1_soc_bus_cti = main_soclinux_cpu_dbus_cti; assign main_soclinux_interface1_soc_bus_bte = main_soclinux_cpu_dbus_bte; assign main_soclinux_cpu_dbus_err = main_soclinux_interface1_soc_bus_err; assign main_soclinux_rom_adr = main_soclinux_rom_bus_adr[12:0]; assign main_soclinux_rom_bus_dat_r = main_soclinux_rom_dat_r; always @(*) begin main_soclinux_sram_we = 4'd0; main_soclinux_sram_we[0] = (((main_soclinux_sram_bus_cyc & main_soclinux_sram_bus_stb) & main_soclinux_sram_bus_we) & main_soclinux_sram_bus_sel[0]); main_soclinux_sram_we[1] = (((main_soclinux_sram_bus_cyc & main_soclinux_sram_bus_stb) & main_soclinux_sram_bus_we) & main_soclinux_sram_bus_sel[1]); main_soclinux_sram_we[2] = (((main_soclinux_sram_bus_cyc & main_soclinux_sram_bus_stb) & main_soclinux_sram_bus_we) & main_soclinux_sram_bus_sel[2]); main_soclinux_sram_we[3] = (((main_soclinux_sram_bus_cyc & main_soclinux_sram_bus_stb) & main_soclinux_sram_bus_we) & main_soclinux_sram_bus_sel[3]); end assign main_soclinux_sram_adr = main_soclinux_sram_bus_adr[9:0]; assign main_soclinux_sram_bus_dat_r = main_soclinux_sram_dat_r; assign main_soclinux_sram_dat_w = main_soclinux_sram_bus_dat_w; always @(*) begin main_soclinux_main_ram_we = 4'd0; main_soclinux_main_ram_we[0] = (((main_soclinux_main_ram_bus_cyc & main_soclinux_main_ram_bus_stb) & main_soclinux_main_ram_bus_we) & main_soclinux_main_ram_bus_sel[0]); main_soclinux_main_ram_we[1] = (((main_soclinux_main_ram_bus_cyc & main_soclinux_main_ram_bus_stb) & main_soclinux_main_ram_bus_we) & main_soclinux_main_ram_bus_sel[1]); main_soclinux_main_ram_we[2] = (((main_soclinux_main_ram_bus_cyc & main_soclinux_main_ram_bus_stb) & main_soclinux_main_ram_bus_we) & main_soclinux_main_ram_bus_sel[2]); main_soclinux_main_ram_we[3] = (((main_soclinux_main_ram_bus_cyc & main_soclinux_main_ram_bus_stb) & main_soclinux_main_ram_bus_we) & main_soclinux_main_ram_bus_sel[3]); end assign main_soclinux_main_ram_adr = main_soclinux_main_ram_bus_adr[22:0]; assign main_soclinux_main_ram_bus_dat_r = main_soclinux_main_ram_dat_r; assign main_soclinux_main_ram_dat_w = main_soclinux_main_ram_bus_dat_w; assign main_soclinux_zero_trigger = (main_soclinux_value != 1'd0); assign main_soclinux_eventmanager_status_w = main_soclinux_zero_status; always @(*) begin main_soclinux_zero_clear = 1'd0; if ((main_soclinux_eventmanager_pending_re & main_soclinux_eventmanager_pending_r)) begin main_soclinux_zero_clear = 1'd1; end end assign main_soclinux_eventmanager_pending_w = main_soclinux_zero_pending; assign main_soclinux_irq = (main_soclinux_eventmanager_pending_w & main_soclinux_eventmanager_storage); assign main_soclinux_zero_status = main_soclinux_zero_trigger; assign main_soclinux_interface_dat_w = main_soclinux_bus_wishbone_dat_w; assign main_soclinux_bus_wishbone_dat_r = main_soclinux_interface_dat_r; always @(*) begin builder_next_state = 1'd0; builder_next_state = builder_state; case (builder_state) 1'd1: begin builder_next_state = 1'd0; end default: begin if ((main_soclinux_bus_wishbone_cyc & main_soclinux_bus_wishbone_stb)) begin builder_next_state = 1'd1; end end endcase end always @(*) begin main_soclinux_interface_adr = 14'd0; case (builder_state) 1'd1: begin end default: begin if ((main_soclinux_bus_wishbone_cyc & main_soclinux_bus_wishbone_stb)) begin main_soclinux_interface_adr = main_soclinux_bus_wishbone_adr; end end endcase end always @(*) begin main_soclinux_bus_wishbone_ack = 1'd0; case (builder_state) 1'd1: begin main_soclinux_bus_wishbone_ack = 1'd1; end default: begin end endcase end always @(*) begin main_soclinux_interface_we = 1'd0; case (builder_state) 1'd1: begin end default: begin if ((main_soclinux_bus_wishbone_cyc & main_soclinux_bus_wishbone_stb)) begin main_soclinux_interface_we = main_soclinux_bus_wishbone_we; end end endcase end assign sys_clk_1 = sys_clk; assign por_clk = sys_clk; assign sys_rst = main_int_rst; always @(*) begin main_we = 4'd0; main_we[0] = (((main_bus_cyc & main_bus_stb) & main_bus_we) & main_bus_sel[0]); main_we[1] = (((main_bus_cyc & main_bus_stb) & main_bus_we) & main_bus_sel[1]); main_we[2] = (((main_bus_cyc & main_bus_stb) & main_bus_we) & main_bus_sel[2]); main_we[3] = (((main_bus_cyc & main_bus_stb) & main_bus_we) & main_bus_sel[3]); end assign main_adr = main_bus_adr[11:0]; assign main_bus_dat_r = main_dat_r; assign main_dat_w = main_bus_dat_w; assign serial_source_valid = main_sink_valid; assign serial_source_data = main_sink_payload_data; assign main_sink_ready = serial_source_ready; assign main_source_valid = serial_sink_valid; assign main_source_payload_data = serial_sink_data; assign serial_sink_ready = main_source_ready; assign main_uart_tx_fifo_sink_valid = main_uart_rxtx_re; assign main_uart_tx_fifo_sink_payload_data = main_uart_rxtx_r; assign main_uart_txfull_status = (~main_uart_tx_fifo_sink_ready); assign main_sink_valid = main_uart_tx_fifo_source_valid; assign main_uart_tx_fifo_source_ready = main_sink_ready; assign main_sink_first = main_uart_tx_fifo_source_first; assign main_sink_last = main_uart_tx_fifo_source_last; assign main_sink_payload_data = main_uart_tx_fifo_source_payload_data; assign main_uart_tx_trigger = (~main_uart_tx_fifo_sink_ready); assign main_uart_rx_fifo_sink_valid = main_source_valid; assign main_source_ready = main_uart_rx_fifo_sink_ready; assign main_uart_rx_fifo_sink_first = main_source_first; assign main_uart_rx_fifo_sink_last = main_source_last; assign main_uart_rx_fifo_sink_payload_data = main_source_payload_data; assign main_uart_rxempty_status = (~main_uart_rx_fifo_source_valid); assign main_uart_rxtx_w = main_uart_rx_fifo_source_payload_data; assign main_uart_rx_fifo_source_ready = main_uart_rx_clear; assign main_uart_rx_trigger = (~main_uart_rx_fifo_source_valid); always @(*) begin main_uart_eventmanager_status_w = 2'd0; main_uart_eventmanager_status_w[0] = main_uart_tx_status; main_uart_eventmanager_status_w[1] = main_uart_rx_status; end always @(*) begin main_uart_tx_clear = 1'd0; if ((main_uart_eventmanager_pending_re & main_uart_eventmanager_pending_r[0])) begin main_uart_tx_clear = 1'd1; end end always @(*) begin main_uart_eventmanager_pending_w = 2'd0; main_uart_eventmanager_pending_w[0] = main_uart_tx_pending; main_uart_eventmanager_pending_w[1] = main_uart_rx_pending; end always @(*) begin main_uart_rx_clear = 1'd0; if ((main_uart_eventmanager_pending_re & main_uart_eventmanager_pending_r[1])) begin main_uart_rx_clear = 1'd1; end end assign main_uart_irq = ((main_uart_eventmanager_pending_w[0] & main_uart_eventmanager_storage[0]) | (main_uart_eventmanager_pending_w[1] & main_uart_eventmanager_storage[1])); assign main_uart_tx_status = main_uart_tx_trigger; assign main_uart_rx_status = main_uart_rx_trigger; assign main_uart_tx_fifo_syncfifo_din = {main_uart_tx_fifo_fifo_in_last, main_uart_tx_fifo_fifo_in_first, main_uart_tx_fifo_fifo_in_payload_data}; assign {main_uart_tx_fifo_fifo_out_last, main_uart_tx_fifo_fifo_out_first, main_uart_tx_fifo_fifo_out_payload_data} = main_uart_tx_fifo_syncfifo_dout; assign {main_uart_tx_fifo_fifo_out_last, main_uart_tx_fifo_fifo_out_first, main_uart_tx_fifo_fifo_out_payload_data} = main_uart_tx_fifo_syncfifo_dout; assign {main_uart_tx_fifo_fifo_out_last, main_uart_tx_fifo_fifo_out_first, main_uart_tx_fifo_fifo_out_payload_data} = main_uart_tx_fifo_syncfifo_dout; assign main_uart_tx_fifo_sink_ready = main_uart_tx_fifo_syncfifo_writable; assign main_uart_tx_fifo_syncfifo_we = main_uart_tx_fifo_sink_valid; assign main_uart_tx_fifo_fifo_in_first = main_uart_tx_fifo_sink_first; assign main_uart_tx_fifo_fifo_in_last = main_uart_tx_fifo_sink_last; assign main_uart_tx_fifo_fifo_in_payload_data = main_uart_tx_fifo_sink_payload_data; assign main_uart_tx_fifo_source_valid = main_uart_tx_fifo_readable; assign main_uart_tx_fifo_source_first = main_uart_tx_fifo_fifo_out_first; assign main_uart_tx_fifo_source_last = main_uart_tx_fifo_fifo_out_last; assign main_uart_tx_fifo_source_payload_data = main_uart_tx_fifo_fifo_out_payload_data; assign main_uart_tx_fifo_re = main_uart_tx_fifo_source_ready; assign main_uart_tx_fifo_syncfifo_re = (main_uart_tx_fifo_syncfifo_readable & ((~main_uart_tx_fifo_readable) | main_uart_tx_fifo_re)); assign main_uart_tx_fifo_level1 = (main_uart_tx_fifo_level0 + main_uart_tx_fifo_readable); always @(*) begin main_uart_tx_fifo_wrport_adr = 4'd0; if (main_uart_tx_fifo_replace) begin main_uart_tx_fifo_wrport_adr = (main_uart_tx_fifo_produce - 1'd1); end else begin main_uart_tx_fifo_wrport_adr = main_uart_tx_fifo_produce; end end assign main_uart_tx_fifo_wrport_dat_w = main_uart_tx_fifo_syncfifo_din; assign main_uart_tx_fifo_wrport_we = (main_uart_tx_fifo_syncfifo_we & (main_uart_tx_fifo_syncfifo_writable | main_uart_tx_fifo_replace)); assign main_uart_tx_fifo_do_read = (main_uart_tx_fifo_syncfifo_readable & main_uart_tx_fifo_syncfifo_re); assign main_uart_tx_fifo_rdport_adr = main_uart_tx_fifo_consume; assign main_uart_tx_fifo_syncfifo_dout = main_uart_tx_fifo_rdport_dat_r; assign main_uart_tx_fifo_rdport_re = main_uart_tx_fifo_do_read; assign main_uart_tx_fifo_syncfifo_writable = (main_uart_tx_fifo_level0 != 5'd16); assign main_uart_tx_fifo_syncfifo_readable = (main_uart_tx_fifo_level0 != 1'd0); assign main_uart_rx_fifo_syncfifo_din = {main_uart_rx_fifo_fifo_in_last, main_uart_rx_fifo_fifo_in_first, main_uart_rx_fifo_fifo_in_payload_data}; assign {main_uart_rx_fifo_fifo_out_last, main_uart_rx_fifo_fifo_out_first, main_uart_rx_fifo_fifo_out_payload_data} = main_uart_rx_fifo_syncfifo_dout; assign {main_uart_rx_fifo_fifo_out_last, main_uart_rx_fifo_fifo_out_first, main_uart_rx_fifo_fifo_out_payload_data} = main_uart_rx_fifo_syncfifo_dout; assign {main_uart_rx_fifo_fifo_out_last, main_uart_rx_fifo_fifo_out_first, main_uart_rx_fifo_fifo_out_payload_data} = main_uart_rx_fifo_syncfifo_dout; assign main_uart_rx_fifo_sink_ready = main_uart_rx_fifo_syncfifo_writable; assign main_uart_rx_fifo_syncfifo_we = main_uart_rx_fifo_sink_valid; assign main_uart_rx_fifo_fifo_in_first = main_uart_rx_fifo_sink_first; assign main_uart_rx_fifo_fifo_in_last = main_uart_rx_fifo_sink_last; assign main_uart_rx_fifo_fifo_in_payload_data = main_uart_rx_fifo_sink_payload_data; assign main_uart_rx_fifo_source_valid = main_uart_rx_fifo_readable; assign main_uart_rx_fifo_source_first = main_uart_rx_fifo_fifo_out_first; assign main_uart_rx_fifo_source_last = main_uart_rx_fifo_fifo_out_last; assign main_uart_rx_fifo_source_payload_data = main_uart_rx_fifo_fifo_out_payload_data; assign main_uart_rx_fifo_re = main_uart_rx_fifo_source_ready; assign main_uart_rx_fifo_syncfifo_re = (main_uart_rx_fifo_syncfifo_readable & ((~main_uart_rx_fifo_readable) | main_uart_rx_fifo_re)); assign main_uart_rx_fifo_level1 = (main_uart_rx_fifo_level0 + main_uart_rx_fifo_readable); always @(*) begin main_uart_rx_fifo_wrport_adr = 4'd0; if (main_uart_rx_fifo_replace) begin main_uart_rx_fifo_wrport_adr = (main_uart_rx_fifo_produce - 1'd1); end else begin main_uart_rx_fifo_wrport_adr = main_uart_rx_fifo_produce; end end assign main_uart_rx_fifo_wrport_dat_w = main_uart_rx_fifo_syncfifo_din; assign main_uart_rx_fifo_wrport_we = (main_uart_rx_fifo_syncfifo_we & (main_uart_rx_fifo_syncfifo_writable | main_uart_rx_fifo_replace)); assign main_uart_rx_fifo_do_read = (main_uart_rx_fifo_syncfifo_readable & main_uart_rx_fifo_syncfifo_re); assign main_uart_rx_fifo_rdport_adr = main_uart_rx_fifo_consume; assign main_uart_rx_fifo_syncfifo_dout = main_uart_rx_fifo_rdport_dat_r; assign main_uart_rx_fifo_rdport_re = main_uart_rx_fifo_do_read; assign main_uart_rx_fifo_syncfifo_writable = (main_uart_rx_fifo_level0 != 5'd16); assign main_uart_rx_fifo_syncfifo_readable = (main_uart_rx_fifo_level0 != 1'd0); assign builder_shared_adr = builder_array_muxed0; assign builder_shared_dat_w = builder_array_muxed1; assign builder_shared_sel = builder_array_muxed2; assign builder_shared_cyc = builder_array_muxed3; assign builder_shared_stb = builder_array_muxed4; assign builder_shared_we = builder_array_muxed5; assign builder_shared_cti = builder_array_muxed6; assign builder_shared_bte = builder_array_muxed7; assign main_soclinux_interface0_soc_bus_dat_r = builder_shared_dat_r; assign main_soclinux_interface1_soc_bus_dat_r = builder_shared_dat_r; assign main_soclinux_interface0_soc_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); assign main_soclinux_interface1_soc_bus_ack = (builder_shared_ack & (builder_grant == 1'd1)); assign main_soclinux_interface0_soc_bus_err = (builder_shared_err & (builder_grant == 1'd0)); assign main_soclinux_interface1_soc_bus_err = (builder_shared_err & (builder_grant == 1'd1)); assign builder_request = {main_soclinux_interface1_soc_bus_cyc, main_soclinux_interface0_soc_bus_cyc}; always @(*) begin builder_slave_sel = 5'd0; builder_slave_sel[0] = (builder_shared_adr[28:13] == 1'd0); builder_slave_sel[1] = (builder_shared_adr[28:10] == 17'd65536); builder_slave_sel[2] = (builder_shared_adr[28:23] == 6'd32); builder_slave_sel[3] = (builder_shared_adr[28:14] == 15'd28672); builder_slave_sel[4] = (builder_shared_adr[28:12] == 16'd32768); end assign main_soclinux_rom_bus_adr = builder_shared_adr; assign main_soclinux_rom_bus_dat_w = builder_shared_dat_w; assign main_soclinux_rom_bus_sel = builder_shared_sel; assign main_soclinux_rom_bus_stb = builder_shared_stb; assign main_soclinux_rom_bus_we = builder_shared_we; assign main_soclinux_rom_bus_cti = builder_shared_cti; assign main_soclinux_rom_bus_bte = builder_shared_bte; assign main_soclinux_sram_bus_adr = builder_shared_adr; assign main_soclinux_sram_bus_dat_w = builder_shared_dat_w; assign main_soclinux_sram_bus_sel = builder_shared_sel; assign main_soclinux_sram_bus_stb = builder_shared_stb; assign main_soclinux_sram_bus_we = builder_shared_we; assign main_soclinux_sram_bus_cti = builder_shared_cti; assign main_soclinux_sram_bus_bte = builder_shared_bte; assign main_soclinux_main_ram_bus_adr = builder_shared_adr; assign main_soclinux_main_ram_bus_dat_w = builder_shared_dat_w; assign main_soclinux_main_ram_bus_sel = builder_shared_sel; assign main_soclinux_main_ram_bus_stb = builder_shared_stb; assign main_soclinux_main_ram_bus_we = builder_shared_we; assign main_soclinux_main_ram_bus_cti = builder_shared_cti; assign main_soclinux_main_ram_bus_bte = builder_shared_bte; assign main_soclinux_bus_wishbone_adr = builder_shared_adr; assign main_soclinux_bus_wishbone_dat_w = builder_shared_dat_w; assign main_soclinux_bus_wishbone_sel = builder_shared_sel; assign main_soclinux_bus_wishbone_stb = builder_shared_stb; assign main_soclinux_bus_wishbone_we = builder_shared_we; assign main_soclinux_bus_wishbone_cti = builder_shared_cti; assign main_soclinux_bus_wishbone_bte = builder_shared_bte; assign main_bus_adr = builder_shared_adr; assign main_bus_dat_w = builder_shared_dat_w; assign main_bus_sel = builder_shared_sel; assign main_bus_stb = builder_shared_stb; assign main_bus_we = builder_shared_we; assign main_bus_cti = builder_shared_cti; assign main_bus_bte = builder_shared_bte; assign main_soclinux_rom_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); assign main_soclinux_sram_bus_cyc = (builder_shared_cyc & builder_slave_sel[1]); assign main_soclinux_main_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[2]); assign main_soclinux_bus_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[3]); assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[4]); always @(*) begin builder_shared_ack = 1'd0; builder_shared_ack = ((((main_soclinux_rom_bus_ack | main_soclinux_sram_bus_ack) | main_soclinux_main_ram_bus_ack) | main_soclinux_bus_wishbone_ack) | main_bus_ack); if (builder_done) begin builder_shared_ack = 1'd1; end end assign builder_shared_err = ((((main_soclinux_rom_bus_err | main_soclinux_sram_bus_err) | main_soclinux_main_ram_bus_err) | main_soclinux_bus_wishbone_err) | main_bus_err); always @(*) begin builder_shared_dat_r = 32'd0; builder_shared_dat_r = ((((({32{builder_slave_sel_r[0]}} & main_soclinux_rom_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & main_soclinux_sram_bus_dat_r)) | ({32{builder_slave_sel_r[2]}} & main_soclinux_main_ram_bus_dat_r)) | ({32{builder_slave_sel_r[3]}} & main_soclinux_bus_wishbone_dat_r)) | ({32{builder_slave_sel_r[4]}} & main_bus_dat_r)); if (builder_done) begin builder_shared_dat_r = 32'd4294967295; end end assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); always @(*) begin builder_error = 1'd0; if (builder_done) begin builder_error = 1'd1; end end assign builder_done = (builder_count == 1'd0); assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1); assign main_soclinux_cpu_latch_r = builder_interface0_bank_bus_dat_w[0]; assign main_soclinux_cpu_latch_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 1'd0)); assign main_soclinux_cpu_latch_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 1'd0)); assign builder_csrbank0_timer_time7_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time7_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 1'd1)); assign builder_csrbank0_timer_time7_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 1'd1)); assign builder_csrbank0_timer_time6_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time6_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 2'd2)); assign builder_csrbank0_timer_time6_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 2'd2)); assign builder_csrbank0_timer_time5_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time5_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 2'd3)); assign builder_csrbank0_timer_time5_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 2'd3)); assign builder_csrbank0_timer_time4_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time4_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 3'd4)); assign builder_csrbank0_timer_time4_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 3'd4)); assign builder_csrbank0_timer_time3_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time3_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 3'd5)); assign builder_csrbank0_timer_time3_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 3'd5)); assign builder_csrbank0_timer_time2_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time2_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 3'd6)); assign builder_csrbank0_timer_time2_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 3'd6)); assign builder_csrbank0_timer_time1_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time1_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 3'd7)); assign builder_csrbank0_timer_time1_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 3'd7)); assign builder_csrbank0_timer_time0_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time0_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd8)); assign builder_csrbank0_timer_time0_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd8)); assign builder_csrbank0_timer_time_cmp7_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp7_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd9)); assign builder_csrbank0_timer_time_cmp7_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd9)); assign builder_csrbank0_timer_time_cmp6_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp6_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd10)); assign builder_csrbank0_timer_time_cmp6_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd10)); assign builder_csrbank0_timer_time_cmp5_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp5_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd11)); assign builder_csrbank0_timer_time_cmp5_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd11)); assign builder_csrbank0_timer_time_cmp4_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp4_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd12)); assign builder_csrbank0_timer_time_cmp4_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd12)); assign builder_csrbank0_timer_time_cmp3_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp3_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd13)); assign builder_csrbank0_timer_time_cmp3_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd13)); assign builder_csrbank0_timer_time_cmp2_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp2_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd14)); assign builder_csrbank0_timer_time_cmp2_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd14)); assign builder_csrbank0_timer_time_cmp1_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp1_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 4'd15)); assign builder_csrbank0_timer_time_cmp1_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 4'd15)); assign builder_csrbank0_timer_time_cmp0_r = builder_interface0_bank_bus_dat_w[7:0]; assign builder_csrbank0_timer_time_cmp0_re = ((builder_csrbank0_sel & builder_interface0_bank_bus_we) & (builder_interface0_bank_bus_adr[4:0] == 5'd16)); assign builder_csrbank0_timer_time_cmp0_we = ((builder_csrbank0_sel & (~builder_interface0_bank_bus_we)) & (builder_interface0_bank_bus_adr[4:0] == 5'd16)); assign builder_csrbank0_timer_time7_w = main_soclinux_cpu_time_status[63:56]; assign builder_csrbank0_timer_time6_w = main_soclinux_cpu_time_status[55:48]; assign builder_csrbank0_timer_time5_w = main_soclinux_cpu_time_status[47:40]; assign builder_csrbank0_timer_time4_w = main_soclinux_cpu_time_status[39:32]; assign builder_csrbank0_timer_time3_w = main_soclinux_cpu_time_status[31:24]; assign builder_csrbank0_timer_time2_w = main_soclinux_cpu_time_status[23:16]; assign builder_csrbank0_timer_time1_w = main_soclinux_cpu_time_status[15:8]; assign builder_csrbank0_timer_time0_w = main_soclinux_cpu_time_status[7:0]; assign main_soclinux_cpu_time_we = builder_csrbank0_timer_time0_we; assign builder_csrbank0_timer_time_cmp7_w = main_soclinux_cpu_time_cmp_storage[63:56]; assign builder_csrbank0_timer_time_cmp6_w = main_soclinux_cpu_time_cmp_storage[55:48]; assign builder_csrbank0_timer_time_cmp5_w = main_soclinux_cpu_time_cmp_storage[47:40]; assign builder_csrbank0_timer_time_cmp4_w = main_soclinux_cpu_time_cmp_storage[39:32]; assign builder_csrbank0_timer_time_cmp3_w = main_soclinux_cpu_time_cmp_storage[31:24]; assign builder_csrbank0_timer_time_cmp2_w = main_soclinux_cpu_time_cmp_storage[23:16]; assign builder_csrbank0_timer_time_cmp1_w = main_soclinux_cpu_time_cmp_storage[15:8]; assign builder_csrbank0_timer_time_cmp0_w = main_soclinux_cpu_time_cmp_storage[7:0]; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd0); assign main_soclinux_ctrl_reset_reset_r = builder_interface1_bank_bus_dat_w[0]; assign main_soclinux_ctrl_reset_reset_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 1'd0)); assign main_soclinux_ctrl_reset_reset_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 1'd0)); assign builder_csrbank1_scratch3_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_scratch3_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 1'd1)); assign builder_csrbank1_scratch3_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 1'd1)); assign builder_csrbank1_scratch2_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_scratch2_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 2'd2)); assign builder_csrbank1_scratch2_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 2'd2)); assign builder_csrbank1_scratch1_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_scratch1_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 2'd3)); assign builder_csrbank1_scratch1_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 2'd3)); assign builder_csrbank1_scratch0_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_scratch0_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 3'd4)); assign builder_csrbank1_scratch0_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 3'd4)); assign builder_csrbank1_bus_errors3_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_bus_errors3_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 3'd5)); assign builder_csrbank1_bus_errors3_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 3'd5)); assign builder_csrbank1_bus_errors2_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_bus_errors2_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 3'd6)); assign builder_csrbank1_bus_errors2_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 3'd6)); assign builder_csrbank1_bus_errors1_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_bus_errors1_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 3'd7)); assign builder_csrbank1_bus_errors1_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 3'd7)); assign builder_csrbank1_bus_errors0_r = builder_interface1_bank_bus_dat_w[7:0]; assign builder_csrbank1_bus_errors0_re = ((builder_csrbank1_sel & builder_interface1_bank_bus_we) & (builder_interface1_bank_bus_adr[3:0] == 4'd8)); assign builder_csrbank1_bus_errors0_we = ((builder_csrbank1_sel & (~builder_interface1_bank_bus_we)) & (builder_interface1_bank_bus_adr[3:0] == 4'd8)); assign builder_csrbank1_scratch3_w = main_soclinux_ctrl_storage[31:24]; assign builder_csrbank1_scratch2_w = main_soclinux_ctrl_storage[23:16]; assign builder_csrbank1_scratch1_w = main_soclinux_ctrl_storage[15:8]; assign builder_csrbank1_scratch0_w = main_soclinux_ctrl_storage[7:0]; assign builder_csrbank1_bus_errors3_w = main_soclinux_ctrl_bus_errors_status[31:24]; assign builder_csrbank1_bus_errors2_w = main_soclinux_ctrl_bus_errors_status[23:16]; assign builder_csrbank1_bus_errors1_w = main_soclinux_ctrl_bus_errors_status[15:8]; assign builder_csrbank1_bus_errors0_w = main_soclinux_ctrl_bus_errors_status[7:0]; assign main_soclinux_ctrl_bus_errors_we = builder_csrbank1_bus_errors0_we; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 3'd4); assign main_finish_finish_r = builder_interface2_bank_bus_dat_w[0]; assign main_finish_finish_re = ((builder_csrbank2_sel & builder_interface2_bank_bus_we) & (builder_interface2_bank_bus_adr[0] == 1'd0)); assign main_finish_finish_we = ((builder_csrbank2_sel & (~builder_interface2_bank_bus_we)) & (builder_interface2_bank_bus_adr[0] == 1'd0)); assign builder_csrbank3_sel = (builder_interface3_bank_bus_adr[13:9] == 2'd3); assign builder_csrbank3_load3_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_load3_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 1'd0)); assign builder_csrbank3_load3_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 1'd0)); assign builder_csrbank3_load2_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_load2_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 1'd1)); assign builder_csrbank3_load2_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 1'd1)); assign builder_csrbank3_load1_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_load1_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 2'd2)); assign builder_csrbank3_load1_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 2'd2)); assign builder_csrbank3_load0_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_load0_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 2'd3)); assign builder_csrbank3_load0_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 2'd3)); assign builder_csrbank3_reload3_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_reload3_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 3'd4)); assign builder_csrbank3_reload3_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 3'd4)); assign builder_csrbank3_reload2_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_reload2_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 3'd5)); assign builder_csrbank3_reload2_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 3'd5)); assign builder_csrbank3_reload1_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_reload1_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 3'd6)); assign builder_csrbank3_reload1_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 3'd6)); assign builder_csrbank3_reload0_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_reload0_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 3'd7)); assign builder_csrbank3_reload0_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 3'd7)); assign builder_csrbank3_en0_r = builder_interface3_bank_bus_dat_w[0]; assign builder_csrbank3_en0_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd8)); assign builder_csrbank3_en0_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd8)); assign builder_csrbank3_update_value0_r = builder_interface3_bank_bus_dat_w[0]; assign builder_csrbank3_update_value0_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd9)); assign builder_csrbank3_update_value0_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd9)); assign builder_csrbank3_value3_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_value3_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd10)); assign builder_csrbank3_value3_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd10)); assign builder_csrbank3_value2_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_value2_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd11)); assign builder_csrbank3_value2_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd11)); assign builder_csrbank3_value1_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_value1_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd12)); assign builder_csrbank3_value1_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd12)); assign builder_csrbank3_value0_r = builder_interface3_bank_bus_dat_w[7:0]; assign builder_csrbank3_value0_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd13)); assign builder_csrbank3_value0_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd13)); assign main_soclinux_eventmanager_status_r = builder_interface3_bank_bus_dat_w[0]; assign main_soclinux_eventmanager_status_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd14)); assign main_soclinux_eventmanager_status_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd14)); assign main_soclinux_eventmanager_pending_r = builder_interface3_bank_bus_dat_w[0]; assign main_soclinux_eventmanager_pending_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 4'd15)); assign main_soclinux_eventmanager_pending_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 4'd15)); assign builder_csrbank3_ev_enable0_r = builder_interface3_bank_bus_dat_w[0]; assign builder_csrbank3_ev_enable0_re = ((builder_csrbank3_sel & builder_interface3_bank_bus_we) & (builder_interface3_bank_bus_adr[4:0] == 5'd16)); assign builder_csrbank3_ev_enable0_we = ((builder_csrbank3_sel & (~builder_interface3_bank_bus_we)) & (builder_interface3_bank_bus_adr[4:0] == 5'd16)); assign builder_csrbank3_load3_w = main_soclinux_load_storage[31:24]; assign builder_csrbank3_load2_w = main_soclinux_load_storage[23:16]; assign builder_csrbank3_load1_w = main_soclinux_load_storage[15:8]; assign builder_csrbank3_load0_w = main_soclinux_load_storage[7:0]; assign builder_csrbank3_reload3_w = main_soclinux_reload_storage[31:24]; assign builder_csrbank3_reload2_w = main_soclinux_reload_storage[23:16]; assign builder_csrbank3_reload1_w = main_soclinux_reload_storage[15:8]; assign builder_csrbank3_reload0_w = main_soclinux_reload_storage[7:0]; assign builder_csrbank3_en0_w = main_soclinux_en_storage; assign builder_csrbank3_update_value0_w = main_soclinux_update_value_storage; assign builder_csrbank3_value3_w = main_soclinux_value_status[31:24]; assign builder_csrbank3_value2_w = main_soclinux_value_status[23:16]; assign builder_csrbank3_value1_w = main_soclinux_value_status[15:8]; assign builder_csrbank3_value0_w = main_soclinux_value_status[7:0]; assign main_soclinux_value_we = builder_csrbank3_value0_we; assign builder_csrbank3_ev_enable0_w = main_soclinux_eventmanager_storage; assign builder_csrbank4_sel = (builder_interface4_bank_bus_adr[13:9] == 2'd2); assign main_uart_rxtx_r = builder_interface4_bank_bus_dat_w[7:0]; assign main_uart_rxtx_re = ((builder_csrbank4_sel & builder_interface4_bank_bus_we) & (builder_interface4_bank_bus_adr[2:0] == 1'd0)); assign main_uart_rxtx_we = ((builder_csrbank4_sel & (~builder_interface4_bank_bus_we)) & (builder_interface4_bank_bus_adr[2:0] == 1'd0)); assign builder_csrbank4_txfull_r = builder_interface4_bank_bus_dat_w[0]; assign builder_csrbank4_txfull_re = ((builder_csrbank4_sel & builder_interface4_bank_bus_we) & (builder_interface4_bank_bus_adr[2:0] == 1'd1)); assign builder_csrbank4_txfull_we = ((builder_csrbank4_sel & (~builder_interface4_bank_bus_we)) & (builder_interface4_bank_bus_adr[2:0] == 1'd1)); assign builder_csrbank4_rxempty_r = builder_interface4_bank_bus_dat_w[0]; assign builder_csrbank4_rxempty_re = ((builder_csrbank4_sel & builder_interface4_bank_bus_we) & (builder_interface4_bank_bus_adr[2:0] == 2'd2)); assign builder_csrbank4_rxempty_we = ((builder_csrbank4_sel & (~builder_interface4_bank_bus_we)) & (builder_interface4_bank_bus_adr[2:0] == 2'd2)); assign main_uart_eventmanager_status_r = builder_interface4_bank_bus_dat_w[1:0]; assign main_uart_eventmanager_status_re = ((builder_csrbank4_sel & builder_interface4_bank_bus_we) & (builder_interface4_bank_bus_adr[2:0] == 2'd3)); assign main_uart_eventmanager_status_we = ((builder_csrbank4_sel & (~builder_interface4_bank_bus_we)) & (builder_interface4_bank_bus_adr[2:0] == 2'd3)); assign main_uart_eventmanager_pending_r = builder_interface4_bank_bus_dat_w[1:0]; assign main_uart_eventmanager_pending_re = ((builder_csrbank4_sel & builder_interface4_bank_bus_we) & (builder_interface4_bank_bus_adr[2:0] == 3'd4)); assign main_uart_eventmanager_pending_we = ((builder_csrbank4_sel & (~builder_interface4_bank_bus_we)) & (builder_interface4_bank_bus_adr[2:0] == 3'd4)); assign builder_csrbank4_ev_enable0_r = builder_interface4_bank_bus_dat_w[1:0]; assign builder_csrbank4_ev_enable0_re = ((builder_csrbank4_sel & builder_interface4_bank_bus_we) & (builder_interface4_bank_bus_adr[2:0] == 3'd5)); assign builder_csrbank4_ev_enable0_we = ((builder_csrbank4_sel & (~builder_interface4_bank_bus_we)) & (builder_interface4_bank_bus_adr[2:0] == 3'd5)); assign builder_csrbank4_txfull_w = main_uart_txfull_status; assign main_uart_txfull_we = builder_csrbank4_txfull_we; assign builder_csrbank4_rxempty_w = main_uart_rxempty_status; assign main_uart_rxempty_we = builder_csrbank4_rxempty_we; assign builder_csrbank4_ev_enable0_w = main_uart_eventmanager_storage[1:0]; assign builder_adr = main_soclinux_interface_adr; assign builder_we = main_soclinux_interface_we; assign builder_dat_w = main_soclinux_interface_dat_w; assign main_soclinux_interface_dat_r = builder_dat_r; assign builder_interface0_bank_bus_adr = builder_adr; assign builder_interface1_bank_bus_adr = builder_adr; assign builder_interface2_bank_bus_adr = builder_adr; assign builder_interface3_bank_bus_adr = builder_adr; assign builder_interface4_bank_bus_adr = builder_adr; assign builder_interface0_bank_bus_we = builder_we; assign builder_interface1_bank_bus_we = builder_we; assign builder_interface2_bank_bus_we = builder_we; assign builder_interface3_bank_bus_we = builder_we; assign builder_interface4_bank_bus_we = builder_we; assign builder_interface0_bank_bus_dat_w = builder_dat_w; assign builder_interface1_bank_bus_dat_w = builder_dat_w; assign builder_interface2_bank_bus_dat_w = builder_dat_w; assign builder_interface3_bank_bus_dat_w = builder_dat_w; assign builder_interface4_bank_bus_dat_w = builder_dat_w; assign builder_dat_r = ((((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r) | builder_interface3_bank_bus_dat_r) | builder_interface4_bank_bus_dat_r); always @(*) begin builder_array_muxed0 = 30'd0; case (builder_grant) 1'd0: begin builder_array_muxed0 = main_soclinux_interface0_soc_bus_adr; end default: begin builder_array_muxed0 = main_soclinux_interface1_soc_bus_adr; end endcase end always @(*) begin builder_array_muxed1 = 32'd0; case (builder_grant) 1'd0: begin builder_array_muxed1 = main_soclinux_interface0_soc_bus_dat_w; end default: begin builder_array_muxed1 = main_soclinux_interface1_soc_bus_dat_w; end endcase end always @(*) begin builder_array_muxed2 = 4'd0; case (builder_grant) 1'd0: begin builder_array_muxed2 = main_soclinux_interface0_soc_bus_sel; end default: begin builder_array_muxed2 = main_soclinux_interface1_soc_bus_sel; end endcase end always @(*) begin builder_array_muxed3 = 1'd0; case (builder_grant) 1'd0: begin builder_array_muxed3 = main_soclinux_interface0_soc_bus_cyc; end default: begin builder_array_muxed3 = main_soclinux_interface1_soc_bus_cyc; end endcase end always @(*) begin builder_array_muxed4 = 1'd0; case (builder_grant) 1'd0: begin builder_array_muxed4 = main_soclinux_interface0_soc_bus_stb; end default: begin builder_array_muxed4 = main_soclinux_interface1_soc_bus_stb; end endcase end always @(*) begin builder_array_muxed5 = 1'd0; case (builder_grant) 1'd0: begin builder_array_muxed5 = main_soclinux_interface0_soc_bus_we; end default: begin builder_array_muxed5 = main_soclinux_interface1_soc_bus_we; end endcase end always @(*) begin builder_array_muxed6 = 3'd0; case (builder_grant) 1'd0: begin builder_array_muxed6 = main_soclinux_interface0_soc_bus_cti; end default: begin builder_array_muxed6 = main_soclinux_interface1_soc_bus_cti; end endcase end always @(*) begin builder_array_muxed7 = 2'd0; case (builder_grant) 1'd0: begin builder_array_muxed7 = main_soclinux_interface0_soc_bus_bte; end default: begin builder_array_muxed7 = main_soclinux_interface1_soc_bus_bte; end endcase end always @(posedge por_clk) begin main_int_rst <= 1'd0; end always @(posedge sys_clk_1) begin if ((main_soclinux_ctrl_bus_errors != 32'd4294967295)) begin if (main_soclinux_ctrl_bus_error) begin main_soclinux_ctrl_bus_errors <= (main_soclinux_ctrl_bus_errors + 1'd1); end end main_soclinux_cpu_time <= (main_soclinux_cpu_time + 1'd1); if (main_soclinux_cpu_latch_re) begin main_soclinux_cpu_time_status <= main_soclinux_cpu_time; end if (main_soclinux_cpu_latch_re) begin main_soclinux_cpu_time_cmp <= main_soclinux_cpu_time_cmp_storage; end main_soclinux_rom_bus_ack <= 1'd0; if (((main_soclinux_rom_bus_cyc & main_soclinux_rom_bus_stb) & (~main_soclinux_rom_bus_ack))) begin main_soclinux_rom_bus_ack <= 1'd1; end main_soclinux_sram_bus_ack <= 1'd0; if (((main_soclinux_sram_bus_cyc & main_soclinux_sram_bus_stb) & (~main_soclinux_sram_bus_ack))) begin main_soclinux_sram_bus_ack <= 1'd1; end main_soclinux_main_ram_bus_ack <= 1'd0; if (((main_soclinux_main_ram_bus_cyc & main_soclinux_main_ram_bus_stb) & (~main_soclinux_main_ram_bus_ack))) begin main_soclinux_main_ram_bus_ack <= 1'd1; end if (main_soclinux_en_storage) begin if ((main_soclinux_value == 1'd0)) begin main_soclinux_value <= main_soclinux_reload_storage; end else begin main_soclinux_value <= (main_soclinux_value - 1'd1); end end else begin main_soclinux_value <= main_soclinux_load_storage; end if (main_soclinux_update_value_re) begin main_soclinux_value_status <= main_soclinux_value; end if (main_soclinux_zero_clear) begin main_soclinux_zero_pending <= 1'd0; end main_soclinux_zero_old_trigger <= main_soclinux_zero_trigger; if (((~main_soclinux_zero_trigger) & main_soclinux_zero_old_trigger)) begin main_soclinux_zero_pending <= 1'd1; end builder_state <= builder_next_state; if ((main_finish_finish_re | main_finish)) begin $finish; end main_bus_ack <= 1'd0; if (((main_bus_cyc & main_bus_stb) & (~main_bus_ack))) begin main_bus_ack <= 1'd1; end if (main_uart_tx_clear) begin main_uart_tx_pending <= 1'd0; end main_uart_tx_old_trigger <= main_uart_tx_trigger; if (((~main_uart_tx_trigger) & main_uart_tx_old_trigger)) begin main_uart_tx_pending <= 1'd1; end if (main_uart_rx_clear) begin main_uart_rx_pending <= 1'd0; end main_uart_rx_old_trigger <= main_uart_rx_trigger; if (((~main_uart_rx_trigger) & main_uart_rx_old_trigger)) begin main_uart_rx_pending <= 1'd1; end if (main_uart_tx_fifo_syncfifo_re) begin main_uart_tx_fifo_readable <= 1'd1; end else begin if (main_uart_tx_fifo_re) begin main_uart_tx_fifo_readable <= 1'd0; end end if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin main_uart_tx_fifo_produce <= (main_uart_tx_fifo_produce + 1'd1); end if (main_uart_tx_fifo_do_read) begin main_uart_tx_fifo_consume <= (main_uart_tx_fifo_consume + 1'd1); end if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin if ((~main_uart_tx_fifo_do_read)) begin main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 + 1'd1); end end else begin if (main_uart_tx_fifo_do_read) begin main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 - 1'd1); end end if (main_uart_rx_fifo_syncfifo_re) begin main_uart_rx_fifo_readable <= 1'd1; end else begin if (main_uart_rx_fifo_re) begin main_uart_rx_fifo_readable <= 1'd0; end end if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin main_uart_rx_fifo_produce <= (main_uart_rx_fifo_produce + 1'd1); end if (main_uart_rx_fifo_do_read) begin main_uart_rx_fifo_consume <= (main_uart_rx_fifo_consume + 1'd1); end if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin if ((~main_uart_rx_fifo_do_read)) begin main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 + 1'd1); end end else begin if (main_uart_rx_fifo_do_read) begin main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 - 1'd1); end end case (builder_grant) 1'd0: begin if ((~builder_request[0])) begin if (builder_request[1]) begin builder_grant <= 1'd1; end end end 1'd1: begin if ((~builder_request[1])) begin if (builder_request[0]) begin builder_grant <= 1'd0; end end end endcase builder_slave_sel_r <= builder_slave_sel; if (builder_wait) begin if ((~builder_done)) begin builder_count <= (builder_count - 1'd1); end end else begin builder_count <= 20'd1000000; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin case (builder_interface0_bank_bus_adr[4:0]) 1'd0: begin builder_interface0_bank_bus_dat_r <= main_soclinux_cpu_latch_w; end 1'd1: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time7_w; end 2'd2: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time6_w; end 2'd3: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time5_w; end 3'd4: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time4_w; end 3'd5: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time3_w; end 3'd6: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time2_w; end 3'd7: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time1_w; end 4'd8: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time0_w; end 4'd9: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp7_w; end 4'd10: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp6_w; end 4'd11: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp5_w; end 4'd12: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp4_w; end 4'd13: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp3_w; end 4'd14: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp2_w; end 4'd15: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp1_w; end 5'd16: begin builder_interface0_bank_bus_dat_r <= builder_csrbank0_timer_time_cmp0_w; end endcase end if (builder_csrbank0_timer_time_cmp7_re) begin main_soclinux_cpu_time_cmp_storage[63:56] <= builder_csrbank0_timer_time_cmp7_r; end if (builder_csrbank0_timer_time_cmp6_re) begin main_soclinux_cpu_time_cmp_storage[55:48] <= builder_csrbank0_timer_time_cmp6_r; end if (builder_csrbank0_timer_time_cmp5_re) begin main_soclinux_cpu_time_cmp_storage[47:40] <= builder_csrbank0_timer_time_cmp5_r; end if (builder_csrbank0_timer_time_cmp4_re) begin main_soclinux_cpu_time_cmp_storage[39:32] <= builder_csrbank0_timer_time_cmp4_r; end if (builder_csrbank0_timer_time_cmp3_re) begin main_soclinux_cpu_time_cmp_storage[31:24] <= builder_csrbank0_timer_time_cmp3_r; end if (builder_csrbank0_timer_time_cmp2_re) begin main_soclinux_cpu_time_cmp_storage[23:16] <= builder_csrbank0_timer_time_cmp2_r; end if (builder_csrbank0_timer_time_cmp1_re) begin main_soclinux_cpu_time_cmp_storage[15:8] <= builder_csrbank0_timer_time_cmp1_r; end if (builder_csrbank0_timer_time_cmp0_re) begin main_soclinux_cpu_time_cmp_storage[7:0] <= builder_csrbank0_timer_time_cmp0_r; end main_soclinux_cpu_time_cmp_re <= builder_csrbank0_timer_time_cmp0_re; builder_interface1_bank_bus_dat_r <= 1'd0; if (builder_csrbank1_sel) begin case (builder_interface1_bank_bus_adr[3:0]) 1'd0: begin builder_interface1_bank_bus_dat_r <= main_soclinux_ctrl_reset_reset_w; end 1'd1: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_scratch3_w; end 2'd2: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_scratch2_w; end 2'd3: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_scratch1_w; end 3'd4: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_scratch0_w; end 3'd5: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_bus_errors3_w; end 3'd6: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_bus_errors2_w; end 3'd7: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_bus_errors1_w; end 4'd8: begin builder_interface1_bank_bus_dat_r <= builder_csrbank1_bus_errors0_w; end endcase end if (builder_csrbank1_scratch3_re) begin main_soclinux_ctrl_storage[31:24] <= builder_csrbank1_scratch3_r; end if (builder_csrbank1_scratch2_re) begin main_soclinux_ctrl_storage[23:16] <= builder_csrbank1_scratch2_r; end if (builder_csrbank1_scratch1_re) begin main_soclinux_ctrl_storage[15:8] <= builder_csrbank1_scratch1_r; end if (builder_csrbank1_scratch0_re) begin main_soclinux_ctrl_storage[7:0] <= builder_csrbank1_scratch0_r; end main_soclinux_ctrl_re <= builder_csrbank1_scratch0_re; builder_interface2_bank_bus_dat_r <= 1'd0; if (builder_csrbank2_sel) begin case (builder_interface2_bank_bus_adr[0]) 1'd0: begin builder_interface2_bank_bus_dat_r <= main_finish_finish_w; end endcase end builder_interface3_bank_bus_dat_r <= 1'd0; if (builder_csrbank3_sel) begin case (builder_interface3_bank_bus_adr[4:0]) 1'd0: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_load3_w; end 1'd1: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_load2_w; end 2'd2: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_load1_w; end 2'd3: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_load0_w; end 3'd4: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_reload3_w; end 3'd5: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_reload2_w; end 3'd6: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_reload1_w; end 3'd7: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_reload0_w; end 4'd8: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_en0_w; end 4'd9: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_update_value0_w; end 4'd10: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_value3_w; end 4'd11: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_value2_w; end 4'd12: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_value1_w; end 4'd13: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_value0_w; end 4'd14: begin builder_interface3_bank_bus_dat_r <= main_soclinux_eventmanager_status_w; end 4'd15: begin builder_interface3_bank_bus_dat_r <= main_soclinux_eventmanager_pending_w; end 5'd16: begin builder_interface3_bank_bus_dat_r <= builder_csrbank3_ev_enable0_w; end endcase end if (builder_csrbank3_load3_re) begin main_soclinux_load_storage[31:24] <= builder_csrbank3_load3_r; end if (builder_csrbank3_load2_re) begin main_soclinux_load_storage[23:16] <= builder_csrbank3_load2_r; end if (builder_csrbank3_load1_re) begin main_soclinux_load_storage[15:8] <= builder_csrbank3_load1_r; end if (builder_csrbank3_load0_re) begin main_soclinux_load_storage[7:0] <= builder_csrbank3_load0_r; end main_soclinux_load_re <= builder_csrbank3_load0_re; if (builder_csrbank3_reload3_re) begin main_soclinux_reload_storage[31:24] <= builder_csrbank3_reload3_r; end if (builder_csrbank3_reload2_re) begin main_soclinux_reload_storage[23:16] <= builder_csrbank3_reload2_r; end if (builder_csrbank3_reload1_re) begin main_soclinux_reload_storage[15:8] <= builder_csrbank3_reload1_r; end if (builder_csrbank3_reload0_re) begin main_soclinux_reload_storage[7:0] <= builder_csrbank3_reload0_r; end main_soclinux_reload_re <= builder_csrbank3_reload0_re; if (builder_csrbank3_en0_re) begin main_soclinux_en_storage <= builder_csrbank3_en0_r; end main_soclinux_en_re <= builder_csrbank3_en0_re; if (builder_csrbank3_update_value0_re) begin main_soclinux_update_value_storage <= builder_csrbank3_update_value0_r; end main_soclinux_update_value_re <= builder_csrbank3_update_value0_re; if (builder_csrbank3_ev_enable0_re) begin main_soclinux_eventmanager_storage <= builder_csrbank3_ev_enable0_r; end main_soclinux_eventmanager_re <= builder_csrbank3_ev_enable0_re; builder_interface4_bank_bus_dat_r <= 1'd0; if (builder_csrbank4_sel) begin case (builder_interface4_bank_bus_adr[2:0]) 1'd0: begin builder_interface4_bank_bus_dat_r <= main_uart_rxtx_w; end 1'd1: begin builder_interface4_bank_bus_dat_r <= builder_csrbank4_txfull_w; end 2'd2: begin builder_interface4_bank_bus_dat_r <= builder_csrbank4_rxempty_w; end 2'd3: begin builder_interface4_bank_bus_dat_r <= main_uart_eventmanager_status_w; end 3'd4: begin builder_interface4_bank_bus_dat_r <= main_uart_eventmanager_pending_w; end 3'd5: begin builder_interface4_bank_bus_dat_r <= builder_csrbank4_ev_enable0_w; end endcase end if (builder_csrbank4_ev_enable0_re) begin main_uart_eventmanager_storage[1:0] <= builder_csrbank4_ev_enable0_r; end main_uart_eventmanager_re <= builder_csrbank4_ev_enable0_re; if (sys_rst) begin main_soclinux_ctrl_storage <= 32'd305419896; main_soclinux_ctrl_re <= 1'd0; main_soclinux_ctrl_bus_errors <= 32'd0; main_soclinux_cpu_time_status <= 64'd0; main_soclinux_cpu_time_cmp_storage <= 64'd18446744073709551615; main_soclinux_cpu_time_cmp_re <= 1'd0; main_soclinux_cpu_time <= 64'd0; main_soclinux_cpu_time_cmp <= 64'd18446744073709551615; main_soclinux_rom_bus_ack <= 1'd0; main_soclinux_sram_bus_ack <= 1'd0; main_soclinux_main_ram_bus_ack <= 1'd0; main_soclinux_load_storage <= 32'd0; main_soclinux_load_re <= 1'd0; main_soclinux_reload_storage <= 32'd0; main_soclinux_reload_re <= 1'd0; main_soclinux_en_storage <= 1'd0; main_soclinux_en_re <= 1'd0; main_soclinux_update_value_storage <= 1'd0; main_soclinux_update_value_re <= 1'd0; main_soclinux_value_status <= 32'd0; main_soclinux_zero_pending <= 1'd0; main_soclinux_zero_old_trigger <= 1'd0; main_soclinux_eventmanager_storage <= 1'd0; main_soclinux_eventmanager_re <= 1'd0; main_soclinux_value <= 32'd0; main_bus_ack <= 1'd0; main_uart_tx_pending <= 1'd0; main_uart_tx_old_trigger <= 1'd0; main_uart_rx_pending <= 1'd0; main_uart_rx_old_trigger <= 1'd0; main_uart_eventmanager_storage <= 2'd0; main_uart_eventmanager_re <= 1'd0; main_uart_tx_fifo_readable <= 1'd0; main_uart_tx_fifo_level0 <= 5'd0; main_uart_tx_fifo_produce <= 4'd0; main_uart_tx_fifo_consume <= 4'd0; main_uart_rx_fifo_readable <= 1'd0; main_uart_rx_fifo_level0 <= 5'd0; main_uart_rx_fifo_produce <= 4'd0; main_uart_rx_fifo_consume <= 4'd0; builder_state <= 1'd0; builder_grant <= 1'd0; builder_slave_sel_r <= 5'd0; builder_count <= 20'd1000000; builder_interface0_bank_bus_dat_r <= 8'd0; builder_interface1_bank_bus_dat_r <= 8'd0; builder_interface2_bank_bus_dat_r <= 8'd0; builder_interface3_bank_bus_dat_r <= 8'd0; builder_interface4_bank_bus_dat_r <= 8'd0; end end reg [31:0] mem[0:8191]; reg [31:0] memdat; always @(posedge sys_clk_1) begin memdat <= mem[main_soclinux_rom_adr]; end assign main_soclinux_rom_dat_r = memdat; initial begin $readmemh("mem.init", mem); end reg [31:0] mem_1[0:1023]; reg [9:0] memadr; always @(posedge sys_clk_1) begin if (main_soclinux_sram_we[0]) mem_1[main_soclinux_sram_adr][7:0] <= main_soclinux_sram_dat_w[7:0]; if (main_soclinux_sram_we[1]) mem_1[main_soclinux_sram_adr][15:8] <= main_soclinux_sram_dat_w[15:8]; if (main_soclinux_sram_we[2]) mem_1[main_soclinux_sram_adr][23:16] <= main_soclinux_sram_dat_w[23:16]; if (main_soclinux_sram_we[3]) mem_1[main_soclinux_sram_adr][31:24] <= main_soclinux_sram_dat_w[31:24]; memadr <= main_soclinux_sram_adr; end assign main_soclinux_sram_dat_r = mem_1[memadr]; initial begin $readmemh("mem_1.init", mem_1); end reg [31:0] mem_2[0:8388607]; reg [22:0] memadr_1; always @(posedge sys_clk_1) begin if (main_soclinux_main_ram_we[0]) mem_2[main_soclinux_main_ram_adr][7:0] <= main_soclinux_main_ram_dat_w[7:0]; if (main_soclinux_main_ram_we[1]) mem_2[main_soclinux_main_ram_adr][15:8] <= main_soclinux_main_ram_dat_w[15:8]; if (main_soclinux_main_ram_we[2]) mem_2[main_soclinux_main_ram_adr][23:16] <= main_soclinux_main_ram_dat_w[23:16]; if (main_soclinux_main_ram_we[3]) mem_2[main_soclinux_main_ram_adr][31:24] <= main_soclinux_main_ram_dat_w[31:24]; memadr_1 <= main_soclinux_main_ram_adr; end assign main_soclinux_main_ram_dat_r = mem_2[memadr_1]; initial begin $readmemh("mem_2.init", mem_2); end reg [31:0] mem_3[0:4095]; reg [11:0] memadr_2; always @(posedge sys_clk_1) begin if (main_we[0]) mem_3[main_adr][7:0] <= main_dat_w[7:0]; if (main_we[1]) mem_3[main_adr][15:8] <= main_dat_w[15:8]; if (main_we[2]) mem_3[main_adr][23:16] <= main_dat_w[23:16]; if (main_we[3]) mem_3[main_adr][31:24] <= main_dat_w[31:24]; memadr_2 <= main_adr; end assign main_dat_r = mem_3[memadr_2]; initial begin $readmemh("mem_3.init", mem_3); end reg [9:0] storage[0:15]; reg [9:0] memdat_1; reg [9:0] memdat_2; always @(posedge sys_clk_1) begin if (main_uart_tx_fifo_wrport_we) storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w; memdat_1 <= storage[main_uart_tx_fifo_wrport_adr]; end always @(posedge sys_clk_1) begin if (main_uart_tx_fifo_rdport_re) memdat_2 <= storage[main_uart_tx_fifo_rdport_adr]; end assign main_uart_tx_fifo_wrport_dat_r = memdat_1; assign main_uart_tx_fifo_rdport_dat_r = memdat_2; reg [9:0] storage_1[0:15]; reg [9:0] memdat_3; reg [9:0] memdat_4; always @(posedge sys_clk_1) begin if (main_uart_rx_fifo_wrport_we) storage_1[main_uart_rx_fifo_wrport_adr] <= main_uart_rx_fifo_wrport_dat_w; memdat_3 <= storage_1[main_uart_rx_fifo_wrport_adr]; end always @(posedge sys_clk_1) begin if (main_uart_rx_fifo_rdport_re) memdat_4 <= storage_1[main_uart_rx_fifo_rdport_adr]; end assign main_uart_rx_fifo_wrport_dat_r = memdat_3; assign main_uart_rx_fifo_rdport_dat_r = memdat_4; VexRiscv VexRiscv( .clk(sys_clk_1), .dBusWishbone_ACK(main_soclinux_cpu_dbus_ack), .dBusWishbone_DAT_MISO(main_soclinux_cpu_dbus_dat_r), .dBusWishbone_ERR(main_soclinux_cpu_dbus_err), .externalInterruptArray(main_soclinux_cpu_interrupt0), .externalResetVector(1'd0), .iBusWishbone_ACK(main_soclinux_cpu_ibus_ack), .iBusWishbone_DAT_MISO(main_soclinux_cpu_ibus_dat_r), .iBusWishbone_ERR(main_soclinux_cpu_ibus_err), .reset((sys_rst | main_soclinux_cpu_reset)), .softwareInterrupt(1'd0), .timerInterrupt(main_soclinux_cpu_interrupt1), .dBusWishbone_ADR(main_soclinux_cpu_dbus_adr), .dBusWishbone_BTE(main_soclinux_cpu_dbus_bte), .dBusWishbone_CTI(main_soclinux_cpu_dbus_cti), .dBusWishbone_CYC(main_soclinux_cpu_dbus_cyc), .dBusWishbone_DAT_MOSI(main_soclinux_cpu_dbus_dat_w), .dBusWishbone_SEL(main_soclinux_cpu_dbus_sel), .dBusWishbone_STB(main_soclinux_cpu_dbus_stb), .dBusWishbone_WE(main_soclinux_cpu_dbus_we), .iBusWishbone_ADR(main_soclinux_cpu_ibus_adr), .iBusWishbone_BTE(main_soclinux_cpu_ibus_bte), .iBusWishbone_CTI(main_soclinux_cpu_ibus_cti), .iBusWishbone_CYC(main_soclinux_cpu_ibus_cyc), .iBusWishbone_DAT_MOSI(main_soclinux_cpu_ibus_dat_w), .iBusWishbone_SEL(main_soclinux_cpu_ibus_sel), .iBusWishbone_STB(main_soclinux_cpu_ibus_stb), .iBusWishbone_WE(main_soclinux_cpu_ibus_we) ); endmodule