$version Generated by VerilatedVcd $end $date Sun Dec 29 19:13:53 2019 $end $timescale 1ns $end $scope module TOP $end $var wire 8 ,M serial_sink_data [7:0] $end $var wire 1 ,L serial_sink_ready $end $var wire 1 ,K serial_sink_valid $end $var wire 8 ,J serial_source_data [7:0] $end $var wire 1 ,I serial_source_ready $end $var wire 1 ,H serial_source_valid $end $var wire 1 ,G sys_clk $end $scope module dut $end $var wire 14 l builder_adr [13:0] $end $var wire 30 C builder_array_muxed0 [29:0] $end $var wire 32 D builder_array_muxed1 [31:0] $end $var wire 4 E builder_array_muxed2 [3:0] $end $var wire 1 "L builder_array_muxed3 $end $var wire 1 G builder_array_muxed4 $end $var wire 1 I builder_array_muxed5 $end $var wire 3 J builder_array_muxed6 [2:0] $end $var wire 2 # builder_array_muxed7 [1:0] $end $var wire 20 "T builder_count [19:0] $end $var wire 1 #' builder_csrbank0_sel $end $var wire 8 n builder_csrbank0_timer_time0_r [7:0] $end $var wire 1 "k builder_csrbank0_timer_time0_re $end $var wire 8 "l builder_csrbank0_timer_time0_w [7:0] $end $var wire 1 : builder_csrbank0_timer_time0_we $end $var wire 8 n builder_csrbank0_timer_time1_r [7:0] $end $var wire 1 "h builder_csrbank0_timer_time1_re $end $var wire 8 "j builder_csrbank0_timer_time1_w [7:0] $end $var wire 1 "i builder_csrbank0_timer_time1_we $end $var wire 8 n builder_csrbank0_timer_time2_r [7:0] $end $var wire 1 "e builder_csrbank0_timer_time2_re $end $var wire 8 "g builder_csrbank0_timer_time2_w [7:0] $end $var wire 1 "f builder_csrbank0_timer_time2_we $end $var wire 8 n builder_csrbank0_timer_time3_r [7:0] $end $var wire 1 "b builder_csrbank0_timer_time3_re $end $var wire 8 "d builder_csrbank0_timer_time3_w [7:0] $end $var wire 1 "c builder_csrbank0_timer_time3_we $end $var wire 8 n builder_csrbank0_timer_time4_r [7:0] $end $var wire 1 "_ builder_csrbank0_timer_time4_re $end $var wire 8 "a builder_csrbank0_timer_time4_w [7:0] $end $var wire 1 "` builder_csrbank0_timer_time4_we $end $var wire 8 n builder_csrbank0_timer_time5_r [7:0] $end $var wire 1 "\ builder_csrbank0_timer_time5_re $end $var wire 8 "^ builder_csrbank0_timer_time5_w [7:0] $end $var wire 1 "] builder_csrbank0_timer_time5_we $end $var wire 8 n builder_csrbank0_timer_time6_r [7:0] $end $var wire 1 "Y builder_csrbank0_timer_time6_re $end $var wire 8 "[ builder_csrbank0_timer_time6_w [7:0] $end $var wire 1 "Z builder_csrbank0_timer_time6_we $end $var wire 8 n builder_csrbank0_timer_time7_r [7:0] $end $var wire 1 "V builder_csrbank0_timer_time7_re $end $var wire 8 "X builder_csrbank0_timer_time7_w [7:0] $end $var wire 1 "W builder_csrbank0_timer_time7_we $end $var wire 8 n builder_csrbank0_timer_time_cmp0_r [7:0] $end $var wire 1 #$ builder_csrbank0_timer_time_cmp0_re $end $var wire 8 #& builder_csrbank0_timer_time_cmp0_w [7:0] $end $var wire 1 #% builder_csrbank0_timer_time_cmp0_we $end $var wire 8 n builder_csrbank0_timer_time_cmp1_r [7:0] $end $var wire 1 #! builder_csrbank0_timer_time_cmp1_re $end $var wire 8 ## builder_csrbank0_timer_time_cmp1_w [7:0] $end $var wire 1 #" builder_csrbank0_timer_time_cmp1_we $end $var wire 8 n builder_csrbank0_timer_time_cmp2_r [7:0] $end $var wire 1 "| builder_csrbank0_timer_time_cmp2_re $end $var wire 8 "~ builder_csrbank0_timer_time_cmp2_w [7:0] $end $var wire 1 "} builder_csrbank0_timer_time_cmp2_we $end $var wire 8 n builder_csrbank0_timer_time_cmp3_r [7:0] $end $var wire 1 "y builder_csrbank0_timer_time_cmp3_re $end $var wire 8 "{ builder_csrbank0_timer_time_cmp3_w [7:0] $end $var wire 1 "z builder_csrbank0_timer_time_cmp3_we $end $var wire 8 n builder_csrbank0_timer_time_cmp4_r [7:0] $end $var wire 1 "v builder_csrbank0_timer_time_cmp4_re $end $var wire 8 "x builder_csrbank0_timer_time_cmp4_w [7:0] $end $var wire 1 "w builder_csrbank0_timer_time_cmp4_we $end $var wire 8 n builder_csrbank0_timer_time_cmp5_r [7:0] $end $var wire 1 "s builder_csrbank0_timer_time_cmp5_re $end $var wire 8 "u builder_csrbank0_timer_time_cmp5_w [7:0] $end $var wire 1 "t builder_csrbank0_timer_time_cmp5_we $end $var wire 8 n builder_csrbank0_timer_time_cmp6_r [7:0] $end $var wire 1 "p builder_csrbank0_timer_time_cmp6_re $end $var wire 8 "r builder_csrbank0_timer_time_cmp6_w [7:0] $end $var wire 1 "q builder_csrbank0_timer_time_cmp6_we $end $var wire 8 n builder_csrbank0_timer_time_cmp7_r [7:0] $end $var wire 1 "m builder_csrbank0_timer_time_cmp7_re $end $var wire 8 "o builder_csrbank0_timer_time_cmp7_w [7:0] $end $var wire 1 "n builder_csrbank0_timer_time_cmp7_we $end $var wire 8 n builder_csrbank1_bus_errors0_r [7:0] $end $var wire 1 #> builder_csrbank1_bus_errors0_re $end $var wire 8 #? builder_csrbank1_bus_errors0_w [7:0] $end $var wire 1 - builder_csrbank1_bus_errors0_we $end $var wire 8 n builder_csrbank1_bus_errors1_r [7:0] $end $var wire 1 #; builder_csrbank1_bus_errors1_re $end $var wire 8 #= builder_csrbank1_bus_errors1_w [7:0] $end $var wire 1 #< builder_csrbank1_bus_errors1_we $end $var wire 8 n builder_csrbank1_bus_errors2_r [7:0] $end $var wire 1 #8 builder_csrbank1_bus_errors2_re $end $var wire 8 #: builder_csrbank1_bus_errors2_w [7:0] $end $var wire 1 #9 builder_csrbank1_bus_errors2_we $end $var wire 8 n builder_csrbank1_bus_errors3_r [7:0] $end $var wire 1 #5 builder_csrbank1_bus_errors3_re $end $var wire 8 #7 builder_csrbank1_bus_errors3_w [7:0] $end $var wire 1 #6 builder_csrbank1_bus_errors3_we $end $var wire 8 n builder_csrbank1_scratch0_r [7:0] $end $var wire 1 #2 builder_csrbank1_scratch0_re $end $var wire 8 #4 builder_csrbank1_scratch0_w [7:0] $end $var wire 1 #3 builder_csrbank1_scratch0_we $end $var wire 8 n builder_csrbank1_scratch1_r [7:0] $end $var wire 1 #/ builder_csrbank1_scratch1_re $end $var wire 8 #1 builder_csrbank1_scratch1_w [7:0] $end $var wire 1 #0 builder_csrbank1_scratch1_we $end $var wire 8 n builder_csrbank1_scratch2_r [7:0] $end $var wire 1 #, builder_csrbank1_scratch2_re $end $var wire 8 #. builder_csrbank1_scratch2_w [7:0] $end $var wire 1 #- builder_csrbank1_scratch2_we $end $var wire 8 n builder_csrbank1_scratch3_r [7:0] $end $var wire 1 #) builder_csrbank1_scratch3_re $end $var wire 8 #+ builder_csrbank1_scratch3_w [7:0] $end $var wire 1 #* builder_csrbank1_scratch3_we $end $var wire 1 #@ builder_csrbank1_sel $end $var wire 1 #B builder_csrbank2_sel $end $var wire 1 ( builder_csrbank3_en0_r $end $var wire 1 #\ builder_csrbank3_en0_re $end $var wire 1 Z builder_csrbank3_en0_w $end $var wire 1 #] builder_csrbank3_en0_we $end $var wire 1 ( builder_csrbank3_ev_enable0_r $end $var wire 1 #k builder_csrbank3_ev_enable0_re $end $var wire 1 i builder_csrbank3_ev_enable0_w $end $var wire 1 #l builder_csrbank3_ev_enable0_we $end $var wire 8 n builder_csrbank3_load0_r [7:0] $end $var wire 1 #M builder_csrbank3_load0_re $end $var wire 8 #O builder_csrbank3_load0_w [7:0] $end $var wire 1 #N builder_csrbank3_load0_we $end $var wire 8 n builder_csrbank3_load1_r [7:0] $end $var wire 1 #J builder_csrbank3_load1_re $end $var wire 8 #L builder_csrbank3_load1_w [7:0] $end $var wire 1 #K builder_csrbank3_load1_we $end $var wire 8 n builder_csrbank3_load2_r [7:0] $end $var wire 1 #G builder_csrbank3_load2_re $end $var wire 8 #I builder_csrbank3_load2_w [7:0] $end $var wire 1 #H builder_csrbank3_load2_we $end $var wire 8 n builder_csrbank3_load3_r [7:0] $end $var wire 1 #D builder_csrbank3_load3_re $end $var wire 8 #F builder_csrbank3_load3_w [7:0] $end $var wire 1 #E builder_csrbank3_load3_we $end $var wire 8 n builder_csrbank3_reload0_r [7:0] $end $var wire 1 #Y builder_csrbank3_reload0_re $end $var wire 8 #[ builder_csrbank3_reload0_w [7:0] $end $var wire 1 #Z builder_csrbank3_reload0_we $end $var wire 8 n builder_csrbank3_reload1_r [7:0] $end $var wire 1 #V builder_csrbank3_reload1_re $end $var wire 8 #X builder_csrbank3_reload1_w [7:0] $end $var wire 1 #W builder_csrbank3_reload1_we $end $var wire 8 n builder_csrbank3_reload2_r [7:0] $end $var wire 1 #S builder_csrbank3_reload2_re $end $var wire 8 #U builder_csrbank3_reload2_w [7:0] $end $var wire 1 #T builder_csrbank3_reload2_we $end $var wire 8 n builder_csrbank3_reload3_r [7:0] $end $var wire 1 #P builder_csrbank3_reload3_re $end $var wire 8 #R builder_csrbank3_reload3_w [7:0] $end $var wire 1 #Q builder_csrbank3_reload3_we $end $var wire 1 #m builder_csrbank3_sel $end $var wire 1 ( builder_csrbank3_update_value0_r $end $var wire 1 #^ builder_csrbank3_update_value0_re $end $var wire 1 \ builder_csrbank3_update_value0_w $end $var wire 1 #_ builder_csrbank3_update_value0_we $end $var wire 8 n builder_csrbank3_value0_r [7:0] $end $var wire 1 #i builder_csrbank3_value0_re $end $var wire 8 #j builder_csrbank3_value0_w [7:0] $end $var wire 1 _ builder_csrbank3_value0_we $end $var wire 8 n builder_csrbank3_value1_r [7:0] $end $var wire 1 #f builder_csrbank3_value1_re $end $var wire 8 #h builder_csrbank3_value1_w [7:0] $end $var wire 1 #g builder_csrbank3_value1_we $end $var wire 8 n builder_csrbank3_value2_r [7:0] $end $var wire 1 #c builder_csrbank3_value2_re $end $var wire 8 #e builder_csrbank3_value2_w [7:0] $end $var wire 1 #d builder_csrbank3_value2_we $end $var wire 8 n builder_csrbank3_value3_r [7:0] $end $var wire 1 #` builder_csrbank3_value3_re $end $var wire 8 #b builder_csrbank3_value3_w [7:0] $end $var wire 1 #a builder_csrbank3_value3_we $end $var wire 2 ". builder_csrbank4_ev_enable0_r [1:0] $end $var wire 1 #q builder_csrbank4_ev_enable0_re $end $var wire 2 "4 builder_csrbank4_ev_enable0_w [1:0] $end $var wire 1 #r builder_csrbank4_ev_enable0_we $end $var wire 1 ( builder_csrbank4_rxempty_r $end $var wire 1 #p builder_csrbank4_rxempty_re $end $var wire 1 "$ builder_csrbank4_rxempty_w $end $var wire 1 "% builder_csrbank4_rxempty_we $end $var wire 1 #s builder_csrbank4_sel $end $var wire 1 ( builder_csrbank4_txfull_r $end $var wire 1 #o builder_csrbank4_txfull_re $end $var wire 1 "" builder_csrbank4_txfull_w $end $var wire 1 "# builder_csrbank4_txfull_we $end $var wire 8 o builder_dat_r [7:0] $end $var wire 8 n builder_dat_w [7:0] $end $var wire 1 "S builder_done $end $var wire 1 . builder_error $end $var wire 1 "O builder_grant $end $var wire 14 l builder_interface0_bank_bus_adr [13:0] $end $var wire 8 "U builder_interface0_bank_bus_dat_r [7:0] $end $var wire 8 n builder_interface0_bank_bus_dat_w [7:0] $end $var wire 1 m builder_interface0_bank_bus_we $end $var wire 14 l builder_interface1_bank_bus_adr [13:0] $end $var wire 8 #( builder_interface1_bank_bus_dat_r [7:0] $end $var wire 8 n builder_interface1_bank_bus_dat_w [7:0] $end $var wire 1 m builder_interface1_bank_bus_we $end $var wire 14 l builder_interface2_bank_bus_adr [13:0] $end $var wire 8 #A builder_interface2_bank_bus_dat_r [7:0] $end $var wire 8 n builder_interface2_bank_bus_dat_w [7:0] $end $var wire 1 m builder_interface2_bank_bus_we $end $var wire 14 l builder_interface3_bank_bus_adr [13:0] $end $var wire 8 #C builder_interface3_bank_bus_dat_r [7:0] $end $var wire 8 n builder_interface3_bank_bus_dat_w [7:0] $end $var wire 1 m builder_interface3_bank_bus_we $end $var wire 14 l builder_interface4_bank_bus_adr [13:0] $end $var wire 8 #n builder_interface4_bank_bus_dat_r [7:0] $end $var wire 8 n builder_interface4_bank_bus_dat_w [7:0] $end $var wire 1 m builder_interface4_bank_bus_we $end $var wire 1 "K builder_next_state $end $var wire 2 "N builder_request [1:0] $end $var wire 1 "M builder_shared_ack $end $var wire 30 C builder_shared_adr [29:0] $end $var wire 2 # builder_shared_bte [1:0] $end $var wire 3 J builder_shared_cti [2:0] $end $var wire 1 "L builder_shared_cyc $end $var wire 32 / builder_shared_dat_r [31:0] $end $var wire 32 D builder_shared_dat_w [31:0] $end $var wire 1 -" builder_shared_err $end $var wire 4 E builder_shared_sel [3:0] $end $var wire 1 G builder_shared_stb $end $var wire 1 I builder_shared_we $end $var wire 5 "P builder_slave_sel [4:0] $end $var wire 5 "Q builder_slave_sel_r [4:0] $end $var wire 1 "J builder_state $end $var wire 1 "R builder_wait $end $var wire 1 m builder_we $end $var wire 12 y main_adr [11:0] $end $var wire 1 x main_bus_ack $end $var wire 30 C main_bus_adr [29:0] $end $var wire 2 # main_bus_bte [1:0] $end $var wire 3 J main_bus_cti [2:0] $end $var wire 1 w main_bus_cyc $end $var wire 32 v main_bus_dat_r [31:0] $end $var wire 32 D main_bus_dat_w [31:0] $end $var wire 1 -" main_bus_err $end $var wire 4 E main_bus_sel [3:0] $end $var wire 1 G main_bus_stb $end $var wire 1 I main_bus_we $end $var wire 32 v main_dat_r [31:0] $end $var wire 32 D main_dat_w [31:0] $end $var wire 1 -" main_finish $end $var wire 1 ( main_finish_finish_r $end $var wire 1 s main_finish_finish_re $end $var wire 1 -" main_finish_finish_w $end $var wire 1 t main_finish_finish_we $end $var wire 1 u main_int_rst $end $var wire 1 { main_sink_first $end $var wire 1 | main_sink_last $end $var wire 8 % main_sink_payload_data [7:0] $end $var wire 1 ,I main_sink_ready $end $var wire 1 $ main_sink_valid $end $var wire 1 r main_soclinux_bus_wishbone_ack $end $var wire 30 C main_soclinux_bus_wishbone_adr [29:0] $end $var wire 2 # main_soclinux_bus_wishbone_bte [1:0] $end $var wire 3 J main_soclinux_bus_wishbone_cti [2:0] $end $var wire 1 q main_soclinux_bus_wishbone_cyc $end $var wire 32 p main_soclinux_bus_wishbone_dat_r [31:0] $end $var wire 32 D main_soclinux_bus_wishbone_dat_w [31:0] $end $var wire 1 -" main_soclinux_bus_wishbone_err $end $var wire 4 E main_soclinux_bus_wishbone_sel [3:0] $end $var wire 1 G main_soclinux_bus_wishbone_stb $end $var wire 1 I main_soclinux_bus_wishbone_we $end $var wire 1 3 main_soclinux_cpu_dbus_ack $end $var wire 30 '` main_soclinux_cpu_dbus_adr [29:0] $end $var wire 2 -% main_soclinux_cpu_dbus_bte [1:0] $end $var wire 3 4 main_soclinux_cpu_dbus_cti [2:0] $end $var wire 1 'c main_soclinux_cpu_dbus_cyc $end $var wire 32 / main_soclinux_cpu_dbus_dat_r [31:0] $end $var wire 32 'a main_soclinux_cpu_dbus_dat_w [31:0] $end $var wire 1 -" main_soclinux_cpu_dbus_err $end $var wire 4 'b main_soclinux_cpu_dbus_sel [3:0] $end $var wire 1 'c main_soclinux_cpu_dbus_stb $end $var wire 1 'd main_soclinux_cpu_dbus_we $end $var wire 1 2 main_soclinux_cpu_ibus_ack $end $var wire 30 '^ main_soclinux_cpu_ibus_adr [29:0] $end $var wire 2 -% main_soclinux_cpu_ibus_bte [1:0] $end $var wire 3 '_ main_soclinux_cpu_ibus_cti [2:0] $end $var wire 1 0 main_soclinux_cpu_ibus_cyc $end $var wire 32 / main_soclinux_cpu_ibus_dat_r [31:0] $end $var wire 32 -# main_soclinux_cpu_ibus_dat_w [31:0] $end $var wire 1 -" main_soclinux_cpu_ibus_err $end $var wire 4 -$ main_soclinux_cpu_ibus_sel [3:0] $end $var wire 1 1 main_soclinux_cpu_ibus_stb $end $var wire 1 -" main_soclinux_cpu_ibus_we $end $var wire 32 5 main_soclinux_cpu_interrupt0 [31:0] $end $var wire 1 > main_soclinux_cpu_interrupt1 $end $var wire 1 ( main_soclinux_cpu_latch_r $end $var wire 1 6 main_soclinux_cpu_latch_re $end $var wire 1 -" main_soclinux_cpu_latch_w $end $var wire 1 7 main_soclinux_cpu_latch_we $end $var wire 1 ' main_soclinux_cpu_reset $end $var wire 64 ? main_soclinux_cpu_time [63:0] $end $var wire 64 A main_soclinux_cpu_time_cmp [63:0] $end $var wire 1 = main_soclinux_cpu_time_cmp_re $end $var wire 64 ; main_soclinux_cpu_time_cmp_storage [63:0] $end $var wire 64 8 main_soclinux_cpu_time_status [63:0] $end $var wire 1 : main_soclinux_cpu_time_we $end $var wire 1 . main_soclinux_ctrl_bus_error $end $var wire 32 , main_soclinux_ctrl_bus_errors [31:0] $end $var wire 32 , main_soclinux_ctrl_bus_errors_status [31:0] $end $var wire 1 - main_soclinux_ctrl_bus_errors_we $end $var wire 1 + main_soclinux_ctrl_re $end $var wire 1 ' main_soclinux_ctrl_reset $end $var wire 1 ( main_soclinux_ctrl_reset_reset_r $end $var wire 1 ' main_soclinux_ctrl_reset_reset_re $end $var wire 1 -" main_soclinux_ctrl_reset_reset_w $end $var wire 1 ) main_soclinux_ctrl_reset_reset_we $end $var wire 32 * main_soclinux_ctrl_storage [31:0] $end $var wire 1 [ main_soclinux_en_re $end $var wire 1 Z main_soclinux_en_storage $end $var wire 1 ( main_soclinux_eventmanager_pending_r $end $var wire 1 g main_soclinux_eventmanager_pending_re $end $var wire 1 b main_soclinux_eventmanager_pending_w $end $var wire 1 h main_soclinux_eventmanager_pending_we $end $var wire 1 j main_soclinux_eventmanager_re $end $var wire 1 ( main_soclinux_eventmanager_status_r $end $var wire 1 e main_soclinux_eventmanager_status_re $end $var wire 1 a main_soclinux_eventmanager_status_w $end $var wire 1 f main_soclinux_eventmanager_status_we $end $var wire 1 i main_soclinux_eventmanager_storage $end $var wire 1 2 main_soclinux_interface0_soc_bus_ack $end $var wire 30 '^ main_soclinux_interface0_soc_bus_adr [29:0] $end $var wire 2 -% main_soclinux_interface0_soc_bus_bte [1:0] $end $var wire 3 '_ main_soclinux_interface0_soc_bus_cti [2:0] $end $var wire 1 0 main_soclinux_interface0_soc_bus_cyc $end $var wire 32 / main_soclinux_interface0_soc_bus_dat_r [31:0] $end $var wire 32 -# main_soclinux_interface0_soc_bus_dat_w [31:0] $end $var wire 1 -" main_soclinux_interface0_soc_bus_err $end $var wire 4 -$ main_soclinux_interface0_soc_bus_sel [3:0] $end $var wire 1 1 main_soclinux_interface0_soc_bus_stb $end $var wire 1 -" main_soclinux_interface0_soc_bus_we $end $var wire 1 3 main_soclinux_interface1_soc_bus_ack $end $var wire 30 '` main_soclinux_interface1_soc_bus_adr [29:0] $end $var wire 2 -% main_soclinux_interface1_soc_bus_bte [1:0] $end $var wire 3 4 main_soclinux_interface1_soc_bus_cti [2:0] $end $var wire 1 'c main_soclinux_interface1_soc_bus_cyc $end $var wire 32 / main_soclinux_interface1_soc_bus_dat_r [31:0] $end $var wire 32 'a main_soclinux_interface1_soc_bus_dat_w [31:0] $end $var wire 1 -" main_soclinux_interface1_soc_bus_err $end $var wire 4 'b main_soclinux_interface1_soc_bus_sel [3:0] $end $var wire 1 'c main_soclinux_interface1_soc_bus_stb $end $var wire 1 'd main_soclinux_interface1_soc_bus_we $end $var wire 14 l main_soclinux_interface_adr [13:0] $end $var wire 8 o main_soclinux_interface_dat_r [7:0] $end $var wire 8 n main_soclinux_interface_dat_w [7:0] $end $var wire 1 m main_soclinux_interface_we $end $var wire 1 ` main_soclinux_irq $end $var wire 1 W main_soclinux_load_re $end $var wire 32 V main_soclinux_load_storage [31:0] $end $var wire 23 T main_soclinux_main_ram_adr [22:0] $end $var wire 1 S main_soclinux_main_ram_bus_ack $end $var wire 30 C main_soclinux_main_ram_bus_adr [29:0] $end $var wire 2 # main_soclinux_main_ram_bus_bte [1:0] $end $var wire 3 J main_soclinux_main_ram_bus_cti [2:0] $end $var wire 1 R main_soclinux_main_ram_bus_cyc $end $var wire 32 Q main_soclinux_main_ram_bus_dat_r [31:0] $end $var wire 32 D main_soclinux_main_ram_bus_dat_w [31:0] $end $var wire 1 -" main_soclinux_main_ram_bus_err $end $var wire 4 E main_soclinux_main_ram_bus_sel [3:0] $end $var wire 1 G main_soclinux_main_ram_bus_stb $end $var wire 1 I main_soclinux_main_ram_bus_we $end $var wire 32 Q main_soclinux_main_ram_dat_r [31:0] $end $var wire 32 D main_soclinux_main_ram_dat_w [31:0] $end $var wire 4 U main_soclinux_main_ram_we [3:0] $end $var wire 1 Y main_soclinux_reload_re $end $var wire 32 X main_soclinux_reload_storage [31:0] $end $var wire 13 K main_soclinux_rom_adr [12:0] $end $var wire 1 H main_soclinux_rom_bus_ack $end $var wire 30 C main_soclinux_rom_bus_adr [29:0] $end $var wire 2 # main_soclinux_rom_bus_bte [1:0] $end $var wire 3 J main_soclinux_rom_bus_cti [2:0] $end $var wire 1 F main_soclinux_rom_bus_cyc $end $var wire 32 'e main_soclinux_rom_bus_dat_r [31:0] $end $var wire 32 D main_soclinux_rom_bus_dat_w [31:0] $end $var wire 1 -" main_soclinux_rom_bus_err $end $var wire 4 E main_soclinux_rom_bus_sel [3:0] $end $var wire 1 G main_soclinux_rom_bus_stb $end $var wire 1 I main_soclinux_rom_bus_we $end $var wire 32 'e main_soclinux_rom_dat_r [31:0] $end $var wire 10 O main_soclinux_sram_adr [9:0] $end $var wire 1 N main_soclinux_sram_bus_ack $end $var wire 30 C main_soclinux_sram_bus_adr [29:0] $end $var wire 2 # main_soclinux_sram_bus_bte [1:0] $end $var wire 3 J main_soclinux_sram_bus_cti [2:0] $end $var wire 1 M main_soclinux_sram_bus_cyc $end $var wire 32 L main_soclinux_sram_bus_dat_r [31:0] $end $var wire 32 D main_soclinux_sram_bus_dat_w [31:0] $end $var wire 1 -" main_soclinux_sram_bus_err $end $var wire 4 E main_soclinux_sram_bus_sel [3:0] $end $var wire 1 G main_soclinux_sram_bus_stb $end $var wire 1 I main_soclinux_sram_bus_we $end $var wire 32 L main_soclinux_sram_dat_r [31:0] $end $var wire 32 D main_soclinux_sram_dat_w [31:0] $end $var wire 4 P main_soclinux_sram_we [3:0] $end $var wire 1 ] main_soclinux_update_value_re $end $var wire 1 \ main_soclinux_update_value_storage $end $var wire 32 k main_soclinux_value [31:0] $end $var wire 32 ^ main_soclinux_value_status [31:0] $end $var wire 1 _ main_soclinux_value_we $end $var wire 1 c main_soclinux_zero_clear $end $var wire 1 d main_soclinux_zero_old_trigger $end $var wire 1 b main_soclinux_zero_pending $end $var wire 1 a main_soclinux_zero_status $end $var wire 1 a main_soclinux_zero_trigger $end $var wire 1 -" main_source_first $end $var wire 1 -" main_source_last $end $var wire 8 ,M main_source_payload_data [7:0] $end $var wire 1 & main_source_ready $end $var wire 1 ,K main_source_valid $end $var wire 2 ". main_uart_eventmanager_pending_r [1:0] $end $var wire 1 "1 main_uart_eventmanager_pending_re $end $var wire 2 "3 main_uart_eventmanager_pending_w [1:0] $end $var wire 1 "2 main_uart_eventmanager_pending_we $end $var wire 1 "5 main_uart_eventmanager_re $end $var wire 2 ". main_uart_eventmanager_status_r [1:0] $end $var wire 1 "- main_uart_eventmanager_status_re $end $var wire 2 "0 main_uart_eventmanager_status_w [1:0] $end $var wire 1 "/ main_uart_eventmanager_status_we $end $var wire 2 "4 main_uart_eventmanager_storage [1:0] $end $var wire 1 "& main_uart_irq $end $var wire 1 "+ main_uart_rx_clear $end $var wire 4 "F main_uart_rx_fifo_consume [3:0] $end $var wire 1 "H main_uart_rx_fifo_do_read $end $var wire 1 -" main_uart_rx_fifo_fifo_in_first $end $var wire 1 -" main_uart_rx_fifo_fifo_in_last $end $var wire 8 ,M main_uart_rx_fifo_fifo_in_payload_data [7:0] $end $var wire 1 "@ main_uart_rx_fifo_fifo_out_first $end $var wire 1 "A main_uart_rx_fifo_fifo_out_last $end $var wire 8 "! main_uart_rx_fifo_fifo_out_payload_data [7:0] $end $var wire 5 "D main_uart_rx_fifo_level0 [4:0] $end $var wire 5 "I main_uart_rx_fifo_level1 [4:0] $end $var wire 4 "E main_uart_rx_fifo_produce [3:0] $end $var wire 4 "F main_uart_rx_fifo_rdport_adr [3:0] $end $var wire 10 'h main_uart_rx_fifo_rdport_dat_r [9:0] $end $var wire 1 "H main_uart_rx_fifo_rdport_re $end $var wire 1 "+ main_uart_rx_fifo_re $end $var wire 1 "? main_uart_rx_fifo_readable $end $var wire 1 -" main_uart_rx_fifo_replace $end $var wire 1 -" main_uart_rx_fifo_sink_first $end $var wire 1 -" main_uart_rx_fifo_sink_last $end $var wire 8 ,M main_uart_rx_fifo_sink_payload_data [7:0] $end $var wire 1 & main_uart_rx_fifo_sink_ready $end $var wire 1 ,K main_uart_rx_fifo_sink_valid $end $var wire 1 "@ main_uart_rx_fifo_source_first $end $var wire 1 "A main_uart_rx_fifo_source_last $end $var wire 8 "! main_uart_rx_fifo_source_payload_data [7:0] $end $var wire 1 "+ main_uart_rx_fifo_source_ready $end $var wire 1 "? main_uart_rx_fifo_source_valid $end $var wire 10 ,N main_uart_rx_fifo_syncfifo_din [9:0] $end $var wire 10 'h main_uart_rx_fifo_syncfifo_dout [9:0] $end $var wire 1 "B main_uart_rx_fifo_syncfifo_re $end $var wire 1 "C main_uart_rx_fifo_syncfifo_readable $end $var wire 1 ,K main_uart_rx_fifo_syncfifo_we $end $var wire 1 & main_uart_rx_fifo_syncfifo_writable $end $var wire 4 "G main_uart_rx_fifo_wrport_adr [3:0] $end $var wire 10 'i main_uart_rx_fifo_wrport_dat_r [9:0] $end $var wire 10 ,N main_uart_rx_fifo_wrport_dat_w [9:0] $end $var wire 1 ,O main_uart_rx_fifo_wrport_we $end $var wire 1 ", main_uart_rx_old_trigger $end $var wire 1 "* main_uart_rx_pending $end $var wire 1 "$ main_uart_rx_status $end $var wire 1 "$ main_uart_rx_trigger $end $var wire 1 "$ main_uart_rxempty_status $end $var wire 1 "% main_uart_rxempty_we $end $var wire 8 n main_uart_rxtx_r [7:0] $end $var wire 1 } main_uart_rxtx_re $end $var wire 8 "! main_uart_rxtx_w [7:0] $end $var wire 1 ~ main_uart_rxtx_we $end $var wire 1 "( main_uart_tx_clear $end $var wire 4 "; main_uart_tx_fifo_consume [3:0] $end $var wire 1 '] main_uart_tx_fifo_do_read $end $var wire 1 -" main_uart_tx_fifo_fifo_in_first $end $var wire 1 -" main_uart_tx_fifo_fifo_in_last $end $var wire 8 n main_uart_tx_fifo_fifo_in_payload_data [7:0] $end $var wire 1 { main_uart_tx_fifo_fifo_out_first $end $var wire 1 | main_uart_tx_fifo_fifo_out_last $end $var wire 8 % main_uart_tx_fifo_fifo_out_payload_data [7:0] $end $var wire 5 "9 main_uart_tx_fifo_level0 [4:0] $end $var wire 5 "> main_uart_tx_fifo_level1 [4:0] $end $var wire 4 ": main_uart_tx_fifo_produce [3:0] $end $var wire 4 "; main_uart_tx_fifo_rdport_adr [3:0] $end $var wire 10 'f main_uart_tx_fifo_rdport_dat_r [9:0] $end $var wire 1 '] main_uart_tx_fifo_rdport_re $end $var wire 1 ,I main_uart_tx_fifo_re $end $var wire 1 $ main_uart_tx_fifo_readable $end $var wire 1 -" main_uart_tx_fifo_replace $end $var wire 1 -" main_uart_tx_fifo_sink_first $end $var wire 1 -" main_uart_tx_fifo_sink_last $end $var wire 8 n main_uart_tx_fifo_sink_payload_data [7:0] $end $var wire 1 "6 main_uart_tx_fifo_sink_ready $end $var wire 1 } main_uart_tx_fifo_sink_valid $end $var wire 1 { main_uart_tx_fifo_source_first $end $var wire 1 | main_uart_tx_fifo_source_last $end $var wire 8 % main_uart_tx_fifo_source_payload_data [7:0] $end $var wire 1 ,I main_uart_tx_fifo_source_ready $end $var wire 1 $ main_uart_tx_fifo_source_valid $end $var wire 10 "8 main_uart_tx_fifo_syncfifo_din [9:0] $end $var wire 10 'f main_uart_tx_fifo_syncfifo_dout [9:0] $end $var wire 1 '\ main_uart_tx_fifo_syncfifo_re $end $var wire 1 "7 main_uart_tx_fifo_syncfifo_readable $end $var wire 1 } main_uart_tx_fifo_syncfifo_we $end $var wire 1 "6 main_uart_tx_fifo_syncfifo_writable $end $var wire 4 "< main_uart_tx_fifo_wrport_adr [3:0] $end $var wire 10 'g main_uart_tx_fifo_wrport_dat_r [9:0] $end $var wire 10 "8 main_uart_tx_fifo_wrport_dat_w [9:0] $end $var wire 1 "= main_uart_tx_fifo_wrport_we $end $var wire 1 ") main_uart_tx_old_trigger $end $var wire 1 "' main_uart_tx_pending $end $var wire 1 "" main_uart_tx_status $end $var wire 1 "" main_uart_tx_trigger $end $var wire 1 "" main_uart_txfull_status $end $var wire 1 "# main_uart_txfull_we $end $var wire 4 z main_we [3:0] $end $var wire 10 'j memadr [9:0] $end $var wire 23 'k memadr_1 [22:0] $end $var wire 12 'l memadr_2 [11:0] $end $var wire 32 'e memdat [31:0] $end $var wire 10 'g memdat_1 [9:0] $end $var wire 10 'f memdat_2 [9:0] $end $var wire 10 'i memdat_3 [9:0] $end $var wire 10 'h memdat_4 [9:0] $end $var wire 1 ,G por_clk $end $var wire 8 ,M serial_sink_data [7:0] $end $var wire 1 & serial_sink_ready $end $var wire 1 ,K serial_sink_valid $end $var wire 8 % serial_source_data [7:0] $end $var wire 1 ,I serial_source_ready $end $var wire 1 $ serial_source_valid $end $var wire 10 'm storage(0) [9:0] $end $var wire 10 'n storage(1) [9:0] $end $var wire 10 'w storage(10) [9:0] $end $var wire 10 'x storage(11) [9:0] $end $var wire 10 'y storage(12) [9:0] $end $var wire 10 'z storage(13) [9:0] $end $var wire 10 '{ storage(14) [9:0] $end $var wire 10 '| storage(15) [9:0] $end $var wire 10 'o storage(2) [9:0] $end $var wire 10 'p storage(3) [9:0] $end $var wire 10 'q storage(4) [9:0] $end $var wire 10 'r storage(5) [9:0] $end $var wire 10 's storage(6) [9:0] $end $var wire 10 't storage(7) [9:0] $end $var wire 10 'u storage(8) [9:0] $end $var wire 10 'v storage(9) [9:0] $end $var wire 10 '} storage_1(0) [9:0] $end $var wire 10 '~ storage_1(1) [9:0] $end $var wire 10 () storage_1(10) [9:0] $end $var wire 10 (* storage_1(11) [9:0] $end $var wire 10 (+ storage_1(12) [9:0] $end $var wire 10 (, storage_1(13) [9:0] $end $var wire 10 (- storage_1(14) [9:0] $end $var wire 10 (. storage_1(15) [9:0] $end $var wire 10 (! storage_1(2) [9:0] $end $var wire 10 (" storage_1(3) [9:0] $end $var wire 10 (# storage_1(4) [9:0] $end $var wire 10 ($ storage_1(5) [9:0] $end $var wire 10 (% storage_1(6) [9:0] $end $var wire 10 (& storage_1(7) [9:0] $end $var wire 10 (' storage_1(8) [9:0] $end $var wire 10 (( storage_1(9) [9:0] $end $var wire 1 ,G sys_clk $end $var wire 1 ,G sys_clk_1 $end $var wire 1 u sys_rst $end $scope module VexRiscv $end $var wire 32 (_ BranchPlugin_jumpInterface_payload [31:0] $end $var wire 1 %( BranchPlugin_jumpInterface_valid $end $var wire 1 -' CsrPlugin_allowException $end $var wire 1 -' CsrPlugin_allowInterrupts $end $var wire 1 &P CsrPlugin_exception $end $var wire 1 )2 CsrPlugin_exceptionPendings_0 $end $var wire 1 )3 CsrPlugin_exceptionPendings_1 $end $var wire 1 )4 CsrPlugin_exceptionPendings_2 $end $var wire 1 )5 CsrPlugin_exceptionPendings_3 $end $var wire 32 +4 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr [31:0] $end $var wire 4 +3 CsrPlugin_exceptionPortCtrl_exceptionContext_code [3:0] $end $var wire 2 &R CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege [1:0] $end $var wire 2 &Q CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped [1:0] $end $var wire 1 )2 CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode $end $var wire 1 )3 CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute $end $var wire 1 )4 CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory $end $var wire 1 )5 CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack $end $var wire 1 &M CsrPlugin_exceptionPortCtrl_exceptionValids_decode $end $var wire 1 &N CsrPlugin_exceptionPortCtrl_exceptionValids_execute $end $var wire 1 &O CsrPlugin_exceptionPortCtrl_exceptionValids_memory $end $var wire 1 &P CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack $end $var wire 1 -" CsrPlugin_forceMachineWire $end $var wire 1 +8 CsrPlugin_hadException $end $var wire 1 ,^ CsrPlugin_interruptJump $end $var wire 4 ,] CsrPlugin_interrupt_code [3:0] $end $var wire 2 +6 CsrPlugin_interrupt_targetPrivilege [1:0] $end $var wire 1 +5 CsrPlugin_interrupt_valid $end $var wire 32 %D CsrPlugin_jumpInterface_payload [31:0] $end $var wire 1 %C CsrPlugin_jumpInterface_valid $end $var wire 1 +7 CsrPlugin_lastStageWasWfi $end $var wire 4 *o CsrPlugin_mcause_exceptionCode [3:0] $end $var wire 1 *n CsrPlugin_mcause_interrupt $end $var wire 64 &H CsrPlugin_mcycle [63:0] $end $var wire 1 *y CsrPlugin_medeleg_ES $end $var wire 1 *x CsrPlugin_medeleg_EU $end $var wire 1 *r CsrPlugin_medeleg_IAF $end $var wire 1 *q CsrPlugin_medeleg_IAM $end $var wire 1 *s CsrPlugin_medeleg_II $end $var wire 1 *z CsrPlugin_medeleg_IPF $end $var wire 1 *u CsrPlugin_medeleg_LAF $end $var wire 1 *t CsrPlugin_medeleg_LAM $end $var wire 1 *{ CsrPlugin_medeleg_LPF $end $var wire 1 *w CsrPlugin_medeleg_SAF $end $var wire 1 *v CsrPlugin_medeleg_SAM $end $var wire 1 *| CsrPlugin_medeleg_SPF $end $var wire 32 *c CsrPlugin_mepc [31:0] $end $var wire 1 *~ CsrPlugin_mideleg_SE $end $var wire 1 +! CsrPlugin_mideleg_SS $end $var wire 1 *} CsrPlugin_mideleg_ST $end $var wire 1 *j CsrPlugin_mie_MEIE $end $var wire 1 *l CsrPlugin_mie_MSIE $end $var wire 1 *k CsrPlugin_mie_MTIE $end $var wire 64 &J CsrPlugin_minstret [63:0] $end $var wire 1 *g CsrPlugin_mip_MEIP $end $var wire 1 *i CsrPlugin_mip_MSIP $end $var wire 1 *h CsrPlugin_mip_MTIP $end $var wire 2 -0 CsrPlugin_misa_base [1:0] $end $var wire 26 -1 CsrPlugin_misa_extensions [25:0] $end $var wire 32 *m CsrPlugin_mscratch [31:0] $end $var wire 1 *d CsrPlugin_mstatus_MIE $end $var wire 1 *e CsrPlugin_mstatus_MPIE $end $var wire 2 *f CsrPlugin_mstatus_MPP [1:0] $end $var wire 32 *p CsrPlugin_mtval [31:0] $end $var wire 30 *b CsrPlugin_mtvec_base [29:0] $end $var wire 2 *a CsrPlugin_mtvec_mode [1:0] $end $var wire 1 &S CsrPlugin_pipelineLiberator_done $end $var wire 2 )6 CsrPlugin_privilege [1:0] $end $var wire 9 -3 CsrPlugin_satp_ASID [8:0] $end $var wire 1 -4 CsrPlugin_satp_MODE [0:0] $end $var wire 22 -2 CsrPlugin_satp_PPN [21:0] $end $var wire 4 +0 CsrPlugin_scause_exceptionCode [3:0] $end $var wire 1 +/ CsrPlugin_scause_interrupt $end $var wire 32 )& CsrPlugin_selfException_payload_badAddr [31:0] $end $var wire 4 %H CsrPlugin_selfException_payload_code [3:0] $end $var wire 1 %G CsrPlugin_selfException_valid $end $var wire 32 +2 CsrPlugin_sepc [31:0] $end $var wire 1 +) CsrPlugin_sie_SEIE $end $var wire 1 ++ CsrPlugin_sie_SSIE $end $var wire 1 +* CsrPlugin_sie_STIE $end $var wire 1 +& CsrPlugin_sip_SEIP_INPUT $end $var wire 1 &L CsrPlugin_sip_SEIP_OR $end $var wire 1 +% CsrPlugin_sip_SEIP_SOFT $end $var wire 1 +( CsrPlugin_sip_SSIP $end $var wire 1 +' CsrPlugin_sip_STIP $end $var wire 32 +. CsrPlugin_sscratch [31:0] $end $var wire 1 +" CsrPlugin_sstatus_SIE $end $var wire 1 +# CsrPlugin_sstatus_SPIE $end $var wire 1 +$ CsrPlugin_sstatus_SPP [0:0] $end $var wire 32 +1 CsrPlugin_stval [31:0] $end $var wire 30 +- CsrPlugin_stvec_base [29:0] $end $var wire 2 +, CsrPlugin_stvec_mode [1:0] $end $var wire 2 &T CsrPlugin_targetPrivilege [1:0] $end $var wire 4 &U CsrPlugin_trapCause [3:0] $end $var wire 30 &W CsrPlugin_xtvec_base [29:0] $end $var wire 2 &V CsrPlugin_xtvec_mode [1:0] $end $var wire 32 ({ DBusCachedPlugin_exceptionBus_payload_badAddr [31:0] $end $var wire 4 %< DBusCachedPlugin_exceptionBus_payload_code [3:0] $end $var wire 1 %; DBusCachedPlugin_exceptionBus_valid $end $var wire 1 %j DBusCachedPlugin_forceDatapath $end $var wire 1 )1 DBusCachedPlugin_mmuBus_busy $end $var wire 1 %2 DBusCachedPlugin_mmuBus_cmd_bypassTranslation $end $var wire 1 #z DBusCachedPlugin_mmuBus_cmd_isValid $end $var wire 32 (9 DBusCachedPlugin_mmuBus_cmd_virtualAddress [31:0] $end $var wire 1 #{ DBusCachedPlugin_mmuBus_end $end $var wire 1 %7 DBusCachedPlugin_mmuBus_rsp_allowExecute $end $var wire 1 %5 DBusCachedPlugin_mmuBus_rsp_allowRead $end $var wire 1 %6 DBusCachedPlugin_mmuBus_rsp_allowWrite $end $var wire 1 %8 DBusCachedPlugin_mmuBus_rsp_exception $end $var wire 1 %4 DBusCachedPlugin_mmuBus_rsp_isIoAccess $end $var wire 32 %3 DBusCachedPlugin_mmuBus_rsp_physicalAddress [31:0] $end $var wire 1 %9 DBusCachedPlugin_mmuBus_rsp_refilling $end $var wire 32 )' DBusCachedPlugin_redoBranch_payload [31:0] $end $var wire 1 %: DBusCachedPlugin_redoBranch_valid $end $var wire 32 )K DBusCachedPlugin_rspCounter [31:0] $end $var wire 1 (5 IBusCachedPlugin_cache_io_cpu_decode_cacheMiss $end $var wire 32 (4 IBusCachedPlugin_cache_io_cpu_decode_data [31:0] $end $var wire 1 (1 IBusCachedPlugin_cache_io_cpu_decode_error $end $var wire 1 (3 IBusCachedPlugin_cache_io_cpu_decode_mmuException $end $var wire 1 (2 IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling $end $var wire 32 (6 IBusCachedPlugin_cache_io_cpu_decode_physicalAddress [31:0] $end $var wire 32 (/ IBusCachedPlugin_cache_io_cpu_fetch_data [31:0] $end $var wire 1 (0 IBusCachedPlugin_cache_io_cpu_fetch_haltIt $end $var wire 1 -" IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation $end $var wire 1 #w IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid $end $var wire 32 ,P IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress [31:0] $end $var wire 1 #x IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end $end $var wire 32 #v IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress [31:0] $end $var wire 1 #u IBusCachedPlugin_cache_io_cpu_prefetch_haltIt $end $var wire 32 (7 IBusCachedPlugin_cache_io_mem_cmd_payload_address [31:0] $end $var wire 3 -& IBusCachedPlugin_cache_io_mem_cmd_payload_size [2:0] $end $var wire 1 #y IBusCachedPlugin_cache_io_mem_cmd_valid $end $var wire 32 )0 IBusCachedPlugin_decodeExceptionPort_payload_badAddr [31:0] $end $var wire 4 %+ IBusCachedPlugin_decodeExceptionPort_payload_code [3:0] $end $var wire 1 %* IBusCachedPlugin_decodeExceptionPort_valid $end $var wire 1 -" IBusCachedPlugin_decodePc_injectedDecode $end $var wire 32 ,Q IBusCachedPlugin_decodePc_pcPlus [31:0] $end $var wire 32 ,R IBusCachedPlugin_decodePc_pcReg [31:0] $end $var wire 1 $N IBusCachedPlugin_decodePrediction_cmd_hadBranch $end $var wire 1 %( IBusCachedPlugin_decodePrediction_rsp_wasWrong $end $var wire 16 )= IBusCachedPlugin_decompressor_bufferData [15:0] $end $var wire 1 %^ IBusCachedPlugin_decompressor_bufferFill $end $var wire 1 )< IBusCachedPlugin_decompressor_bufferValid $end $var wire 1 $a IBusCachedPlugin_decompressor_decodeInput_payload_isRvc $end $var wire 32 ); IBusCachedPlugin_decompressor_decodeInput_payload_pc [31:0] $end $var wire 1 -/ IBusCachedPlugin_decompressor_decodeInput_payload_rsp_error $end $var wire 32 $` IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst [31:0] $end $var wire 1 %[ IBusCachedPlugin_decompressor_decodeInput_ready $end $var wire 1 %Z IBusCachedPlugin_decompressor_decodeInput_valid $end $var wire 32 %] IBusCachedPlugin_decompressor_decompressed [31:0] $end $var wire 1 $a IBusCachedPlugin_decompressor_isRvc $end $var wire 32 %\ IBusCachedPlugin_decompressor_rawInDecode [31:0] $end $var wire 1 )7 IBusCachedPlugin_fetchPc_booted $end $var wire 1 %N IBusCachedPlugin_fetchPc_corrected $end $var wire 1 )8 IBusCachedPlugin_fetchPc_inc $end $var wire 32 %M IBusCachedPlugin_fetchPc_output_payload [31:0] $end $var wire 1 %L IBusCachedPlugin_fetchPc_output_ready $end $var wire 1 %K IBusCachedPlugin_fetchPc_output_valid $end $var wire 32 %M IBusCachedPlugin_fetchPc_pc [31:0] $end $var wire 32 ,P IBusCachedPlugin_fetchPc_pcReg [31:0] $end $var wire 1 %O IBusCachedPlugin_fetchPc_pcRegPropagate $end $var wire 1 %# IBusCachedPlugin_fetcherHalt $end $var wire 1 %$ IBusCachedPlugin_fetcherflushIt $end $var wire 1 %X IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt $end $var wire 1 -, IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample $end $var wire 32 ); IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload [31:0] $end $var wire 1 %T IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready $end $var wire 1 ): IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid $end $var wire 32 ); IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload [31:0] $end $var wire 1 %W IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready $end $var wire 1 %V IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid $end $var wire 1 -. IBusCachedPlugin_iBusRsp_output_payload_isRvc $end $var wire 32 ); IBusCachedPlugin_iBusRsp_output_payload_pc [31:0] $end $var wire 1 -- IBusCachedPlugin_iBusRsp_output_payload_rsp_error $end $var wire 32 (4 IBusCachedPlugin_iBusRsp_output_payload_rsp_inst [31:0] $end $var wire 1 %W IBusCachedPlugin_iBusRsp_output_ready $end $var wire 1 %V IBusCachedPlugin_iBusRsp_output_valid $end $var wire 1 %Y IBusCachedPlugin_iBusRsp_readyForError $end $var wire 1 %R IBusCachedPlugin_iBusRsp_stages_0_halt $end $var wire 1 -' IBusCachedPlugin_iBusRsp_stages_0_inputSample $end $var wire 32 %M IBusCachedPlugin_iBusRsp_stages_0_input_payload [31:0] $end $var wire 1 %L IBusCachedPlugin_iBusRsp_stages_0_input_ready $end $var wire 1 %K IBusCachedPlugin_iBusRsp_stages_0_input_valid $end $var wire 32 %M IBusCachedPlugin_iBusRsp_stages_0_output_payload [31:0] $end $var wire 1 %Q IBusCachedPlugin_iBusRsp_stages_0_output_ready $end $var wire 1 %P IBusCachedPlugin_iBusRsp_stages_0_output_valid $end $var wire 1 %U IBusCachedPlugin_iBusRsp_stages_1_halt $end $var wire 1 -+ IBusCachedPlugin_iBusRsp_stages_1_inputSample $end $var wire 32 ,P IBusCachedPlugin_iBusRsp_stages_1_input_payload [31:0] $end $var wire 1 %Q IBusCachedPlugin_iBusRsp_stages_1_input_ready $end $var wire 1 )9 IBusCachedPlugin_iBusRsp_stages_1_input_valid $end $var wire 32 ,P IBusCachedPlugin_iBusRsp_stages_1_output_payload [31:0] $end $var wire 1 %T IBusCachedPlugin_iBusRsp_stages_1_output_ready $end $var wire 1 %S IBusCachedPlugin_iBusRsp_stages_1_output_valid $end $var wire 1 %% IBusCachedPlugin_incomingInstruction $end $var wire 1 )> IBusCachedPlugin_injector_decodeRemoved $end $var wire 1 ), IBusCachedPlugin_injector_nextPcCalc_valids_0 $end $var wire 1 )- IBusCachedPlugin_injector_nextPcCalc_valids_1 $end $var wire 1 ). IBusCachedPlugin_injector_nextPcCalc_valids_2 $end $var wire 1 )/ IBusCachedPlugin_injector_nextPcCalc_valids_3 $end $var wire 32 %J IBusCachedPlugin_jump_pcLoad_payload [31:0] $end $var wire 1 %I IBusCachedPlugin_jump_pcLoad_valid $end $var wire 1 (0 IBusCachedPlugin_mmuBus_busy $end $var wire 1 -" IBusCachedPlugin_mmuBus_cmd_bypassTranslation $end $var wire 1 #w IBusCachedPlugin_mmuBus_cmd_isValid $end $var wire 32 ,P IBusCachedPlugin_mmuBus_cmd_virtualAddress [31:0] $end $var wire 1 #x IBusCachedPlugin_mmuBus_end $end $var wire 1 %/ IBusCachedPlugin_mmuBus_rsp_allowExecute $end $var wire 1 %- IBusCachedPlugin_mmuBus_rsp_allowRead $end $var wire 1 %. IBusCachedPlugin_mmuBus_rsp_allowWrite $end $var wire 1 %0 IBusCachedPlugin_mmuBus_rsp_exception $end $var wire 1 %, IBusCachedPlugin_mmuBus_rsp_isIoAccess $end $var wire 32 #v IBusCachedPlugin_mmuBus_rsp_physicalAddress [31:0] $end $var wire 1 %1 IBusCachedPlugin_mmuBus_rsp_refilling $end $var wire 1 ), IBusCachedPlugin_pcValids_0 $end $var wire 1 )- IBusCachedPlugin_pcValids_1 $end $var wire 1 ). IBusCachedPlugin_pcValids_2 $end $var wire 1 )/ IBusCachedPlugin_pcValids_3 $end $var wire 32 %' IBusCachedPlugin_predictionJumpInterface_payload [31:0] $end $var wire 1 %& IBusCachedPlugin_predictionJumpInterface_valid $end $var wire 32 ,R IBusCachedPlugin_redoBranch_payload [31:0] $end $var wire 1 %) IBusCachedPlugin_redoBranch_valid $end $var wire 32 )A IBusCachedPlugin_rspCounter [31:0] $end $var wire 1 -" IBusCachedPlugin_rsp_iBusRspOutputHalt $end $var wire 1 $^ IBusCachedPlugin_rsp_issueDetected $end $var wire 1 %) IBusCachedPlugin_rsp_redoFetch $end $var wire 1 -" IBusCachedPlugin_s0_tightlyCoupledHit $end $var wire 1 )B IBusCachedPlugin_s1_tightlyCoupledHit $end $var wire 1 )C IBusCachedPlugin_s2_tightlyCoupledHit $end $var wire 32 %? MmuPlugin_dBusAccess_cmd_payload_address [31:0] $end $var wire 32 -# MmuPlugin_dBusAccess_cmd_payload_data [31:0] $end $var wire 2 -( MmuPlugin_dBusAccess_cmd_payload_size [1:0] $end $var wire 1 -" MmuPlugin_dBusAccess_cmd_payload_write $end $var wire 4 -) MmuPlugin_dBusAccess_cmd_payload_writeMask [3:0] $end $var wire 1 %> MmuPlugin_dBusAccess_cmd_ready $end $var wire 1 %= MmuPlugin_dBusAccess_cmd_valid $end $var wire 32 #} MmuPlugin_dBusAccess_rsp_payload_data [31:0] $end $var wire 1 %A MmuPlugin_dBusAccess_rsp_payload_error $end $var wire 1 $$ MmuPlugin_dBusAccess_rsp_payload_redo $end $var wire 1 %@ MmuPlugin_dBusAccess_rsp_valid $end $var wire 1 %n MmuPlugin_ports_0_cacheHit $end $var wire 1 )~ MmuPlugin_ports_0_cacheHits_0 $end $var wire 1 %k MmuPlugin_ports_0_cacheHits_1 $end $var wire 1 %l MmuPlugin_ports_0_cacheHits_2 $end $var wire 1 %m MmuPlugin_ports_0_cacheHits_3 $end $var wire 1 %x MmuPlugin_ports_0_cacheLine_allowExecute $end $var wire 1 %v MmuPlugin_ports_0_cacheLine_allowRead $end $var wire 1 %y MmuPlugin_ports_0_cacheLine_allowUser $end $var wire 1 %w MmuPlugin_ports_0_cacheLine_allowWrite $end $var wire 1 %p MmuPlugin_ports_0_cacheLine_exception $end $var wire 10 %t MmuPlugin_ports_0_cacheLine_physicalAddress_0 [9:0] $end $var wire 10 %u MmuPlugin_ports_0_cacheLine_physicalAddress_1 [9:0] $end $var wire 1 %q MmuPlugin_ports_0_cacheLine_superPage $end $var wire 1 %o MmuPlugin_ports_0_cacheLine_valid $end $var wire 10 %r MmuPlugin_ports_0_cacheLine_virtualAddress_0 [9:0] $end $var wire 10 %s MmuPlugin_ports_0_cacheLine_virtualAddress_1 [9:0] $end $var wire 1 )[ MmuPlugin_ports_0_cache_0_allowExecute $end $var wire 1 )Y MmuPlugin_ports_0_cache_0_allowRead $end $var wire 1 )\ MmuPlugin_ports_0_cache_0_allowUser $end $var wire 1 )Z MmuPlugin_ports_0_cache_0_allowWrite $end $var wire 1 )S MmuPlugin_ports_0_cache_0_exception $end $var wire 10 )W MmuPlugin_ports_0_cache_0_physicalAddress_0 [9:0] $end $var wire 10 )X MmuPlugin_ports_0_cache_0_physicalAddress_1 [9:0] $end $var wire 1 )T MmuPlugin_ports_0_cache_0_superPage $end $var wire 1 )R MmuPlugin_ports_0_cache_0_valid $end $var wire 10 )U MmuPlugin_ports_0_cache_0_virtualAddress_0 [9:0] $end $var wire 10 )V MmuPlugin_ports_0_cache_0_virtualAddress_1 [9:0] $end $var wire 1 )f MmuPlugin_ports_0_cache_1_allowExecute $end $var wire 1 )d MmuPlugin_ports_0_cache_1_allowRead $end $var wire 1 )g MmuPlugin_ports_0_cache_1_allowUser $end $var wire 1 )e MmuPlugin_ports_0_cache_1_allowWrite $end $var wire 1 )^ MmuPlugin_ports_0_cache_1_exception $end $var wire 10 )b MmuPlugin_ports_0_cache_1_physicalAddress_0 [9:0] $end $var wire 10 )c MmuPlugin_ports_0_cache_1_physicalAddress_1 [9:0] $end $var wire 1 )_ MmuPlugin_ports_0_cache_1_superPage $end $var wire 1 )] MmuPlugin_ports_0_cache_1_valid $end $var wire 10 )` MmuPlugin_ports_0_cache_1_virtualAddress_0 [9:0] $end $var wire 10 )a MmuPlugin_ports_0_cache_1_virtualAddress_1 [9:0] $end $var wire 1 )q MmuPlugin_ports_0_cache_2_allowExecute $end $var wire 1 )o MmuPlugin_ports_0_cache_2_allowRead $end $var wire 1 )r MmuPlugin_ports_0_cache_2_allowUser $end $var wire 1 )p MmuPlugin_ports_0_cache_2_allowWrite $end $var wire 1 )i MmuPlugin_ports_0_cache_2_exception $end $var wire 10 )m MmuPlugin_ports_0_cache_2_physicalAddress_0 [9:0] $end $var wire 10 )n MmuPlugin_ports_0_cache_2_physicalAddress_1 [9:0] $end $var wire 1 )j MmuPlugin_ports_0_cache_2_superPage $end $var wire 1 )h MmuPlugin_ports_0_cache_2_valid $end $var wire 10 )k MmuPlugin_ports_0_cache_2_virtualAddress_0 [9:0] $end $var wire 10 )l MmuPlugin_ports_0_cache_2_virtualAddress_1 [9:0] $end $var wire 1 )| MmuPlugin_ports_0_cache_3_allowExecute $end $var wire 1 )z MmuPlugin_ports_0_cache_3_allowRead $end $var wire 1 )} MmuPlugin_ports_0_cache_3_allowUser $end $var wire 1 ){ MmuPlugin_ports_0_cache_3_allowWrite $end $var wire 1 )t MmuPlugin_ports_0_cache_3_exception $end $var wire 10 )x MmuPlugin_ports_0_cache_3_physicalAddre