// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Design implementation internals // See Vdut.h for the primary calling header #include "Vdut_VexRiscv.h" // For This #include "Vdut__Syms.h" #include "verilated_dpi.h" //-------------------- // STATIC VARIABLES VL_ST_SIGW(Vdut_VexRiscv::__Vtable1___PVT__decode_SRC1_CTRL_string[4],95,0,3); VL_ST_SIGW(Vdut_VexRiscv::__Vtable7___PVT__decode_SHIFT_CTRL_string[4],71,0,3); VL_ST_SIGW(Vdut_VexRiscv::__Vtable11___PVT__memory_SHIFT_CTRL_string[4],71,0,3); VL_ST_SIGW(Vdut_VexRiscv::__Vtable13___PVT__execute_SHIFT_CTRL_string[4],71,0,3); VL_ST_SIGW(Vdut_VexRiscv::__Vtable15___PVT__execute_SRC1_CTRL_string[4],95,0,3); VL_ST_SIG64(Vdut_VexRiscv::__Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[8],47,0); VL_ST_SIGW(Vdut_VexRiscv::__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string[4],71,0,3); VL_ST_SIGW(Vdut_VexRiscv::__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string[4],71,0,3); VL_ST_SIGW(Vdut_VexRiscv::__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string[4],95,0,3); VL_ST_SIG8(Vdut_VexRiscv::__Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[8],0,0); //-------------------- VL_CTOR_IMP(Vdut_VexRiscv) { // Reset internal values // Reset structure values _ctor_var_reset(); } void Vdut_VexRiscv::__Vconfigure(Vdut__Syms* vlSymsp, bool first) { if (0 && first) {} // Prevent unused this->__VlSymsp = vlSymsp; } Vdut_VexRiscv::~Vdut_VexRiscv() { } //-------------------- // Internal Methods void Vdut_VexRiscv::_initial__TOP__dut__VexRiscv__1(Vdut__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ Vdut_VexRiscv::_initial__TOP__dut__VexRiscv__1\n"); ); Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body // INITIAL at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2514 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcycle = VL_ULL(0); // INITIAL at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2515 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_minstret = VL_ULL(0); } void Vdut_VexRiscv::_settle__TOP__dut__VexRiscv__2(Vdut__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ Vdut_VexRiscv::_settle__TOP__dut__VexRiscv__2\n"); ); Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables VL_SIGW(__Vtemp8,95,0,3); VL_SIGW(__Vtemp9,95,0,3); VL_SIGW(__Vtemp10,95,0,3); VL_SIGW(__Vtemp11,95,0,3); // Body vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_12_ = (1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_36_ = (3U & VL_NEGATE_I((IData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3824 vlSymsp->TOP__dut__VexRiscv.__Vtableidx11 = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable11___PVT__memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx11][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable11___PVT__memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx11][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable11___PVT__memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx11][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3878 vlSymsp->TOP__dut__VexRiscv.__Vtableidx15 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable15___PVT__execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx15][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable15___PVT__execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx15][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable15___PVT__execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx15][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4087 vlSymsp->TOP__dut__VexRiscv.__Vtableidx23 = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx23][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx23][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx23][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4096 vlSymsp->TOP__dut__VexRiscv.__Vtableidx24 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx24][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx24][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx24][2U]; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_235_ = ( ((QData)((IData)( vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[0U])) << 1U) | (QData)((IData)( (1U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1 >> 0x1fU)))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5890 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x1fU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffff7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x200000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x400000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x800000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x1000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x4000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x8000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x10000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x20000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x40000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:924 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_error))); vlSymsp->TOP__dut__VexRiscv.lastStagePc = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:226 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wayToAllocate_willIncrement = 0U; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wayToAllocate_willIncrement = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_238_ = ( (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 >> 0x1fU) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS2_SIGNED)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6697 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_ = ( (VL_ULL(0xffffffff) & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_) | ((QData)((IData)( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS1_SIGNED) & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 >> 0x1fU)))) << 0x20U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_ = ( (VL_ULL(0x100000000) & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_) | (IData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap) << 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_239_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_DIV) & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 >> 0x1fU)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS1_SIGNED)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_ = ((vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data + ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu)) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0)) + ((0xfffffffcU & (VL_NEGATE_I((IData)((1U & (((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu)) ? 1U : 0U) >> 1U)))) << 2U)) | ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu)) ? 1U : 0U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3842 vlSymsp->TOP__dut__VexRiscv.__Vtableidx13 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable13___PVT__execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx13][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable13___PVT__execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx13][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable13___PVT__execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx13][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4078 vlSymsp->TOP__dut__VexRiscv.__Vtableidx22 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx22][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx22][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx22][2U]; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_18_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_20_ = (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_colisions) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_320_ = (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0x1cU)); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_IS_DBUS_SHARING = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING; vlSymsp->TOP__dut__VexRiscv.lastStageInstruction = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION; vlSymsp->TOP__dut__VexRiscv.lastStageIsValid = vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid; vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_address = (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6115 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_privilege = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_; vlSymsp->TOP__dut__VexRiscv.__PVT__iBus_rsp_valid = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_248_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_; vlSymsp->TOP__dut__VexRiscv.__PVT__dBus_rsp_valid = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:186 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_1_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_1_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_352_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) | (1U > (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_356_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE) | (3U > (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_229_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MTIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MTIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_230_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MSIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MSIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_231_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MEIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MEIE)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6262 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause = vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4644 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_incomingInstruction = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_incomingInstruction = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) & (3U != (3U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferData))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_incomingInstruction = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:201 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_) { if ((7U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s1_tightlyCoupledHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5553 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode; if (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv)) & (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup = 0U; } if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_306_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_308_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_309_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_REGFILE_WRITE_VALID)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5242 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6131 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 3U; if ((8U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SPF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LPF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IPF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } else { if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code) >> 1U)))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_ES) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_EU) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } } else { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAM) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAM) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_II) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAM) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_242_ = (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_241_ & vlSymsp->TOP__dut__VexRiscv.__PVT__externalInterruptArray_regNext); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_244_ = (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_243_ & vlSymsp->TOP__dut__VexRiscv.__PVT__externalInterruptArray_regNext); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_INPUT)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_)); vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_DO)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_305_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_332_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_334_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_REGFILE_WRITE_VALID)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5232 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_ENABLE)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6244 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done = ((0U == (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid)))) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_3)); if ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_MANAGMENT)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DIV)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_ = (0U == ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack)) << 2U) | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory)) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5257 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) ? ((0xffff0000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen << 0x10U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferData)) : ((0xffff0000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen) | (0xffffU & ((2U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U) : vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s2_tightlyCoupledHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1030 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) ? vlSymsp->TOP__dut__VexRiscv.__PVT__dBusWishbone_DAT_MISO_regNext : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0); if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved))); } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_344_ = (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_345_ = (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_346_ = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_347_ = (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_348_ = (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_349_ = (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_350_ = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_351_ = (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_237_ = ( (0x2000U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION) ? vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[0U] : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_247_) == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_166_)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:873 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultReg; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4007 vlSymsp->TOP__dut__VexRiscv.__Vtableidx19 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1___05Fstring = vlSymsp->TOP__dut__VexRiscv.__Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring [vlSymsp->TOP__dut__VexRiscv.__Vtableidx19]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6035 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0x7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xf7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6073 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x3ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x5ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x6ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x77fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6088 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x3ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x5ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x6ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x77fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7bfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7dfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7efffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7f7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7feffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4738 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt = 0U; if (((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5645 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address = 0U; if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_) >> 2U)))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address = ((0xffc00000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_PPN1) << 0x16U)) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_PPN0) << 0xcU) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0) << 2U))); } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address = ((vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_ppn << 0xcU) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1) << 2U)); } } } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5757 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ = ( (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 : ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL)) ? ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RVC) ? 2U : 4U) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL)) ? (0xfffff000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) : (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5776 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0x7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xf7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5800 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0x7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xf7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6308 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 1U; if ((0x80000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x40000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((0x1000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } else { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } } else { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } else { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 1U; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid)) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5625 vlSymsp->TOP__dut__VexRiscv.__Vtableidx25 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid = vlSymsp->TOP__dut__VexRiscv.__Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid [vlSymsp->TOP__dut__VexRiscv.__Vtableidx25]; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_337_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_316_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6430 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL)))) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_249_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface1_soc_bus_ack)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_236_ = (VL_ULL(0x1ffffffff) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_235_ - (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs2)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid) | (0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:193 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_2_ = 0U; if ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire) | (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_2_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_353_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_ST)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_357_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_ST))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_354_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SS)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_358_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SS))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_13_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending) & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5454 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode)); if (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv)) & (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup = 0U; } if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) { if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv)) | (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6255 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped)) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)); } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6470 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = 0U; if ((0x80000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x40000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_242_; } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((0x1000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? 3U : 2U)); } else { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = (1U | vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData); } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_244_; } } } } } } } } } else { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = (0x1000U | (0xffffe000U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = (0x2000000U | (0xfc0fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData)); } } } } } } } } } } } else { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_241_; } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_243_; } } } } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MEIP) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MTIP) << 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MSIP) << 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP) << 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR) << 9U)); } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtval; } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcause_interrupt) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff0U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcause_exceptionCode)); } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mepc : vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mscratch); } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MEIE) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MTIE) << 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MSIE) << 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE) << 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE) << 1U)); } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffe7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPIE) << 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE) << 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP) << 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE) << 1U)); } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfff00000U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_ppn); } } } } } } } } else { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP) << 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR) << 9U)); } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stval; } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_interrupt) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff0U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_exceptionCode)); } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sepc : vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sscratch); } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((3U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_base << 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_mode)); } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE) << 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE) << 1U)); } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP) << 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE) << 1U)); } } } } } } } } } } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1042 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4447 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_99_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_FORMAL_PC_NEXT; if (vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_99_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_CALC; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4569 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext = 1U; } vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interruptJump = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6662 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4551 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_haltItself = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_haltItself = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4327 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA; if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_; } else { if (((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL)) | (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_result; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:740 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 2U)); } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address = ((0x3f8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 2U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:726 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:905 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_20_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 1U; } } } } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_refilling))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_exception) | ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowWrite)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr))) | ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowRead)) & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo))))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_size)) & (0U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress))) | ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_size)) & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1002 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:987 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) ? 0U : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) ? 0U : 7U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:972 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) ? (0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) ? (0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress) : (0xffffffe0U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1017 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr = 0U; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:768 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mask; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = 0xfU; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePc_pcPlus = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? 2U : 4U)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4769 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError = 1U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) & (3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_ = ( (0x18U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_ = ( (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x38U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4836 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0x7ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xbffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xdffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xeffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xf7fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xfbfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xfdfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xfe0U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4863 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x3fffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 2U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x5fffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x6fffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x77ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7bffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7dffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7effU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7f7fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7fbfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7fdfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7fefU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ff7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ffbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ffdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ffeU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4882 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_ = ( (3U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_ = ( (5U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_ = ( (6U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4952 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x3fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x5fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x6fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x77U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x7bU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x7dU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x7eU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4848 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x1ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x2ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x37fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4889 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x1ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x2ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x37fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4904 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0xfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x17U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x1bU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x1dU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x1eU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_314_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_leaf = (1U & ((vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U) | (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5310 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW))) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = ((0xffffff00U & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted) | (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 8U))); } else { if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW))) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = ((0xffff0000U & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted) | (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x10U))); } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW))) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = ((0xffffff00U & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted) | (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x18U))); } } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_459_ = (VL_ULL(0x1ffffffff) & ((QData)((IData)( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_needRevert) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_237_) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_237_))) + (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_needRevert)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:754 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data = vlSymsp->TOP__dut__VexRiscv.__PVT__dBusWishbone_DAT_MISO_regNext; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6058 if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2 = ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ << 0xcU) | (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2 = ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_) << 0x15U) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xbU)) | ((0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 9U)) | (0x7feU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))))) : ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ << 0xdU) | ((0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U)) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION << 4U)) | ((0x7e0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)) | (0x1eU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U))))))); if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PREDICTION_HAD_BRANCHED2) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2 = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RVC) ? 2U : 4U); } } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_output_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHit = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1) << 1U) | ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_ = ( (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3)) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3))); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh = ((0x10000U & ((((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) | (2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU)))) << 0x10U) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xfU))) | (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x10U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5853 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1fU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffff7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x200000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x400000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x800000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x1000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x4000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x8000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x10000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x20000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x40000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5823 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ = ( (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ << 0xcU) | (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))) : ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ << 0xcU) | ((0xfe0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)) | (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U)))) : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5166 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_265_ = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_WR; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_265_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5208 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_LRSC) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_ = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5220 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_269_ = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_AMO; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_269_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5189 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_266_ = ( (0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? ((0xff000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 0x18U)) | ((0xff0000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 0x10U)) | ((0xff00U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 8U)) | (0xffU & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2)))) : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? ((0xffff0000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 0x10U)) | (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2)) : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_266_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5198 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_ = (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_ = 2U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5402 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHit = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1) << 1U) | ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_ = ( (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3)) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6300 vlSymsp->TOP__dut__VexRiscv.execute_CsrPlugin_inWfi = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_316_) { vlSymsp->TOP__dut__VexRiscv.execute_CsrPlugin_inWfi = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_336_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_)) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_249_) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_454_ = ( ((QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1)) << 1U) | (QData)((IData)( (1U & (~ (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_236_ >> 0x20U))))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6766 vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_STB = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_) { vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_STB = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6759 vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_CYC = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_) { vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_CYC = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6269 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode = 0U; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_mode; } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtvec_mode; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6283 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base = 0U; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_base; } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtvec_base; } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_355_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_359_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SE))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6594 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData; if ((0x344U == (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT) << 9U)); } else { if ((0x144U == (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT) << 9U)); } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1052 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_valueNext = (7U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow = ((7U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) | (IData)(vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interruptJump)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5266 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5146 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_ENABLE)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_ = 1U; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5295 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR) ? 7U : 5U); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR) ? 6U : 4U); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR) ? 0xfU : 0xdU); } } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception = (1U & (((~ vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data) | ((~ (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)) & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U))) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5276 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 0U; } } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_ = ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_refilling) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_) << 0xbU) | ((0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 2U)) | ((0x300U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | ((0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (0xeU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_) << 0xbU) | ((0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 2U)) | ((0x300U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | ((0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (0xeU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_) << 8U) | ((0xc0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | ((0x18U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (6U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U)))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4438 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_314_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_ = (1U & ((vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted >> 7U) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xeU)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_ = (1U & ((vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted >> 0xfU) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xeU)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5603 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_refilling = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3414 if ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowUser; } else { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowUser; } else { if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowUser; } else { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowUser; } } } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed = ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq = (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ == vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh = ((0x10000U & (((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) << 0x10U) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0xfU))) | (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0x10U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5841 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub = ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ + ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_USE_SUB_LESS) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)) + ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_USE_SUB_LESS) ? 1U : 0U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_FORCE_ZERO) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5506 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_refilling = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3357 if ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowUser; } else { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowUser; } else { if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowUser; } else { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowUser; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6449 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_336_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code = 2U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_337_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code = ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)) ? 8U : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)) ? 9U : 0xbU)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6439 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_336_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_337_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_341_ = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6608 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData = ((0x2000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? ((0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData & (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_)) : (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_)) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:675 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:685 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_error; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:692 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address = (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 0xcU)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:665 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 5U)); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 5U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:655 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4664 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base << 2U); } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { if ((3U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mepc; } else { if ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sepc; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4654 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4594 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_19_ = (((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4601 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:642 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:699 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:936 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent))); if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_18_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_20_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 1U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:816 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid = 1U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:832 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) { if ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) ? (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_18_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 1U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4779 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = 0U; if ((0x10U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_) >> 3U)))) { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x12023U | (((0xc000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x13U)) | (0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xdU))) | ((0x1f00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | (0xe00U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))); } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = ((0x400U == (0x7ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))) ? 0x100073U : ((0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))) ? (0x67U | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (((0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode) ? 1U : 0U) << 7U))) : (0x33U | ((0x1f00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0xf8000U & (((0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U) : 0U) << 0xfU)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))))); } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x12003U | ((0xc000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x18U)) | ((0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xdU)) | ((0x1c00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode))))); } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x1013U | ((0x1f00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))); } } } } } else { if ((8U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? (0x41063U | ((0x80000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x13U)) | ((0x7e000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x14U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | ((0xf00U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 7U)) | (0x80U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) >> 4U))))))) : (0x40063U | ((0x80000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x13U)) | ((0x7e000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x14U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | ((0xf00U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 7U)) | (0x80U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) >> 4U)))))))) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? (0x6fU | ((0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ << 0xbU)) | ((0x7fe00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ << 0x14U)) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ << 9U)) | (0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_))))) : (0x40400U | ((((2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_) : (((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) | ((3U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) & (0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))))) << 5U)) << 0x19U) | ((0x1f00000U & (((1U & ((~ (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU)) | (3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U) : (8U | (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U)))) << 0x14U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | ((((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 5U : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 5U : ((2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 7U : ((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))) ? 0U : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))) ? 4U : ((2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))) ? 6U : 7U)))))) << 0xcU) | ((0x380U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode) | ((3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 0x13U : 0x33U))))))))) : ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((2U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))) ? (0x13U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_) << 0x1dU) | ((0x18000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x18U)) | ((0x4000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x15U)) | ((0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x17U)) | ((0x1000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))))))) : (0x37U | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_) << 0x11U) | (0x1f000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xaU))) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))) : (0x13U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_) << 0x14U) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? (0xefU | ((0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ << 0xbU)) | ((0x7fe00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ << 0x14U)) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ << 9U)) | (0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_))))) : (0x13U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_) << 0x14U) | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode))))))); } else { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x842023U | ((0xfe000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_) << 0x14U)) | ((0x700000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_) << 7U)))))); } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x42403U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_) << 0x14U) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0x380U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 5U))))); } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x10413U | ((0x3c000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x13U)) | ((0x3000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xdU)) | ((0x800000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0x400000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x10U)) | (0x380U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 5U))))))); } } } } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_exception) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowExecute))))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5328 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1eU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1dU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1cU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1bU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1aU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x19U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x18U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x17U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x16U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x15U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x10U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffff7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xfU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xeU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xdU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xcU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffff00U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | (0xffU & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5357 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1eU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1dU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1cU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1bU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1aU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x19U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x18U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x17U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x16U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x15U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x10U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffff0000U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_342_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_refilling)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5563 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup) ? (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_) << 0x16U) | ((0x3ff000U & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_) ? (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_)) << 0xcU)) | (0xfffU & vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg))) : vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5157 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address; } } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less = (1U & (((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1fU)) == (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0x1fU))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub >> 0x1fU) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_LESS_UNSIGNED) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0x1fU) : (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1fU)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_343_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_refilling)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5466 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup) ? (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_) << 0x16U) | ((0x3ff000U & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_)) << 0xcU)) | (0xfffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA))) : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4544 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6229 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4584 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:866 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_19_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isFlushed = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) | (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isFlushed = ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext))) | (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) << 2U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:599 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_2_ = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_2_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:592 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_ = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:806 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4576 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst = ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed : vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4431 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4384 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_ = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_DATA; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_ = ((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ : vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted)); } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_MUL))) { __Vtemp8[0U] = (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW); __Vtemp8[1U] = ((0xfff00000U & (VL_NEGATE_I((IData)( (1U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW >> 0x33U))))) << 0x14U)) | (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW >> 0x20U))); __Vtemp8[2U] = (3U & (VL_NEGATE_I((IData)((1U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW >> 0x33U))))) >> 0xcU)); VL_EXTEND_WQ(66,34, __Vtemp9, vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_HH); VL_SHIFTL_WWI(66,66,32, __Vtemp10, __Vtemp9, 0x20U); VL_ADD_W(3, __Vtemp11, __Vtemp8, __Vtemp10); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_ = ((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW) : __Vtemp11[1U]); } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_mask = (0xfU & (((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_)) ? 1U : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_)) ? 3U : 0xfU)) << (3U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4250 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_ = ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ ^ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_))) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less) : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub)); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_305_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address; } vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFlushed = ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext)))) | (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) << 3U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4512 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } if ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_ENABLE))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_316_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_wfiWake)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_305_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4561 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6222 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4533 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6212 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_leaf) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_21_ = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze)))); vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt))); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_haltItself) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5012 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x3ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x5ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x6ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x77fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5027 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x3ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x5ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x6ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x77fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7bfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7dfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7efffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7f7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7feffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4987 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x3ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x5ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x6ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x77fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7bfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7dfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7efffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7f7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7feffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1fU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_212_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_213_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_214_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_215_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ = ( ((QData)((IData)( (0U != (((0x48U == (0x48U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 6U) | (((0x1010U == (0x1010U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x2010U == (0x2010U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x2008U == (0x2008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10U == (0x50U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((4U == (0xcU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0U == (0x28U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))))))) << 0x22U) | (((QData)((IData)( (0U != (((0x2000U == (0x2010U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x1000U == (0x5000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))))) << 0x21U) | (((QData)((IData)( (0U != (((0x40U == (0x44U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x2010U == (0x2014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x40000030U == (0x40000034U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 0x20U) | (QData)((IData)( (((0x10000008U == (0x10000008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1fU) | (((0U != (((0x20U == (0x34U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x20U == (0x64U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x8000020U == (0x8000070U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x10000070U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))))) << 0x1eU) | (((0x1000U == (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1dU) | (((0x2000U == (0x3000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1cU) | (((0x4008U == (0x4048U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1bU) | (((0U != (((0x8000020U == (0x8000020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x20U == (0x10000020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x28U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))) << 0x1aU) | (((0x2000030U == (0x2004074U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x19U) | (((0x2000050U == (0x2003050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x18U) | (((0U != (((0x48U == (0x48U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x4050U == (0x4050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (4U == (0x2014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))) << 0x17U) | (((0U != (((0x4050U == (0x4050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (4U == (0x4cU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0x16U) | (((0U == (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x15U) | (((0x2004020U == (0x2004064U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x14U) | (((0x50U == (0x2203050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x13U) | (((0x50U == (0x2403050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x12U) | (((0U != (((0x5010U == (0x7034U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x5020U == (0x2007064U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0x11U) | (((0U != (((0x40001010U == (0x40003054U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x1010U == (0x7034U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x1010U == (0x2007054U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))) << 0x10U) | (((8U == (0x10000008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xfU) | (((0U != (((0x48U == (0x48U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (4U == (0x1cU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0xeU) | (((0x40U == (0x58U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xdU) | (((0x24U == (0x64U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xcU) | (((0U != (((0x1050U == (0x1050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x2050U == (0x2050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0xbU) | (((0U != (((4U == (4U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x70U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0xaU) | (((0U != (((4U == (4U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0U == (0x20U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 9U) | (((0U != (((0x2000U == (0x2050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0U == (0x58U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 8U) | (((0x1008U == (0x5048U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 7U) | (((0U == (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 6U) | (((0x4010U == (0x4014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x2010U == (0x6014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0U != (((0x40U == (0x40U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x4020U == (0x4020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10U == (0x30U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((4U == (0xcU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x2000028U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 3U) | (((0U != (((4U == (0xcU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x2010U == (0x2030U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10U == (0x1030U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x20U == (0x2003020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x2020U == (0x2002068U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 2U) | (((0U != (((0U == (0x44U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0U == (0x18U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x2000U == (0x6004U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x1000U == (0x5004U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x2000U == (0x2050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 1U) | (0U != (((0x2040U == (0x2040U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x1040U == (0x1040U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x40U == (0x50U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x40U == (0x2400040U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0U == (0x38U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x10002008U == (0x18002008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))))))))))))))))))))))))))))))))))))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_valid))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_))); vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_data = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5435 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5534 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement = 1U; } } vlSymsp->TOP__dut__VexRiscv.lastStageIsFiring = vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_206_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5718 vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring)); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_194_) { vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6671 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear = 0U; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck))); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4296 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile [(0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))]; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_207_) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_208_) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_209_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_306_) { if (((0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_308_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_212_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_309_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_214_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4266 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile [(0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))]; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_207_) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_208_) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_209_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_306_) { if (((0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_308_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_213_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_309_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_215_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4372 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_REGFILE_WRITE_VALID = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x22U))); if ((0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 7U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_REGFILE_WRITE_VALID = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3662 vlSymsp->TOP__dut__VexRiscv.__Vtableidx1 = (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable1___PVT__decode_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx1][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable1___PVT__decode_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx1][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable1___PVT__decode_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx1][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3716 vlSymsp->TOP__dut__VexRiscv.__Vtableidx7 = (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable7___PVT__decode_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx7][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable7___PVT__decode_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx7][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable7___PVT__decode_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx7][2U]; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_payload = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((2U == (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))) ? ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_) << 0x15U) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xbU)) | ((0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 9U)) | (0x7feU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)))))) : ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ << 0xdU) | ((0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x13U)) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst << 4U)) | ((0x7e0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)) | (0x1eU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 7U)))))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((2U == (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))) | ((1U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ >> 0x12U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5925 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_332_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_212_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 1U; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_334_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_214_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 1U; } } } if ((1U & (~ (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 1U))))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5953 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_332_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_213_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 1U; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_334_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_215_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 1U; } } } if ((1U & (~ (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1eU))))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5066 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_314_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4424 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5447 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_valueNext = (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5546 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_valueNext = (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4365 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_61_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_61_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6680 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_valueNext = (0x3fU & (((0x21U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement)) ? 0U : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement)))); if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_valueNext = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:614 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:628 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:621 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_payload = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_payload = (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ >> 5U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:635 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ >> 2U)); } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable = (((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers))); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5079 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling))); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_ = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_ = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_error)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5391 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck))); } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5099 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = 0xcU; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5089 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4417 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4749 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid = ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid)) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) | (~ (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U))))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_decodeRemoved))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_254_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT__decodeExceptionPort_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (0U == (((0x17U == (0x5fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x18U) | (((0x6fU == (0x7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x17U) | (((3U == (0x106fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x16U) | (((0x1073U == (0x107fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x15U) | (((0x2073U == (0x207fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x14U) | (((0x4063U == (0x407fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x13U) | (((0x2013U == (0x207fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x12U) | (((0x23U == (0x603fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x11U) | (((3U == (0x207fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x10U) | (((3U == (0x505fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xfU) | (((0x63U == (0x707bU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xeU) | (((0xfU == (0x607fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xdU) | (((0x202fU == (0x1800707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xcU) | (((0x33U == (0xfc00007fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xbU) | (((0x800202fU == (0xe800707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xaU) | (((0x500fU == (0x1f0707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 9U) | (((0x5013U == (0xbc00707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 8U) | (((0x1013U == (0xfc00307fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 7U) | (((0x5033U == (0xbe00707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 6U) | (((0x33U == (0xbe00707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x1000202fU == (0xf9f0707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x12000073U == (0xfe007fffU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10200073U == (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x10500073U == vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst) << 1U) | (0x73U == vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))))))))))))))))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4468 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself = 0U; if (((((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid)) & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 8U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4475 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid; } if ((0U != ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL))) << 2U) | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL))) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL))))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:210 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending)); if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_3_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_254_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_232_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decodeExceptionPort_valid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_ = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decodeExceptionPort_valid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4454 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_ = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? 2U : 4U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_ = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_payload; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_ = vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) << 4U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid) << 2U) | ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid)))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_105_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid) << 4U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid))))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4727 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4502 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6202 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4491 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4694 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_corrected = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_corrected = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_105_) & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_105_) - (IData)(1U)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_322_ = (1U & ((~ (((3U == (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid)))) & (~ (((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid)) | (~ (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck) | (((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U))) & (3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U))))) | (((3U == (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid)) & (3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U)))))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4621 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 0U; if ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode)))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFiring = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_ = ( (4U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 2U)) | ((2U & ((0x7ffffffeU & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 1U)) | (0x3ffffffeU & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 2U)))) | (1U & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 3U))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_321_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready)); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_output_valid = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_booted)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4634 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt = 0U; if ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext)))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFiring))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3337 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_282_ = ( (4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_payload : ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_CALC) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload : vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4967 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferFill = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_321_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_322_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferFill = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4708 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg + ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc) << 2U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = (0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_282_; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = (0xfffffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4701 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pcRegPropagate = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pcRegPropagate = 1U; } } VL_INLINE_OPT void Vdut_VexRiscv::_sequent__TOP__dut__VexRiscv__3(Vdut__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ Vdut_VexRiscv::_sequent__TOP__dut__VexRiscv__3\n"); ); Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables VL_SIG8(__Vdlyvdim0__RegFilePlugin_regFile__v0,4,0); VL_SIG8(__Vdlyvset__RegFilePlugin_regFile__v0,0,0); VL_SIG8(__Vdly__IBusCachedPlugin_fetchPc_booted,0,0); VL_SIG8(__Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_0,0,0); VL_SIG8(__Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_1,0,0); VL_SIG8(__Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_2,0,0); VL_SIG8(__Vdly___zz_154_,0,0); VL_SIG8(__Vdly__MmuPlugin_ports_0_entryToReplace_value,1,0); VL_SIG8(__Vdly__MmuPlugin_ports_1_entryToReplace_value,1,0); VL_SIG8(__Vdly__MmuPlugin_shared_state_1_,2,0); VL_SIG8(__Vdly__CsrPlugin_mstatus_MIE,0,0); VL_SIG8(__Vdly__CsrPlugin_mstatus_MPIE,0,0); VL_SIG8(__Vdly__CsrPlugin_mstatus_MPP,1,0); VL_SIG8(__Vdly__CsrPlugin_sstatus_SIE,0,0); VL_SIG8(__Vdly__CsrPlugin_sstatus_SPIE,0,0); VL_SIG8(__Vdly__CsrPlugin_sstatus_SPP,0,0); VL_SIG8(__Vdly__execute_arbitration_isValid,0,0); VL_SIG8(__Vdly__memory_arbitration_isValid,0,0); VL_SIG8(__Vdly__writeBack_arbitration_isValid,0,0); VL_SIG8(__Vdly___zz_245_,2,0); VL_SIG8(__Vdly___zz_247_,2,0); VL_SIG8(__Vdlyvdim0__IBusCachedPlugin_cache__DOT__ways_0_tags__v0,6,0); VL_SIG8(__Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_tags__v0,0,0); VL_SIG8(__Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_datas__v0,0,0); VL_SIG8(__Vdly__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex,2,0); VL_SIG8(__Vdly__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter,7,0); VL_SIG8(__Vdlyvdim0__dataCache_1___DOT__ways_0_tags__v0,6,0); VL_SIG8(__Vdlyvset__dataCache_1___DOT__ways_0_tags__v0,0,0); VL_SIG8(__Vdlyvval__dataCache_1___DOT__ways_0_data_symbol0__v0,7,0); VL_SIG8(__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol0__v0,0,0); VL_SIG8(__Vdlyvval__dataCache_1___DOT__ways_0_data_symbol1__v0,7,0); VL_SIG8(__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol1__v0,0,0); VL_SIG8(__Vdlyvval__dataCache_1___DOT__ways_0_data_symbol2__v0,7,0); VL_SIG8(__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol2__v0,0,0); VL_SIG8(__Vdlyvval__dataCache_1___DOT__ways_0_data_symbol3__v0,7,0); VL_SIG8(__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol3__v0,0,0); VL_SIG8(__Vdly__dataCache_1___DOT__stageB_flusher_valid,0,0); VL_SIG8(__Vdly__dataCache_1___DOT__loader_valid,0,0); VL_SIG8(__Vdly__dataCache_1___DOT__loader_error,0,0); VL_SIG16(__Vdlyvdim0__IBusCachedPlugin_cache__DOT__ways_0_datas__v0,9,0); VL_SIG16(__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol0__v0,9,0); VL_SIG16(__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol1__v0,9,0); VL_SIG16(__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol2__v0,9,0); VL_SIG16(__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol3__v0,9,0); VL_SIG(__Vdlyvval__RegFilePlugin_regFile__v0,31,0); VL_SIG(__Vdly__IBusCachedPlugin_fetchPc_pcReg,31,0); VL_SIG(__Vdly__IBusCachedPlugin_rspCounter,31,0); VL_SIG(__Vdly__DBusCachedPlugin_rspCounter,31,0); VL_SIG(__Vdlyvval__IBusCachedPlugin_cache__DOT__ways_0_tags__v0,21,0); VL_SIG(__Vdlyvval__IBusCachedPlugin_cache__DOT__ways_0_datas__v0,31,0); VL_SIG(__Vdlyvval__dataCache_1___DOT__ways_0_tags__v0,21,0); VL_SIG(__Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress,31,0); VL_SIGW(__Vtemp22,95,0,3); VL_SIGW(__Vtemp23,95,0,3); VL_SIGW(__Vtemp24,95,0,3); VL_SIGW(__Vtemp25,95,0,3); VL_SIG64(__Vdly__CsrPlugin_mcycle,63,0); VL_SIG64(__Vdly__CsrPlugin_minstret,63,0); // Body __Vdly__CsrPlugin_mcycle = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcycle; __Vdlyvset__dataCache_1___DOT__ways_0_tags__v0 = 0U; __Vdly__CsrPlugin_minstret = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_minstret; __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol0__v0 = 0U; __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol1__v0 = 0U; __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol2__v0 = 0U; __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol3__v0 = 0U; __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter; __Vdlyvset__RegFilePlugin_regFile__v0 = 0U; __Vdly__dataCache_1___DOT__loader_error = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_error; __Vdly__dataCache_1___DOT__stageB_flusher_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid; __Vdly__dataCache_1___DOT__loader_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid; __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress; __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_0; __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_1; __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_2 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_2; __Vdly__IBusCachedPlugin_rspCounter = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rspCounter; __Vdly__DBusCachedPlugin_rspCounter = vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_rspCounter; __Vdly__IBusCachedPlugin_fetchPc_booted = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_booted; __Vdly__MmuPlugin_ports_0_entryToReplace_value = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value; __Vdly__MmuPlugin_ports_1_entryToReplace_value = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value; __Vdly__CsrPlugin_mstatus_MPIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPIE; __Vdly__CsrPlugin_sstatus_SPIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE; __Vdly__CsrPlugin_sstatus_SPP = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP; __Vdly__CsrPlugin_mstatus_MIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE; __Vdly__CsrPlugin_sstatus_SIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE; __Vdly__CsrPlugin_mstatus_MPP = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP; __Vdly__IBusCachedPlugin_fetchPc_pcReg = vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg; __Vdly___zz_247_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_247_; __Vdly___zz_154_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_; __Vdly__MmuPlugin_shared_state_1_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_; __Vdly___zz_245_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_; __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex; __Vdly__memory_arbitration_isValid = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid; __Vdly__execute_arbitration_isValid = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid; __Vdly__writeBack_arbitration_isValid = vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid; __Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_datas__v0 = 0U; __Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_tags__v0 = 0U; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if (VL_UNLIKELY((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt))) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { VL_WRITEF("ERROR writeBack stuck by another plugin is not allowed\n"); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 __Vdly__CsrPlugin_mcycle = (VL_ULL(1) + vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcycle); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_error = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_address = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_address = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:553 if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_2_) { __Vdlyvval__dataCache_1___DOT__ways_0_tags__v0 = ((vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid))); __Vdlyvset__dataCache_1___DOT__ways_0_tags__v0 = 1U; __Vdlyvdim0__dataCache_1___DOT__ways_0_tags__v0 = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring) { __Vdly__CsrPlugin_minstret = (VL_ULL(1) + vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_minstret); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:569 if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_))) { __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol0__v0 = (0xffU & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data); __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol0__v0 = 1U; __Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol0__v0 = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:569 if ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask) >> 1U) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_))) { __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol1__v0 = (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data >> 8U)); __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol1__v0 = 1U; __Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol1__v0 = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:569 if ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask) >> 2U) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_))) { __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol2__v0 = (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data >> 0x10U)); __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol2__v0 = 1U; __Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol2__v0 = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:569 if ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask) >> 3U) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_))) { __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol3__v0 = (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data >> 0x18U)); __Vdlyvset__dataCache_1___DOT__ways_0_data_symbol3__v0 = 1U; __Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol3__v0 = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:310 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_12_) { __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter = (0xffU & ((IData)(1U) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter))); } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_3_ = (1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_13_) { __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3226 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_61_) { __Vdlyvval__RegFilePlugin_regFile__v0 = vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_data; __Vdlyvset__RegFilePlugin_regFile__v0 = 1U; __Vdlyvdim0__RegFilePlugin_regFile__v0 = vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_352_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_353_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 5U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_354_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 1U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_355_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 9U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 1U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_356_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_357_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 5U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 3U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_358_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 1U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 3U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_359_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 9U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 3U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_229_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 7U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 3U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_230_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 3U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 3U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_231_) { vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code = 0xbU; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege = 3U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MEIP = (0U != vlSymsp->TOP__dut__VexRiscv.__PVT___zz_242_); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_INPUT = (0U != vlSymsp->TOP__dut__VexRiscv.__PVT___zz_244_); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__externalInterruptArray_regNext = vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_interrupt0; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_FORMAL_PC_NEXT = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_FORMAL_PC_NEXT; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_LRSC = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1fU))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_AMO = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xfU))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS1_SIGNED = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x15U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 4U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1cU))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_FORMAL_PC_NEXT = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_99_; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_LESS_UNSIGNED = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x21U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_FORCE_ZERO = (1U & ((IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xcU)) & (~ (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x20U))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_USE_SUB_LESS = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x20U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_HH = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_HH; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 9U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x16U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT = (IData)((VL_ULL(0x1ffffffff) & VL_SHIFTRS_QQI(33,33,5, (((QData)((IData)( ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL)) & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed >> 0x1fU)))) << 0x20U) | (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed))), (0x1fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 2U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__dBusWishbone_DAT_MISO_regNext = vlSymsp->TOP__dut.__PVT__builder_shared_dat_r; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_MEMORY_STAGE; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_ADDRESS_LOW; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_WR; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_MUL = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_MUL; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW = (VL_ULL(0xfffffffffffff) & (((((QData)((IData)( (0x7ffffU & VL_NEGATE_I((IData)( (1U & (IData)( ((QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_LL)) >> 0x20U)))))))) << 0x21U) | (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_LL))) + (((QData)((IData)( (3U & VL_NEGATE_I((IData)( (1U & (IData)( (VL_ULL(1) & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_LH >> 0x21U))))))))) << 0x32U) | (VL_ULL(0x3ffffffffffff) & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_LH << 0x10U)))) + (((QData)((IData)( (3U & VL_NEGATE_I((IData)( (1U & (IData)( (VL_ULL(1) & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_HL >> 0x21U))))))))) << 0x32U) | (VL_ULL(0x3ffffffffffff) & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_HL << 0x10U))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xbU))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_VALID; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_MANAGMENT = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1bU))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DIV = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_DIV; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MTIP = (vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time >= vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_cmp); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_V = (1U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_R = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_W = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_X = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_U = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_G = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_A = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 6U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_D = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_RSW = (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_PPN0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_PPN1 = (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE = (0x20U != (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 7U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE = (1U & (~ (((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))) & (0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU)))) | ((3U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))) & (0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid = 1U; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_DO = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PREDICTION_HAD_BRANCHED2) != ((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) & ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) | ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) | ((0U == (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq) : ((1U == (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq)) : ((5U == (5U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less)) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less)))))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_valid = (1U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_error = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_address = (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ >> 2U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_colisions = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_colisions_regNextWhen) | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 2U)))) & (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_mask) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:310 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_error = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ >> 1U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits = (((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0xcU)) == (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ >> 2U))) & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_ENABLE; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:310 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_valid = (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ & ((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ >> 2U)) == (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0xcU)))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultReg = ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) ^ (((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)) == (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_ >> 0x1fU) : ((3U == (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) >> 1U))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU) : (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)))))) ? vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data | vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0)) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data ^ vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1125 if (vlSymsp->TOP__dut.__Vcellinp__VexRiscv__reset) { __Vdly__dataCache_1___DOT__stageB_flusher_valid = 1U; __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent = 0U; __Vdly__dataCache_1___DOT__loader_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator = 1U; __Vdly__dataCache_1___DOT__loader_error = 0U; } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_21_) { __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { if ((0x7fU != (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 5U)))) { __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = ((0xfffff01fU & __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress) | (0xfe0U & (((IData)(1U) + (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 5U)) << 5U))); } else { __Vdly__dataCache_1___DOT__stageB_flusher_valid = 0U; } } if ((((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo))) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_valueNext; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator = (1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_36_)); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved = 0U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_19_) { __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = (0xfffff01fU & __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress); __Vdly__dataCache_1___DOT__stageB_flusher_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid) { __Vdly__dataCache_1___DOT__loader_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { __Vdly__dataCache_1___DOT__loader_error = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_error; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { __Vdly__dataCache_1___DOT__loader_valid = 0U; __Vdly__dataCache_1___DOT__loader_error = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RVC = (3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_321_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferData = (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_206_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_208_ = (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_209_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_CALC = (0xfffffffeU & (((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC) + vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1 = ((VL_ULL(0x100000000) & vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1) | (IData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_454_))); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[0U] = ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_236_ >> 0x20U))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_235_) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_236_)); if ((0x20U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_result = (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_459_); } } } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[0U] = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[1U] = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[2U] = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1 = (VL_ULL(0x1ffffffff) & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_239_) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_) + (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_239_)))); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs2 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_238_) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2) : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_238_)); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_needRevert = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_239_) ^ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_238_) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU)))) & (~ (((0U == vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS2_SIGNED)) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s2_tightlyCoupledHit = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s1_tightlyCoupledHit; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_21_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess = (((0xbU == (0xfU & (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0x1cU))) | (0xeU == (0xfU & (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0x1cU)))) | (0xfU == (0xfU & (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0x1cU)))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowRead = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup)) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_))))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowWrite = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowExecute = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHit) & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum)))) | ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_)) & (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_refilling = vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_refilling; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MSIP = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_interrupt = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException))); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_exceptionCode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sepc = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stval = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; } } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcause_interrupt = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException))); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcause_exceptionCode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mepc = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtval = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; } } } } if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MSIP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 3U)); } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mepc = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mscratch = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtvec_base = (0x3fffffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtvec_mode = (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData); } } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_ppn = (0xfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData); } } } } } } } } } else { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stval = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_interrupt = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_exceptionCode = (0xfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData); } } } else { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sepc = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sscratch = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_base = (0x3fffffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_mode = (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData); } } } } } } } } } } } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:174 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_1_) { __Vdlyvval__IBusCachedPlugin_cache__DOT__ways_0_datas__v0 = vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_DAT_MISO_regNext; __Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_datas__v0 = 1U; __Vdlyvdim0__IBusCachedPlugin_cache__DOT__ways_0_datas__v0 = ((0x3f8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 2U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:162 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_2_) { __Vdlyvval__IBusCachedPlugin_cache__DOT__ways_0_tags__v0 = ((0x3ffffcU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 0xaU)) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_hadError) << 1U) | (1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U)))); __Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_tags__v0 = 1U; __Vdlyvdim0__IBusCachedPlugin_cache__DOT__ways_0_tags__v0 = (0x7fU & ((0x80U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 5U) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter))); } vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcycle = __Vdly__CsrPlugin_mcycle; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_minstret = __Vdly__CsrPlugin_minstret; // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3228 if (__Vdlyvset__RegFilePlugin_regFile__v0) { vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[__Vdlyvdim0__RegFilePlugin_regFile__v0] = __Vdlyvval__RegFilePlugin_regFile__v0; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_error = __Vdly__dataCache_1___DOT__loader_error; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid = __Vdly__dataCache_1___DOT__stageB_flusher_valid; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid = __Vdly__dataCache_1___DOT__loader_valid; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = __Vdly__dataCache_1___DOT__stageB_mmuRsp_physicalAddress; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter = __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_FORMAL_PC_NEXT = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3824 vlSymsp->TOP__dut__VexRiscv.__Vtableidx11 = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable11___PVT__memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx11][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable11___PVT__memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx11][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable11___PVT__memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx11][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4087 vlSymsp->TOP__dut__VexRiscv.__Vtableidx23 = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx23][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx23][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx23][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_HH = (VL_ULL(0x3ffffffff) & VL_MULS_QQQ(34,34,34, (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh)), (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh)))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3878 vlSymsp->TOP__dut__VexRiscv.__Vtableidx15 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable15___PVT__execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx15][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable15___PVT__execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx15][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable15___PVT__execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx15][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4096 vlSymsp->TOP__dut__VexRiscv.__Vtableidx24 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx24][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx24][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx24][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5890 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x1fU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffffbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffff7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x200000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x400000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x800000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x1000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x4000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x8000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x10000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x20000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x40000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_) | (0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT << 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x10U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_MEMORY_STAGE = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 3U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_ADDRESS_LOW = (3U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_WR = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_WR; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_MUL = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_MUL; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_HL = (VL_ULL(0x3ffffffff) & VL_MULS_QQQ(34,34,34, (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh)), (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_))))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_LH = (VL_ULL(0x3ffffffff) & VL_MULS_QQQ(34,34,34, (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_))), (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh)))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MUL_LL = ((0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_) * (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_VALID = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_REGFILE_WRITE_VALID; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_DIV = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x14U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PREDICTION_HAD_BRANCHED2 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_colisions_regNextWhen = ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ >> 2U)))) & (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_mask) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask)))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:559 if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_tags [vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_payload]; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_ENABLE = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_ENABLE; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:168 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__ways_0_tags [(0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc >> 5U))]; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_41_) << 0x18U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_40_) << 0x10U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_39_) << 8U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_38_)))); } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_36_ = (3U & VL_NEGATE_I((IData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_wr; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_data; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_size = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_size; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_isLrsc; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_isAmo; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_amoCtrl_swap; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_amoCtrl_alu; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:310 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s1_tightlyCoupledHit) ? 0U : vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_11_); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU))); } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_235_ = ( ((QData)((IData)( vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[0U])) << 1U) | (QData)((IData)( (1U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1 >> 0x1fU)))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS2_SIGNED = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 6U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((0x20U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:924 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_error))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_PC; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code = ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_232_) & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_232_) - (IData)(1U))))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code) : 2U); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr = ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_232_) & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_232_) - (IData)(1U))))) ? (0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_) : vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code = vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_DATA; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_DAT_MISO_regNext = vlSymsp->TOP__dut.__PVT__builder_shared_dat_r; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_12_ = (1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:271 if (vlSymsp->TOP__dut.__Vcellinp__VexRiscv__reset) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_hadError = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending = 1U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent = 0U; __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex = 0U; } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_) { __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex = (7U & ((IData)(1U) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex))); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_hadError = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_254_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface0_soc_bus_ack))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:310 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_physicalAddress; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:555 if (__Vdlyvset__dataCache_1___DOT__ways_0_tags__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_tags[__Vdlyvdim0__dataCache_1___DOT__ways_0_tags__v0] = __Vdlyvval__dataCache_1___DOT__ways_0_tags__v0; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:164 if (__Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_tags__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__ways_0_tags[__Vdlyvdim0__IBusCachedPlugin_cache__DOT__ways_0_tags__v0] = __Vdlyvval__IBusCachedPlugin_cache__DOT__ways_0_tags__v0; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_236_ = (VL_ULL(0x1ffffffff) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_235_ - (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs2)))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex = __Vdly__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3842 vlSymsp->TOP__dut__VexRiscv.__Vtableidx13 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable13___PVT__execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx13][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable13___PVT__execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx13][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable13___PVT__execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx13][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4078 vlSymsp->TOP__dut__VexRiscv.__Vtableidx22 = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx22][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx22][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx22][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_WR = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1aU))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_MUL = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x19U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_REGFILE_WRITE_VALID = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_REGFILE_WRITE_VALID; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_ENABLE = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 8U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:583 if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_38_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol0 [vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload]; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_39_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol1 [vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload]; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_40_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol2 [vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload]; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_41_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol3 [vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload]; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap) << 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_ = ((vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data + ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu)) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0)) + ((0xfffffffcU & (VL_NEGATE_I((IData)((1U & (((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu)) ? 1U : 0U) >> 1U)))) << 2U)) | ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu)) ? 1U : 0U))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_18_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_wr = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_265_; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_data = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_266_; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_size = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_isLrsc = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_isAmo = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_269_; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_amoCtrl_swap = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_amoCtrl_alu = (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU)); } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_20_ = (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_colisions) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:180 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_11_ = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__ways_0_datas [(0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc >> 2U))]; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s1_tightlyCoupledHit = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6697 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_ = ( (VL_ULL(0xffffffff) & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_) | ((QData)((IData)( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS1_SIGNED) & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 >> 0x1fU)))) << 0x20U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_ = ( (VL_ULL(0x100000000) & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_240_) | (IData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_239_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_DIV) & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 >> 0x1fU)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS1_SIGNED)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_454_ = ( ((QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1)) << 1U) | (QData)((IData)( (1U & (~ (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_236_ >> 0x20U))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_238_ = ( (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 >> 0x1fU) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RS2_SIGNED)); vlSymsp->TOP__dut__VexRiscv.lastStagePc = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_PC = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ = vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg; } if ((((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ = (2U | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:226 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wayToAllocate_willIncrement = 0U; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wayToAllocate_willIncrement = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:310 if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_physicalAddress = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_isIoAccess = (((0xbU == (0xfU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0x1cU))) | (0xeU == (0xfU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0x1cU)))) | (0xfU == (0xfU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0x1cU)))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowRead = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup)) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowWrite = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowExecute = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHit) & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum)))) | ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_)) & (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_refilling; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:570 if (__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol0__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol0[__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol0__v0] = __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol0__v0; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:573 if (__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol1__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol1[__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol1__v0] = __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol1__v0; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:576 if (__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol2__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol2[__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol2__v0] = __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol2__v0; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:579 if (__Vdlyvset__dataCache_1___DOT__ways_0_data_symbol3__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__ways_0_data_symbol3[__Vdlyvdim0__dataCache_1___DOT__ways_0_data_symbol3__v0] = __Vdlyvval__dataCache_1___DOT__ways_0_data_symbol3__v0; } // ALWAYSPOST at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:176 if (__Vdlyvset__IBusCachedPlugin_cache__DOT__ways_0_datas__v0) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__ways_0_datas[__Vdlyvdim0__IBusCachedPlugin_cache__DOT__ways_0_datas__v0] = __Vdlyvval__IBusCachedPlugin_cache__DOT__ways_0_datas__v0; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC = vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6794 if (vlSymsp->TOP__dut.__Vcellinp__VexRiscv__reset) { __Vdly__IBusCachedPlugin_fetchPc_pcReg = 0U; __Vdly__IBusCachedPlugin_fetchPc_booted = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid = 0U; __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_0 = 0U; __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_1 = 0U; __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_2 = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_3 = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_decodeRemoved = 0U; __Vdly__IBusCachedPlugin_rspCounter = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_153_; __Vdly___zz_154_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_ = 0U; __Vdly__DBusCachedPlugin_rspCounter = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_168_; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid = 0U; __Vdly__MmuPlugin_ports_0_entryToReplace_value = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid = 0U; __Vdly__MmuPlugin_ports_1_entryToReplace_value = 0U; __Vdly__MmuPlugin_shared_state_1_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_194_ = 1U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_207_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_ = 3U; __Vdly__CsrPlugin_mstatus_MIE = 0U; __Vdly__CsrPlugin_mstatus_MPIE = 0U; __Vdly__CsrPlugin_mstatus_MPP = 3U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MEIE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MTIE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MSIE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAM = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAF = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_II = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAM = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAF = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAM = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAF = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_EU = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_ES = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IPF = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LPF = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SPF = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_ST = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SS = 0U; __Vdly__CsrPlugin_sstatus_SIE = 0U; __Vdly__CsrPlugin_sstatus_SPIE = 0U; __Vdly__CsrPlugin_sstatus_SPP = 1U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_lastStageWasWfi = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_wfiWake = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_241_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_243_ = 0U; __Vdly__execute_arbitration_isValid = 0U; __Vdly__memory_arbitration_isValid = 0U; __Vdly__writeBack_arbitration_isValid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_DATA = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION = 0U; __Vdly___zz_245_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_ = 0U; __Vdly___zz_247_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_ = 0U; __Vdly__IBusCachedPlugin_rspCounter = 0U; __Vdly__DBusCachedPlugin_rspCounter = 0U; vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg = 0U; } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__iBus_rsp_valid) { __Vdly__IBusCachedPlugin_rspCounter = ((IData)(1U) + vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rspCounter); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dBus_rsp_valid) { __Vdly__DBusCachedPlugin_rspCounter = ((IData)(1U) + vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_rspCounter); } if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid) { __Vdly__MmuPlugin_shared_state_1_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) { __Vdly__MmuPlugin_shared_state_1_ = 3U; } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready) { __Vdly__MmuPlugin_shared_state_1_ = 4U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid) { __Vdly__MmuPlugin_shared_state_1_ = 3U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_leaf) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception))) { __Vdly__MmuPlugin_shared_state_1_ = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) { __Vdly__MmuPlugin_shared_state_1_ = 1U; } } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready) { __Vdly__MmuPlugin_shared_state_1_ = 2U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_342_) { __Vdly__MmuPlugin_shared_state_1_ = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_343_) { __Vdly__MmuPlugin_shared_state_1_ = 1U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_) { if (vlSymsp->TOP__dut.__PVT__main_soclinux_interface0_soc_bus_ack) { __Vdly___zz_245_ = (7U & ((IData)(1U) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_))); } } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_248_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_249_))) { __Vdly___zz_247_ = (7U & ((IData)(1U) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_247_))); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_) { __Vdly___zz_247_ = 0U; } } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_corrected) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pcRegPropagate))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc = 0U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_booted) & ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt))) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pcRegPropagate)))) { __Vdly__IBusCachedPlugin_fetchPc_pcReg = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_ = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_ = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_output_valid; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid = 0U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_3 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_2; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_decodeRemoved = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready) { __Vdly___zz_154_ = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_valid; } __Vdly__MmuPlugin_ports_0_entryToReplace_value = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_valueNext; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid = 0U; } } __Vdly__MmuPlugin_ports_1_entryToReplace_value = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_valueNext; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_194_ = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_207_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_206_; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)))); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_lastStageWasWfi = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring) & (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL))); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_ = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { __Vdly__CsrPlugin_sstatus_SPIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE; __Vdly__CsrPlugin_sstatus_SPP = (1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_privilege)); __Vdly__CsrPlugin_sstatus_SIE = 0U; } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { __Vdly__CsrPlugin_mstatus_MPIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE; __Vdly__CsrPlugin_mstatus_MPP = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_privilege; __Vdly__CsrPlugin_mstatus_MIE = 0U; } } } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_wfiWake = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_231_) << 5U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_230_) << 4U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_229_) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_))))))); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_valueNext; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_DATA = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready)); } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_IS_DBUS_SHARING; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_CYC) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface0_soc_bus_ack)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_ = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_248_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface1_soc_bus_ack)); if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_output_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFiring) { vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePc_pcPlus; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_output_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt))); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_ = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_321_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_322_; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_3 = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_decodeRemoved = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_341_) { __Vdly___zz_154_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_exception) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid = 0U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_352_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_353_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_354_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_355_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_320_))) { __Vdly__CsrPlugin_mstatus_MIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPIE; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_ = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP; __Vdly__CsrPlugin_mstatus_MPP = 0U; __Vdly__CsrPlugin_mstatus_MPIE = 1U; } else { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_320_))) { __Vdly__CsrPlugin_sstatus_SIE = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_ = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP; __Vdly__CsrPlugin_sstatus_SPP = 0U; __Vdly__CsrPlugin_sstatus_SPIE = 1U; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING = 0U; } if (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_output_valid)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc = 0U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid) & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt)))) { vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_282_; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_344_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_345_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_346_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_347_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid = 1U; } } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_348_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_349_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_350_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_351_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid = 1U; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_356_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_357_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_358_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_359_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_229_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_230_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_231_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid = 1U; } } if ((0x80000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_241_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_243_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData; } } } } } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 9U)); } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MEIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MTIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MSIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); } } } } else { if ( (0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_ST = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SS = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_EU = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_II = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAF = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LPF = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0xdU)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAM = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAF = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAF = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_ES = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IPF = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0xcU)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SPF = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0xfU)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAM = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 6U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAM = (1U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData); } } } else { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x11U)); __Vdly__CsrPlugin_mstatus_MPP = (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0xbU)); __Vdly__CsrPlugin_mstatus_MPIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 7U)); __Vdly__CsrPlugin_mstatus_MIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 3U)); __Vdly__CsrPlugin_sstatus_SPP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 8U)); __Vdly__CsrPlugin_sstatus_SPIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); __Vdly__CsrPlugin_sstatus_SIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); } } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x1fU)); } } } } } } } } } else { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 9U)); } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); } } } } else { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 0x11U)); __Vdly__CsrPlugin_sstatus_SPP = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 8U)); __Vdly__CsrPlugin_sstatus_SPIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 5U)); __Vdly__CsrPlugin_sstatus_SIE = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData >> 1U)); } } } } } } } } } } } } } __Vdly__IBusCachedPlugin_fetchPc_booted = 1U; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_2 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_1; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_SFENCE_VMA))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_2 = 0U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_0; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt)))) { __Vdly__writeBack_arbitration_isValid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_1 = 0U; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt))))) { __Vdly__writeBack_arbitration_isValid = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid; } __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_0 = 1U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt) { __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_0 = 0U; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt)))) { __Vdly__memory_arbitration_isValid = 0U; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt))))) { __Vdly__memory_arbitration_isValid = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt)))) { __Vdly__execute_arbitration_isValid = 0U; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt))))) { __Vdly__execute_arbitration_isValid = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid; } } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rspCounter = __Vdly__IBusCachedPlugin_rspCounter; vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_rspCounter = __Vdly__DBusCachedPlugin_rspCounter; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_2 = __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_2; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_1 = __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_1; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_0 = __Vdly__IBusCachedPlugin_injector_nextPcCalc_valids_0; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_booted = __Vdly__IBusCachedPlugin_fetchPc_booted; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPIE = __Vdly__CsrPlugin_mstatus_MPIE; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE = __Vdly__CsrPlugin_sstatus_SPIE; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP = __Vdly__CsrPlugin_sstatus_SPP; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE = __Vdly__CsrPlugin_sstatus_SIE; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE = __Vdly__CsrPlugin_mstatus_MIE; vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP = __Vdly__CsrPlugin_mstatus_MPP; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_247_ = __Vdly___zz_247_; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_ = __Vdly___zz_245_; vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid = __Vdly__memory_arbitration_isValid; vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid = __Vdly__execute_arbitration_isValid; vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid = __Vdly__writeBack_arbitration_isValid; vlSymsp->TOP__dut__VexRiscv.__PVT__iBus_rsp_valid = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:186 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_1_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_1_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:201 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_246_) { if ((7U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s1_tightlyCoupledHit))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_231_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MEIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MEIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_229_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MTIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MTIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_230_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MSIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MSIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6131 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 3U; if ((8U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SPF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LPF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IPF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } else { if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code) >> 1U)))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_ES) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_EU) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } } else { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_SAM) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_LAM) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_II) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAF) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_medeleg_IAM) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 1U; } } } } } vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_INPUT)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_242_ = (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_241_ & vlSymsp->TOP__dut__VexRiscv.__PVT__externalInterruptArray_regNext); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_244_ = (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_243_ & vlSymsp->TOP__dut__VexRiscv.__PVT__externalInterruptArray_regNext); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_320_ = (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0x1cU)); vlSymsp->TOP__dut__VexRiscv.lastStageInstruction = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION; vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_address = (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_248_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6115 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_privilege = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_352_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) | (1U > (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_356_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE) | (3U > (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5553 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode; if (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv)) & (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup = 0U; } if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT__memory_IS_DBUS_SHARING = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5242 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6262 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause = vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code; } vlSymsp->TOP__dut__VexRiscv.__PVT__dBus_rsp_valid = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_; vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_SFENCE_VMA = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_SFENCE_VMA; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid) | (0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_308_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_DO)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_332_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_VALID)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5232 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_MEMORY_ENABLE)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DBUS_SHARING) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_DIV)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_309_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_305_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_334_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_MANAGMENT)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_155_) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_163_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_156_ : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_164_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_157_ : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_165_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_158_) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mask)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_166_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_159_) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_167_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_160_) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId) { if ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)))) { if ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_exception = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception) | ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (0U != (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_0 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_1 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_physicalAddress_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_physicalAddress_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowRead = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowWrite = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowExecute = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowUser = (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_superPage = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)); } } } vlSymsp->TOP__dut__VexRiscv.lastStageIsValid = vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_306_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6244 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done = ((0U == (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid)))) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_nextPcCalc_valids_3)); if ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_ = (0U == ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack)) << 2U) | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory)) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5257 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) ? ((0xffff0000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen << 0x10U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferData)) : ((0xffff0000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen) | (0xffffU & ((2U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U) : vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4644 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_incomingInstruction = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_incomingInstruction = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) & (3U != (3U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferData))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_incomingInstruction = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_s2_tightlyCoupledHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:193 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_2_ = 0U; if ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire) | (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_2_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_13_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending) & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_353_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_ST)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_357_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_226_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_ST))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_354_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SS)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_358_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_227_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SS))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6255 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_targetPrivilege; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped)) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)); } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5454 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode)); if (((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv)) & (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup = 0U; } if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))) { if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv)) | (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1042 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6766 vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_STB = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_) { vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_STB = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6759 vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_CYC = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_340_) { vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_CYC = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4447 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_99_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_FORMAL_PC_NEXT; if (vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_99_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_CALC; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4569 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6662 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4551 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_haltItself = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_haltItself = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_ = __Vdly___zz_154_; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value = __Vdly__MmuPlugin_ports_0_entryToReplace_value; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value = __Vdly__MmuPlugin_ports_1_entryToReplace_value; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1030 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) ? vlSymsp->TOP__dut__VexRiscv.__PVT__dBusWishbone_DAT_MISO_regNext : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0); if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved))); } vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interruptJump = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:740 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 2U)); } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address = ((0x3f8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 2U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:726 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:905 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_20_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 1U; } } } } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_refilling))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_exception) | ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowWrite)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr))) | ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowRead)) & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo))))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) & (((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_size)) & (0U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress))) | ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_size)) & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePc_pcPlus = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? 2U : 4U)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4769 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError = 1U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) & (3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_ = ( (0x18U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_ = ( (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x38U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4836 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0x7ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xbffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xdffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xeffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xf7fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xfbfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xfdfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_ = ( (0xfe0U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_)) | (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4863 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x3fffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 2U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x5fffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x6fffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x77ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7bffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7dffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7effU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7f7fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7fbfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7fdfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7fefU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ff7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ffbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ffdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_ = ( (0x7ffeU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4882 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_ = ( (3U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_ = ( (5U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_ = ( (6U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4952 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x3fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x5fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x6fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x77U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x7bU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x7dU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_ = ( (0x7eU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4848 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x1ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x2ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x37fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_ = ( (0x3feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4889 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x1ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x2ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 4U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x37fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 6U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_ = ( (0x3feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4904 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0xfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 8U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x17U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x1bU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x1dU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_ = ( (0x1eU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_314_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6269 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode = 0U; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_mode; } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtvec_mode; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6283 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base = 0U; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_base; } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtvec_base; } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_355_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SE)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_359_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_228_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mideleg_SE))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1052 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_valueNext = (7U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow = ((7U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_IS_SFENCE_VMA = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_SFENCE_VMA; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_247_) == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_166_)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_341_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_155_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_156_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_157_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_158_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mask; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_159_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_160_ = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_237_ = ( (0x2000U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION) ? vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_accumulator[0U] : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_rs1)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_344_ = (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_345_ = (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_346_ = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_347_ = (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_348_ = (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_349_ = (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_350_ = (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_351_ = (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_leaf = (1U & ((vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U) | (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5310 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data; if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW))) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = ((0xffffff00U & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted) | (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 8U))); } else { if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW))) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = ((0xffff0000U & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted) | (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x10U))); } else { if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW))) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted = ((0xffffff00U & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted) | (0xffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x18U))); } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_) >> 2U)))) { if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_) >> 1U)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_342_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId = 0U; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU)); } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_343_) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0 = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId = 1U; } } } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException) | (IData)(vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interruptJump)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5266 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5295 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR) ? 7U : 5U); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR) ? 6U : 4U); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_payload_code = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_WR) ? 0xfU : 0xdU); } } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception = (1U & (((~ vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data) | ((~ (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)) & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U))) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5276 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_326_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid = 0U; } } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_ = ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_refilling) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_127_) << 0xbU) | ((0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 2U)) | ((0x300U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | ((0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (0xeU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_134_) << 0xbU) | ((0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 2U)) | ((0x300U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 1U)) | ((0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | ((0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (0xeU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_137_) << 8U) | ((0xc0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 1U)) | ((0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 3U)) | ((0x18U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U)) | (6U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U)))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4438 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_314_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:675 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:685 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_error; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:692 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address = (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 0xcU)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:665 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 5U)); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress >> 5U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:655 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1002 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:987 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) ? 0U : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) ? 0U : 7U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1017 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr = 0U; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:972 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) ? (0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) ? (0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress) : (0xffffffe0U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:873 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultReg; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_459_ = (VL_ULL(0x1ffffffff) & ((QData)((IData)( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_needRevert) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_237_) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_237_))) + (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_needRevert)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_ = (1U & ((vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted >> 7U) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xeU)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_ = (1U & ((vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted >> 0xfU) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xeU)))); vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg = __Vdly__IBusCachedPlugin_fetchPc_pcReg; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_ = __Vdly__MmuPlugin_shared_state_1_; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4664 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base << 2U); } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { if ((3U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mepc; } else { if ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sepc; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4654 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4594 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4601 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:642 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:699 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:936 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent))); if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_18_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_20_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 1U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:816 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_)))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid = 1U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:832 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess) { if ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr) ? (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_253_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_18_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr)) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 1U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_16_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_13_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4779 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = 0U; if ((0x10U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_) >> 3U)))) { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x12023U | (((0xc000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x13U)) | (0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xdU))) | ((0x1f00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | (0xe00U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))); } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = ((0x400U == (0x7ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))) ? 0x100073U : ((0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U))) ? (0x67U | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (((0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode) ? 1U : 0U) << 7U))) : (0x33U | ((0x1f00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0xf8000U & (((0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U) : 0U) << 0xfU)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))))); } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x12003U | ((0xc000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x18U)) | ((0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xdU)) | ((0x1c00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode))))); } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x1013U | ((0x1f00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))); } } } } } else { if ((8U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? (0x41063U | ((0x80000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x13U)) | ((0x7e000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x14U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | ((0xf00U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 7U)) | (0x80U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) >> 4U))))))) : (0x40063U | ((0x80000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x13U)) | ((0x7e000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 0x14U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | ((0xf00U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) << 7U)) | (0x80U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_138_) >> 4U)))))))) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? (0x6fU | ((0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ << 0xbU)) | ((0x7fe00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ << 0x14U)) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_ << 9U)) | (0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_135_))))) : (0x40400U | ((((2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_146_) : (((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) | ((3U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) & (0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))))) << 5U)) << 0x19U) | ((0x1f00000U & (((1U & ((~ (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xbU)) | (3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U) : (8U | (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 2U)))) << 0x14U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | ((((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 5U : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 5U : ((2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 7U : ((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))) ? 0U : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))) ? 4U : ((2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 5U))) ? 6U : 7U)))))) << 0xcU) | ((0x380U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode) | ((3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 0xaU))) ? 0x13U : 0x33U))))))))) : ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? ((2U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode >> 7U))) ? (0x13U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_132_) << 0x1dU) | ((0x18000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x18U)) | ((0x4000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x15U)) | ((0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x17U)) | ((0x1000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))))))) : (0x37U | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_130_) << 0x11U) | (0x1f000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xaU))) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))) : (0x13U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_) << 0x14U) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)) ? (0xefU | ((0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ << 0xbU)) | ((0x7fe00000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ << 0x14U)) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_ << 9U)) | (0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_128_))))) : (0x13U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_125_) << 0x14U) | ((0xf8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode))))))); } else { if ((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x842023U | ((0xfe000000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_) << 0x14U)) | ((0x700000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0xf80U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_) << 7U)))))); } } } else { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_))) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x42403U | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_123_) << 0x14U) | ((0x38000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 8U)) | (0x380U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 5U))))); } } else { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_363_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed = (0x10413U | ((0x3c000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x13U)) | ((0x3000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0xdU)) | ((0x800000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x12U)) | ((0x400000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 0x10U)) | (0x380U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode << 5U))))))); } } } } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_exception) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowExecute))))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_SFENCE_VMA = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x18U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL = (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x12U))); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:754 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data = vlSymsp->TOP__dut__VexRiscv.__PVT__dBusWishbone_DAT_MISO_regNext; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mask = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_mask; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6035 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0x7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xf7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xfffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ = ( (0xffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6073 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x3ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x5ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x6ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x77fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_ = ( (0x7feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6088 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x3ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x5ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x6ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x77fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7bfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7dfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7efffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7f7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7feffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7ffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ = ( (0x7fffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6470 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = 0U; if ((0x80000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x40000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_242_; } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((0x1000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? 3U : 2U)); } else { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = (1U | vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData); } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_244_; } } } } } } } } } else { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = (0x1000U | (0xffffe000U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = (0x2000000U | (0xfc0fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData)); } } } } } } } } } } } else { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_241_; } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_243_; } } } } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MEIP) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MTIP) << 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mip_MSIP) << 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP) << 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR) << 9U)); } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mtval; } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcause_interrupt) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff0U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcause_exceptionCode)); } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mepc : vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mscratch); } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MEIE) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MTIE) << 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mie_MSIE) << 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE) << 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE) << 1U)); } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffe7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPP) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MPIE) << 7U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mstatus_MIE) << 3U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP) << 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE) << 1U)); } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_mode) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfff00000U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_ppn); } } } } } } } } else { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_STIP) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SSIP) << 1U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR) << 9U)); } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stval; } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_interrupt) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffff0U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_scause_exceptionCode)); } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sepc : vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sscratch); } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((3U & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_base << 2U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_stvec_mode)); } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SEIE) << 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_STIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sie_SSIE) << 1U)); } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mxr) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_sum) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_status_mprv) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPP) << 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SPIE) << 5U)); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData = ((0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sstatus_SIE) << 1U)); } } } } } } } } } } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5757 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ = ( (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 : ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL)) ? ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RVC) ? 2U : 4U) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL)) ? (0xfffff000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) : (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5776 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0x7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xf7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xfffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ = ( (0xffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5800 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0x7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xf7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xfffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ = ( (0xffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6308 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 1U; if ((0x80000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x40000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((0x1000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } else { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } } else { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1eU)))) { if ((0x20000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))) { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ((0x200000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ( (0x100000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } else { if ((0x10000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((0x8000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1aU)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x16U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } else { if ((0x4000000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x19U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x18U)))) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x17U)))) { if ((0x400000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION)) { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } else { if ((1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x15U)))) { if ( (1U & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } } } } } } } } } } } } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 1U; } if ((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid)) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5328 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1eU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1dU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1cU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1bU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x1aU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x19U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x18U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x17U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x16U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x15U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0x10U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffff7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xfU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xeU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xdU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xcU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xbU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 0xaU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 9U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_170_) << 8U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ = ( (0xffffff00U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_) | (0xffU & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5357 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1fU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1eU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1dU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1cU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1bU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x1aU)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x19U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x18U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x17U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x16U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x15U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x14U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x13U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x12U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x11U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_172_) << 0x10U)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ = ( (0xffff0000U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_) | (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted)); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:7356 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4007 vlSymsp->TOP__dut__VexRiscv.__Vtableidx19 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1___05Fstring = vlSymsp->TOP__dut__VexRiscv.__Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring [vlSymsp->TOP__dut__VexRiscv.__Vtableidx19]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4738 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt = 0U; if (((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5645 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address = 0U; if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_) >> 2U)))) { if ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address = ((0xffc00000U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_PPN1) << 0x16U)) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_pteBuffer_PPN0) << 0xcU) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_0) << 2U))); } } else { if ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address = ((vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_satp_ppn << 0xcU) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_vpn_1) << 2U)); } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5625 vlSymsp->TOP__dut__VexRiscv.__Vtableidx25 = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_; vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid = vlSymsp->TOP__dut__VexRiscv.__Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid [vlSymsp->TOP__dut__VexRiscv.__Vtableidx25]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6229 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4584 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_exceptionBus_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isFlushed = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) | (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isFlushed = ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext))) | (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) << 2U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:599 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_2_ = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_2_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:592 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_ = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_1_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:806 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_DBUS_SHARING) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_wr))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) | (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt)))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst = ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed : vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4431 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_97_; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4576 vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6058 if ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2 = ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_220_ << 0xcU) | (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))); } else { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2 = ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_222_) << 0x15U) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xbU)) | ((0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 9U)) | (0x7feU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))))) : ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_224_ << 0xdU) | ((0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x13U)) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION << 4U)) | ((0x7e0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)) | (0x1eU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U))))))); if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PREDICTION_HAD_BRANCHED2) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2 = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_RVC) ? 2U : 4U); } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6594 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData; if ((0x344U == (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT) << 9U)); } else { if ((0x144U == (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData = ((0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_SOFT) << 9U)); } } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh = ((0x10000U & ((((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) | (2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU)))) << 0x10U) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xfU))) | (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x10U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5853 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1fU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffeffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffffbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffff7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffefffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffdfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffffbfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffff7fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffeffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 1U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffdffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 3U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfffbffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 5U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfff7ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x80000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffefffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 9U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffdfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x200000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0xbU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xffbfffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x400000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xff7fffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x800000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfeffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x1000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfdffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x2000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xfbffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x4000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xf7ffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x8000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xefffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x10000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x20000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0xbfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x40000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ = ( (0x7fffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_) | (0x80000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ << 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5823 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ = ( (0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_198_ << 0xcU) | (0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))) : ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_200_ << 0xcU) | ((0xfe0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U)) | (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U)))) : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4384 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_ = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_DATA; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MEMORY_ENABLE))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_ = ((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ : vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted)); } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_IS_MUL))) { __Vtemp22[0U] = (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW); __Vtemp22[1U] = ((0xfff00000U & (VL_NEGATE_I((IData)( (1U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW >> 0x33U))))) << 0x14U)) | (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW >> 0x20U))); __Vtemp22[2U] = (3U & (VL_NEGATE_I((IData)( (1U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW >> 0x33U))))) >> 0xcU)); VL_EXTEND_WQ(66,34, __Vtemp23, vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_HH); VL_SHIFTL_WWI(66,66,32, __Vtemp24, __Vtemp23, 0x20U); VL_ADD_W(3, __Vtemp25, __Vtemp22, __Vtemp24); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_ = ((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_MUL_LOW) : __Vtemp25[1U]); } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHit = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1) << 1U) | ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_ = ( (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3)) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_output_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_116_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5166 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_265_ = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_WR; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_265_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5208 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_LRSC) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_ = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5220 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_269_ = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_AMO; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_269_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5189 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_266_ = ( (0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? ((0xff000000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 0x18U)) | ((0xff0000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 0x10U)) | ((0xff00U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 8U)) | (0xffU & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2)))) : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? ((0xffff0000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2 << 0x10U)) | (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2)) : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS2)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_266_ = 0U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5198 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_ = (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_ = 2U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5402 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5146 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_ENABLE)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_ = 1U; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4561 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6222 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_rsp_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_leaf) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5012 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x3ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x5ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x6ffU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x77fU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7bfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7dfU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7efU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7f7U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7fbU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7fdU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_ = ( (0x7feU & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_)) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5027 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x3ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x5ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x6ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x77fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7bfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7dfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7efffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7f7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7feffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7ffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ = ( (0x7fffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1fU))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4987 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x3ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x40000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x5ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x20000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xeU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x6ffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x10000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x77fffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x8000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7bfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x4000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x11U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7dfffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x2000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x12U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7efffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x13U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7f7ffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fbffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x400U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x15U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fdffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x200U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7feffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x100U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x17U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ff7fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x80U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x18U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ffbfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x40U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x19U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ffdfU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x20U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1aU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7ffefU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (0x10U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1bU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fff7U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1cU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fffbU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (4U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1dU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fffdU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (2U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1eU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ = ( (0x7fffeU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_) | (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x1fU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_212_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_213_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_214_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_215_ = ( (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ = ( ((QData)((IData)( (0U != (((0x48U == (0x48U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 6U) | (((0x1010U == (0x1010U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x2010U == (0x2010U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x2008U == (0x2008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10U == (0x50U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((4U == (0xcU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0U == (0x28U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))))))) << 0x22U) | (((QData)((IData)( (0U != (((0x2000U == (0x2010U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x1000U == (0x5000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))))) << 0x21U) | (((QData)((IData)( (0U != (((0x40U == (0x44U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x2010U == (0x2014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x40000030U == (0x40000034U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 0x20U) | (QData)((IData)( (((0x10000008U == (0x10000008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1fU) | (((0U != (((0x20U == (0x34U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x20U == (0x64U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x8000020U == (0x8000070U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x10000070U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))))) << 0x1eU) | (((0x1000U == (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1dU) | (((0x2000U == (0x3000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1cU) | (((0x4008U == (0x4048U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x1bU) | (((0U != (((0x8000020U == (0x8000020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x20U == (0x10000020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x28U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))) << 0x1aU) | (((0x2000030U == (0x2004074U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x19U) | (((0x2000050U == (0x2003050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x18U) | (((0U != (((0x48U == (0x48U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x4050U == (0x4050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (4U == (0x2014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))) << 0x17U) | (((0U != (((0x4050U == (0x4050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (4U == (0x4cU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0x16U) | (((0U == (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x15U) | (((0x2004020U == (0x2004064U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x14U) | (((0x50U == (0x2203050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x13U) | (((0x50U == (0x2403050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x12U) | (((0U != (((0x5010U == (0x7034U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x5020U == (0x2007064U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0x11U) | (((0U != (((0x40001010U == (0x40003054U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x1010U == (0x7034U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x1010U == (0x2007054U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))) << 0x10U) | (((8U == (0x10000008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xfU) | (((0U != (((0x48U == (0x48U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (4U == (0x1cU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0xeU) | (((0x40U == (0x58U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xdU) | (((0x24U == (0x64U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xcU) | (((0U != (((0x1050U == (0x1050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x2050U == (0x2050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0xbU) | (((0U != (((4U == (4U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x70U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 0xaU) | (((0U != (((4U == (4U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0U == (0x20U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 9U) | (((0U != (((0x2000U == (0x2050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0U == (0x58U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))) << 8U) | (((0x1008U == (0x5048U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 7U) | (((0U == (0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 6U) | (((0x4010U == (0x4014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x2010U == (0x6014U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0U != (((0x40U == (0x40U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x4020U == (0x4020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10U == (0x30U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((4U == (0xcU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x20U == (0x2000028U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 3U) | (((0U != (((4U == (0xcU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x2010U == (0x2030U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10U == (0x1030U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x20U == (0x2003020U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x2020U == (0x2002068U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 2U) | (((0U != (((0U == (0x44U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0U == (0x18U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x2000U == (0x6004U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x1000U == (0x5004U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x2000U == (0x2050U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))) << 1U) | (0U != (((0x2040U == (0x2040U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x1040U == (0x1040U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x40U == (0x50U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x40U == (0x2400040U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0U == (0x38U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 1U) | (0x10002008U == (0x18002008U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)))))))))))))))))))))))))))))))))))))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_valid))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_337_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_316_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6430 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL)))) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1cU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:768 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_14_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mask; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_17_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = 0xfU; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1060 if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_mask = vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_mask; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_21_ = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze)))); vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_removeIt))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6608 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData = ((0x2000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? ((0x1000U & vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData & (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_)) : (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_)) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed = ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_202_ : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq = (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ == vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh = ((0x10000U & (((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) << 0x10U) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0xfU))) | (0xffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0x10U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5841 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub = ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ + ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_USE_SUB_LESS) ? (~ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)) + ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_USE_SUB_LESS) ? 1U : 0U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_FORCE_ZERO) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_; } vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_data = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5603 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_refilling = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3414 if ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_allowUser; } else { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_1_allowUser; } else { if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_179_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_2_allowUser; } else { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_3_allowUser; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4327 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA; if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_203_; } else { if (((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL)) | (3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_RIGHT; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_310_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_ = vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_result; } vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3 = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_19_ = (((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5435 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5534 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_327_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4372 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_REGFILE_WRITE_VALID = (1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x22U))); if ((0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 7U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_REGFILE_WRITE_VALID = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3662 vlSymsp->TOP__dut__VexRiscv.__Vtableidx1 = (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x16U))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable1___PVT__decode_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx1][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable1___PVT__decode_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx1][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable1___PVT__decode_SRC1_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx1][2U]; // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3716 vlSymsp->TOP__dut__VexRiscv.__Vtableidx7 = (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x10U))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string[0U] = vlSymsp->TOP__dut__VexRiscv.__Vtable7___PVT__decode_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx7][0U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string[1U] = vlSymsp->TOP__dut__VexRiscv.__Vtable7___PVT__decode_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx7][1U]; vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string[2U] = vlSymsp->TOP__dut__VexRiscv.__Vtable7___PVT__decode_SHIFT_CTRL_string [vlSymsp->TOP__dut__VexRiscv.__Vtableidx7][2U]; vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_payload = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((2U == (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))) ? ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_150_) << 0x15U) | ((0x100000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xbU)) | ((0xff000U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 9U)) | (0x7feU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)))))) : ((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_152_ << 0xdU) | ((0x1000U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x13U)) | ((0x800U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst << 4U)) | ((0x7e0U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)) | (0x1eU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 7U)))))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((2U == (3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))) | ((1U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_148_ >> 0x12U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5925 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_332_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_212_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 1U; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_334_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_214_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 1U; } } } if ((1U & (~ (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 1U))))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_ = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5953 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_332_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_213_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 1U; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_334_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE)))) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_215_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 1U; } } } if ((1U & (~ (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1eU))))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_ = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5066 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_314_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4424 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_ = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_96_; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_ = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6300 vlSymsp->TOP__dut__VexRiscv.execute_CsrPlugin_inWfi = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_316_) { vlSymsp->TOP__dut__VexRiscv.execute_CsrPlugin_inWfi = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_336_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction)); vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_haltItself) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)); vlSymsp->TOP__dut__VexRiscv.lastStageIsFiring = vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_206_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5718 vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_REGFILE_WRITE_VALID) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isFiring)); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_194_) { vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5157 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address; } } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less = (1U & (((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1fU)) == (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0x1fU))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub >> 0x1fU) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC_LESS_UNSIGNED) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_ >> 0x1fU) : (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ >> 0x1fU)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_342_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_refilling)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5563 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup) ? (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_) << 0x16U) | ((0x3ff000U & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_) ? (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_)) << 0xcU)) | (0xfffU & vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg))) : vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg); vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHit = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1) << 1U) | ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_ = ( (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3)) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:866 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_19_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5447 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_valueNext = (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5546 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_valueNext = (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5079 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling))); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_312_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_ = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError)))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_ = 0U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_error)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6449 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_336_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code = 2U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_337_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_payload_code = ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)) ? 8U : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)) ? 9U : 0xbU)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6439 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_336_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_337_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6671 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear = 0U; if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck))); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4365 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_61_ = 0U; if (vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_61_ = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_mask = (0xfU & (((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_)) ? 1U : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_)) ? 3U : 0xfU)) << (3U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4250 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_ = ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ ^ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_))) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less) : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub)); if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_305_) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_ = vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_payload_address; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5506 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_refilling = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHit))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3357 if ((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_0_allowUser; } else { if ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_1_allowUser; } else { if ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_176_))) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_2_allowUser; } else { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_valid; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_exception; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_superPage; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_virtualAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_physicalAddress_0; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_physicalAddress_1; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowRead; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowWrite; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowExecute; vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_ = vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cache_3_allowUser; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4512 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 0U; if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } if ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_MEMORY_ENABLE))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_316_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_wfiWake)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_305_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself = 1U; } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5099 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = 0xcU; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5089 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_313_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4417 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_95_; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_311_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4533 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6212 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4544 vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_selfException_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6680 vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_valueNext = (0x3fU & (((0x21U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement)) ? 0U : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement)))); if (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear) { vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_valueNext = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:614 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:628 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_valid = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_valid = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:621 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_payload = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_payload = (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ >> 5U)); } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:635 vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_12_) { vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload = (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ >> 2U)); } vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable = (((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4266 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile [(0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))]; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_207_) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_208_) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_209_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_306_) { if (((0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_308_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_213_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_309_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_215_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS2 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_; } } } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4296 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile [(0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))]; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_207_) { if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_208_) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_209_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_306_) { if (((0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 7U)) == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_93_; } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_308_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_212_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_43_; } } } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_309_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_214_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_RS1 = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_42_; } } } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_343_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_refilling)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5466 vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup) ? (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_) << 0x16U) | ((0x3ff000U & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 0xcU) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_)) << 0xcU)) | (0xfffU & vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA))) : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA); vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_haltItself) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4749 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFlushed = ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext)))) | (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushIt) << 3U))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:5391 vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_324_) { if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready = (1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck))); } } } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_118_) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid = ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid)) : ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid) | (~ (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U))))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_injector_decodeRemoved))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_254_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 7U))); vlSymsp->TOP__dut__VexRiscv.__PVT__decodeExceptionPort_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (0U == (((0x17U == (0x5fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x18U) | (((0x6fU == (0x7fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x17U) | (((3U == (0x106fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x16U) | (((0x1073U == (0x107fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x15U) | (((0x2073U == (0x207fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x14U) | (((0x4063U == (0x407fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x13U) | (((0x2013U == (0x207fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x12U) | (((0x23U == (0x603fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x11U) | (((3U == (0x207fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0x10U) | (((3U == (0x505fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xfU) | (((0x63U == (0x707bU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xeU) | (((0xfU == (0x607fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xdU) | (((0x202fU == (0x1800707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xcU) | (((0x33U == (0xfc00007fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xbU) | (((0x800202fU == (0xe800707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 0xaU) | (((0x500fU == (0x1f0707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 9U) | (((0x5013U == (0xbc00707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 8U) | (((0x1013U == (0xfc00307fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 7U) | (((0x5033U == (0xbe00707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 6U) | (((0x33U == (0xbe00707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 5U) | (((0x1000202fU == (0xf9f0707fU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 4U) | (((0x12000073U == (0xfe007fffU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 3U) | (((0x10200073U == (0xdfffffffU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst)) << 2U) | (((0x10500073U == vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst) << 1U) | (0x73U == vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst))))))))))))))))))))))))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4468 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself = 0U; if (((((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1_)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_portId)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid)) & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 8U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4475 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_204_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_205_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_interrupt_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid; } if ((0U != ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL))) << 2U) | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL))) << 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL))))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:210 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending)); if ((1U & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = 1U; } if ((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_3_)))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_254_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_232_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decodeExceptionPort_valid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid)); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_ = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decodeExceptionPort_valid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodeExceptionPort_valid))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4454 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_ = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? 2U : 4U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_ = vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_payload; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) { vlSymsp->TOP__dut__VexRiscv.__PVT___zz_100_ = vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid = (0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) << 4U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid) << 2U) | ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid)))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_105_ = ( ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid) << 4U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__BranchPlugin_jumpInterface_valid) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_valid) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_redoBranch_valid))))); vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuck) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_haltItself)))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4727 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_0_halt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4502 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_redoFetch) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:6202 vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 0U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4491 vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_315_) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFlushed) { vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4694 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_corrected = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_corrected = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_105_) & (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_105_) - (IData)(1U)))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_322_ = (1U & ((~ (((3U == (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid)))) & (~ (((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck)))))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid)) | (~ (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck) | (((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (~ (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_119_ >> 1U))) & (3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U))))) | (((3U == (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferValid)) & (3U != (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen >> 0x10U)))))))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4621 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 0U; if ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode)))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_318_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 1U; } if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_319_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt = 1U; } vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFiring = (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_ = ( (4U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 2U)) | ((2U & ((0x7ffffffeU & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 1U)) | (0x3ffffffeU & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 2U)))) | (1U & (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 1U) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_106_) >> 3U))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_321_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready)); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt))); vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_output_valid = ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherHalt)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_booted)); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4634 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt = 0U; if ((0U != (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_arbitration_flushNext) << 3U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_flushNext) << 2U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_flushNext) << 1U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext)))))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt = 1U; } if (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isFiring))) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt = 1U; } // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:3337 vlSymsp->TOP__dut__VexRiscv.__PVT___zz_282_ = ( (4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_predictionJumpInterface_payload : ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_BRANCH_CALC) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_512_)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_jumpInterface_payload : vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_PC))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4967 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferFill = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_321_) { if (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_322_) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferFill = 1U; } } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_halt))); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4708 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg + ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc) << 2U)); if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_inc) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = (0xfffffffdU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc); } if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_jump_pcLoad_valid) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = vlSymsp->TOP__dut__VexRiscv.__PVT___zz_282_; } vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc = (0xfffffffeU & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pc); // ALWAYS at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:4701 vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pcRegPropagate = 0U; if (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) { vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetchPc_pcRegPropagate = 1U; } } VL_INLINE_OPT void Vdut_VexRiscv::_sequent__TOP__dut__VexRiscv__4(Vdut__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ Vdut_VexRiscv::_sequent__TOP__dut__VexRiscv__4\n"); ); Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body vlSymsp->TOP__dut__VexRiscv.__PVT___zz_249_ = ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface1_soc_bus_ack)); vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_)) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_249_) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_))))); vlSymsp->TOP__dut__VexRiscv.__PVT___zz_341_ = (1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready)))); } void Vdut_VexRiscv::_ctor_var_reset() { VL_DEBUG_IF(VL_DBG_MSGF("+ Vdut_VexRiscv::_ctor_var_reset\n"); ); // Body __PVT__externalResetVector = VL_RAND_RESET_I(32); __PVT__timerInterrupt = VL_RAND_RESET_I(1); __PVT__softwareInterrupt = VL_RAND_RESET_I(1); __PVT__externalInterruptArray = VL_RAND_RESET_I(32); __PVT__iBusWishbone_CYC = VL_RAND_RESET_I(1); __PVT__iBusWishbone_STB = VL_RAND_RESET_I(1); __PVT__iBusWishbone_ACK = VL_RAND_RESET_I(1); __PVT__iBusWishbone_WE = VL_RAND_RESET_I(1); __PVT__iBusWishbone_ADR = VL_RAND_RESET_I(30); __PVT__iBusWishbone_DAT_MISO = VL_RAND_RESET_I(32); __PVT__iBusWishbone_DAT_MOSI = VL_RAND_RESET_I(32); __PVT__iBusWishbone_SEL = VL_RAND_RESET_I(4); __PVT__iBusWishbone_ERR = VL_RAND_RESET_I(1); __PVT__iBusWishbone_BTE = VL_RAND_RESET_I(2); __PVT__iBusWishbone_CTI = VL_RAND_RESET_I(3); __PVT__dBusWishbone_CYC = VL_RAND_RESET_I(1); __PVT__dBusWishbone_STB = VL_RAND_RESET_I(1); __PVT__dBusWishbone_ACK = VL_RAND_RESET_I(1); __PVT__dBusWishbone_WE = VL_RAND_RESET_I(1); __PVT__dBusWishbone_ADR = VL_RAND_RESET_I(30); __PVT__dBusWishbone_DAT_MISO = VL_RAND_RESET_I(32); __PVT__dBusWishbone_DAT_MOSI = VL_RAND_RESET_I(32); __PVT__dBusWishbone_SEL = VL_RAND_RESET_I(4); __PVT__dBusWishbone_ERR = VL_RAND_RESET_I(1); __PVT__dBusWishbone_BTE = VL_RAND_RESET_I(2); __PVT__dBusWishbone_CTI = VL_RAND_RESET_I(3); __PVT__clk = VL_RAND_RESET_I(1); __PVT__reset = VL_RAND_RESET_I(1); __PVT___zz_254_ = VL_RAND_RESET_I(1); __PVT___zz_256_ = VL_RAND_RESET_I(1); __PVT___zz_259_ = VL_RAND_RESET_I(1); __PVT___zz_262_ = VL_RAND_RESET_I(1); __PVT___zz_263_ = VL_RAND_RESET_I(1); __PVT___zz_264_ = VL_RAND_RESET_I(32); __PVT___zz_265_ = VL_RAND_RESET_I(1); __PVT___zz_266_ = VL_RAND_RESET_I(32); __PVT___zz_267_ = VL_RAND_RESET_I(2); __PVT___zz_268_ = VL_RAND_RESET_I(1); __PVT___zz_269_ = VL_RAND_RESET_I(1); __PVT___zz_272_ = VL_RAND_RESET_I(1); __PVT___zz_275_ = VL_RAND_RESET_I(1); __PVT___zz_278_ = VL_RAND_RESET_I(1); __PVT___zz_282_ = VL_RAND_RESET_I(32); __PVT___zz_283_ = VL_RAND_RESET_I(1); __PVT___zz_284_ = VL_RAND_RESET_I(1); __PVT___zz_285_ = VL_RAND_RESET_I(1); __PVT___zz_286_ = VL_RAND_RESET_I(10); __PVT___zz_287_ = VL_RAND_RESET_I(10); __PVT___zz_288_ = VL_RAND_RESET_I(10); __PVT___zz_289_ = VL_RAND_RESET_I(10); __PVT___zz_290_ = VL_RAND_RESET_I(1); __PVT___zz_291_ = VL_RAND_RESET_I(1); __PVT___zz_292_ = VL_RAND_RESET_I(1); __PVT___zz_293_ = VL_RAND_RESET_I(1); __PVT___zz_294_ = VL_RAND_RESET_I(1); __PVT___zz_295_ = VL_RAND_RESET_I(1); __PVT___zz_296_ = VL_RAND_RESET_I(1); __PVT___zz_297_ = VL_RAND_RESET_I(10); __PVT___zz_298_ = VL_RAND_RESET_I(10); __PVT___zz_299_ = VL_RAND_RESET_I(10); __PVT___zz_300_ = VL_RAND_RESET_I(10); __PVT___zz_301_ = VL_RAND_RESET_I(1); __PVT___zz_302_ = VL_RAND_RESET_I(1); __PVT___zz_303_ = VL_RAND_RESET_I(1); __PVT___zz_304_ = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache_io_mem_cmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_cpu_writeBack_haltIt = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_cpu_writeBack_data = VL_RAND_RESET_I(32); __PVT__dataCache_1___05Fio_cpu_writeBack_mmuException = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_cpu_writeBack_accessError = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_cpu_flush_ready = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_cpu_redo = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_mem_cmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_mem_cmd_payload_wr = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_mem_cmd_payload_address = VL_RAND_RESET_I(32); __PVT__dataCache_1___05Fio_mem_cmd_payload_length = VL_RAND_RESET_I(3); __PVT__dataCache_1___05Fio_mem_cmd_payload_last = VL_RAND_RESET_I(1); __PVT___zz_305_ = VL_RAND_RESET_I(1); __PVT___zz_306_ = VL_RAND_RESET_I(1); __PVT___zz_308_ = VL_RAND_RESET_I(1); __PVT___zz_309_ = VL_RAND_RESET_I(1); __PVT___zz_310_ = VL_RAND_RESET_I(1); __PVT___zz_311_ = VL_RAND_RESET_I(1); __PVT___zz_312_ = VL_RAND_RESET_I(1); __PVT___zz_313_ = VL_RAND_RESET_I(1); __PVT___zz_314_ = VL_RAND_RESET_I(1); __PVT___zz_315_ = VL_RAND_RESET_I(1); __PVT___zz_316_ = VL_RAND_RESET_I(1); __PVT___zz_318_ = VL_RAND_RESET_I(1); __PVT___zz_319_ = VL_RAND_RESET_I(1); __PVT___zz_320_ = VL_RAND_RESET_I(2); __PVT___zz_321_ = VL_RAND_RESET_I(1); __PVT___zz_322_ = VL_RAND_RESET_I(1); __PVT___zz_324_ = VL_RAND_RESET_I(1); __PVT___zz_326_ = VL_RAND_RESET_I(1); __PVT___zz_327_ = VL_RAND_RESET_I(1); __PVT___zz_332_ = VL_RAND_RESET_I(1); __PVT___zz_334_ = VL_RAND_RESET_I(1); __PVT___zz_336_ = VL_RAND_RESET_I(1); __PVT___zz_337_ = VL_RAND_RESET_I(1); __PVT___zz_340_ = VL_RAND_RESET_I(1); __PVT___zz_341_ = VL_RAND_RESET_I(1); __PVT___zz_342_ = VL_RAND_RESET_I(1); __PVT___zz_343_ = VL_RAND_RESET_I(1); __PVT___zz_344_ = VL_RAND_RESET_I(1); __PVT___zz_345_ = VL_RAND_RESET_I(1); __PVT___zz_346_ = VL_RAND_RESET_I(1); __PVT___zz_347_ = VL_RAND_RESET_I(1); __PVT___zz_348_ = VL_RAND_RESET_I(1); __PVT___zz_349_ = VL_RAND_RESET_I(1); __PVT___zz_350_ = VL_RAND_RESET_I(1); __PVT___zz_351_ = VL_RAND_RESET_I(1); __PVT___zz_352_ = VL_RAND_RESET_I(1); __PVT___zz_353_ = VL_RAND_RESET_I(1); __PVT___zz_354_ = VL_RAND_RESET_I(1); __PVT___zz_355_ = VL_RAND_RESET_I(1); __PVT___zz_356_ = VL_RAND_RESET_I(1); __PVT___zz_357_ = VL_RAND_RESET_I(1); __PVT___zz_358_ = VL_RAND_RESET_I(1); __PVT___zz_359_ = VL_RAND_RESET_I(1); __PVT___zz_363_ = VL_RAND_RESET_I(5); __PVT___zz_454_ = VL_RAND_RESET_Q(33); __PVT___zz_459_ = VL_RAND_RESET_Q(33); __PVT___zz_512_ = VL_RAND_RESET_I(3); __PVT___zz_42_ = VL_RAND_RESET_I(32); __PVT__decode_RS2 = VL_RAND_RESET_I(32); __PVT__decode_RS1 = VL_RAND_RESET_I(32); __PVT___zz_43_ = VL_RAND_RESET_I(32); __PVT___zz_61_ = VL_RAND_RESET_I(1); __PVT__decode_REGFILE_WRITE_VALID = VL_RAND_RESET_I(1); __PVT__memory_IS_DBUS_SHARING = VL_RAND_RESET_I(1); __PVT___zz_93_ = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_rsp_issueDetected = VL_RAND_RESET_I(1); __PVT___zz_95_ = VL_RAND_RESET_I(1); __PVT___zz_96_ = VL_RAND_RESET_I(1); __PVT___zz_97_ = VL_RAND_RESET_I(1); __PVT___zz_99_ = VL_RAND_RESET_I(32); __PVT___zz_100_ = VL_RAND_RESET_I(32); __PVT__decode_arbitration_haltItself = VL_RAND_RESET_I(1); __PVT__decode_arbitration_haltByOther = VL_RAND_RESET_I(1); __PVT__decode_arbitration_removeIt = VL_RAND_RESET_I(1); __PVT__decode_arbitration_flushNext = VL_RAND_RESET_I(1); __PVT__decode_arbitration_isValid = VL_RAND_RESET_I(1); __PVT__decode_arbitration_isStuck = VL_RAND_RESET_I(1); __PVT__decode_arbitration_isFlushed = VL_RAND_RESET_I(1); __PVT__decode_arbitration_isFiring = VL_RAND_RESET_I(1); __PVT__execute_arbitration_haltItself = VL_RAND_RESET_I(1); __PVT__execute_arbitration_removeIt = VL_RAND_RESET_I(1); __PVT__execute_arbitration_flushNext = VL_RAND_RESET_I(1); __PVT__execute_arbitration_isValid = VL_RAND_RESET_I(1); __PVT__execute_arbitration_isStuck = VL_RAND_RESET_I(1); __PVT__execute_arbitration_isStuckByOthers = VL_RAND_RESET_I(1); __PVT__execute_arbitration_isFlushed = VL_RAND_RESET_I(1); __PVT__memory_arbitration_haltItself = VL_RAND_RESET_I(1); __PVT__memory_arbitration_removeIt = VL_RAND_RESET_I(1); __PVT__memory_arbitration_flushNext = VL_RAND_RESET_I(1); __PVT__memory_arbitration_isValid = VL_RAND_RESET_I(1); __PVT__memory_arbitration_isStuck = VL_RAND_RESET_I(1); __PVT__memory_arbitration_isFlushed = VL_RAND_RESET_I(1); __PVT__writeBack_arbitration_haltItself = VL_RAND_RESET_I(1); __PVT__writeBack_arbitration_removeIt = VL_RAND_RESET_I(1); __PVT__writeBack_arbitration_flushIt = VL_RAND_RESET_I(1); __PVT__writeBack_arbitration_flushNext = VL_RAND_RESET_I(1); __PVT__writeBack_arbitration_isValid = VL_RAND_RESET_I(1); __PVT__writeBack_arbitration_isFiring = VL_RAND_RESET_I(1); lastStageInstruction = VL_RAND_RESET_I(32); lastStagePc = VL_RAND_RESET_I(32); lastStageIsValid = VL_RAND_RESET_I(1); lastStageIsFiring = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_fetcherHalt = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_fetcherflushIt = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_incomingInstruction = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_predictionJumpInterface_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_predictionJumpInterface_payload = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_decodeExceptionPort_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_decodeExceptionPort_payload_code = VL_RAND_RESET_I(4); __PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_mmuBus_rsp_refilling = VL_RAND_RESET_I(1); __PVT__DBusCachedPlugin_mmuBus_cmd_bypassTranslation = VL_RAND_RESET_I(1); __PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress = VL_RAND_RESET_I(32); __PVT__DBusCachedPlugin_mmuBus_rsp_refilling = VL_RAND_RESET_I(1); __PVT__DBusCachedPlugin_redoBranch_valid = VL_RAND_RESET_I(1); __PVT__DBusCachedPlugin_exceptionBus_valid = VL_RAND_RESET_I(1); __PVT__DBusCachedPlugin_exceptionBus_payload_code = VL_RAND_RESET_I(4); __PVT__MmuPlugin_dBusAccess_cmd_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_dBusAccess_cmd_ready = VL_RAND_RESET_I(1); __PVT__MmuPlugin_dBusAccess_cmd_payload_address = VL_RAND_RESET_I(32); __PVT__MmuPlugin_dBusAccess_rsp_valid = VL_RAND_RESET_I(1); __PVT__decodeExceptionPort_valid = VL_RAND_RESET_I(1); __PVT__BranchPlugin_jumpInterface_valid = VL_RAND_RESET_I(1); __PVT__CsrPlugin_jumpInterface_valid = VL_RAND_RESET_I(1); __PVT__CsrPlugin_jumpInterface_payload = VL_RAND_RESET_I(32); __PVT__CsrPlugin_privilege = VL_RAND_RESET_I(2); __PVT__CsrPlugin_selfException_valid = VL_RAND_RESET_I(1); __PVT__CsrPlugin_selfException_payload_code = VL_RAND_RESET_I(4); __PVT__IBusCachedPlugin_jump_pcLoad_valid = VL_RAND_RESET_I(1); __PVT___zz_105_ = VL_RAND_RESET_I(5); __PVT___zz_106_ = VL_RAND_RESET_I(5); __PVT__IBusCachedPlugin_fetchPc_output_valid = VL_RAND_RESET_I(1); IBusCachedPlugin_fetchPc_pcReg = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_fetchPc_corrected = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_fetchPc_pcRegPropagate = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_fetchPc_booted = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_fetchPc_inc = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_fetchPc_pc = VL_RAND_RESET_I(32); IBusCachedPlugin_decodePc_pcReg = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_decodePc_pcPlus = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_iBusRsp_stages_0_halt = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_stages_1_output_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_stages_1_halt = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_stages_1_inputSample = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample = VL_RAND_RESET_I(1); __PVT___zz_116_ = VL_RAND_RESET_I(1); __PVT___zz_118_ = VL_RAND_RESET_I(1); __PVT___zz_119_ = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_iBusRsp_readyForError = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_output_ready = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_output_payload_rsp_error = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_iBusRsp_output_payload_isRvc = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_decompressor_decodeInput_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_error = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_decompressor_bufferValid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_decompressor_bufferData = VL_RAND_RESET_I(16); __PVT__IBusCachedPlugin_decompressor_rawInDecode = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_decompressor_decompressed = VL_RAND_RESET_I(32); __PVT___zz_123_ = VL_RAND_RESET_I(12); __PVT___zz_125_ = VL_RAND_RESET_I(12); __PVT___zz_127_ = VL_RAND_RESET_I(10); __PVT___zz_128_ = VL_RAND_RESET_I(21); __PVT___zz_130_ = VL_RAND_RESET_I(15); __PVT___zz_132_ = VL_RAND_RESET_I(3); __PVT___zz_134_ = VL_RAND_RESET_I(10); __PVT___zz_135_ = VL_RAND_RESET_I(21); __PVT___zz_137_ = VL_RAND_RESET_I(5); __PVT___zz_138_ = VL_RAND_RESET_I(13); __PVT___zz_146_ = VL_RAND_RESET_I(7); __PVT__IBusCachedPlugin_decompressor_bufferFill = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_injector_nextPcCalc_valids_0 = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_injector_nextPcCalc_valids_1 = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_injector_nextPcCalc_valids_2 = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_injector_nextPcCalc_valids_3 = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_injector_decodeRemoved = VL_RAND_RESET_I(1); __PVT___zz_148_ = VL_RAND_RESET_I(19); __PVT___zz_150_ = VL_RAND_RESET_I(11); __PVT___zz_152_ = VL_RAND_RESET_I(19); __PVT__iBus_rsp_valid = VL_RAND_RESET_I(1); __PVT___zz_153_ = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_rspCounter = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_s1_tightlyCoupledHit = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_s2_tightlyCoupledHit = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_rsp_redoFetch = VL_RAND_RESET_I(1); __PVT__dBus_rsp_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready = VL_RAND_RESET_I(1); __PVT___zz_154_ = VL_RAND_RESET_I(1); __PVT___zz_155_ = VL_RAND_RESET_I(1); __PVT___zz_156_ = VL_RAND_RESET_I(32); __PVT___zz_157_ = VL_RAND_RESET_I(32); __PVT___zz_158_ = VL_RAND_RESET_I(4); __PVT___zz_159_ = VL_RAND_RESET_I(3); __PVT___zz_160_ = VL_RAND_RESET_I(1); __PVT___zz_161_ = VL_RAND_RESET_I(1); __PVT___zz_162_ = VL_RAND_RESET_I(1); __PVT___zz_163_ = VL_RAND_RESET_I(32); __PVT___zz_164_ = VL_RAND_RESET_I(32); __PVT___zz_165_ = VL_RAND_RESET_I(4); __PVT___zz_166_ = VL_RAND_RESET_I(3); __PVT___zz_167_ = VL_RAND_RESET_I(1); __PVT___zz_168_ = VL_RAND_RESET_I(32); __PVT__DBusCachedPlugin_rspCounter = VL_RAND_RESET_I(32); __PVT__writeBack_DBusCachedPlugin_rspShifted = VL_RAND_RESET_I(32); __PVT___zz_170_ = VL_RAND_RESET_I(1); __PVT___zz_171_ = VL_RAND_RESET_I(32); __PVT___zz_172_ = VL_RAND_RESET_I(1); __PVT___zz_173_ = VL_RAND_RESET_I(32); __PVT__DBusCachedPlugin_forceDatapath = VL_RAND_RESET_I(1); __PVT__MmuPlugin_status_sum = VL_RAND_RESET_I(1); __PVT__MmuPlugin_status_mxr = VL_RAND_RESET_I(1); __PVT__MmuPlugin_status_mprv = VL_RAND_RESET_I(1); __PVT__MmuPlugin_satp_mode = VL_RAND_RESET_I(1); __PVT__MmuPlugin_satp_ppn = VL_RAND_RESET_I(20); __PVT__MmuPlugin_ports_0_cache_0_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_0_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_0_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_0_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_0_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_0_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_0_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_0_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_0_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_0_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_0_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_1_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_1_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_1_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_1_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_1_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_2_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_2_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_2_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_2_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_2_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_3_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_3_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_3_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_0_cache_3_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cache_3_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cacheHits_1 = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cacheHits_2 = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cacheHits_3 = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_cacheHit = VL_RAND_RESET_I(1); __PVT___zz_176_ = VL_RAND_RESET_I(2); __PVT__MmuPlugin_ports_0_entryToReplace_willIncrement = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_0_entryToReplace_valueNext = VL_RAND_RESET_I(2); __PVT__MmuPlugin_ports_0_entryToReplace_value = VL_RAND_RESET_I(2); __PVT__MmuPlugin_ports_0_requireMmuLockup = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_0_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_0_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_0_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_0_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_1_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_1_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_1_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_1_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_1_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_2_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_2_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_2_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_2_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_2_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_valid = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_superPage = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_virtualAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_3_virtualAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_3_physicalAddress_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_3_physicalAddress_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_ports_1_cache_3_allowRead = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_allowWrite = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_allowExecute = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cache_3_allowUser = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cacheHits_1 = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cacheHits_2 = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cacheHits_3 = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_cacheHit = VL_RAND_RESET_I(1); __PVT___zz_179_ = VL_RAND_RESET_I(2); __PVT__MmuPlugin_ports_1_entryToReplace_willIncrement = VL_RAND_RESET_I(1); __PVT__MmuPlugin_ports_1_entryToReplace_valueNext = VL_RAND_RESET_I(2); __PVT__MmuPlugin_ports_1_entryToReplace_value = VL_RAND_RESET_I(2); __PVT__MmuPlugin_ports_1_requireMmuLockup = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_state_1_ = VL_RAND_RESET_I(3); __PVT__MmuPlugin_shared_vpn_0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_shared_vpn_1 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_shared_portId = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_dBusRsp_exception = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_dBusRsp_leaf = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_V = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_R = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_W = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_X = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_U = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_G = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_A = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_D = VL_RAND_RESET_I(1); __PVT__MmuPlugin_shared_pteBuffer_RSW = VL_RAND_RESET_I(2); __PVT__MmuPlugin_shared_pteBuffer_PPN0 = VL_RAND_RESET_I(10); __PVT__MmuPlugin_shared_pteBuffer_PPN1 = VL_RAND_RESET_I(12); __PVT___zz_180_ = VL_RAND_RESET_Q(35); lastStageRegFileWrite_valid = VL_RAND_RESET_I(1); lastStageRegFileWrite_payload_address = VL_RAND_RESET_I(5); lastStageRegFileWrite_payload_data = VL_RAND_RESET_I(32); __PVT___zz_194_ = VL_RAND_RESET_I(1); __PVT___zz_196_ = VL_RAND_RESET_I(32); __PVT___zz_198_ = VL_RAND_RESET_I(20); __PVT___zz_200_ = VL_RAND_RESET_I(20); __PVT___zz_201_ = VL_RAND_RESET_I(32); __PVT__execute_SrcPlugin_addSub = VL_RAND_RESET_I(32); __PVT__execute_SrcPlugin_less = VL_RAND_RESET_I(1); __PVT___zz_202_ = VL_RAND_RESET_I(32); __PVT__execute_FullBarrelShifterPlugin_reversed = VL_RAND_RESET_I(32); __PVT___zz_203_ = VL_RAND_RESET_I(32); __PVT___zz_204_ = VL_RAND_RESET_I(1); __PVT___zz_205_ = VL_RAND_RESET_I(1); __PVT___zz_206_ = VL_RAND_RESET_I(1); __PVT___zz_207_ = VL_RAND_RESET_I(1); __PVT___zz_208_ = VL_RAND_RESET_I(5); __PVT___zz_209_ = VL_RAND_RESET_I(32); __PVT___zz_212_ = VL_RAND_RESET_I(1); __PVT___zz_213_ = VL_RAND_RESET_I(1); __PVT___zz_214_ = VL_RAND_RESET_I(1); __PVT___zz_215_ = VL_RAND_RESET_I(1); __PVT__execute_BranchPlugin_eq = VL_RAND_RESET_I(1); __PVT__execute_BranchPlugin_branch_src2 = VL_RAND_RESET_I(32); __PVT___zz_220_ = VL_RAND_RESET_I(20); __PVT___zz_222_ = VL_RAND_RESET_I(11); __PVT___zz_224_ = VL_RAND_RESET_I(19); __PVT___zz_225_ = VL_RAND_RESET_I(2); __PVT__CsrPlugin_mtvec_mode = VL_RAND_RESET_I(2); __PVT__CsrPlugin_mtvec_base = VL_RAND_RESET_I(30); __PVT__CsrPlugin_mepc = VL_RAND_RESET_I(32); __PVT__CsrPlugin_mstatus_MIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mstatus_MPIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mstatus_MPP = VL_RAND_RESET_I(2); __PVT__CsrPlugin_mip_MEIP = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mip_MTIP = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mip_MSIP = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mie_MEIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mie_MTIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mie_MSIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mscratch = VL_RAND_RESET_I(32); __PVT__CsrPlugin_mcause_interrupt = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mcause_exceptionCode = VL_RAND_RESET_I(4); __PVT__CsrPlugin_mtval = VL_RAND_RESET_I(32); __PVT__CsrPlugin_mcycle = VL_RAND_RESET_Q(64); __PVT__CsrPlugin_minstret = VL_RAND_RESET_Q(64); __PVT__CsrPlugin_medeleg_IAM = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_IAF = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_II = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_LAM = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_LAF = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_SAM = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_SAF = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_EU = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_ES = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_IPF = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_LPF = VL_RAND_RESET_I(1); __PVT__CsrPlugin_medeleg_SPF = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mideleg_ST = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mideleg_SE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_mideleg_SS = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sstatus_SIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sstatus_SPIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sstatus_SPP = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sip_SEIP_SOFT = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sip_SEIP_INPUT = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sip_SEIP_OR = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sip_STIP = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sip_SSIP = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sie_SEIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sie_STIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_sie_SSIE = VL_RAND_RESET_I(1); __PVT__CsrPlugin_stvec_mode = VL_RAND_RESET_I(2); __PVT__CsrPlugin_stvec_base = VL_RAND_RESET_I(30); __PVT__CsrPlugin_sscratch = VL_RAND_RESET_I(32); __PVT__CsrPlugin_scause_interrupt = VL_RAND_RESET_I(1); __PVT__CsrPlugin_scause_exceptionCode = VL_RAND_RESET_I(4); __PVT__CsrPlugin_stval = VL_RAND_RESET_I(32); __PVT__CsrPlugin_sepc = VL_RAND_RESET_I(32); __PVT__CsrPlugin_satp_PPN = VL_RAND_RESET_I(22); __PVT__CsrPlugin_satp_ASID = VL_RAND_RESET_I(9); __PVT__CsrPlugin_satp_MODE = VL_RAND_RESET_I(1); __PVT___zz_226_ = VL_RAND_RESET_I(1); __PVT___zz_227_ = VL_RAND_RESET_I(1); __PVT___zz_228_ = VL_RAND_RESET_I(1); __PVT___zz_229_ = VL_RAND_RESET_I(1); __PVT___zz_230_ = VL_RAND_RESET_I(1); __PVT___zz_231_ = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack = VL_RAND_RESET_I(1); __PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_code = VL_RAND_RESET_I(4); __PVT__CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr = VL_RAND_RESET_I(32); __PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = VL_RAND_RESET_I(2); __PVT___zz_232_ = VL_RAND_RESET_I(2); __PVT__CsrPlugin_interrupt_valid = VL_RAND_RESET_I(1); CsrPlugin_interrupt_code = VL_RAND_RESET_I(4); __PVT__CsrPlugin_interrupt_targetPrivilege = VL_RAND_RESET_I(2); __PVT__CsrPlugin_lastStageWasWfi = VL_RAND_RESET_I(1); __PVT__CsrPlugin_pipelineLiberator_done = VL_RAND_RESET_I(1); CsrPlugin_interruptJump = VL_RAND_RESET_I(1); __PVT__CsrPlugin_hadException = VL_RAND_RESET_I(1); __PVT__CsrPlugin_targetPrivilege = VL_RAND_RESET_I(2); __PVT__CsrPlugin_trapCause = VL_RAND_RESET_I(4); __PVT__CsrPlugin_xtvec_mode = VL_RAND_RESET_I(2); __PVT__CsrPlugin_xtvec_base = VL_RAND_RESET_I(30); execute_CsrPlugin_inWfi = VL_RAND_RESET_I(1); __PVT__execute_CsrPlugin_wfiWake = VL_RAND_RESET_I(1); __PVT__execute_CsrPlugin_blockedBySideEffects = VL_RAND_RESET_I(1); __PVT__execute_CsrPlugin_illegalAccess = VL_RAND_RESET_I(1); __PVT__execute_CsrPlugin_illegalInstruction = VL_RAND_RESET_I(1); __PVT__execute_CsrPlugin_readData = VL_RAND_RESET_I(32); __PVT__execute_CsrPlugin_writeEnable = VL_RAND_RESET_I(1); __PVT__execute_CsrPlugin_readToWriteData = VL_RAND_RESET_I(32); __PVT__execute_CsrPlugin_writeData = VL_RAND_RESET_I(32); __PVT__execute_MulPlugin_aHigh = VL_RAND_RESET_I(17); __PVT__execute_MulPlugin_bHigh = VL_RAND_RESET_I(17); __PVT__memory_DivPlugin_rs1 = VL_RAND_RESET_Q(33); __PVT__memory_DivPlugin_rs2 = VL_RAND_RESET_I(32); VL_RAND_RESET_W(65,__PVT__memory_DivPlugin_accumulator); __PVT__memory_DivPlugin_div_needRevert = VL_RAND_RESET_I(1); __PVT__memory_DivPlugin_div_counter_willIncrement = VL_RAND_RESET_I(1); __PVT__memory_DivPlugin_div_counter_willClear = VL_RAND_RESET_I(1); __PVT__memory_DivPlugin_div_counter_valueNext = VL_RAND_RESET_I(6); __PVT__memory_DivPlugin_div_counter_value = VL_RAND_RESET_I(6); __PVT__memory_DivPlugin_div_done = VL_RAND_RESET_I(1); __PVT__memory_DivPlugin_div_result = VL_RAND_RESET_I(32); __PVT___zz_235_ = VL_RAND_RESET_Q(33); __PVT___zz_236_ = VL_RAND_RESET_Q(33); __PVT___zz_237_ = VL_RAND_RESET_I(32); __PVT___zz_238_ = VL_RAND_RESET_I(1); __PVT___zz_239_ = VL_RAND_RESET_I(1); __PVT___zz_240_ = VL_RAND_RESET_Q(33); __PVT__externalInterruptArray_regNext = VL_RAND_RESET_I(32); __PVT___zz_241_ = VL_RAND_RESET_I(32); __PVT___zz_242_ = VL_RAND_RESET_I(32); __PVT___zz_243_ = VL_RAND_RESET_I(32); __PVT___zz_244_ = VL_RAND_RESET_I(32); __PVT__decode_to_execute_PREDICTION_HAD_BRANCHED2 = VL_RAND_RESET_I(1); __PVT__decode_to_execute_MEMORY_LRSC = VL_RAND_RESET_I(1); __PVT__decode_to_execute_BYPASSABLE_EXECUTE_STAGE = VL_RAND_RESET_I(1); __PVT__decode_to_execute_CSR_WRITE_OPCODE = VL_RAND_RESET_I(1); __PVT__execute_to_memory_SHIFT_RIGHT = VL_RAND_RESET_I(32); __PVT__decode_to_execute_IS_CSR = VL_RAND_RESET_I(1); __PVT__decode_to_execute_IS_RVC = VL_RAND_RESET_I(1); __PVT__decode_to_execute_SHIFT_CTRL = VL_RAND_RESET_I(2); __PVT__execute_to_memory_SHIFT_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_SRC1_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_IS_RS2_SIGNED = VL_RAND_RESET_I(1); __PVT__decode_to_execute_SRC2_FORCE_ZERO = VL_RAND_RESET_I(1); __PVT__decode_to_execute_REGFILE_WRITE_VALID = VL_RAND_RESET_I(1); __PVT__execute_to_memory_REGFILE_WRITE_VALID = VL_RAND_RESET_I(1); __PVT__memory_to_writeBack_REGFILE_WRITE_VALID = VL_RAND_RESET_I(1); __PVT__decode_to_execute_MEMORY_WR = VL_RAND_RESET_I(1); __PVT__execute_to_memory_MEMORY_WR = VL_RAND_RESET_I(1); __PVT__memory_to_writeBack_MEMORY_WR = VL_RAND_RESET_I(1); __PVT__decode_to_execute_IS_SFENCE_VMA = VL_RAND_RESET_I(1); __PVT__execute_to_memory_IS_SFENCE_VMA = VL_RAND_RESET_I(1); __PVT__memory_to_writeBack_IS_SFENCE_VMA = VL_RAND_RESET_I(1); __PVT__decode_to_execute_BRANCH_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_RS2 = VL_RAND_RESET_I(32); __PVT__execute_to_memory_MEMORY_ADDRESS_LOW = VL_RAND_RESET_I(2); __PVT__memory_to_writeBack_MEMORY_ADDRESS_LOW = VL_RAND_RESET_I(2); __PVT__execute_to_memory_MUL_HL = VL_RAND_RESET_Q(34); __PVT__decode_to_execute_FORMAL_PC_NEXT = VL_RAND_RESET_I(32); __PVT__execute_to_memory_FORMAL_PC_NEXT = VL_RAND_RESET_I(32); __PVT__memory_to_writeBack_FORMAL_PC_NEXT = VL_RAND_RESET_I(32); __PVT__decode_to_execute_SRC_USE_SUB_LESS = VL_RAND_RESET_I(1); __PVT__decode_to_execute_MEMORY_ENABLE = VL_RAND_RESET_I(1); __PVT__execute_to_memory_MEMORY_ENABLE = VL_RAND_RESET_I(1); __PVT__memory_to_writeBack_MEMORY_ENABLE = VL_RAND_RESET_I(1); __PVT__decode_to_execute_IS_RS1_SIGNED = VL_RAND_RESET_I(1); __PVT__execute_to_memory_MUL_LL = VL_RAND_RESET_I(32); __PVT__decode_to_execute_IS_MUL = VL_RAND_RESET_I(1); __PVT__execute_to_memory_IS_MUL = VL_RAND_RESET_I(1); __PVT__memory_to_writeBack_IS_MUL = VL_RAND_RESET_I(1); __PVT__decode_to_execute_BYPASSABLE_MEMORY_STAGE = VL_RAND_RESET_I(1); __PVT__execute_to_memory_BYPASSABLE_MEMORY_STAGE = VL_RAND_RESET_I(1); __PVT__execute_to_memory_REGFILE_WRITE_DATA = VL_RAND_RESET_I(32); __PVT__memory_to_writeBack_REGFILE_WRITE_DATA = VL_RAND_RESET_I(32); __PVT__decode_to_execute_RS1 = VL_RAND_RESET_I(32); __PVT__decode_to_execute_CSR_READ_OPCODE = VL_RAND_RESET_I(1); __PVT__execute_to_memory_IS_DBUS_SHARING = VL_RAND_RESET_I(1); __PVT__memory_to_writeBack_IS_DBUS_SHARING = VL_RAND_RESET_I(1); __PVT__decode_to_execute_SRC2_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_INSTRUCTION = VL_RAND_RESET_I(32); __PVT__execute_to_memory_INSTRUCTION = VL_RAND_RESET_I(32); __PVT__memory_to_writeBack_INSTRUCTION = VL_RAND_RESET_I(32); __PVT__execute_to_memory_BRANCH_CALC = VL_RAND_RESET_I(32); __PVT__memory_to_writeBack_MUL_LOW = VL_RAND_RESET_Q(52); __PVT__execute_to_memory_BRANCH_DO = VL_RAND_RESET_I(1); __PVT__decode_to_execute_MEMORY_AMO = VL_RAND_RESET_I(1); __PVT__execute_to_memory_MUL_HH = VL_RAND_RESET_Q(34); __PVT__memory_to_writeBack_MUL_HH = VL_RAND_RESET_Q(34); __PVT__decode_to_execute_SRC_LESS_UNSIGNED = VL_RAND_RESET_I(1); __PVT__decode_to_execute_PC = VL_RAND_RESET_I(32); __PVT__execute_to_memory_PC = VL_RAND_RESET_I(32); __PVT__memory_to_writeBack_PC = VL_RAND_RESET_I(32); __PVT__decode_to_execute_ENV_CTRL = VL_RAND_RESET_I(2); __PVT__execute_to_memory_ENV_CTRL = VL_RAND_RESET_I(2); __PVT__memory_to_writeBack_ENV_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_MEMORY_MANAGMENT = VL_RAND_RESET_I(1); __PVT__decode_to_execute_ALU_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_ALU_BITWISE_CTRL = VL_RAND_RESET_I(2); __PVT__decode_to_execute_IS_DIV = VL_RAND_RESET_I(1); __PVT__execute_to_memory_IS_DIV = VL_RAND_RESET_I(1); __PVT__execute_to_memory_MUL_LH = VL_RAND_RESET_Q(34); __PVT___zz_245_ = VL_RAND_RESET_I(3); __PVT___zz_246_ = VL_RAND_RESET_I(1); __PVT__iBusWishbone_DAT_MISO_regNext = VL_RAND_RESET_I(32); __PVT___zz_247_ = VL_RAND_RESET_I(3); __PVT___zz_248_ = VL_RAND_RESET_I(1); __PVT___zz_249_ = VL_RAND_RESET_I(1); __PVT___zz_251_ = VL_RAND_RESET_I(1); __PVT___zz_253_ = VL_RAND_RESET_I(1); __PVT__dBusWishbone_DAT_MISO_regNext = VL_RAND_RESET_I(32); VL_RAND_RESET_W(96,__PVT__decode_SRC1_CTRL_string); VL_RAND_RESET_W(72,__PVT__decode_SHIFT_CTRL_string); VL_RAND_RESET_W(72,__PVT__memory_SHIFT_CTRL_string); VL_RAND_RESET_W(72,__PVT__execute_SHIFT_CTRL_string); VL_RAND_RESET_W(96,__PVT__execute_SRC1_CTRL_string); __PVT__MmuPlugin_shared_state_1___05Fstring = VL_RAND_RESET_Q(48); VL_RAND_RESET_W(72,__PVT__decode_to_execute_SHIFT_CTRL_string); VL_RAND_RESET_W(72,__PVT__execute_to_memory_SHIFT_CTRL_string); VL_RAND_RESET_W(96,__PVT__decode_to_execute_SRC1_CTRL_string); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { RegFilePlugin_regFile[__Vi0] = VL_RAND_RESET_I(32); }} __PVT__IBusCachedPlugin_cache__DOT___zz_10_ = VL_RAND_RESET_I(22); __PVT__IBusCachedPlugin_cache__DOT___zz_11_ = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_cache__DOT___zz_12_ = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT___zz_13_ = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT___zz_1_ = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT___zz_2_ = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_address = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_hadError = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter = VL_RAND_RESET_I(8); __PVT__IBusCachedPlugin_cache__DOT___zz_3_ = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_wayToAllocate_willIncrement = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex = VL_RAND_RESET_I(3); __PVT__IBusCachedPlugin_cache__DOT__io_cpu_fetch_data_regNextWhen = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_physicalAddress = VL_RAND_RESET_I(32); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_isIoAccess = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowRead = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowWrite = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowExecute = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_exception = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_refilling = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_valid = VL_RAND_RESET_I(1); __PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_error = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { __PVT__IBusCachedPlugin_cache__DOT__ways_0_tags[__Vi0] = VL_RAND_RESET_I(22); }} { int __Vi0=0; for (; __Vi0<1024; ++__Vi0) { __PVT__IBusCachedPlugin_cache__DOT__ways_0_datas[__Vi0] = VL_RAND_RESET_I(32); }} __PVT__dataCache_1___DOT___zz_10_ = VL_RAND_RESET_I(22); __PVT__dataCache_1___DOT___zz_12_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_13_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_14_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_16_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_17_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_18_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_19_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_20_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_21_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_22_ = VL_RAND_RESET_I(3); __PVT__dataCache_1___DOT___zz_25_ = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT___zz_36_ = VL_RAND_RESET_I(2); __PVT__dataCache_1___DOT___zz_1_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT___zz_2_ = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsReadCmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsReadCmd_payload = VL_RAND_RESET_I(7); __PVT__dataCache_1___DOT__tagsWriteCmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteCmd_payload_way = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteCmd_payload_address = VL_RAND_RESET_I(7); __PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address = VL_RAND_RESET_I(20); __PVT__dataCache_1___DOT__tagsWriteLastCmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_way = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_address = VL_RAND_RESET_I(7); __PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_error = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_address = VL_RAND_RESET_I(20); __PVT__dataCache_1___DOT__dataReadCmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__dataReadCmd_payload = VL_RAND_RESET_I(10); __PVT__dataCache_1___DOT__dataWriteCmd_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__dataWriteCmd_payload_way = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__dataWriteCmd_payload_address = VL_RAND_RESET_I(10); __PVT__dataCache_1___DOT__dataWriteCmd_payload_data = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__dataWriteCmd_payload_mask = VL_RAND_RESET_I(4); __PVT__dataCache_1___DOT__stage0_mask = VL_RAND_RESET_I(4); __PVT__dataCache_1___DOT__stageA_request_wr = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageA_request_data = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__stageA_request_size = VL_RAND_RESET_I(2); __PVT__dataCache_1___DOT__stageA_request_isLrsc = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageA_request_isAmo = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageA_request_amoCtrl_swap = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageA_request_amoCtrl_alu = VL_RAND_RESET_I(3); __PVT__dataCache_1___DOT__stageA_mask = VL_RAND_RESET_I(4); __PVT__dataCache_1___DOT__stage0_colisions_regNextWhen = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_request_wr = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_request_data = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__stageB_request_size = VL_RAND_RESET_I(2); __PVT__dataCache_1___DOT__stageB_request_isLrsc = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_isAmo = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu = VL_RAND_RESET_I(3); __PVT__dataCache_1___DOT__stageB_mmuRspFreeze = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mmuRsp_allowRead = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mmuRsp_allowWrite = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mmuRsp_allowExecute = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mmuRsp_exception = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mmuRsp_refilling = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_error = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_address = VL_RAND_RESET_I(20); __PVT__dataCache_1___DOT__stageB_dataReadRsp_0 = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__stageB_waysHits = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_mask = VL_RAND_RESET_I(4); __PVT__dataCache_1___DOT__stageB_colisions = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_loaderValid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_flusher_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_lrsc_reserved = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_requestDataBypass = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__stageB_amo_resultRegValid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__stageB_amo_resultReg = VL_RAND_RESET_I(32); __PVT__dataCache_1___DOT__stageB_memCmdSent = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__loader_valid = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__loader_counter_willIncrement = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__loader_counter_valueNext = VL_RAND_RESET_I(3); __PVT__dataCache_1___DOT__loader_counter_value = VL_RAND_RESET_I(3); __PVT__dataCache_1___DOT__loader_counter_willOverflow = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__loader_waysAllocator = VL_RAND_RESET_I(1); __PVT__dataCache_1___DOT__loader_error = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { __PVT__dataCache_1___DOT__ways_0_tags[__Vi0] = VL_RAND_RESET_I(22); }} { int __Vi0=0; for (; __Vi0<1024; ++__Vi0) { __PVT__dataCache_1___DOT__ways_0_data_symbol0[__Vi0] = VL_RAND_RESET_I(8); }} { int __Vi0=0; for (; __Vi0<1024; ++__Vi0) { __PVT__dataCache_1___DOT__ways_0_data_symbol1[__Vi0] = VL_RAND_RESET_I(8); }} { int __Vi0=0; for (; __Vi0<1024; ++__Vi0) { __PVT__dataCache_1___DOT__ways_0_data_symbol2[__Vi0] = VL_RAND_RESET_I(8); }} { int __Vi0=0; for (; __Vi0<1024; ++__Vi0) { __PVT__dataCache_1___DOT__ways_0_data_symbol3[__Vi0] = VL_RAND_RESET_I(8); }} __PVT__dataCache_1___DOT___zz_38_ = VL_RAND_RESET_I(8); __PVT__dataCache_1___DOT___zz_39_ = VL_RAND_RESET_I(8); __PVT__dataCache_1___DOT___zz_40_ = VL_RAND_RESET_I(8); __PVT__dataCache_1___DOT___zz_41_ = VL_RAND_RESET_I(8); __Vtableidx1 = VL_RAND_RESET_I(2); VL_CONST_W_3X(96,__Vtable1___PVT__decode_SRC1_CTRL_string[0],0x52532020,0x20202020,0x20202020); VL_CONST_W_3X(96,__Vtable1___PVT__decode_SRC1_CTRL_string[1],0x494d5520,0x20202020,0x20202020); VL_CONST_W_3X(96,__Vtable1___PVT__decode_SRC1_CTRL_string[2],0x50435f49,0x4e435245,0x4d454e54); VL_CONST_W_3X(96,__Vtable1___PVT__decode_SRC1_CTRL_string[3],0x55525331,0x20202020,0x20202020); __Vtableidx7 = VL_RAND_RESET_I(2); VL_CONST_W_3X(72,__Vtable7___PVT__decode_SHIFT_CTRL_string[0],0x00000044,0x49534142,0x4c455f31); VL_CONST_W_3X(72,__Vtable7___PVT__decode_SHIFT_CTRL_string[1],0x00000053,0x4c4c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable7___PVT__decode_SHIFT_CTRL_string[2],0x00000053,0x524c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable7___PVT__decode_SHIFT_CTRL_string[3],0x00000053,0x52415f31,0x20202020); __Vtableidx11 = VL_RAND_RESET_I(2); VL_CONST_W_3X(72,__Vtable11___PVT__memory_SHIFT_CTRL_string[0],0x00000044,0x49534142,0x4c455f31); VL_CONST_W_3X(72,__Vtable11___PVT__memory_SHIFT_CTRL_string[1],0x00000053,0x4c4c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable11___PVT__memory_SHIFT_CTRL_string[2],0x00000053,0x524c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable11___PVT__memory_SHIFT_CTRL_string[3],0x00000053,0x52415f31,0x20202020); __Vtableidx13 = VL_RAND_RESET_I(2); VL_CONST_W_3X(72,__Vtable13___PVT__execute_SHIFT_CTRL_string[0],0x00000044,0x49534142,0x4c455f31); VL_CONST_W_3X(72,__Vtable13___PVT__execute_SHIFT_CTRL_string[1],0x00000053,0x4c4c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable13___PVT__execute_SHIFT_CTRL_string[2],0x00000053,0x524c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable13___PVT__execute_SHIFT_CTRL_string[3],0x00000053,0x52415f31,0x20202020); __Vtableidx15 = VL_RAND_RESET_I(2); VL_CONST_W_3X(96,__Vtable15___PVT__execute_SRC1_CTRL_string[0],0x52532020,0x20202020,0x20202020); VL_CONST_W_3X(96,__Vtable15___PVT__execute_SRC1_CTRL_string[1],0x494d5520,0x20202020,0x20202020); VL_CONST_W_3X(96,__Vtable15___PVT__execute_SRC1_CTRL_string[2],0x50435f49,0x4e435245,0x4d454e54); VL_CONST_W_3X(96,__Vtable15___PVT__execute_SRC1_CTRL_string[3],0x55525331,0x20202020,0x20202020); __Vtableidx19 = VL_RAND_RESET_I(3); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[0] = VL_ULL(0x49444c452020); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[1] = VL_ULL(0x4c315f434d44); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[2] = VL_ULL(0x4c315f525350); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[3] = VL_ULL(0x4c305f434d44); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[4] = VL_ULL(0x4c305f525350); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[5] = VL_ULL(0x3f3f3f3f3f3f); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[6] = VL_ULL(0x3f3f3f3f3f3f); __Vtable19___PVT__MmuPlugin_shared_state_1___05Fstring[7] = VL_ULL(0x3f3f3f3f3f3f); __Vtableidx22 = VL_RAND_RESET_I(2); VL_CONST_W_3X(72,__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string[0],0x00000044,0x49534142,0x4c455f31); VL_CONST_W_3X(72,__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string[1],0x00000053,0x4c4c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string[2],0x00000053,0x524c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable22___PVT__decode_to_execute_SHIFT_CTRL_string[3],0x00000053,0x52415f31,0x20202020); __Vtableidx23 = VL_RAND_RESET_I(2); VL_CONST_W_3X(72,__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string[0],0x00000044,0x49534142,0x4c455f31); VL_CONST_W_3X(72,__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string[1],0x00000053,0x4c4c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string[2],0x00000053,0x524c5f31,0x20202020); VL_CONST_W_3X(72,__Vtable23___PVT__execute_to_memory_SHIFT_CTRL_string[3],0x00000053,0x52415f31,0x20202020); __Vtableidx24 = VL_RAND_RESET_I(2); VL_CONST_W_3X(96,__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string[0],0x52532020,0x20202020,0x20202020); VL_CONST_W_3X(96,__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string[1],0x494d5520,0x20202020,0x20202020); VL_CONST_W_3X(96,__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string[2],0x50435f49,0x4e435245,0x4d454e54); VL_CONST_W_3X(96,__Vtable24___PVT__decode_to_execute_SRC1_CTRL_string[3],0x55525331,0x20202020,0x20202020); __Vtableidx25 = VL_RAND_RESET_I(3); __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[0] = 0U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[1] = 1U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[2] = 0U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[3] = 1U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[4] = 0U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[5] = 0U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[6] = 0U; __Vtable25___PVT__MmuPlugin_dBusAccess_cmd_valid[7] = 0U; }