// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Tracing implementation internals #include "verilated_vcd_c.h" #include "Vdut__Syms.h" //====================== void Vdut::trace (VerilatedVcdC* tfp, int, int) { tfp->spTrace()->addCallback (&Vdut::traceInit, &Vdut::traceFull, &Vdut::traceChg, this); } void Vdut::traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code) { // Callback from vcd->open() Vdut* t=(Vdut*)userthis; Vdut__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table if (!Verilated::calcUnusedSigs()) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); vcdp->scopeEscape(' '); t->traceInitThis (vlSymsp, vcdp, code); vcdp->scopeEscape('.'); } void Vdut::traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code) { // Callback from vcd->dump() Vdut* t=(Vdut*)userthis; Vdut__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table t->traceFullThis (vlSymsp, vcdp, code); } //====================== void Vdut::traceInitThis(Vdut__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; int c=code; if (0 && vcdp && c) {} // Prevent unused vcdp->module(vlSymsp->name()); // Setup signal names // Body { vlTOPp->traceInitThis__1(vlSymsp, vcdp, code); } } void Vdut::traceFullThis(Vdut__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; int c=code; if (0 && vcdp && c) {} // Prevent unused // Body { vlTOPp->traceFullThis__1(vlSymsp, vcdp, code); } // Final vlTOPp->__Vm_traceActivity = 0U; } void Vdut::traceInitThis__1(Vdut__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; int c=code; if (0 && vcdp && c) {} // Prevent unused // Body { vcdp->declBit (c+1071,"sys_clk",-1); vcdp->declBit (c+1072,"serial_source_valid",-1); vcdp->declBit (c+1073,"serial_source_ready",-1); vcdp->declBus (c+1074,"serial_source_data",-1,7,0); vcdp->declBit (c+1075,"serial_sink_valid",-1); vcdp->declBit (c+1076,"serial_sink_ready",-1); vcdp->declBus (c+1077,"serial_sink_data",-1,7,0); vcdp->declBit (c+1071,"dut sys_clk",-1); vcdp->declBit (c+2,"dut serial_source_valid",-1); vcdp->declBit (c+1073,"dut serial_source_ready",-1); vcdp->declBus (c+3,"dut serial_source_data",-1,7,0); vcdp->declBit (c+1075,"dut serial_sink_valid",-1); vcdp->declBit (c+4,"dut serial_sink_ready",-1); vcdp->declBus (c+1077,"dut serial_sink_data",-1,7,0); vcdp->declBit (c+5,"dut main_soclinux_ctrl_reset_reset_re",-1); vcdp->declBit (c+6,"dut main_soclinux_ctrl_reset_reset_r",-1); vcdp->declBit (c+7,"dut main_soclinux_ctrl_reset_reset_we",-1); vcdp->declBit (c+1128,"dut main_soclinux_ctrl_reset_reset_w",-1); vcdp->declBus (c+8,"dut main_soclinux_ctrl_storage",-1,31,0); vcdp->declBit (c+9,"dut main_soclinux_ctrl_re",-1); vcdp->declBus (c+10,"dut main_soclinux_ctrl_bus_errors_status",-1,31,0); vcdp->declBit (c+11,"dut main_soclinux_ctrl_bus_errors_we",-1); vcdp->declBit (c+5,"dut main_soclinux_ctrl_reset",-1); vcdp->declBit (c+12,"dut main_soclinux_ctrl_bus_error",-1); vcdp->declBus (c+10,"dut main_soclinux_ctrl_bus_errors",-1,31,0); vcdp->declBit (c+5,"dut main_soclinux_cpu_reset",-1); vcdp->declBus (c+624,"dut main_soclinux_cpu_ibus_adr",-1,29,0); vcdp->declBus (c+1129,"dut main_soclinux_cpu_ibus_dat_w",-1,31,0); vcdp->declBus (c+13,"dut main_soclinux_cpu_ibus_dat_r",-1,31,0); vcdp->declBus (c+1130,"dut main_soclinux_cpu_ibus_sel",-1,3,0); vcdp->declBit (c+14,"dut main_soclinux_cpu_ibus_cyc",-1); vcdp->declBit (c+15,"dut main_soclinux_cpu_ibus_stb",-1); vcdp->declBit (c+16,"dut main_soclinux_cpu_ibus_ack",-1); vcdp->declBit (c+1128,"dut main_soclinux_cpu_ibus_we",-1); vcdp->declBus (c+625,"dut main_soclinux_cpu_ibus_cti",-1,2,0); vcdp->declBus (c+1131,"dut main_soclinux_cpu_ibus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_cpu_ibus_err",-1); vcdp->declBus (c+626,"dut main_soclinux_cpu_dbus_adr",-1,29,0); vcdp->declBus (c+627,"dut main_soclinux_cpu_dbus_dat_w",-1,31,0); vcdp->declBus (c+13,"dut main_soclinux_cpu_dbus_dat_r",-1,31,0); vcdp->declBus (c+628,"dut main_soclinux_cpu_dbus_sel",-1,3,0); vcdp->declBit (c+629,"dut main_soclinux_cpu_dbus_cyc",-1); vcdp->declBit (c+629,"dut main_soclinux_cpu_dbus_stb",-1); vcdp->declBit (c+17,"dut main_soclinux_cpu_dbus_ack",-1); vcdp->declBit (c+630,"dut main_soclinux_cpu_dbus_we",-1); vcdp->declBus (c+18,"dut main_soclinux_cpu_dbus_cti",-1,2,0); vcdp->declBus (c+1131,"dut main_soclinux_cpu_dbus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_cpu_dbus_err",-1); vcdp->declBus (c+19,"dut main_soclinux_cpu_interrupt0",-1,31,0); vcdp->declBit (c+20,"dut main_soclinux_cpu_latch_re",-1); vcdp->declBit (c+6,"dut main_soclinux_cpu_latch_r",-1); vcdp->declBit (c+21,"dut main_soclinux_cpu_latch_we",-1); vcdp->declBit (c+1128,"dut main_soclinux_cpu_latch_w",-1); vcdp->declQuad (c+22,"dut main_soclinux_cpu_time_status",-1,63,0); vcdp->declBit (c+24,"dut main_soclinux_cpu_time_we",-1); vcdp->declQuad (c+25,"dut main_soclinux_cpu_time_cmp_storage",-1,63,0); vcdp->declBit (c+27,"dut main_soclinux_cpu_time_cmp_re",-1); vcdp->declBit (c+28,"dut main_soclinux_cpu_interrupt1",-1); vcdp->declQuad (c+29,"dut main_soclinux_cpu_time",-1,63,0); vcdp->declQuad (c+31,"dut main_soclinux_cpu_time_cmp",-1,63,0); vcdp->declBus (c+624,"dut main_soclinux_interface0_soc_bus_adr",-1,29,0); vcdp->declBus (c+1129,"dut main_soclinux_interface0_soc_bus_dat_w",-1,31,0); vcdp->declBus (c+13,"dut main_soclinux_interface0_soc_bus_dat_r",-1,31,0); vcdp->declBus (c+1130,"dut main_soclinux_interface0_soc_bus_sel",-1,3,0); vcdp->declBit (c+14,"dut main_soclinux_interface0_soc_bus_cyc",-1); vcdp->declBit (c+15,"dut main_soclinux_interface0_soc_bus_stb",-1); vcdp->declBit (c+16,"dut main_soclinux_interface0_soc_bus_ack",-1); vcdp->declBit (c+1128,"dut main_soclinux_interface0_soc_bus_we",-1); vcdp->declBus (c+625,"dut main_soclinux_interface0_soc_bus_cti",-1,2,0); vcdp->declBus (c+1131,"dut main_soclinux_interface0_soc_bus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_interface0_soc_bus_err",-1); vcdp->declBus (c+626,"dut main_soclinux_interface1_soc_bus_adr",-1,29,0); vcdp->declBus (c+627,"dut main_soclinux_interface1_soc_bus_dat_w",-1,31,0); vcdp->declBus (c+13,"dut main_soclinux_interface1_soc_bus_dat_r",-1,31,0); vcdp->declBus (c+628,"dut main_soclinux_interface1_soc_bus_sel",-1,3,0); vcdp->declBit (c+629,"dut main_soclinux_interface1_soc_bus_cyc",-1); vcdp->declBit (c+629,"dut main_soclinux_interface1_soc_bus_stb",-1); vcdp->declBit (c+17,"dut main_soclinux_interface1_soc_bus_ack",-1); vcdp->declBit (c+630,"dut main_soclinux_interface1_soc_bus_we",-1); vcdp->declBus (c+18,"dut main_soclinux_interface1_soc_bus_cti",-1,2,0); vcdp->declBus (c+1131,"dut main_soclinux_interface1_soc_bus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_interface1_soc_bus_err",-1); vcdp->declBus (c+33,"dut main_soclinux_rom_bus_adr",-1,29,0); vcdp->declBus (c+34,"dut main_soclinux_rom_bus_dat_w",-1,31,0); vcdp->declBus (c+631,"dut main_soclinux_rom_bus_dat_r",-1,31,0); vcdp->declBus (c+35,"dut main_soclinux_rom_bus_sel",-1,3,0); vcdp->declBit (c+36,"dut main_soclinux_rom_bus_cyc",-1); vcdp->declBit (c+37,"dut main_soclinux_rom_bus_stb",-1); vcdp->declBit (c+38,"dut main_soclinux_rom_bus_ack",-1); vcdp->declBit (c+39,"dut main_soclinux_rom_bus_we",-1); vcdp->declBus (c+40,"dut main_soclinux_rom_bus_cti",-1,2,0); vcdp->declBus (c+1,"dut main_soclinux_rom_bus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_rom_bus_err",-1); vcdp->declBus (c+41,"dut main_soclinux_rom_adr",-1,12,0); vcdp->declBus (c+631,"dut main_soclinux_rom_dat_r",-1,31,0); vcdp->declBus (c+33,"dut main_soclinux_sram_bus_adr",-1,29,0); vcdp->declBus (c+34,"dut main_soclinux_sram_bus_dat_w",-1,31,0); vcdp->declBus (c+42,"dut main_soclinux_sram_bus_dat_r",-1,31,0); vcdp->declBus (c+35,"dut main_soclinux_sram_bus_sel",-1,3,0); vcdp->declBit (c+43,"dut main_soclinux_sram_bus_cyc",-1); vcdp->declBit (c+37,"dut main_soclinux_sram_bus_stb",-1); vcdp->declBit (c+44,"dut main_soclinux_sram_bus_ack",-1); vcdp->declBit (c+39,"dut main_soclinux_sram_bus_we",-1); vcdp->declBus (c+40,"dut main_soclinux_sram_bus_cti",-1,2,0); vcdp->declBus (c+1,"dut main_soclinux_sram_bus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_sram_bus_err",-1); vcdp->declBus (c+45,"dut main_soclinux_sram_adr",-1,9,0); vcdp->declBus (c+42,"dut main_soclinux_sram_dat_r",-1,31,0); vcdp->declBus (c+46,"dut main_soclinux_sram_we",-1,3,0); vcdp->declBus (c+34,"dut main_soclinux_sram_dat_w",-1,31,0); vcdp->declBus (c+33,"dut main_soclinux_main_ram_bus_adr",-1,29,0); vcdp->declBus (c+34,"dut main_soclinux_main_ram_bus_dat_w",-1,31,0); vcdp->declBus (c+47,"dut main_soclinux_main_ram_bus_dat_r",-1,31,0); vcdp->declBus (c+35,"dut main_soclinux_main_ram_bus_sel",-1,3,0); vcdp->declBit (c+48,"dut main_soclinux_main_ram_bus_cyc",-1); vcdp->declBit (c+37,"dut main_soclinux_main_ram_bus_stb",-1); vcdp->declBit (c+49,"dut main_soclinux_main_ram_bus_ack",-1); vcdp->declBit (c+39,"dut main_soclinux_main_ram_bus_we",-1); vcdp->declBus (c+40,"dut main_soclinux_main_ram_bus_cti",-1,2,0); vcdp->declBus (c+1,"dut main_soclinux_main_ram_bus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_main_ram_bus_err",-1); vcdp->declBus (c+50,"dut main_soclinux_main_ram_adr",-1,22,0); vcdp->declBus (c+47,"dut main_soclinux_main_ram_dat_r",-1,31,0); vcdp->declBus (c+51,"dut main_soclinux_main_ram_we",-1,3,0); vcdp->declBus (c+34,"dut main_soclinux_main_ram_dat_w",-1,31,0); vcdp->declBus (c+52,"dut main_soclinux_load_storage",-1,31,0); vcdp->declBit (c+53,"dut main_soclinux_load_re",-1); vcdp->declBus (c+54,"dut main_soclinux_reload_storage",-1,31,0); vcdp->declBit (c+55,"dut main_soclinux_reload_re",-1); vcdp->declBit (c+56,"dut main_soclinux_en_storage",-1); vcdp->declBit (c+57,"dut main_soclinux_en_re",-1); vcdp->declBit (c+58,"dut main_soclinux_update_value_storage",-1); vcdp->declBit (c+59,"dut main_soclinux_update_value_re",-1); vcdp->declBus (c+60,"dut main_soclinux_value_status",-1,31,0); vcdp->declBit (c+61,"dut main_soclinux_value_we",-1); vcdp->declBit (c+62,"dut main_soclinux_irq",-1); vcdp->declBit (c+63,"dut main_soclinux_zero_status",-1); vcdp->declBit (c+64,"dut main_soclinux_zero_pending",-1); vcdp->declBit (c+63,"dut main_soclinux_zero_trigger",-1); vcdp->declBit (c+65,"dut main_soclinux_zero_clear",-1); vcdp->declBit (c+66,"dut main_soclinux_zero_old_trigger",-1); vcdp->declBit (c+67,"dut main_soclinux_eventmanager_status_re",-1); vcdp->declBit (c+6,"dut main_soclinux_eventmanager_status_r",-1); vcdp->declBit (c+68,"dut main_soclinux_eventmanager_status_we",-1); vcdp->declBit (c+63,"dut main_soclinux_eventmanager_status_w",-1); vcdp->declBit (c+69,"dut main_soclinux_eventmanager_pending_re",-1); vcdp->declBit (c+6,"dut main_soclinux_eventmanager_pending_r",-1); vcdp->declBit (c+70,"dut main_soclinux_eventmanager_pending_we",-1); vcdp->declBit (c+64,"dut main_soclinux_eventmanager_pending_w",-1); vcdp->declBit (c+71,"dut main_soclinux_eventmanager_storage",-1); vcdp->declBit (c+72,"dut main_soclinux_eventmanager_re",-1); vcdp->declBus (c+73,"dut main_soclinux_value",-1,31,0); vcdp->declBus (c+74,"dut main_soclinux_interface_adr",-1,13,0); vcdp->declBit (c+75,"dut main_soclinux_interface_we",-1); vcdp->declBus (c+76,"dut main_soclinux_interface_dat_w",-1,7,0); vcdp->declBus (c+77,"dut main_soclinux_interface_dat_r",-1,7,0); vcdp->declBus (c+33,"dut main_soclinux_bus_wishbone_adr",-1,29,0); vcdp->declBus (c+34,"dut main_soclinux_bus_wishbone_dat_w",-1,31,0); vcdp->declBus (c+78,"dut main_soclinux_bus_wishbone_dat_r",-1,31,0); vcdp->declBus (c+35,"dut main_soclinux_bus_wishbone_sel",-1,3,0); vcdp->declBit (c+79,"dut main_soclinux_bus_wishbone_cyc",-1); vcdp->declBit (c+37,"dut main_soclinux_bus_wishbone_stb",-1); vcdp->declBit (c+80,"dut main_soclinux_bus_wishbone_ack",-1); vcdp->declBit (c+39,"dut main_soclinux_bus_wishbone_we",-1); vcdp->declBus (c+40,"dut main_soclinux_bus_wishbone_cti",-1,2,0); vcdp->declBus (c+1,"dut main_soclinux_bus_wishbone_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_soclinux_bus_wishbone_err",-1); vcdp->declBit (c+81,"dut main_finish_finish_re",-1); vcdp->declBit (c+6,"dut main_finish_finish_r",-1); vcdp->declBit (c+82,"dut main_finish_finish_we",-1); vcdp->declBit (c+1128,"dut main_finish_finish_w",-1); vcdp->declBit (c+1128,"dut main_finish",-1); vcdp->declBit (c+1071,"dut sys_clk_1",-1); vcdp->declBit (c+83,"dut sys_rst",-1); vcdp->declBit (c+1071,"dut por_clk",-1); vcdp->declBit (c+83,"dut main_int_rst",-1); vcdp->declBus (c+33,"dut main_bus_adr",-1,29,0); vcdp->declBus (c+34,"dut main_bus_dat_w",-1,31,0); vcdp->declBus (c+84,"dut main_bus_dat_r",-1,31,0); vcdp->declBus (c+35,"dut main_bus_sel",-1,3,0); vcdp->declBit (c+85,"dut main_bus_cyc",-1); vcdp->declBit (c+37,"dut main_bus_stb",-1); vcdp->declBit (c+86,"dut main_bus_ack",-1); vcdp->declBit (c+39,"dut main_bus_we",-1); vcdp->declBus (c+40,"dut main_bus_cti",-1,2,0); vcdp->declBus (c+1,"dut main_bus_bte",-1,1,0); vcdp->declBit (c+1128,"dut main_bus_err",-1); vcdp->declBus (c+87,"dut main_adr",-1,11,0); vcdp->declBus (c+84,"dut main_dat_r",-1,31,0); vcdp->declBus (c+88,"dut main_we",-1,3,0); vcdp->declBus (c+34,"dut main_dat_w",-1,31,0); vcdp->declBit (c+2,"dut main_sink_valid",-1); vcdp->declBit (c+1073,"dut main_sink_ready",-1); vcdp->declBit (c+89,"dut main_sink_first",-1); vcdp->declBit (c+90,"dut main_sink_last",-1); vcdp->declBus (c+3,"dut main_sink_payload_data",-1,7,0); vcdp->declBit (c+1075,"dut main_source_valid",-1); vcdp->declBit (c+4,"dut main_source_ready",-1); vcdp->declBit (c+1128,"dut main_source_first",-1); vcdp->declBit (c+1128,"dut main_source_last",-1); vcdp->declBus (c+1077,"dut main_source_payload_data",-1,7,0); vcdp->declBit (c+91,"dut main_uart_rxtx_re",-1); vcdp->declBus (c+76,"dut main_uart_rxtx_r",-1,7,0); vcdp->declBit (c+92,"dut main_uart_rxtx_we",-1); vcdp->declBus (c+93,"dut main_uart_rxtx_w",-1,7,0); vcdp->declBit (c+94,"dut main_uart_txfull_status",-1); vcdp->declBit (c+95,"dut main_uart_txfull_we",-1); vcdp->declBit (c+96,"dut main_uart_rxempty_status",-1); vcdp->declBit (c+97,"dut main_uart_rxempty_we",-1); vcdp->declBit (c+98,"dut main_uart_irq",-1); vcdp->declBit (c+94,"dut main_uart_tx_status",-1); vcdp->declBit (c+99,"dut main_uart_tx_pending",-1); vcdp->declBit (c+94,"dut main_uart_tx_trigger",-1); vcdp->declBit (c+100,"dut main_uart_tx_clear",-1); vcdp->declBit (c+101,"dut main_uart_tx_old_trigger",-1); vcdp->declBit (c+96,"dut main_uart_rx_status",-1); vcdp->declBit (c+102,"dut main_uart_rx_pending",-1); vcdp->declBit (c+96,"dut main_uart_rx_trigger",-1); vcdp->declBit (c+103,"dut main_uart_rx_clear",-1); vcdp->declBit (c+104,"dut main_uart_rx_old_trigger",-1); vcdp->declBit (c+105,"dut main_uart_eventmanager_status_re",-1); vcdp->declBus (c+106,"dut main_uart_eventmanager_status_r",-1,1,0); vcdp->declBit (c+107,"dut main_uart_eventmanager_status_we",-1); vcdp->declBus (c+108,"dut main_uart_eventmanager_status_w",-1,1,0); vcdp->declBit (c+109,"dut main_uart_eventmanager_pending_re",-1); vcdp->declBus (c+106,"dut main_uart_eventmanager_pending_r",-1,1,0); vcdp->declBit (c+110,"dut main_uart_eventmanager_pending_we",-1); vcdp->declBus (c+111,"dut main_uart_eventmanager_pending_w",-1,1,0); vcdp->declBus (c+112,"dut main_uart_eventmanager_storage",-1,1,0); vcdp->declBit (c+113,"dut main_uart_eventmanager_re",-1); vcdp->declBit (c+91,"dut main_uart_tx_fifo_sink_valid",-1); vcdp->declBit (c+114,"dut main_uart_tx_fifo_sink_ready",-1); vcdp->declBit (c+1128,"dut main_uart_tx_fifo_sink_first",-1); vcdp->declBit (c+1128,"dut main_uart_tx_fifo_sink_last",-1); vcdp->declBus (c+76,"dut main_uart_tx_fifo_sink_payload_data",-1,7,0); vcdp->declBit (c+2,"dut main_uart_tx_fifo_source_valid",-1); vcdp->declBit (c+1073,"dut main_uart_tx_fifo_source_ready",-1); vcdp->declBit (c+89,"dut main_uart_tx_fifo_source_first",-1); vcdp->declBit (c+90,"dut main_uart_tx_fifo_source_last",-1); vcdp->declBus (c+3,"dut main_uart_tx_fifo_source_payload_data",-1,7,0); vcdp->declBit (c+1073,"dut main_uart_tx_fifo_re",-1); vcdp->declBit (c+2,"dut main_uart_tx_fifo_readable",-1); vcdp->declBit (c+91,"dut main_uart_tx_fifo_syncfifo_we",-1); vcdp->declBit (c+114,"dut main_uart_tx_fifo_syncfifo_writable",-1); vcdp->declBit (c+622,"dut main_uart_tx_fifo_syncfifo_re",-1); vcdp->declBit (c+115,"dut main_uart_tx_fifo_syncfifo_readable",-1); vcdp->declBus (c+116,"dut main_uart_tx_fifo_syncfifo_din",-1,9,0); vcdp->declBus (c+632,"dut main_uart_tx_fifo_syncfifo_dout",-1,9,0); vcdp->declBus (c+117,"dut main_uart_tx_fifo_level0",-1,4,0); vcdp->declBit (c+1128,"dut main_uart_tx_fifo_replace",-1); vcdp->declBus (c+118,"dut main_uart_tx_fifo_produce",-1,3,0); vcdp->declBus (c+119,"dut main_uart_tx_fifo_consume",-1,3,0); vcdp->declBus (c+120,"dut main_uart_tx_fifo_wrport_adr",-1,3,0); vcdp->declBus (c+633,"dut main_uart_tx_fifo_wrport_dat_r",-1,9,0); vcdp->declBit (c+121,"dut main_uart_tx_fifo_wrport_we",-1); vcdp->declBus (c+116,"dut main_uart_tx_fifo_wrport_dat_w",-1,9,0); vcdp->declBit (c+623,"dut main_uart_tx_fifo_do_read",-1); vcdp->declBus (c+119,"dut main_uart_tx_fifo_rdport_adr",-1,3,0); vcdp->declBus (c+632,"dut main_uart_tx_fifo_rdport_dat_r",-1,9,0); vcdp->declBit (c+623,"dut main_uart_tx_fifo_rdport_re",-1); vcdp->declBus (c+122,"dut main_uart_tx_fifo_level1",-1,4,0); vcdp->declBus (c+76,"dut main_uart_tx_fifo_fifo_in_payload_data",-1,7,0); vcdp->declBit (c+1128,"dut main_uart_tx_fifo_fifo_in_first",-1); vcdp->declBit (c+1128,"dut main_uart_tx_fifo_fifo_in_last",-1); vcdp->declBus (c+3,"dut main_uart_tx_fifo_fifo_out_payload_data",-1,7,0); vcdp->declBit (c+89,"dut main_uart_tx_fifo_fifo_out_first",-1); vcdp->declBit (c+90,"dut main_uart_tx_fifo_fifo_out_last",-1); vcdp->declBit (c+1075,"dut main_uart_rx_fifo_sink_valid",-1); vcdp->declBit (c+4,"dut main_uart_rx_fifo_sink_ready",-1); vcdp->declBit (c+1128,"dut main_uart_rx_fifo_sink_first",-1); vcdp->declBit (c+1128,"dut main_uart_rx_fifo_sink_last",-1); vcdp->declBus (c+1077,"dut main_uart_rx_fifo_sink_payload_data",-1,7,0); vcdp->declBit (c+123,"dut main_uart_rx_fifo_source_valid",-1); vcdp->declBit (c+103,"dut main_uart_rx_fifo_source_ready",-1); vcdp->declBit (c+124,"dut main_uart_rx_fifo_source_first",-1); vcdp->declBit (c+125,"dut main_uart_rx_fifo_source_last",-1); vcdp->declBus (c+93,"dut main_uart_rx_fifo_source_payload_data",-1,7,0); vcdp->declBit (c+103,"dut main_uart_rx_fifo_re",-1); vcdp->declBit (c+123,"dut main_uart_rx_fifo_readable",-1); vcdp->declBit (c+1075,"dut main_uart_rx_fifo_syncfifo_we",-1); vcdp->declBit (c+4,"dut main_uart_rx_fifo_syncfifo_writable",-1); vcdp->declBit (c+126,"dut main_uart_rx_fifo_syncfifo_re",-1); vcdp->declBit (c+127,"dut main_uart_rx_fifo_syncfifo_readable",-1); vcdp->declBus (c+1078,"dut main_uart_rx_fifo_syncfifo_din",-1,9,0); vcdp->declBus (c+634,"dut main_uart_rx_fifo_syncfifo_dout",-1,9,0); vcdp->declBus (c+128,"dut main_uart_rx_fifo_level0",-1,4,0); vcdp->declBit (c+1128,"dut main_uart_rx_fifo_replace",-1); vcdp->declBus (c+129,"dut main_uart_rx_fifo_produce",-1,3,0); vcdp->declBus (c+130,"dut main_uart_rx_fifo_consume",-1,3,0); vcdp->declBus (c+131,"dut main_uart_rx_fifo_wrport_adr",-1,3,0); vcdp->declBus (c+635,"dut main_uart_rx_fifo_wrport_dat_r",-1,9,0); vcdp->declBit (c+1079,"dut main_uart_rx_fifo_wrport_we",-1); vcdp->declBus (c+1078,"dut main_uart_rx_fifo_wrport_dat_w",-1,9,0); vcdp->declBit (c+132,"dut main_uart_rx_fifo_do_read",-1); vcdp->declBus (c+130,"dut main_uart_rx_fifo_rdport_adr",-1,3,0); vcdp->declBus (c+634,"dut main_uart_rx_fifo_rdport_dat_r",-1,9,0); vcdp->declBit (c+132,"dut main_uart_rx_fifo_rdport_re",-1); vcdp->declBus (c+133,"dut main_uart_rx_fifo_level1",-1,4,0); vcdp->declBus (c+1077,"dut main_uart_rx_fifo_fifo_in_payload_data",-1,7,0); vcdp->declBit (c+1128,"dut main_uart_rx_fifo_fifo_in_first",-1); vcdp->declBit (c+1128,"dut main_uart_rx_fifo_fifo_in_last",-1); vcdp->declBus (c+93,"dut main_uart_rx_fifo_fifo_out_payload_data",-1,7,0); vcdp->declBit (c+124,"dut main_uart_rx_fifo_fifo_out_first",-1); vcdp->declBit (c+125,"dut main_uart_rx_fifo_fifo_out_last",-1); vcdp->declBit (c+134,"dut builder_state",-1); vcdp->declBit (c+135,"dut builder_next_state",-1); vcdp->declBus (c+33,"dut builder_shared_adr",-1,29,0); vcdp->declBus (c+34,"dut builder_shared_dat_w",-1,31,0); vcdp->declBus (c+13,"dut builder_shared_dat_r",-1,31,0); vcdp->declBus (c+35,"dut builder_shared_sel",-1,3,0); vcdp->declBit (c+136,"dut builder_shared_cyc",-1); vcdp->declBit (c+37,"dut builder_shared_stb",-1); vcdp->declBit (c+137,"dut builder_shared_ack",-1); vcdp->declBit (c+39,"dut builder_shared_we",-1); vcdp->declBus (c+40,"dut builder_shared_cti",-1,2,0); vcdp->declBus (c+1,"dut builder_shared_bte",-1,1,0); vcdp->declBit (c+1128,"dut builder_shared_err",-1); vcdp->declBus (c+138,"dut builder_request",-1,1,0); vcdp->declBit (c+139,"dut builder_grant",-1); vcdp->declBus (c+140,"dut builder_slave_sel",-1,4,0); vcdp->declBus (c+141,"dut builder_slave_sel_r",-1,4,0); vcdp->declBit (c+12,"dut builder_error",-1); vcdp->declBit (c+142,"dut builder_wait",-1); vcdp->declBit (c+143,"dut builder_done",-1); vcdp->declBus (c+144,"dut builder_count",-1,19,0); vcdp->declBus (c+74,"dut builder_interface0_bank_bus_adr",-1,13,0); vcdp->declBit (c+75,"dut builder_interface0_bank_bus_we",-1); vcdp->declBus (c+76,"dut builder_interface0_bank_bus_dat_w",-1,7,0); vcdp->declBus (c+145,"dut builder_interface0_bank_bus_dat_r",-1,7,0); vcdp->declBit (c+146,"dut builder_csrbank0_timer_time7_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time7_r",-1,7,0); vcdp->declBit (c+147,"dut builder_csrbank0_timer_time7_we",-1); vcdp->declBus (c+148,"dut builder_csrbank0_timer_time7_w",-1,7,0); vcdp->declBit (c+149,"dut builder_csrbank0_timer_time6_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time6_r",-1,7,0); vcdp->declBit (c+150,"dut builder_csrbank0_timer_time6_we",-1); vcdp->declBus (c+151,"dut builder_csrbank0_timer_time6_w",-1,7,0); vcdp->declBit (c+152,"dut builder_csrbank0_timer_time5_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time5_r",-1,7,0); vcdp->declBit (c+153,"dut builder_csrbank0_timer_time5_we",-1); vcdp->declBus (c+154,"dut builder_csrbank0_timer_time5_w",-1,7,0); vcdp->declBit (c+155,"dut builder_csrbank0_timer_time4_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time4_r",-1,7,0); vcdp->declBit (c+156,"dut builder_csrbank0_timer_time4_we",-1); vcdp->declBus (c+157,"dut builder_csrbank0_timer_time4_w",-1,7,0); vcdp->declBit (c+158,"dut builder_csrbank0_timer_time3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time3_r",-1,7,0); vcdp->declBit (c+159,"dut builder_csrbank0_timer_time3_we",-1); vcdp->declBus (c+160,"dut builder_csrbank0_timer_time3_w",-1,7,0); vcdp->declBit (c+161,"dut builder_csrbank0_timer_time2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time2_r",-1,7,0); vcdp->declBit (c+162,"dut builder_csrbank0_timer_time2_we",-1); vcdp->declBus (c+163,"dut builder_csrbank0_timer_time2_w",-1,7,0); vcdp->declBit (c+164,"dut builder_csrbank0_timer_time1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time1_r",-1,7,0); vcdp->declBit (c+165,"dut builder_csrbank0_timer_time1_we",-1); vcdp->declBus (c+166,"dut builder_csrbank0_timer_time1_w",-1,7,0); vcdp->declBit (c+167,"dut builder_csrbank0_timer_time0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time0_r",-1,7,0); vcdp->declBit (c+24,"dut builder_csrbank0_timer_time0_we",-1); vcdp->declBus (c+168,"dut builder_csrbank0_timer_time0_w",-1,7,0); vcdp->declBit (c+169,"dut builder_csrbank0_timer_time_cmp7_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp7_r",-1,7,0); vcdp->declBit (c+170,"dut builder_csrbank0_timer_time_cmp7_we",-1); vcdp->declBus (c+171,"dut builder_csrbank0_timer_time_cmp7_w",-1,7,0); vcdp->declBit (c+172,"dut builder_csrbank0_timer_time_cmp6_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp6_r",-1,7,0); vcdp->declBit (c+173,"dut builder_csrbank0_timer_time_cmp6_we",-1); vcdp->declBus (c+174,"dut builder_csrbank0_timer_time_cmp6_w",-1,7,0); vcdp->declBit (c+175,"dut builder_csrbank0_timer_time_cmp5_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp5_r",-1,7,0); vcdp->declBit (c+176,"dut builder_csrbank0_timer_time_cmp5_we",-1); vcdp->declBus (c+177,"dut builder_csrbank0_timer_time_cmp5_w",-1,7,0); vcdp->declBit (c+178,"dut builder_csrbank0_timer_time_cmp4_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp4_r",-1,7,0); vcdp->declBit (c+179,"dut builder_csrbank0_timer_time_cmp4_we",-1); vcdp->declBus (c+180,"dut builder_csrbank0_timer_time_cmp4_w",-1,7,0); vcdp->declBit (c+181,"dut builder_csrbank0_timer_time_cmp3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp3_r",-1,7,0); vcdp->declBit (c+182,"dut builder_csrbank0_timer_time_cmp3_we",-1); vcdp->declBus (c+183,"dut builder_csrbank0_timer_time_cmp3_w",-1,7,0); vcdp->declBit (c+184,"dut builder_csrbank0_timer_time_cmp2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp2_r",-1,7,0); vcdp->declBit (c+185,"dut builder_csrbank0_timer_time_cmp2_we",-1); vcdp->declBus (c+186,"dut builder_csrbank0_timer_time_cmp2_w",-1,7,0); vcdp->declBit (c+187,"dut builder_csrbank0_timer_time_cmp1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp1_r",-1,7,0); vcdp->declBit (c+188,"dut builder_csrbank0_timer_time_cmp1_we",-1); vcdp->declBus (c+189,"dut builder_csrbank0_timer_time_cmp1_w",-1,7,0); vcdp->declBit (c+190,"dut builder_csrbank0_timer_time_cmp0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank0_timer_time_cmp0_r",-1,7,0); vcdp->declBit (c+191,"dut builder_csrbank0_timer_time_cmp0_we",-1); vcdp->declBus (c+192,"dut builder_csrbank0_timer_time_cmp0_w",-1,7,0); vcdp->declBit (c+193,"dut builder_csrbank0_sel",-1); vcdp->declBus (c+74,"dut builder_interface1_bank_bus_adr",-1,13,0); vcdp->declBit (c+75,"dut builder_interface1_bank_bus_we",-1); vcdp->declBus (c+76,"dut builder_interface1_bank_bus_dat_w",-1,7,0); vcdp->declBus (c+194,"dut builder_interface1_bank_bus_dat_r",-1,7,0); vcdp->declBit (c+195,"dut builder_csrbank1_scratch3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_scratch3_r",-1,7,0); vcdp->declBit (c+196,"dut builder_csrbank1_scratch3_we",-1); vcdp->declBus (c+197,"dut builder_csrbank1_scratch3_w",-1,7,0); vcdp->declBit (c+198,"dut builder_csrbank1_scratch2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_scratch2_r",-1,7,0); vcdp->declBit (c+199,"dut builder_csrbank1_scratch2_we",-1); vcdp->declBus (c+200,"dut builder_csrbank1_scratch2_w",-1,7,0); vcdp->declBit (c+201,"dut builder_csrbank1_scratch1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_scratch1_r",-1,7,0); vcdp->declBit (c+202,"dut builder_csrbank1_scratch1_we",-1); vcdp->declBus (c+203,"dut builder_csrbank1_scratch1_w",-1,7,0); vcdp->declBit (c+204,"dut builder_csrbank1_scratch0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_scratch0_r",-1,7,0); vcdp->declBit (c+205,"dut builder_csrbank1_scratch0_we",-1); vcdp->declBus (c+206,"dut builder_csrbank1_scratch0_w",-1,7,0); vcdp->declBit (c+207,"dut builder_csrbank1_bus_errors3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_bus_errors3_r",-1,7,0); vcdp->declBit (c+208,"dut builder_csrbank1_bus_errors3_we",-1); vcdp->declBus (c+209,"dut builder_csrbank1_bus_errors3_w",-1,7,0); vcdp->declBit (c+210,"dut builder_csrbank1_bus_errors2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_bus_errors2_r",-1,7,0); vcdp->declBit (c+211,"dut builder_csrbank1_bus_errors2_we",-1); vcdp->declBus (c+212,"dut builder_csrbank1_bus_errors2_w",-1,7,0); vcdp->declBit (c+213,"dut builder_csrbank1_bus_errors1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_bus_errors1_r",-1,7,0); vcdp->declBit (c+214,"dut builder_csrbank1_bus_errors1_we",-1); vcdp->declBus (c+215,"dut builder_csrbank1_bus_errors1_w",-1,7,0); vcdp->declBit (c+216,"dut builder_csrbank1_bus_errors0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank1_bus_errors0_r",-1,7,0); vcdp->declBit (c+11,"dut builder_csrbank1_bus_errors0_we",-1); vcdp->declBus (c+217,"dut builder_csrbank1_bus_errors0_w",-1,7,0); vcdp->declBit (c+218,"dut builder_csrbank1_sel",-1); vcdp->declBus (c+74,"dut builder_interface2_bank_bus_adr",-1,13,0); vcdp->declBit (c+75,"dut builder_interface2_bank_bus_we",-1); vcdp->declBus (c+76,"dut builder_interface2_bank_bus_dat_w",-1,7,0); vcdp->declBus (c+219,"dut builder_interface2_bank_bus_dat_r",-1,7,0); vcdp->declBit (c+220,"dut builder_csrbank2_sel",-1); vcdp->declBus (c+74,"dut builder_interface3_bank_bus_adr",-1,13,0); vcdp->declBit (c+75,"dut builder_interface3_bank_bus_we",-1); vcdp->declBus (c+76,"dut builder_interface3_bank_bus_dat_w",-1,7,0); vcdp->declBus (c+221,"dut builder_interface3_bank_bus_dat_r",-1,7,0); vcdp->declBit (c+222,"dut builder_csrbank3_load3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_load3_r",-1,7,0); vcdp->declBit (c+223,"dut builder_csrbank3_load3_we",-1); vcdp->declBus (c+224,"dut builder_csrbank3_load3_w",-1,7,0); vcdp->declBit (c+225,"dut builder_csrbank3_load2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_load2_r",-1,7,0); vcdp->declBit (c+226,"dut builder_csrbank3_load2_we",-1); vcdp->declBus (c+227,"dut builder_csrbank3_load2_w",-1,7,0); vcdp->declBit (c+228,"dut builder_csrbank3_load1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_load1_r",-1,7,0); vcdp->declBit (c+229,"dut builder_csrbank3_load1_we",-1); vcdp->declBus (c+230,"dut builder_csrbank3_load1_w",-1,7,0); vcdp->declBit (c+231,"dut builder_csrbank3_load0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_load0_r",-1,7,0); vcdp->declBit (c+232,"dut builder_csrbank3_load0_we",-1); vcdp->declBus (c+233,"dut builder_csrbank3_load0_w",-1,7,0); vcdp->declBit (c+234,"dut builder_csrbank3_reload3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_reload3_r",-1,7,0); vcdp->declBit (c+235,"dut builder_csrbank3_reload3_we",-1); vcdp->declBus (c+236,"dut builder_csrbank3_reload3_w",-1,7,0); vcdp->declBit (c+237,"dut builder_csrbank3_reload2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_reload2_r",-1,7,0); vcdp->declBit (c+238,"dut builder_csrbank3_reload2_we",-1); vcdp->declBus (c+239,"dut builder_csrbank3_reload2_w",-1,7,0); vcdp->declBit (c+240,"dut builder_csrbank3_reload1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_reload1_r",-1,7,0); vcdp->declBit (c+241,"dut builder_csrbank3_reload1_we",-1); vcdp->declBus (c+242,"dut builder_csrbank3_reload1_w",-1,7,0); vcdp->declBit (c+243,"dut builder_csrbank3_reload0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_reload0_r",-1,7,0); vcdp->declBit (c+244,"dut builder_csrbank3_reload0_we",-1); vcdp->declBus (c+245,"dut builder_csrbank3_reload0_w",-1,7,0); vcdp->declBit (c+246,"dut builder_csrbank3_en0_re",-1); vcdp->declBit (c+6,"dut builder_csrbank3_en0_r",-1); vcdp->declBit (c+247,"dut builder_csrbank3_en0_we",-1); vcdp->declBit (c+56,"dut builder_csrbank3_en0_w",-1); vcdp->declBit (c+248,"dut builder_csrbank3_update_value0_re",-1); vcdp->declBit (c+6,"dut builder_csrbank3_update_value0_r",-1); vcdp->declBit (c+249,"dut builder_csrbank3_update_value0_we",-1); vcdp->declBit (c+58,"dut builder_csrbank3_update_value0_w",-1); vcdp->declBit (c+250,"dut builder_csrbank3_value3_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_value3_r",-1,7,0); vcdp->declBit (c+251,"dut builder_csrbank3_value3_we",-1); vcdp->declBus (c+252,"dut builder_csrbank3_value3_w",-1,7,0); vcdp->declBit (c+253,"dut builder_csrbank3_value2_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_value2_r",-1,7,0); vcdp->declBit (c+254,"dut builder_csrbank3_value2_we",-1); vcdp->declBus (c+255,"dut builder_csrbank3_value2_w",-1,7,0); vcdp->declBit (c+256,"dut builder_csrbank3_value1_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_value1_r",-1,7,0); vcdp->declBit (c+257,"dut builder_csrbank3_value1_we",-1); vcdp->declBus (c+258,"dut builder_csrbank3_value1_w",-1,7,0); vcdp->declBit (c+259,"dut builder_csrbank3_value0_re",-1); vcdp->declBus (c+76,"dut builder_csrbank3_value0_r",-1,7,0); vcdp->declBit (c+61,"dut builder_csrbank3_value0_we",-1); vcdp->declBus (c+260,"dut builder_csrbank3_value0_w",-1,7,0); vcdp->declBit (c+261,"dut builder_csrbank3_ev_enable0_re",-1); vcdp->declBit (c+6,"dut builder_csrbank3_ev_enable0_r",-1); vcdp->declBit (c+262,"dut builder_csrbank3_ev_enable0_we",-1); vcdp->declBit (c+71,"dut builder_csrbank3_ev_enable0_w",-1); vcdp->declBit (c+263,"dut builder_csrbank3_sel",-1); vcdp->declBus (c+74,"dut builder_interface4_bank_bus_adr",-1,13,0); vcdp->declBit (c+75,"dut builder_interface4_bank_bus_we",-1); vcdp->declBus (c+76,"dut builder_interface4_bank_bus_dat_w",-1,7,0); vcdp->declBus (c+264,"dut builder_interface4_bank_bus_dat_r",-1,7,0); vcdp->declBit (c+265,"dut builder_csrbank4_txfull_re",-1); vcdp->declBit (c+6,"dut builder_csrbank4_txfull_r",-1); vcdp->declBit (c+95,"dut builder_csrbank4_txfull_we",-1); vcdp->declBit (c+94,"dut builder_csrbank4_txfull_w",-1); vcdp->declBit (c+266,"dut builder_csrbank4_rxempty_re",-1); vcdp->declBit (c+6,"dut builder_csrbank4_rxempty_r",-1); vcdp->declBit (c+97,"dut builder_csrbank4_rxempty_we",-1); vcdp->declBit (c+96,"dut builder_csrbank4_rxempty_w",-1); vcdp->declBit (c+267,"dut builder_csrbank4_ev_enable0_re",-1); vcdp->declBus (c+106,"dut builder_csrbank4_ev_enable0_r",-1,1,0); vcdp->declBit (c+268,"dut builder_csrbank4_ev_enable0_we",-1); vcdp->declBus (c+112,"dut builder_csrbank4_ev_enable0_w",-1,1,0); vcdp->declBit (c+269,"dut builder_csrbank4_sel",-1); vcdp->declBus (c+74,"dut builder_adr",-1,13,0); vcdp->declBit (c+75,"dut builder_we",-1); vcdp->declBus (c+76,"dut builder_dat_w",-1,7,0); vcdp->declBus (c+77,"dut builder_dat_r",-1,7,0); vcdp->declBus (c+33,"dut builder_array_muxed0",-1,29,0); vcdp->declBus (c+34,"dut builder_array_muxed1",-1,31,0); vcdp->declBus (c+35,"dut builder_array_muxed2",-1,3,0); vcdp->declBit (c+136,"dut builder_array_muxed3",-1); vcdp->declBit (c+37,"dut builder_array_muxed4",-1); vcdp->declBit (c+39,"dut builder_array_muxed5",-1); vcdp->declBus (c+40,"dut builder_array_muxed6",-1,2,0); vcdp->declBus (c+1,"dut builder_array_muxed7",-1,1,0); // Tracing: dut mem // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/rust-litex/build/sim/gateware/dut.v:1615 vcdp->declBus (c+631,"dut memdat",-1,31,0); // Tracing: dut mem_1 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/rust-litex/build/sim/gateware/dut.v:1627 vcdp->declBus (c+636,"dut memadr",-1,9,0); // Tracing: dut mem_2 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/rust-litex/build/sim/gateware/dut.v:1647 vcdp->declBus (c+637,"dut memadr_1",-1,22,0); // Tracing: dut mem_3 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/rust-litex/build/sim/gateware/dut.v:1667 vcdp->declBus (c+638,"dut memadr_2",-1,11,0); {int i; for (i=0; i<16; i++) { vcdp->declBus (c+639+i*1,"dut storage",(i+0),9,0);}} vcdp->declBus (c+633,"dut memdat_1",-1,9,0); vcdp->declBus (c+632,"dut memdat_2",-1,9,0); {int i; for (i=0; i<16; i++) { vcdp->declBus (c+655+i*1,"dut storage_1",(i+0),9,0);}} vcdp->declBus (c+635,"dut memdat_3",-1,9,0); vcdp->declBus (c+634,"dut memdat_4",-1,9,0); vcdp->declBus (c+1129,"dut VexRiscv externalResetVector",-1,31,0); vcdp->declBit (c+28,"dut VexRiscv timerInterrupt",-1); vcdp->declBit (c+1128,"dut VexRiscv softwareInterrupt",-1); vcdp->declBus (c+19,"dut VexRiscv externalInterruptArray",-1,31,0); vcdp->declBit (c+14,"dut VexRiscv iBusWishbone_CYC",-1); vcdp->declBit (c+15,"dut VexRiscv iBusWishbone_STB",-1); vcdp->declBit (c+16,"dut VexRiscv iBusWishbone_ACK",-1); vcdp->declBit (c+1128,"dut VexRiscv iBusWishbone_WE",-1); vcdp->declBus (c+624,"dut VexRiscv iBusWishbone_ADR",-1,29,0); vcdp->declBus (c+13,"dut VexRiscv iBusWishbone_DAT_MISO",-1,31,0); vcdp->declBus (c+1129,"dut VexRiscv iBusWishbone_DAT_MOSI",-1,31,0); vcdp->declBus (c+1130,"dut VexRiscv iBusWishbone_SEL",-1,3,0); vcdp->declBit (c+1128,"dut VexRiscv iBusWishbone_ERR",-1); vcdp->declBus (c+1131,"dut VexRiscv iBusWishbone_BTE",-1,1,0); vcdp->declBus (c+625,"dut VexRiscv iBusWishbone_CTI",-1,2,0); vcdp->declBit (c+629,"dut VexRiscv dBusWishbone_CYC",-1); vcdp->declBit (c+629,"dut VexRiscv dBusWishbone_STB",-1); vcdp->declBit (c+17,"dut VexRiscv dBusWishbone_ACK",-1); vcdp->declBit (c+630,"dut VexRiscv dBusWishbone_WE",-1); vcdp->declBus (c+626,"dut VexRiscv dBusWishbone_ADR",-1,29,0); vcdp->declBus (c+13,"dut VexRiscv dBusWishbone_DAT_MISO",-1,31,0); vcdp->declBus (c+627,"dut VexRiscv dBusWishbone_DAT_MOSI",-1,31,0); vcdp->declBus (c+628,"dut VexRiscv dBusWishbone_SEL",-1,3,0); vcdp->declBit (c+1128,"dut VexRiscv dBusWishbone_ERR",-1); vcdp->declBus (c+1131,"dut VexRiscv dBusWishbone_BTE",-1,1,0); vcdp->declBus (c+18,"dut VexRiscv dBusWishbone_CTI",-1,2,0); vcdp->declBit (c+1071,"dut VexRiscv clk",-1); vcdp->declBit (c+270,"dut VexRiscv reset",-1); // Tracing: dut VexRiscv _zz_254_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1210 // Tracing: dut VexRiscv _zz_255_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1211 // Tracing: dut VexRiscv _zz_256_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1212 // Tracing: dut VexRiscv _zz_257_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1213 // Tracing: dut VexRiscv _zz_258_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1214 // Tracing: dut VexRiscv _zz_259_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1215 // Tracing: dut VexRiscv _zz_260_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1216 // Tracing: dut VexRiscv _zz_261_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1217 // Tracing: dut VexRiscv _zz_262_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1218 // Tracing: dut VexRiscv _zz_263_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1219 // Tracing: dut VexRiscv _zz_264_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1220 // Tracing: dut VexRiscv _zz_265_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1221 // Tracing: dut VexRiscv _zz_266_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1222 // Tracing: dut VexRiscv _zz_267_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1223 // Tracing: dut VexRiscv _zz_268_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1224 // Tracing: dut VexRiscv _zz_269_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1225 // Tracing: dut VexRiscv _zz_270_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1226 // Tracing: dut VexRiscv _zz_271_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1227 // Tracing: dut VexRiscv _zz_272_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1228 // Tracing: dut VexRiscv _zz_273_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1229 // Tracing: dut VexRiscv _zz_274_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1230 // Tracing: dut VexRiscv _zz_275_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1231 // Tracing: dut VexRiscv _zz_276_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1232 // Tracing: dut VexRiscv _zz_277_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1233 // Tracing: dut VexRiscv _zz_278_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1234 // Tracing: dut VexRiscv _zz_279_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1235 // Tracing: dut VexRiscv _zz_280_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1236 // Tracing: dut VexRiscv _zz_281_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1237 // Tracing: dut VexRiscv _zz_282_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1238 // Tracing: dut VexRiscv _zz_283_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1239 // Tracing: dut VexRiscv _zz_284_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1240 // Tracing: dut VexRiscv _zz_285_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1241 // Tracing: dut VexRiscv _zz_286_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1242 // Tracing: dut VexRiscv _zz_287_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1243 // Tracing: dut VexRiscv _zz_288_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1244 // Tracing: dut VexRiscv _zz_289_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1245 // Tracing: dut VexRiscv _zz_290_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1246 // Tracing: dut VexRiscv _zz_291_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1247 // Tracing: dut VexRiscv _zz_292_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1248 // Tracing: dut VexRiscv _zz_293_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1249 // Tracing: dut VexRiscv _zz_294_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1250 // Tracing: dut VexRiscv _zz_295_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1251 // Tracing: dut VexRiscv _zz_296_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1252 // Tracing: dut VexRiscv _zz_297_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1253 // Tracing: dut VexRiscv _zz_298_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1254 // Tracing: dut VexRiscv _zz_299_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1255 // Tracing: dut VexRiscv _zz_300_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1256 // Tracing: dut VexRiscv _zz_301_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1257 // Tracing: dut VexRiscv _zz_302_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1258 // Tracing: dut VexRiscv _zz_303_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1259 // Tracing: dut VexRiscv _zz_304_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1260 vcdp->declBit (c+271,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_prefetch_haltIt",-1); vcdp->declBus (c+671,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_data",-1,31,0); vcdp->declBus (c+272,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress",-1,31,0); vcdp->declBit (c+672,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_haltIt",-1); vcdp->declBit (c+273,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid",-1); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation",-1); vcdp->declBit (c+274,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end",-1); vcdp->declBit (c+673,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_decode_error",-1); vcdp->declBit (c+674,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling",-1); vcdp->declBit (c+675,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_decode_mmuException",-1); vcdp->declBus (c+676,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_decode_data",-1,31,0); vcdp->declBit (c+677,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_decode_cacheMiss",-1); vcdp->declBus (c+678,"dut VexRiscv IBusCachedPlugin_cache_io_cpu_decode_physicalAddress",-1,31,0); vcdp->declBit (c+275,"dut VexRiscv IBusCachedPlugin_cache_io_mem_cmd_valid",-1); vcdp->declBus (c+679,"dut VexRiscv IBusCachedPlugin_cache_io_mem_cmd_payload_address",-1,31,0); vcdp->declBus (c+1132,"dut VexRiscv IBusCachedPlugin_cache_io_mem_cmd_payload_size",-1,2,0); vcdp->declBit (c+680,"dut VexRiscv dataCache_1__io_cpu_memory_isWrite",-1); vcdp->declBit (c+276,"dut VexRiscv dataCache_1__io_cpu_memory_mmuBus_cmd_isValid",-1); vcdp->declBus (c+681,"dut VexRiscv dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation",-1); vcdp->declBit (c+277,"dut VexRiscv dataCache_1__io_cpu_memory_mmuBus_end",-1); vcdp->declBit (c+278,"dut VexRiscv dataCache_1__io_cpu_writeBack_haltIt",-1); vcdp->declBus (c+279,"dut VexRiscv dataCache_1__io_cpu_writeBack_data",-1,31,0); vcdp->declBit (c+280,"dut VexRiscv dataCache_1__io_cpu_writeBack_mmuException",-1); vcdp->declBit (c+281,"dut VexRiscv dataCache_1__io_cpu_writeBack_unalignedAccess",-1); vcdp->declBit (c+282,"dut VexRiscv dataCache_1__io_cpu_writeBack_accessError",-1); vcdp->declBit (c+682,"dut VexRiscv dataCache_1__io_cpu_writeBack_isWrite",-1); vcdp->declBit (c+283,"dut VexRiscv dataCache_1__io_cpu_flush_ready",-1); vcdp->declBit (c+284,"dut VexRiscv dataCache_1__io_cpu_redo",-1); vcdp->declBit (c+285,"dut VexRiscv dataCache_1__io_mem_cmd_valid",-1); vcdp->declBit (c+286,"dut VexRiscv dataCache_1__io_mem_cmd_payload_wr",-1); vcdp->declBus (c+287,"dut VexRiscv dataCache_1__io_mem_cmd_payload_address",-1,31,0); vcdp->declBus (c+288,"dut VexRiscv dataCache_1__io_mem_cmd_payload_data",-1,31,0); vcdp->declBus (c+683,"dut VexRiscv dataCache_1__io_mem_cmd_payload_mask",-1,3,0); vcdp->declBus (c+289,"dut VexRiscv dataCache_1__io_mem_cmd_payload_length",-1,2,0); vcdp->declBit (c+290,"dut VexRiscv dataCache_1__io_mem_cmd_payload_last",-1); // Tracing: dut VexRiscv _zz_305_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1298 // Tracing: dut VexRiscv _zz_306_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1299 // Tracing: dut VexRiscv _zz_307_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1300 // Tracing: dut VexRiscv _zz_308_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1301 // Tracing: dut VexRiscv _zz_309_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1302 // Tracing: dut VexRiscv _zz_310_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1303 // Tracing: dut VexRiscv _zz_311_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1304 // Tracing: dut VexRiscv _zz_312_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1305 // Tracing: dut VexRiscv _zz_313_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1306 // Tracing: dut VexRiscv _zz_314_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1307 // Tracing: dut VexRiscv _zz_315_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1308 // Tracing: dut VexRiscv _zz_316_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1309 // Tracing: dut VexRiscv _zz_317_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1310 // Tracing: dut VexRiscv _zz_318_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1311 // Tracing: dut VexRiscv _zz_319_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1312 // Tracing: dut VexRiscv _zz_320_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1313 // Tracing: dut VexRiscv _zz_321_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1314 // Tracing: dut VexRiscv _zz_322_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1315 // Tracing: dut VexRiscv _zz_323_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1316 // Tracing: dut VexRiscv _zz_324_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1317 // Tracing: dut VexRiscv _zz_325_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1318 // Tracing: dut VexRiscv _zz_326_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1319 // Tracing: dut VexRiscv _zz_327_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1320 // Tracing: dut VexRiscv _zz_328_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1321 // Tracing: dut VexRiscv _zz_329_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1322 // Tracing: dut VexRiscv _zz_330_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1323 // Tracing: dut VexRiscv _zz_331_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1324 // Tracing: dut VexRiscv _zz_332_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1325 // Tracing: dut VexRiscv _zz_333_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1326 // Tracing: dut VexRiscv _zz_334_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1327 // Tracing: dut VexRiscv _zz_335_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1328 // Tracing: dut VexRiscv _zz_336_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1329 // Tracing: dut VexRiscv _zz_337_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1330 // Tracing: dut VexRiscv _zz_338_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1331 // Tracing: dut VexRiscv _zz_339_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1332 // Tracing: dut VexRiscv _zz_340_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1333 // Tracing: dut VexRiscv _zz_341_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1334 // Tracing: dut VexRiscv _zz_342_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1335 // Tracing: dut VexRiscv _zz_343_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1336 // Tracing: dut VexRiscv _zz_344_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1337 // Tracing: dut VexRiscv _zz_345_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1338 // Tracing: dut VexRiscv _zz_346_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1339 // Tracing: dut VexRiscv _zz_347_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1340 // Tracing: dut VexRiscv _zz_348_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1341 // Tracing: dut VexRiscv _zz_349_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1342 // Tracing: dut VexRiscv _zz_350_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1343 // Tracing: dut VexRiscv _zz_351_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1344 // Tracing: dut VexRiscv _zz_352_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1345 // Tracing: dut VexRiscv _zz_353_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1346 // Tracing: dut VexRiscv _zz_354_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1347 // Tracing: dut VexRiscv _zz_355_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1348 // Tracing: dut VexRiscv _zz_356_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1349 // Tracing: dut VexRiscv _zz_357_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1350 // Tracing: dut VexRiscv _zz_358_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1351 // Tracing: dut VexRiscv _zz_359_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1352 // Tracing: dut VexRiscv _zz_360_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1353 // Tracing: dut VexRiscv _zz_361_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1354 // Tracing: dut VexRiscv _zz_362_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1355 // Tracing: dut VexRiscv _zz_363_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1356 // Tracing: dut VexRiscv _zz_364_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1357 // Tracing: dut VexRiscv _zz_365_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1358 // Tracing: dut VexRiscv _zz_366_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1359 // Tracing: dut VexRiscv _zz_367_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1360 // Tracing: dut VexRiscv _zz_368_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1361 // Tracing: dut VexRiscv _zz_369_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1362 // Tracing: dut VexRiscv _zz_370_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1363 // Tracing: dut VexRiscv _zz_371_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1364 // Tracing: dut VexRiscv _zz_372_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1365 // Tracing: dut VexRiscv _zz_373_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1366 // Tracing: dut VexRiscv _zz_374_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1367 // Tracing: dut VexRiscv _zz_375_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1368 // Tracing: dut VexRiscv _zz_376_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1369 // Tracing: dut VexRiscv _zz_377_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1370 // Tracing: dut VexRiscv _zz_378_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1371 // Tracing: dut VexRiscv _zz_379_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1372 // Tracing: dut VexRiscv _zz_380_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1373 // Tracing: dut VexRiscv _zz_381_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1374 // Tracing: dut VexRiscv _zz_382_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1375 // Tracing: dut VexRiscv _zz_383_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1376 // Tracing: dut VexRiscv _zz_384_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1377 // Tracing: dut VexRiscv _zz_385_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1378 // Tracing: dut VexRiscv _zz_386_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1379 // Tracing: dut VexRiscv _zz_387_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1380 // Tracing: dut VexRiscv _zz_388_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1381 // Tracing: dut VexRiscv _zz_389_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1382 // Tracing: dut VexRiscv _zz_390_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1383 // Tracing: dut VexRiscv _zz_391_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1384 // Tracing: dut VexRiscv _zz_392_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1385 // Tracing: dut VexRiscv _zz_393_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1386 // Tracing: dut VexRiscv _zz_394_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1387 // Tracing: dut VexRiscv _zz_395_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1388 // Tracing: dut VexRiscv _zz_396_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1389 // Tracing: dut VexRiscv _zz_397_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1390 // Tracing: dut VexRiscv _zz_398_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1391 // Tracing: dut VexRiscv _zz_399_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1392 // Tracing: dut VexRiscv _zz_400_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1393 // Tracing: dut VexRiscv _zz_401_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1394 // Tracing: dut VexRiscv _zz_402_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1395 // Tracing: dut VexRiscv _zz_403_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1396 // Tracing: dut VexRiscv _zz_404_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1397 // Tracing: dut VexRiscv _zz_405_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1398 // Tracing: dut VexRiscv _zz_406_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1399 // Tracing: dut VexRiscv _zz_407_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1400 // Tracing: dut VexRiscv _zz_408_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1401 // Tracing: dut VexRiscv _zz_409_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1402 // Tracing: dut VexRiscv _zz_410_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1403 // Tracing: dut VexRiscv _zz_411_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1404 // Tracing: dut VexRiscv _zz_412_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1405 // Tracing: dut VexRiscv _zz_413_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1406 // Tracing: dut VexRiscv _zz_414_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1407 // Tracing: dut VexRiscv _zz_415_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1408 // Tracing: dut VexRiscv _zz_416_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1409 // Tracing: dut VexRiscv _zz_417_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1410 // Tracing: dut VexRiscv _zz_418_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1411 // Tracing: dut VexRiscv _zz_419_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1412 // Tracing: dut VexRiscv _zz_420_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1413 // Tracing: dut VexRiscv _zz_421_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1414 // Tracing: dut VexRiscv _zz_422_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1415 // Tracing: dut VexRiscv _zz_423_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1416 // Tracing: dut VexRiscv _zz_424_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1417 // Tracing: dut VexRiscv _zz_425_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1418 // Tracing: dut VexRiscv _zz_426_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1419 // Tracing: dut VexRiscv _zz_427_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1420 // Tracing: dut VexRiscv _zz_428_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1421 // Tracing: dut VexRiscv _zz_429_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1422 // Tracing: dut VexRiscv _zz_430_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1423 // Tracing: dut VexRiscv _zz_431_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1424 // Tracing: dut VexRiscv _zz_432_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1425 // Tracing: dut VexRiscv _zz_433_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1426 // Tracing: dut VexRiscv _zz_434_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1427 // Tracing: dut VexRiscv _zz_435_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1428 // Tracing: dut VexRiscv _zz_436_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1429 // Tracing: dut VexRiscv _zz_437_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1430 // Tracing: dut VexRiscv _zz_438_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1431 // Tracing: dut VexRiscv _zz_439_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1432 // Tracing: dut VexRiscv _zz_440_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1433 // Tracing: dut VexRiscv _zz_441_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1434 // Tracing: dut VexRiscv _zz_442_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1435 // Tracing: dut VexRiscv _zz_443_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1436 // Tracing: dut VexRiscv _zz_444_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1437 // Tracing: dut VexRiscv _zz_445_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1438 // Tracing: dut VexRiscv _zz_446_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1439 // Tracing: dut VexRiscv _zz_447_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1440 // Tracing: dut VexRiscv _zz_448_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1441 // Tracing: dut VexRiscv _zz_449_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1442 // Tracing: dut VexRiscv _zz_450_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1443 // Tracing: dut VexRiscv _zz_451_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1444 // Tracing: dut VexRiscv _zz_452_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1445 // Tracing: dut VexRiscv _zz_453_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1446 // Tracing: dut VexRiscv _zz_454_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1447 // Tracing: dut VexRiscv _zz_455_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1448 // Tracing: dut VexRiscv _zz_456_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1449 // Tracing: dut VexRiscv _zz_457_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1450 // Tracing: dut VexRiscv _zz_458_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1451 // Tracing: dut VexRiscv _zz_459_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1452 // Tracing: dut VexRiscv _zz_460_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1453 // Tracing: dut VexRiscv _zz_461_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1454 // Tracing: dut VexRiscv _zz_462_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1455 // Tracing: dut VexRiscv _zz_463_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1456 // Tracing: dut VexRiscv _zz_464_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1457 // Tracing: dut VexRiscv _zz_465_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1458 // Tracing: dut VexRiscv _zz_466_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1459 // Tracing: dut VexRiscv _zz_467_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1460 // Tracing: dut VexRiscv _zz_468_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1461 // Tracing: dut VexRiscv _zz_469_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1462 // Tracing: dut VexRiscv _zz_470_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1463 // Tracing: dut VexRiscv _zz_471_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1464 // Tracing: dut VexRiscv _zz_472_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1465 // Tracing: dut VexRiscv _zz_473_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1466 // Tracing: dut VexRiscv _zz_474_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1467 // Tracing: dut VexRiscv _zz_475_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1468 // Tracing: dut VexRiscv _zz_476_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1469 // Tracing: dut VexRiscv _zz_477_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1470 // Tracing: dut VexRiscv _zz_478_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1471 // Tracing: dut VexRiscv _zz_479_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1472 // Tracing: dut VexRiscv _zz_480_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1473 // Tracing: dut VexRiscv _zz_481_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1474 // Tracing: dut VexRiscv _zz_482_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1475 // Tracing: dut VexRiscv _zz_483_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1476 // Tracing: dut VexRiscv _zz_484_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1477 // Tracing: dut VexRiscv _zz_485_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1478 // Tracing: dut VexRiscv _zz_486_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1479 // Tracing: dut VexRiscv _zz_487_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1480 // Tracing: dut VexRiscv _zz_488_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1481 // Tracing: dut VexRiscv _zz_489_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1482 // Tracing: dut VexRiscv _zz_490_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1483 // Tracing: dut VexRiscv _zz_491_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1484 // Tracing: dut VexRiscv _zz_492_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1485 // Tracing: dut VexRiscv _zz_493_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1486 // Tracing: dut VexRiscv _zz_494_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1487 // Tracing: dut VexRiscv _zz_495_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1488 // Tracing: dut VexRiscv _zz_496_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1489 // Tracing: dut VexRiscv _zz_497_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1490 // Tracing: dut VexRiscv _zz_498_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1491 // Tracing: dut VexRiscv _zz_499_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1492 // Tracing: dut VexRiscv _zz_500_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1493 // Tracing: dut VexRiscv _zz_501_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1494 // Tracing: dut VexRiscv _zz_502_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1495 // Tracing: dut VexRiscv _zz_503_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1496 // Tracing: dut VexRiscv _zz_504_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1497 // Tracing: dut VexRiscv _zz_505_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1498 // Tracing: dut VexRiscv _zz_506_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1499 // Tracing: dut VexRiscv _zz_507_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1500 // Tracing: dut VexRiscv _zz_508_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1501 // Tracing: dut VexRiscv _zz_509_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1502 // Tracing: dut VexRiscv _zz_510_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1503 // Tracing: dut VexRiscv _zz_511_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1504 // Tracing: dut VexRiscv _zz_512_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1505 // Tracing: dut VexRiscv _zz_513_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1506 // Tracing: dut VexRiscv _zz_514_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1507 // Tracing: dut VexRiscv _zz_515_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1508 // Tracing: dut VexRiscv _zz_516_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1509 // Tracing: dut VexRiscv _zz_517_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1510 // Tracing: dut VexRiscv _zz_518_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1511 // Tracing: dut VexRiscv _zz_519_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1512 // Tracing: dut VexRiscv _zz_520_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1513 // Tracing: dut VexRiscv _zz_521_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1514 // Tracing: dut VexRiscv _zz_522_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1515 // Tracing: dut VexRiscv _zz_523_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1516 // Tracing: dut VexRiscv _zz_524_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1517 // Tracing: dut VexRiscv _zz_525_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1518 // Tracing: dut VexRiscv _zz_526_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1519 // Tracing: dut VexRiscv _zz_527_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1520 // Tracing: dut VexRiscv _zz_528_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1521 // Tracing: dut VexRiscv _zz_529_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1522 // Tracing: dut VexRiscv _zz_530_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1523 // Tracing: dut VexRiscv _zz_531_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1524 // Tracing: dut VexRiscv _zz_532_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1525 // Tracing: dut VexRiscv _zz_533_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1526 // Tracing: dut VexRiscv _zz_534_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1527 // Tracing: dut VexRiscv _zz_535_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1528 // Tracing: dut VexRiscv _zz_536_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1529 // Tracing: dut VexRiscv _zz_537_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1530 // Tracing: dut VexRiscv _zz_538_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1531 // Tracing: dut VexRiscv _zz_539_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1532 // Tracing: dut VexRiscv _zz_540_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1533 // Tracing: dut VexRiscv _zz_541_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1534 // Tracing: dut VexRiscv _zz_542_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1535 // Tracing: dut VexRiscv _zz_543_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1536 // Tracing: dut VexRiscv _zz_544_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1537 // Tracing: dut VexRiscv _zz_545_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1538 // Tracing: dut VexRiscv _zz_546_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1539 // Tracing: dut VexRiscv _zz_547_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1540 // Tracing: dut VexRiscv _zz_548_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1541 // Tracing: dut VexRiscv _zz_549_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1542 // Tracing: dut VexRiscv _zz_550_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1543 // Tracing: dut VexRiscv _zz_551_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1544 // Tracing: dut VexRiscv _zz_552_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1545 // Tracing: dut VexRiscv _zz_553_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1546 // Tracing: dut VexRiscv _zz_554_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1547 // Tracing: dut VexRiscv _zz_555_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1548 // Tracing: dut VexRiscv _zz_556_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1549 // Tracing: dut VexRiscv _zz_557_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1550 // Tracing: dut VexRiscv _zz_558_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1551 // Tracing: dut VexRiscv _zz_559_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1552 // Tracing: dut VexRiscv _zz_560_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1553 // Tracing: dut VexRiscv _zz_561_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1554 // Tracing: dut VexRiscv _zz_562_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1555 // Tracing: dut VexRiscv _zz_563_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1556 // Tracing: dut VexRiscv _zz_564_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1557 // Tracing: dut VexRiscv _zz_565_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1558 // Tracing: dut VexRiscv _zz_566_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1559 // Tracing: dut VexRiscv _zz_567_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1560 // Tracing: dut VexRiscv _zz_568_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1561 // Tracing: dut VexRiscv _zz_569_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1562 // Tracing: dut VexRiscv _zz_570_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1563 // Tracing: dut VexRiscv _zz_571_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1564 // Tracing: dut VexRiscv _zz_572_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1565 // Tracing: dut VexRiscv _zz_573_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1566 // Tracing: dut VexRiscv _zz_574_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1567 // Tracing: dut VexRiscv _zz_575_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1568 // Tracing: dut VexRiscv _zz_576_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1569 // Tracing: dut VexRiscv _zz_577_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1570 // Tracing: dut VexRiscv _zz_578_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1571 // Tracing: dut VexRiscv _zz_579_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1572 // Tracing: dut VexRiscv _zz_580_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1573 // Tracing: dut VexRiscv _zz_581_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1574 // Tracing: dut VexRiscv _zz_582_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1575 // Tracing: dut VexRiscv _zz_583_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1576 // Tracing: dut VexRiscv _zz_584_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1577 // Tracing: dut VexRiscv _zz_585_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1578 // Tracing: dut VexRiscv _zz_586_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1579 // Tracing: dut VexRiscv _zz_587_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1580 // Tracing: dut VexRiscv _zz_588_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1581 // Tracing: dut VexRiscv _zz_589_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1582 // Tracing: dut VexRiscv _zz_590_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1583 // Tracing: dut VexRiscv _zz_591_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1584 // Tracing: dut VexRiscv _zz_592_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1585 // Tracing: dut VexRiscv _zz_593_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1586 // Tracing: dut VexRiscv _zz_594_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1587 // Tracing: dut VexRiscv _zz_595_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1588 // Tracing: dut VexRiscv _zz_596_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1589 // Tracing: dut VexRiscv _zz_597_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1590 // Tracing: dut VexRiscv _zz_598_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1591 // Tracing: dut VexRiscv _zz_599_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1592 // Tracing: dut VexRiscv _zz_600_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1593 // Tracing: dut VexRiscv _zz_601_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1594 // Tracing: dut VexRiscv _zz_602_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1595 // Tracing: dut VexRiscv _zz_603_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1596 // Tracing: dut VexRiscv _zz_604_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1597 // Tracing: dut VexRiscv _zz_605_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1598 // Tracing: dut VexRiscv _zz_606_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1599 // Tracing: dut VexRiscv _zz_607_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1600 // Tracing: dut VexRiscv _zz_608_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1601 // Tracing: dut VexRiscv _zz_609_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1602 // Tracing: dut VexRiscv _zz_610_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1603 // Tracing: dut VexRiscv _zz_611_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1604 // Tracing: dut VexRiscv _zz_612_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1605 // Tracing: dut VexRiscv _zz_613_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1606 // Tracing: dut VexRiscv _zz_614_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1607 // Tracing: dut VexRiscv _zz_615_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1608 // Tracing: dut VexRiscv _zz_616_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1609 // Tracing: dut VexRiscv _zz_617_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1610 // Tracing: dut VexRiscv _zz_618_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1611 // Tracing: dut VexRiscv _zz_619_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1612 // Tracing: dut VexRiscv _zz_620_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1613 // Tracing: dut VexRiscv _zz_621_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1614 // Tracing: dut VexRiscv _zz_622_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1615 // Tracing: dut VexRiscv _zz_623_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1616 // Tracing: dut VexRiscv _zz_624_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1617 // Tracing: dut VexRiscv _zz_625_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1618 // Tracing: dut VexRiscv _zz_626_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1619 // Tracing: dut VexRiscv _zz_627_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1620 // Tracing: dut VexRiscv _zz_628_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1621 // Tracing: dut VexRiscv _zz_629_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1622 // Tracing: dut VexRiscv _zz_630_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1623 // Tracing: dut VexRiscv _zz_631_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1624 // Tracing: dut VexRiscv _zz_632_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1625 // Tracing: dut VexRiscv _zz_633_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1626 // Tracing: dut VexRiscv _zz_634_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1627 // Tracing: dut VexRiscv _zz_635_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1628 // Tracing: dut VexRiscv _zz_636_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1629 // Tracing: dut VexRiscv _zz_637_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1630 // Tracing: dut VexRiscv _zz_638_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1631 // Tracing: dut VexRiscv _zz_639_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1632 // Tracing: dut VexRiscv _zz_640_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1633 // Tracing: dut VexRiscv _zz_641_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1634 // Tracing: dut VexRiscv _zz_642_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1635 // Tracing: dut VexRiscv _zz_643_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1636 // Tracing: dut VexRiscv _zz_644_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1637 // Tracing: dut VexRiscv _zz_645_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1638 // Tracing: dut VexRiscv _zz_646_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1639 // Tracing: dut VexRiscv _zz_647_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1640 // Tracing: dut VexRiscv _zz_648_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1641 // Tracing: dut VexRiscv _zz_649_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1642 // Tracing: dut VexRiscv _zz_650_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1643 // Tracing: dut VexRiscv _zz_651_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1644 // Tracing: dut VexRiscv _zz_652_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1645 // Tracing: dut VexRiscv _zz_653_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1646 // Tracing: dut VexRiscv _zz_654_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1647 // Tracing: dut VexRiscv _zz_655_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1648 // Tracing: dut VexRiscv _zz_656_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1649 // Tracing: dut VexRiscv _zz_657_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1650 // Tracing: dut VexRiscv _zz_658_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1651 // Tracing: dut VexRiscv _zz_659_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1652 // Tracing: dut VexRiscv _zz_660_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1653 // Tracing: dut VexRiscv _zz_661_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1654 // Tracing: dut VexRiscv _zz_662_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1655 // Tracing: dut VexRiscv _zz_663_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1656 // Tracing: dut VexRiscv _zz_664_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1657 // Tracing: dut VexRiscv _zz_665_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1658 // Tracing: dut VexRiscv _zz_666_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1659 // Tracing: dut VexRiscv _zz_667_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1660 // Tracing: dut VexRiscv _zz_668_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1661 // Tracing: dut VexRiscv _zz_669_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1662 // Tracing: dut VexRiscv _zz_670_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1663 // Tracing: dut VexRiscv _zz_671_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1664 // Tracing: dut VexRiscv _zz_672_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1665 // Tracing: dut VexRiscv _zz_673_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1666 // Tracing: dut VexRiscv _zz_674_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1667 // Tracing: dut VexRiscv _zz_675_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1668 // Tracing: dut VexRiscv _zz_676_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1669 // Tracing: dut VexRiscv _zz_677_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1670 // Tracing: dut VexRiscv _zz_678_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1671 // Tracing: dut VexRiscv _zz_679_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1672 // Tracing: dut VexRiscv _zz_680_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1673 // Tracing: dut VexRiscv _zz_681_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1674 // Tracing: dut VexRiscv _zz_682_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1675 // Tracing: dut VexRiscv _zz_683_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1676 // Tracing: dut VexRiscv _zz_684_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1677 // Tracing: dut VexRiscv _zz_685_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1678 // Tracing: dut VexRiscv _zz_686_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1679 // Tracing: dut VexRiscv _zz_687_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1680 // Tracing: dut VexRiscv _zz_688_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1681 // Tracing: dut VexRiscv _zz_689_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1682 // Tracing: dut VexRiscv _zz_690_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1683 // Tracing: dut VexRiscv _zz_691_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1684 // Tracing: dut VexRiscv _zz_692_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1685 // Tracing: dut VexRiscv _zz_693_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1686 // Tracing: dut VexRiscv _zz_694_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1687 // Tracing: dut VexRiscv _zz_695_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1688 // Tracing: dut VexRiscv _zz_696_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1689 // Tracing: dut VexRiscv _zz_697_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1690 // Tracing: dut VexRiscv _zz_698_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1691 // Tracing: dut VexRiscv _zz_699_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1692 // Tracing: dut VexRiscv _zz_700_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1693 // Tracing: dut VexRiscv _zz_701_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1694 // Tracing: dut VexRiscv _zz_702_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1695 // Tracing: dut VexRiscv _zz_703_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1696 // Tracing: dut VexRiscv _zz_704_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1697 // Tracing: dut VexRiscv _zz_705_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1698 // Tracing: dut VexRiscv _zz_706_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1699 // Tracing: dut VexRiscv _zz_707_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1700 // Tracing: dut VexRiscv _zz_708_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1701 // Tracing: dut VexRiscv _zz_709_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1702 // Tracing: dut VexRiscv _zz_710_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1703 // Tracing: dut VexRiscv _zz_711_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1704 // Tracing: dut VexRiscv _zz_712_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1705 // Tracing: dut VexRiscv _zz_713_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1706 // Tracing: dut VexRiscv _zz_714_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1707 // Tracing: dut VexRiscv _zz_715_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1708 // Tracing: dut VexRiscv _zz_716_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1709 // Tracing: dut VexRiscv _zz_717_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1710 // Tracing: dut VexRiscv _zz_718_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1711 // Tracing: dut VexRiscv _zz_719_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1712 // Tracing: dut VexRiscv _zz_720_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1713 // Tracing: dut VexRiscv _zz_721_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1714 // Tracing: dut VexRiscv _zz_722_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1715 // Tracing: dut VexRiscv _zz_723_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1716 // Tracing: dut VexRiscv _zz_724_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1717 // Tracing: dut VexRiscv _zz_725_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1718 // Tracing: dut VexRiscv _zz_726_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1719 // Tracing: dut VexRiscv _zz_727_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1720 // Tracing: dut VexRiscv _zz_728_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1721 // Tracing: dut VexRiscv _zz_729_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1722 // Tracing: dut VexRiscv _zz_730_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1723 // Tracing: dut VexRiscv _zz_731_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1724 // Tracing: dut VexRiscv _zz_732_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1725 // Tracing: dut VexRiscv _zz_733_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1726 // Tracing: dut VexRiscv _zz_734_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1727 // Tracing: dut VexRiscv _zz_735_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1728 vcdp->declQuad (c+291,"dut VexRiscv execute_MUL_LH",-1,33,0); vcdp->declBit (c+293,"dut VexRiscv decode_IS_DIV",-1); vcdp->declBus (c+294,"dut VexRiscv decode_ALU_BITWISE_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_1_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1732 // Tracing: dut VexRiscv _zz_2_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1733 // Tracing: dut VexRiscv _zz_3_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1734 vcdp->declBus (c+295,"dut VexRiscv decode_ALU_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_4_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1736 // Tracing: dut VexRiscv _zz_5_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1737 // Tracing: dut VexRiscv _zz_6_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1738 vcdp->declBit (c+296,"dut VexRiscv decode_MEMORY_MANAGMENT",-1); // Tracing: dut VexRiscv _zz_7_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1740 // Tracing: dut VexRiscv _zz_8_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1741 // Tracing: dut VexRiscv _zz_9_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1742 // Tracing: dut VexRiscv _zz_10_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1743 vcdp->declBus (c+297,"dut VexRiscv decode_ENV_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_11_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1745 // Tracing: dut VexRiscv _zz_12_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1746 // Tracing: dut VexRiscv _zz_13_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1747 vcdp->declBus (c+684,"dut VexRiscv memory_PC",-1,31,0); vcdp->declBit (c+298,"dut VexRiscv decode_SRC_LESS_UNSIGNED",-1); vcdp->declQuad (c+685,"dut VexRiscv memory_MUL_HH",-1,33,0); vcdp->declQuad (c+299,"dut VexRiscv execute_MUL_HH",-1,33,0); vcdp->declBit (c+301,"dut VexRiscv decode_MEMORY_AMO",-1); vcdp->declBit (c+302,"dut VexRiscv execute_BRANCH_DO",-1); vcdp->declQuad (c+687,"dut VexRiscv memory_MUL_LOW",-1,51,0); vcdp->declBus (c+303,"dut VexRiscv execute_BRANCH_CALC",-1,31,0); vcdp->declBus (c+304,"dut VexRiscv decode_SRC2_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_14_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1757 // Tracing: dut VexRiscv _zz_15_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1758 // Tracing: dut VexRiscv _zz_16_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1759 vcdp->declBit (c+305,"dut VexRiscv execute_IS_DBUS_SHARING",-1); vcdp->declBit (c+306,"dut VexRiscv decode_CSR_READ_OPCODE",-1); vcdp->declBus (c+307,"dut VexRiscv execute_REGFILE_WRITE_DATA",-1,31,0); vcdp->declBit (c+689,"dut VexRiscv execute_BYPASSABLE_MEMORY_STAGE",-1); vcdp->declBit (c+308,"dut VexRiscv decode_BYPASSABLE_MEMORY_STAGE",-1); vcdp->declBit (c+690,"dut VexRiscv memory_IS_MUL",-1); vcdp->declBit (c+691,"dut VexRiscv execute_IS_MUL",-1); vcdp->declBit (c+309,"dut VexRiscv decode_IS_MUL",-1); vcdp->declBus (c+310,"dut VexRiscv execute_MUL_LL",-1,31,0); vcdp->declBit (c+311,"dut VexRiscv decode_IS_RS1_SIGNED",-1); vcdp->declBus (c+692,"dut VexRiscv writeBack_FORMAL_PC_NEXT",-1,31,0); vcdp->declBus (c+693,"dut VexRiscv memory_FORMAL_PC_NEXT",-1,31,0); vcdp->declBus (c+694,"dut VexRiscv execute_FORMAL_PC_NEXT",-1,31,0); vcdp->declBus (c+1081,"dut VexRiscv decode_FORMAL_PC_NEXT",-1,31,0); vcdp->declQuad (c+312,"dut VexRiscv execute_MUL_HL",-1,33,0); vcdp->declBus (c+695,"dut VexRiscv memory_MEMORY_ADDRESS_LOW",-1,1,0); vcdp->declBus (c+314,"dut VexRiscv execute_MEMORY_ADDRESS_LOW",-1,1,0); // Tracing: dut VexRiscv _zz_17_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1777 // Tracing: dut VexRiscv _zz_18_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1778 vcdp->declBit (c+696,"dut VexRiscv memory_IS_SFENCE_VMA",-1); vcdp->declBit (c+697,"dut VexRiscv execute_IS_SFENCE_VMA",-1); vcdp->declBit (c+315,"dut VexRiscv decode_IS_SFENCE_VMA",-1); vcdp->declBit (c+698,"dut VexRiscv memory_MEMORY_WR",-1); vcdp->declBit (c+316,"dut VexRiscv decode_MEMORY_WR",-1); vcdp->declBit (c+317,"dut VexRiscv decode_SRC2_FORCE_ZERO",-1); vcdp->declBit (c+318,"dut VexRiscv decode_IS_RS2_SIGNED",-1); vcdp->declBus (c+319,"dut VexRiscv decode_SRC1_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_19_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1787 // Tracing: dut VexRiscv _zz_20_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1788 // Tracing: dut VexRiscv _zz_21_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1789 // Tracing: dut VexRiscv _zz_22_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1790 // Tracing: dut VexRiscv _zz_23_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1791 vcdp->declBus (c+320,"dut VexRiscv decode_SHIFT_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_24_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1793 // Tracing: dut VexRiscv _zz_25_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1794 // Tracing: dut VexRiscv _zz_26_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1795 vcdp->declBit (c+321,"dut VexRiscv decode_IS_CSR",-1); vcdp->declBus (c+322,"dut VexRiscv execute_SHIFT_RIGHT",-1,31,0); vcdp->declBit (c+323,"dut VexRiscv decode_CSR_WRITE_OPCODE",-1); vcdp->declBit (c+324,"dut VexRiscv decode_BYPASSABLE_EXECUTE_STAGE",-1); vcdp->declBit (c+325,"dut VexRiscv decode_MEMORY_LRSC",-1); vcdp->declBit (c+326,"dut VexRiscv decode_PREDICTION_HAD_BRANCHED2",-1); vcdp->declBit (c+699,"dut VexRiscv execute_IS_RS1_SIGNED",-1); vcdp->declBit (c+700,"dut VexRiscv execute_IS_DIV",-1); vcdp->declBit (c+701,"dut VexRiscv execute_IS_RS2_SIGNED",-1); vcdp->declBit (c+702,"dut VexRiscv memory_IS_DIV",-1); vcdp->declBit (c+703,"dut VexRiscv writeBack_IS_MUL",-1); vcdp->declQuad (c+704,"dut VexRiscv writeBack_MUL_HH",-1,33,0); vcdp->declQuad (c+706,"dut VexRiscv writeBack_MUL_LOW",-1,51,0); vcdp->declQuad (c+708,"dut VexRiscv memory_MUL_HL",-1,33,0); vcdp->declQuad (c+710,"dut VexRiscv memory_MUL_LH",-1,33,0); vcdp->declBus (c+712,"dut VexRiscv memory_MUL_LL",-1,31,0); // Tracing: dut VexRiscv _zz_27_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1812 // Tracing: dut VexRiscv _zz_28_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1813 // Tracing: dut VexRiscv _zz_29_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1814 // Tracing: dut VexRiscv _zz_30_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1815 // Tracing: dut VexRiscv _zz_31_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1816 vcdp->declBit (c+713,"dut VexRiscv execute_CSR_READ_OPCODE",-1); vcdp->declBit (c+714,"dut VexRiscv execute_CSR_WRITE_OPCODE",-1); vcdp->declBit (c+715,"dut VexRiscv execute_IS_CSR",-1); vcdp->declBus (c+716,"dut VexRiscv memory_ENV_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_32_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1821 vcdp->declBus (c+717,"dut VexRiscv execute_ENV_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_33_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1823 // Tracing: dut VexRiscv _zz_34_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1824 // Tracing: dut VexRiscv _zz_35_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1825 vcdp->declBus (c+718,"dut VexRiscv writeBack_ENV_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_36_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1827 vcdp->declBus (c+719,"dut VexRiscv memory_BRANCH_CALC",-1,31,0); vcdp->declBit (c+720,"dut VexRiscv memory_BRANCH_DO",-1); // Tracing: dut VexRiscv _zz_37_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1830 vcdp->declBus (c+721,"dut VexRiscv execute_PC",-1,31,0); vcdp->declBus (c+722,"dut VexRiscv execute_RS1",-1,31,0); vcdp->declBit (c+327,"dut VexRiscv execute_BRANCH_COND_RESULT",-1); vcdp->declBit (c+723,"dut VexRiscv execute_PREDICTION_HAD_BRANCHED2",-1); // Tracing: dut VexRiscv _zz_38_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1835 vcdp->declBus (c+724,"dut VexRiscv execute_BRANCH_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_39_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1837 // Tracing: dut VexRiscv _zz_40_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1838 // Tracing: dut VexRiscv _zz_41_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1839 vcdp->declBit (c+328,"dut VexRiscv decode_RS2_USE",-1); vcdp->declBit (c+329,"dut VexRiscv decode_RS1_USE",-1); // Tracing: dut VexRiscv _zz_42_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1842 vcdp->declBit (c+725,"dut VexRiscv execute_REGFILE_WRITE_VALID",-1); vcdp->declBit (c+726,"dut VexRiscv execute_BYPASSABLE_EXECUTE_STAGE",-1); vcdp->declBit (c+727,"dut VexRiscv memory_REGFILE_WRITE_VALID",-1); vcdp->declBus (c+728,"dut VexRiscv memory_INSTRUCTION",-1,31,0); vcdp->declBit (c+729,"dut VexRiscv memory_BYPASSABLE_MEMORY_STAGE",-1); vcdp->declBit (c+730,"dut VexRiscv writeBack_REGFILE_WRITE_VALID",-1); vcdp->declBus (c+330,"dut VexRiscv decode_RS2",-1,31,0); vcdp->declBus (c+331,"dut VexRiscv decode_RS1",-1,31,0); vcdp->declBus (c+731,"dut VexRiscv memory_SHIFT_RIGHT",-1,31,0); // Tracing: dut VexRiscv _zz_43_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1852 vcdp->declBus (c+732,"dut VexRiscv memory_SHIFT_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_44_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1854 // Tracing: dut VexRiscv _zz_45_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1855 vcdp->declBus (c+733,"dut VexRiscv execute_SHIFT_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_46_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1857 // Tracing: dut VexRiscv _zz_47_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1858 // Tracing: dut VexRiscv _zz_48_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1859 // Tracing: dut VexRiscv _zz_49_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1860 vcdp->declBit (c+734,"dut VexRiscv execute_SRC_LESS_UNSIGNED",-1); vcdp->declBit (c+735,"dut VexRiscv execute_SRC2_FORCE_ZERO",-1); vcdp->declBit (c+736,"dut VexRiscv execute_SRC_USE_SUB_LESS",-1); // Tracing: dut VexRiscv _zz_50_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1864 vcdp->declBus (c+737,"dut VexRiscv execute_SRC2_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_51_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1866 // Tracing: dut VexRiscv _zz_52_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1867 vcdp->declBit (c+738,"dut VexRiscv execute_IS_RVC",-1); vcdp->declBus (c+739,"dut VexRiscv execute_SRC1_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_53_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1870 // Tracing: dut VexRiscv _zz_54_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1871 vcdp->declBit (c+332,"dut VexRiscv decode_SRC_USE_SUB_LESS",-1); vcdp->declBit (c+333,"dut VexRiscv decode_SRC_ADD_ZERO",-1); // Tracing: dut VexRiscv _zz_55_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1874 vcdp->declBus (c+334,"dut VexRiscv execute_SRC_ADD_SUB",-1,31,0); vcdp->declBit (c+335,"dut VexRiscv execute_SRC_LESS",-1); vcdp->declBus (c+740,"dut VexRiscv execute_ALU_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_56_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1878 // Tracing: dut VexRiscv _zz_57_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1879 vcdp->declBus (c+336,"dut VexRiscv execute_SRC2",-1,31,0); vcdp->declBus (c+337,"dut VexRiscv execute_SRC1",-1,31,0); vcdp->declBus (c+741,"dut VexRiscv execute_ALU_BITWISE_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_58_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1883 // Tracing: dut VexRiscv _zz_59_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1884 // Tracing: dut VexRiscv _zz_60_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1885 // Tracing: dut VexRiscv _zz_61_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1886 // Tracing: dut VexRiscv _zz_62_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1887 // Tracing: dut VexRiscv _zz_63_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1888 vcdp->declBit (c+338,"dut VexRiscv decode_REGFILE_WRITE_VALID",-1); vcdp->declBit (c+339,"dut VexRiscv decode_LEGAL_INSTRUCTION",-1); vcdp->declBit (c+1133,"dut VexRiscv decode_INSTRUCTION_READY",-1); // Tracing: dut VexRiscv _zz_64_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1892 // Tracing: dut VexRiscv _zz_65_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1893 // Tracing: dut VexRiscv _zz_66_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1894 // Tracing: dut VexRiscv _zz_67_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1895 // Tracing: dut VexRiscv _zz_68_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1896 // Tracing: dut VexRiscv _zz_69_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1897 // Tracing: dut VexRiscv _zz_70_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1898 // Tracing: dut VexRiscv _zz_71_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1899 // Tracing: dut VexRiscv _zz_72_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1900 // Tracing: dut VexRiscv _zz_73_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1901 // Tracing: dut VexRiscv _zz_74_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1902 // Tracing: dut VexRiscv _zz_75_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1903 // Tracing: dut VexRiscv _zz_76_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1904 // Tracing: dut VexRiscv _zz_77_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1905 // Tracing: dut VexRiscv _zz_78_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1906 // Tracing: dut VexRiscv _zz_79_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1907 // Tracing: dut VexRiscv _zz_80_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1908 // Tracing: dut VexRiscv _zz_81_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1909 // Tracing: dut VexRiscv _zz_82_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1910 // Tracing: dut VexRiscv _zz_83_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1911 // Tracing: dut VexRiscv _zz_84_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1912 // Tracing: dut VexRiscv _zz_85_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1913 // Tracing: dut VexRiscv _zz_86_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1914 // Tracing: dut VexRiscv _zz_87_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1915 // Tracing: dut VexRiscv _zz_88_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1916 // Tracing: dut VexRiscv _zz_89_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1917 // Tracing: dut VexRiscv _zz_90_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1918 // Tracing: dut VexRiscv _zz_91_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1919 vcdp->declBit (c+742,"dut VexRiscv writeBack_IS_SFENCE_VMA",-1); vcdp->declBit (c+743,"dut VexRiscv writeBack_IS_DBUS_SHARING",-1); vcdp->declBit (c+744,"dut VexRiscv memory_IS_DBUS_SHARING",-1); // Tracing: dut VexRiscv _zz_92_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1923 // Tracing: dut VexRiscv _zz_93_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1924 vcdp->declBus (c+745,"dut VexRiscv writeBack_MEMORY_ADDRESS_LOW",-1,1,0); vcdp->declBit (c+746,"dut VexRiscv writeBack_MEMORY_WR",-1); vcdp->declBus (c+747,"dut VexRiscv writeBack_REGFILE_WRITE_DATA",-1,31,0); vcdp->declBit (c+748,"dut VexRiscv writeBack_MEMORY_ENABLE",-1); vcdp->declBus (c+681,"dut VexRiscv memory_REGFILE_WRITE_DATA",-1,31,0); vcdp->declBit (c+749,"dut VexRiscv memory_MEMORY_ENABLE",-1); // Tracing: dut VexRiscv _zz_94_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1931 vcdp->declBit (c+750,"dut VexRiscv execute_MEMORY_AMO",-1); vcdp->declBit (c+751,"dut VexRiscv execute_MEMORY_LRSC",-1); vcdp->declBit (c+752,"dut VexRiscv execute_MEMORY_MANAGMENT",-1); vcdp->declBus (c+753,"dut VexRiscv execute_RS2",-1,31,0); vcdp->declBit (c+754,"dut VexRiscv execute_MEMORY_WR",-1); vcdp->declBus (c+334,"dut VexRiscv execute_SRC_ADD",-1,31,0); vcdp->declBit (c+755,"dut VexRiscv execute_MEMORY_ENABLE",-1); vcdp->declBus (c+756,"dut VexRiscv execute_INSTRUCTION",-1,31,0); vcdp->declBit (c+340,"dut VexRiscv decode_MEMORY_ENABLE",-1); vcdp->declBit (c+341,"dut VexRiscv decode_FLUSH_ALL",-1); vcdp->declBit (c+342,"dut VexRiscv IBusCachedPlugin_rsp_issueDetected",-1); // Tracing: dut VexRiscv _zz_95_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1943 // Tracing: dut VexRiscv _zz_96_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1944 // Tracing: dut VexRiscv _zz_97_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1945 vcdp->declBus (c+343,"dut VexRiscv decode_BRANCH_CTRL",-1,1,0); // Tracing: dut VexRiscv _zz_98_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1947 vcdp->declBus (c+344,"dut VexRiscv decode_INSTRUCTION",-1,31,0); // Tracing: dut VexRiscv _zz_99_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1949 // Tracing: dut VexRiscv _zz_100_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1950 vcdp->declBus (c+1082,"dut VexRiscv decode_PC",-1,31,0); // Tracing: dut VexRiscv _zz_101_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1952 // Tracing: dut VexRiscv _zz_102_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1953 // Tracing: dut VexRiscv _zz_103_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1954 // Tracing: dut VexRiscv _zz_104_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:1955 vcdp->declBit (c+345,"dut VexRiscv decode_IS_RVC",-1); vcdp->declBus (c+757,"dut VexRiscv writeBack_PC",-1,31,0); vcdp->declBus (c+758,"dut VexRiscv writeBack_INSTRUCTION",-1,31,0); vcdp->declBit (c+346,"dut VexRiscv decode_arbitration_haltItself",-1); vcdp->declBit (c+347,"dut VexRiscv decode_arbitration_haltByOther",-1); vcdp->declBit (c+348,"dut VexRiscv decode_arbitration_removeIt",-1); vcdp->declBit (c+1128,"dut VexRiscv decode_arbitration_flushIt",-1); vcdp->declBit (c+349,"dut VexRiscv decode_arbitration_flushNext",-1); vcdp->declBit (c+350,"dut VexRiscv decode_arbitration_isValid",-1); vcdp->declBit (c+351,"dut VexRiscv decode_arbitration_isStuck",-1); vcdp->declBit (c+352,"dut VexRiscv decode_arbitration_isStuckByOthers",-1); vcdp->declBit (c+353,"dut VexRiscv decode_arbitration_isFlushed",-1); vcdp->declBit (c+354,"dut VexRiscv decode_arbitration_isMoving",-1); vcdp->declBit (c+355,"dut VexRiscv decode_arbitration_isFiring",-1); vcdp->declBit (c+356,"dut VexRiscv execute_arbitration_haltItself",-1); vcdp->declBit (c+1128,"dut VexRiscv execute_arbitration_haltByOther",-1); vcdp->declBit (c+357,"dut VexRiscv execute_arbitration_removeIt",-1); vcdp->declBit (c+1128,"dut VexRiscv execute_arbitration_flushIt",-1); vcdp->declBit (c+358,"dut VexRiscv execute_arbitration_flushNext",-1); vcdp->declBit (c+759,"dut VexRiscv execute_arbitration_isValid",-1); vcdp->declBit (c+359,"dut VexRiscv execute_arbitration_isStuck",-1); vcdp->declBit (c+360,"dut VexRiscv execute_arbitration_isStuckByOthers",-1); vcdp->declBit (c+361,"dut VexRiscv execute_arbitration_isFlushed",-1); vcdp->declBit (c+362,"dut VexRiscv execute_arbitration_isMoving",-1); vcdp->declBit (c+363,"dut VexRiscv execute_arbitration_isFiring",-1); vcdp->declBit (c+364,"dut VexRiscv memory_arbitration_haltItself",-1); vcdp->declBit (c+1128,"dut VexRiscv memory_arbitration_haltByOther",-1); vcdp->declBit (c+365,"dut VexRiscv memory_arbitration_removeIt",-1); vcdp->declBit (c+1128,"dut VexRiscv memory_arbitration_flushIt",-1); vcdp->declBit (c+366,"dut VexRiscv memory_arbitration_flushNext",-1); vcdp->declBit (c+760,"dut VexRiscv memory_arbitration_isValid",-1); vcdp->declBit (c+367,"dut VexRiscv memory_arbitration_isStuck",-1); vcdp->declBit (c+368,"dut VexRiscv memory_arbitration_isStuckByOthers",-1); vcdp->declBit (c+369,"dut VexRiscv memory_arbitration_isFlushed",-1); vcdp->declBit (c+370,"dut VexRiscv memory_arbitration_isMoving",-1); vcdp->declBit (c+371,"dut VexRiscv memory_arbitration_isFiring",-1); vcdp->declBit (c+368,"dut VexRiscv writeBack_arbitration_haltItself",-1); vcdp->declBit (c+1128,"dut VexRiscv writeBack_arbitration_haltByOther",-1); vcdp->declBit (c+372,"dut VexRiscv writeBack_arbitration_removeIt",-1); vcdp->declBit (c+373,"dut VexRiscv writeBack_arbitration_flushIt",-1); vcdp->declBit (c+374,"dut VexRiscv writeBack_arbitration_flushNext",-1); vcdp->declBit (c+761,"dut VexRiscv writeBack_arbitration_isValid",-1); vcdp->declBit (c+368,"dut VexRiscv writeBack_arbitration_isStuck",-1); vcdp->declBit (c+1128,"dut VexRiscv writeBack_arbitration_isStuckByOthers",-1); vcdp->declBit (c+373,"dut VexRiscv writeBack_arbitration_isFlushed",-1); vcdp->declBit (c+375,"dut VexRiscv writeBack_arbitration_isMoving",-1); vcdp->declBit (c+376,"dut VexRiscv writeBack_arbitration_isFiring",-1); vcdp->declBus (c+1083,"dut VexRiscv lastStageInstruction",-1,31,0); vcdp->declBus (c+1084,"dut VexRiscv lastStagePc",-1,31,0); vcdp->declBit (c+1085,"dut VexRiscv lastStageIsValid",-1); vcdp->declBit (c+1086,"dut VexRiscv lastStageIsFiring",-1); vcdp->declBit (c+377,"dut VexRiscv IBusCachedPlugin_fetcherHalt",-1); vcdp->declBit (c+378,"dut VexRiscv IBusCachedPlugin_fetcherflushIt",-1); vcdp->declBit (c+379,"dut VexRiscv IBusCachedPlugin_incomingInstruction",-1); vcdp->declBit (c+380,"dut VexRiscv IBusCachedPlugin_predictionJumpInterface_valid",-1); vcdp->declBus (c+381,"dut VexRiscv IBusCachedPlugin_predictionJumpInterface_payload",-1,31,0); vcdp->declBit (c+326,"dut VexRiscv IBusCachedPlugin_decodePrediction_cmd_hadBranch",-1); vcdp->declBit (c+382,"dut VexRiscv IBusCachedPlugin_decodePrediction_rsp_wasWrong",-1); vcdp->declBit (c+762,"dut VexRiscv IBusCachedPlugin_pcValids_0",-1); vcdp->declBit (c+763,"dut VexRiscv IBusCachedPlugin_pcValids_1",-1); vcdp->declBit (c+764,"dut VexRiscv IBusCachedPlugin_pcValids_2",-1); vcdp->declBit (c+765,"dut VexRiscv IBusCachedPlugin_pcValids_3",-1); vcdp->declBit (c+383,"dut VexRiscv IBusCachedPlugin_redoBranch_valid",-1); vcdp->declBus (c+1082,"dut VexRiscv IBusCachedPlugin_redoBranch_payload",-1,31,0); vcdp->declBit (c+384,"dut VexRiscv IBusCachedPlugin_decodeExceptionPort_valid",-1); vcdp->declBus (c+385,"dut VexRiscv IBusCachedPlugin_decodeExceptionPort_payload_code",-1,3,0); vcdp->declBus (c+766,"dut VexRiscv IBusCachedPlugin_decodeExceptionPort_payload_badAddr",-1,31,0); vcdp->declBit (c+273,"dut VexRiscv IBusCachedPlugin_mmuBus_cmd_isValid",-1); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_mmuBus_cmd_virtualAddress",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_mmuBus_cmd_bypassTranslation",-1); vcdp->declBus (c+272,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_physicalAddress",-1,31,0); vcdp->declBit (c+386,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_isIoAccess",-1); vcdp->declBit (c+387,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_allowRead",-1); vcdp->declBit (c+388,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_allowWrite",-1); vcdp->declBit (c+389,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_allowExecute",-1); vcdp->declBit (c+390,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_exception",-1); vcdp->declBit (c+391,"dut VexRiscv IBusCachedPlugin_mmuBus_rsp_refilling",-1); vcdp->declBit (c+274,"dut VexRiscv IBusCachedPlugin_mmuBus_end",-1); vcdp->declBit (c+672,"dut VexRiscv IBusCachedPlugin_mmuBus_busy",-1); vcdp->declBit (c+276,"dut VexRiscv DBusCachedPlugin_mmuBus_cmd_isValid",-1); vcdp->declBus (c+681,"dut VexRiscv DBusCachedPlugin_mmuBus_cmd_virtualAddress",-1,31,0); vcdp->declBit (c+392,"dut VexRiscv DBusCachedPlugin_mmuBus_cmd_bypassTranslation",-1); vcdp->declBus (c+393,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_physicalAddress",-1,31,0); vcdp->declBit (c+394,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_isIoAccess",-1); vcdp->declBit (c+395,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_allowRead",-1); vcdp->declBit (c+396,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_allowWrite",-1); vcdp->declBit (c+397,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_allowExecute",-1); vcdp->declBit (c+398,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_exception",-1); vcdp->declBit (c+399,"dut VexRiscv DBusCachedPlugin_mmuBus_rsp_refilling",-1); vcdp->declBit (c+277,"dut VexRiscv DBusCachedPlugin_mmuBus_end",-1); vcdp->declBit (c+767,"dut VexRiscv DBusCachedPlugin_mmuBus_busy",-1); vcdp->declBit (c+400,"dut VexRiscv DBusCachedPlugin_redoBranch_valid",-1); vcdp->declBus (c+757,"dut VexRiscv DBusCachedPlugin_redoBranch_payload",-1,31,0); vcdp->declBit (c+401,"dut VexRiscv DBusCachedPlugin_exceptionBus_valid",-1); vcdp->declBus (c+402,"dut VexRiscv DBusCachedPlugin_exceptionBus_payload_code",-1,3,0); vcdp->declBus (c+747,"dut VexRiscv DBusCachedPlugin_exceptionBus_payload_badAddr",-1,31,0); vcdp->declBit (c+403,"dut VexRiscv MmuPlugin_dBusAccess_cmd_valid",-1); vcdp->declBit (c+404,"dut VexRiscv MmuPlugin_dBusAccess_cmd_ready",-1); vcdp->declBus (c+405,"dut VexRiscv MmuPlugin_dBusAccess_cmd_payload_address",-1,31,0); vcdp->declBus (c+1134,"dut VexRiscv MmuPlugin_dBusAccess_cmd_payload_size",-1,1,0); vcdp->declBit (c+1128,"dut VexRiscv MmuPlugin_dBusAccess_cmd_payload_write",-1); vcdp->declBus (c+1129,"dut VexRiscv MmuPlugin_dBusAccess_cmd_payload_data",-1,31,0); vcdp->declBus (c+1135,"dut VexRiscv MmuPlugin_dBusAccess_cmd_payload_writeMask",-1,3,0); vcdp->declBit (c+406,"dut VexRiscv MmuPlugin_dBusAccess_rsp_valid",-1); vcdp->declBus (c+279,"dut VexRiscv MmuPlugin_dBusAccess_rsp_payload_data",-1,31,0); vcdp->declBit (c+407,"dut VexRiscv MmuPlugin_dBusAccess_rsp_payload_error",-1); vcdp->declBit (c+284,"dut VexRiscv MmuPlugin_dBusAccess_rsp_payload_redo",-1); vcdp->declBit (c+408,"dut VexRiscv decodeExceptionPort_valid",-1); vcdp->declBus (c+1136,"dut VexRiscv decodeExceptionPort_payload_code",-1,3,0); vcdp->declBus (c+344,"dut VexRiscv decodeExceptionPort_payload_badAddr",-1,31,0); vcdp->declBit (c+382,"dut VexRiscv BranchPlugin_jumpInterface_valid",-1); vcdp->declBus (c+719,"dut VexRiscv BranchPlugin_jumpInterface_payload",-1,31,0); vcdp->declBit (c+409,"dut VexRiscv CsrPlugin_jumpInterface_valid",-1); vcdp->declBus (c+410,"dut VexRiscv CsrPlugin_jumpInterface_payload",-1,31,0); vcdp->declBit (c+768,"dut VexRiscv CsrPlugin_exceptionPendings_0",-1); vcdp->declBit (c+769,"dut VexRiscv CsrPlugin_exceptionPendings_1",-1); vcdp->declBit (c+770,"dut VexRiscv CsrPlugin_exceptionPendings_2",-1); vcdp->declBit (c+771,"dut VexRiscv CsrPlugin_exceptionPendings_3",-1); vcdp->declBit (c+411,"dut VexRiscv externalInterrupt",-1); vcdp->declBit (c+412,"dut VexRiscv externalInterruptS",-1); vcdp->declBit (c+409,"dut VexRiscv contextSwitching",-1); vcdp->declBus (c+772,"dut VexRiscv CsrPlugin_privilege",-1,1,0); vcdp->declBit (c+1128,"dut VexRiscv CsrPlugin_forceMachineWire",-1); vcdp->declBit (c+413,"dut VexRiscv CsrPlugin_selfException_valid",-1); vcdp->declBus (c+414,"dut VexRiscv CsrPlugin_selfException_payload_code",-1,3,0); vcdp->declBus (c+756,"dut VexRiscv CsrPlugin_selfException_payload_badAddr",-1,31,0); vcdp->declBit (c+1133,"dut VexRiscv CsrPlugin_allowInterrupts",-1); vcdp->declBit (c+1133,"dut VexRiscv CsrPlugin_allowException",-1); vcdp->declBit (c+415,"dut VexRiscv IBusCachedPlugin_jump_pcLoad_valid",-1); vcdp->declBus (c+416,"dut VexRiscv IBusCachedPlugin_jump_pcLoad_payload",-1,31,0); // Tracing: dut VexRiscv _zz_105_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2086 // Tracing: dut VexRiscv _zz_106_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2087 // Tracing: dut VexRiscv _zz_107_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2088 // Tracing: dut VexRiscv _zz_108_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2089 // Tracing: dut VexRiscv _zz_109_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2090 // Tracing: dut VexRiscv _zz_110_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2091 vcdp->declBit (c+417,"dut VexRiscv IBusCachedPlugin_fetchPc_output_valid",-1); vcdp->declBit (c+418,"dut VexRiscv IBusCachedPlugin_fetchPc_output_ready",-1); vcdp->declBus (c+419,"dut VexRiscv IBusCachedPlugin_fetchPc_output_payload",-1,31,0); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_fetchPc_pcReg",-1,31,0); vcdp->declBit (c+420,"dut VexRiscv IBusCachedPlugin_fetchPc_corrected",-1); vcdp->declBit (c+421,"dut VexRiscv IBusCachedPlugin_fetchPc_pcRegPropagate",-1); vcdp->declBit (c+773,"dut VexRiscv IBusCachedPlugin_fetchPc_booted",-1); vcdp->declBit (c+774,"dut VexRiscv IBusCachedPlugin_fetchPc_inc",-1); vcdp->declBus (c+419,"dut VexRiscv IBusCachedPlugin_fetchPc_pc",-1,31,0); vcdp->declBus (c+1082,"dut VexRiscv IBusCachedPlugin_decodePc_pcReg",-1,31,0); vcdp->declBus (c+1081,"dut VexRiscv IBusCachedPlugin_decodePc_pcPlus",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_decodePc_injectedDecode",-1); vcdp->declBit (c+417,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_input_valid",-1); vcdp->declBit (c+418,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_input_ready",-1); vcdp->declBus (c+419,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_input_payload",-1,31,0); vcdp->declBit (c+422,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_output_valid",-1); vcdp->declBit (c+423,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_output_ready",-1); vcdp->declBus (c+419,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_output_payload",-1,31,0); vcdp->declBit (c+424,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_halt",-1); vcdp->declBit (c+1133,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_0_inputSample",-1); vcdp->declBit (c+775,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_input_valid",-1); vcdp->declBit (c+423,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_input_ready",-1); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_input_payload",-1,31,0); vcdp->declBit (c+425,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_output_valid",-1); vcdp->declBit (c+426,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_output_ready",-1); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_output_payload",-1,31,0); vcdp->declBit (c+427,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_halt",-1); vcdp->declBit (c+1137,"dut VexRiscv IBusCachedPlugin_iBusRsp_stages_1_inputSample",-1); vcdp->declBit (c+776,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid",-1); vcdp->declBit (c+426,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready",-1); vcdp->declBus (c+777,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload",-1,31,0); vcdp->declBit (c+428,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid",-1); vcdp->declBit (c+429,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready",-1); vcdp->declBus (c+777,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload",-1,31,0); vcdp->declBit (c+430,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt",-1); vcdp->declBit (c+1138,"dut VexRiscv IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample",-1); // Tracing: dut VexRiscv _zz_111_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2128 // Tracing: dut VexRiscv _zz_112_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2129 // Tracing: dut VexRiscv _zz_113_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2130 // Tracing: dut VexRiscv _zz_114_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2131 // Tracing: dut VexRiscv _zz_115_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2132 // Tracing: dut VexRiscv _zz_116_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2133 // Tracing: dut VexRiscv _zz_117_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2134 // Tracing: dut VexRiscv _zz_118_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2135 // Tracing: dut VexRiscv _zz_119_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2136 vcdp->declBit (c+431,"dut VexRiscv IBusCachedPlugin_iBusRsp_readyForError",-1); vcdp->declBit (c+428,"dut VexRiscv IBusCachedPlugin_iBusRsp_output_valid",-1); vcdp->declBit (c+429,"dut VexRiscv IBusCachedPlugin_iBusRsp_output_ready",-1); vcdp->declBus (c+777,"dut VexRiscv IBusCachedPlugin_iBusRsp_output_payload_pc",-1,31,0); vcdp->declBit (c+1139,"dut VexRiscv IBusCachedPlugin_iBusRsp_output_payload_rsp_error",-1); vcdp->declBus (c+676,"dut VexRiscv IBusCachedPlugin_iBusRsp_output_payload_rsp_inst",-1,31,0); vcdp->declBit (c+1140,"dut VexRiscv IBusCachedPlugin_iBusRsp_output_payload_isRvc",-1); vcdp->declBit (c+432,"dut VexRiscv IBusCachedPlugin_decompressor_decodeInput_valid",-1); vcdp->declBit (c+433,"dut VexRiscv IBusCachedPlugin_decompressor_decodeInput_ready",-1); vcdp->declBus (c+777,"dut VexRiscv IBusCachedPlugin_decompressor_decodeInput_payload_pc",-1,31,0); vcdp->declBit (c+1141,"dut VexRiscv IBusCachedPlugin_decompressor_decodeInput_payload_rsp_error",-1); vcdp->declBus (c+344,"dut VexRiscv IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst",-1,31,0); vcdp->declBit (c+345,"dut VexRiscv IBusCachedPlugin_decompressor_decodeInput_payload_isRvc",-1); vcdp->declBit (c+778,"dut VexRiscv IBusCachedPlugin_decompressor_bufferValid",-1); vcdp->declBus (c+779,"dut VexRiscv IBusCachedPlugin_decompressor_bufferData",-1,15,0); vcdp->declBus (c+434,"dut VexRiscv IBusCachedPlugin_decompressor_rawInDecode",-1,31,0); vcdp->declBit (c+345,"dut VexRiscv IBusCachedPlugin_decompressor_isRvc",-1); // Tracing: dut VexRiscv _zz_120_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2154 vcdp->declBus (c+435,"dut VexRiscv IBusCachedPlugin_decompressor_decompressed",-1,31,0); // Tracing: dut VexRiscv _zz_121_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2156 // Tracing: dut VexRiscv _zz_122_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2157 // Tracing: dut VexRiscv _zz_123_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2158 // Tracing: dut VexRiscv _zz_124_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2159 // Tracing: dut VexRiscv _zz_125_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2160 // Tracing: dut VexRiscv _zz_126_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2161 // Tracing: dut VexRiscv _zz_127_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2162 // Tracing: dut VexRiscv _zz_128_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2163 // Tracing: dut VexRiscv _zz_129_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2164 // Tracing: dut VexRiscv _zz_130_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2165 // Tracing: dut VexRiscv _zz_131_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2166 // Tracing: dut VexRiscv _zz_132_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2167 // Tracing: dut VexRiscv _zz_133_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2168 // Tracing: dut VexRiscv _zz_134_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2169 // Tracing: dut VexRiscv _zz_135_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2170 // Tracing: dut VexRiscv _zz_136_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2171 // Tracing: dut VexRiscv _zz_137_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2172 // Tracing: dut VexRiscv _zz_138_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2173 // Tracing: dut VexRiscv _zz_139_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2174 // Tracing: dut VexRiscv _zz_140_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2175 // Tracing: dut VexRiscv _zz_141_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2176 // Tracing: dut VexRiscv _zz_142_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2177 // Tracing: dut VexRiscv _zz_143_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2178 // Tracing: dut VexRiscv _zz_144_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2179 // Tracing: dut VexRiscv _zz_145_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2180 // Tracing: dut VexRiscv _zz_146_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2181 vcdp->declBit (c+436,"dut VexRiscv IBusCachedPlugin_decompressor_bufferFill",-1); vcdp->declBit (c+762,"dut VexRiscv IBusCachedPlugin_injector_nextPcCalc_valids_0",-1); vcdp->declBit (c+763,"dut VexRiscv IBusCachedPlugin_injector_nextPcCalc_valids_1",-1); vcdp->declBit (c+764,"dut VexRiscv IBusCachedPlugin_injector_nextPcCalc_valids_2",-1); vcdp->declBit (c+765,"dut VexRiscv IBusCachedPlugin_injector_nextPcCalc_valids_3",-1); vcdp->declBit (c+780,"dut VexRiscv IBusCachedPlugin_injector_decodeRemoved",-1); // Tracing: dut VexRiscv _zz_147_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2188 // Tracing: dut VexRiscv _zz_148_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2189 // Tracing: dut VexRiscv _zz_149_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2190 // Tracing: dut VexRiscv _zz_150_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2191 // Tracing: dut VexRiscv _zz_151_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2192 // Tracing: dut VexRiscv _zz_152_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2193 vcdp->declBit (c+275,"dut VexRiscv iBus_cmd_valid",-1); vcdp->declBit (c+437,"dut VexRiscv iBus_cmd_ready",-1); vcdp->declBus (c+679,"dut VexRiscv iBus_cmd_payload_address",-1,31,0); vcdp->declBus (c+1132,"dut VexRiscv iBus_cmd_payload_size",-1,2,0); vcdp->declBit (c+781,"dut VexRiscv iBus_rsp_valid",-1); vcdp->declBus (c+782,"dut VexRiscv iBus_rsp_payload_data",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv iBus_rsp_payload_error",-1); // Tracing: dut VexRiscv _zz_153_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2201 vcdp->declBus (c+783,"dut VexRiscv IBusCachedPlugin_rspCounter",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_s0_tightlyCoupledHit",-1); vcdp->declBit (c+784,"dut VexRiscv IBusCachedPlugin_s1_tightlyCoupledHit",-1); vcdp->declBit (c+785,"dut VexRiscv IBusCachedPlugin_s2_tightlyCoupledHit",-1); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_rsp_iBusRspOutputHalt",-1); vcdp->declBit (c+383,"dut VexRiscv IBusCachedPlugin_rsp_redoFetch",-1); vcdp->declBit (c+629,"dut VexRiscv dBus_cmd_valid",-1); vcdp->declBit (c+438,"dut VexRiscv dBus_cmd_ready",-1); vcdp->declBit (c+630,"dut VexRiscv dBus_cmd_payload_wr",-1); vcdp->declBus (c+786,"dut VexRiscv dBus_cmd_payload_address",-1,31,0); vcdp->declBus (c+627,"dut VexRiscv dBus_cmd_payload_data",-1,31,0); vcdp->declBus (c+787,"dut VexRiscv dBus_cmd_payload_mask",-1,3,0); vcdp->declBus (c+788,"dut VexRiscv dBus_cmd_payload_length",-1,2,0); vcdp->declBit (c+789,"dut VexRiscv dBus_cmd_payload_last",-1); vcdp->declBit (c+790,"dut VexRiscv dBus_rsp_valid",-1); vcdp->declBus (c+791,"dut VexRiscv dBus_rsp_payload_data",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv dBus_rsp_payload_error",-1); vcdp->declBit (c+439,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_valid",-1); vcdp->declBit (c+440,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_ready",-1); vcdp->declBit (c+441,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_payload_wr",-1); vcdp->declBus (c+442,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_payload_address",-1,31,0); vcdp->declBus (c+443,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_payload_data",-1,31,0); vcdp->declBus (c+792,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_payload_mask",-1,3,0); vcdp->declBus (c+444,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_payload_length",-1,2,0); vcdp->declBit (c+445,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_payload_last",-1); // Tracing: dut VexRiscv _zz_154_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2227 // Tracing: dut VexRiscv _zz_155_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2228 // Tracing: dut VexRiscv _zz_156_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2229 // Tracing: dut VexRiscv _zz_157_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2230 // Tracing: dut VexRiscv _zz_158_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2231 // Tracing: dut VexRiscv _zz_159_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2232 // Tracing: dut VexRiscv _zz_160_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2233 vcdp->declBit (c+629,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid",-1); vcdp->declBit (c+438,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready",-1); vcdp->declBit (c+630,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr",-1); vcdp->declBus (c+786,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address",-1,31,0); vcdp->declBus (c+627,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data",-1,31,0); vcdp->declBus (c+787,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask",-1,3,0); vcdp->declBus (c+788,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length",-1,2,0); vcdp->declBit (c+789,"dut VexRiscv dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last",-1); // Tracing: dut VexRiscv _zz_161_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2242 // Tracing: dut VexRiscv _zz_162_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2243 // Tracing: dut VexRiscv _zz_163_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2244 // Tracing: dut VexRiscv _zz_164_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2245 // Tracing: dut VexRiscv _zz_165_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2246 // Tracing: dut VexRiscv _zz_166_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2247 // Tracing: dut VexRiscv _zz_167_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2248 // Tracing: dut VexRiscv _zz_168_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2249 vcdp->declBus (c+793,"dut VexRiscv DBusCachedPlugin_rspCounter",-1,31,0); vcdp->declBus (c+794,"dut VexRiscv execute_DBusCachedPlugin_size",-1,1,0); // Tracing: dut VexRiscv _zz_169_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2252 vcdp->declBus (c+446,"dut VexRiscv writeBack_DBusCachedPlugin_rspShifted",-1,31,0); // Tracing: dut VexRiscv _zz_170_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2254 // Tracing: dut VexRiscv _zz_171_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2255 // Tracing: dut VexRiscv _zz_172_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2256 // Tracing: dut VexRiscv _zz_173_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2257 vcdp->declBus (c+447,"dut VexRiscv writeBack_DBusCachedPlugin_rspFormated",-1,31,0); vcdp->declBit (c+448,"dut VexRiscv DBusCachedPlugin_forceDatapath",-1); vcdp->declBit (c+795,"dut VexRiscv MmuPlugin_status_sum",-1); vcdp->declBit (c+796,"dut VexRiscv MmuPlugin_status_mxr",-1); vcdp->declBit (c+797,"dut VexRiscv MmuPlugin_status_mprv",-1); vcdp->declBit (c+798,"dut VexRiscv MmuPlugin_satp_mode",-1); vcdp->declBus (c+799,"dut VexRiscv MmuPlugin_satp_ppn",-1,19,0); vcdp->declBit (c+800,"dut VexRiscv MmuPlugin_ports_0_cache_0_valid",-1); vcdp->declBit (c+801,"dut VexRiscv MmuPlugin_ports_0_cache_0_exception",-1); vcdp->declBit (c+802,"dut VexRiscv MmuPlugin_ports_0_cache_0_superPage",-1); vcdp->declBus (c+803,"dut VexRiscv MmuPlugin_ports_0_cache_0_virtualAddress_0",-1,9,0); vcdp->declBus (c+804,"dut VexRiscv MmuPlugin_ports_0_cache_0_virtualAddress_1",-1,9,0); vcdp->declBus (c+805,"dut VexRiscv MmuPlugin_ports_0_cache_0_physicalAddress_0",-1,9,0); vcdp->declBus (c+806,"dut VexRiscv MmuPlugin_ports_0_cache_0_physicalAddress_1",-1,9,0); vcdp->declBit (c+807,"dut VexRiscv MmuPlugin_ports_0_cache_0_allowRead",-1); vcdp->declBit (c+808,"dut VexRiscv MmuPlugin_ports_0_cache_0_allowWrite",-1); vcdp->declBit (c+809,"dut VexRiscv MmuPlugin_ports_0_cache_0_allowExecute",-1); vcdp->declBit (c+810,"dut VexRiscv MmuPlugin_ports_0_cache_0_allowUser",-1); vcdp->declBit (c+811,"dut VexRiscv MmuPlugin_ports_0_cache_1_valid",-1); vcdp->declBit (c+812,"dut VexRiscv MmuPlugin_ports_0_cache_1_exception",-1); vcdp->declBit (c+813,"dut VexRiscv MmuPlugin_ports_0_cache_1_superPage",-1); vcdp->declBus (c+814,"dut VexRiscv MmuPlugin_ports_0_cache_1_virtualAddress_0",-1,9,0); vcdp->declBus (c+815,"dut VexRiscv MmuPlugin_ports_0_cache_1_virtualAddress_1",-1,9,0); vcdp->declBus (c+816,"dut VexRiscv MmuPlugin_ports_0_cache_1_physicalAddress_0",-1,9,0); vcdp->declBus (c+817,"dut VexRiscv MmuPlugin_ports_0_cache_1_physicalAddress_1",-1,9,0); vcdp->declBit (c+818,"dut VexRiscv MmuPlugin_ports_0_cache_1_allowRead",-1); vcdp->declBit (c+819,"dut VexRiscv MmuPlugin_ports_0_cache_1_allowWrite",-1); vcdp->declBit (c+820,"dut VexRiscv MmuPlugin_ports_0_cache_1_allowExecute",-1); vcdp->declBit (c+821,"dut VexRiscv MmuPlugin_ports_0_cache_1_allowUser",-1); vcdp->declBit (c+822,"dut VexRiscv MmuPlugin_ports_0_cache_2_valid",-1); vcdp->declBit (c+823,"dut VexRiscv MmuPlugin_ports_0_cache_2_exception",-1); vcdp->declBit (c+824,"dut VexRiscv MmuPlugin_ports_0_cache_2_superPage",-1); vcdp->declBus (c+825,"dut VexRiscv MmuPlugin_ports_0_cache_2_virtualAddress_0",-1,9,0); vcdp->declBus (c+826,"dut VexRiscv MmuPlugin_ports_0_cache_2_virtualAddress_1",-1,9,0); vcdp->declBus (c+827,"dut VexRiscv MmuPlugin_ports_0_cache_2_physicalAddress_0",-1,9,0); vcdp->declBus (c+828,"dut VexRiscv MmuPlugin_ports_0_cache_2_physicalAddress_1",-1,9,0); vcdp->declBit (c+829,"dut VexRiscv MmuPlugin_ports_0_cache_2_allowRead",-1); vcdp->declBit (c+830,"dut VexRiscv MmuPlugin_ports_0_cache_2_allowWrite",-1); vcdp->declBit (c+831,"dut VexRiscv MmuPlugin_ports_0_cache_2_allowExecute",-1); vcdp->declBit (c+832,"dut VexRiscv MmuPlugin_ports_0_cache_2_allowUser",-1); vcdp->declBit (c+833,"dut VexRiscv MmuPlugin_ports_0_cache_3_valid",-1); vcdp->declBit (c+834,"dut VexRiscv MmuPlugin_ports_0_cache_3_exception",-1); vcdp->declBit (c+835,"dut VexRiscv MmuPlugin_ports_0_cache_3_superPage",-1); vcdp->declBus (c+836,"dut VexRiscv MmuPlugin_ports_0_cache_3_virtualAddress_0",-1,9,0); vcdp->declBus (c+837,"dut VexRiscv MmuPlugin_ports_0_cache_3_virtualAddress_1",-1,9,0); vcdp->declBus (c+838,"dut VexRiscv MmuPlugin_ports_0_cache_3_physicalAddress_0",-1,9,0); vcdp->declBus (c+839,"dut VexRiscv MmuPlugin_ports_0_cache_3_physicalAddress_1",-1,9,0); vcdp->declBit (c+840,"dut VexRiscv MmuPlugin_ports_0_cache_3_allowRead",-1); vcdp->declBit (c+841,"dut VexRiscv MmuPlugin_ports_0_cache_3_allowWrite",-1); vcdp->declBit (c+842,"dut VexRiscv MmuPlugin_ports_0_cache_3_allowExecute",-1); vcdp->declBit (c+843,"dut VexRiscv MmuPlugin_ports_0_cache_3_allowUser",-1); vcdp->declBit (c+844,"dut VexRiscv MmuPlugin_ports_0_cacheHits_0",-1); vcdp->declBit (c+449,"dut VexRiscv MmuPlugin_ports_0_cacheHits_1",-1); vcdp->declBit (c+450,"dut VexRiscv MmuPlugin_ports_0_cacheHits_2",-1); vcdp->declBit (c+451,"dut VexRiscv MmuPlugin_ports_0_cacheHits_3",-1); vcdp->declBit (c+452,"dut VexRiscv MmuPlugin_ports_0_cacheHit",-1); // Tracing: dut VexRiscv _zz_174_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2314 // Tracing: dut VexRiscv _zz_175_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2315 // Tracing: dut VexRiscv _zz_176_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2316 vcdp->declBit (c+453,"dut VexRiscv MmuPlugin_ports_0_cacheLine_valid",-1); vcdp->declBit (c+454,"dut VexRiscv MmuPlugin_ports_0_cacheLine_exception",-1); vcdp->declBit (c+455,"dut VexRiscv MmuPlugin_ports_0_cacheLine_superPage",-1); vcdp->declBus (c+456,"dut VexRiscv MmuPlugin_ports_0_cacheLine_virtualAddress_0",-1,9,0); vcdp->declBus (c+457,"dut VexRiscv MmuPlugin_ports_0_cacheLine_virtualAddress_1",-1,9,0); vcdp->declBus (c+458,"dut VexRiscv MmuPlugin_ports_0_cacheLine_physicalAddress_0",-1,9,0); vcdp->declBus (c+459,"dut VexRiscv MmuPlugin_ports_0_cacheLine_physicalAddress_1",-1,9,0); vcdp->declBit (c+460,"dut VexRiscv MmuPlugin_ports_0_cacheLine_allowRead",-1); vcdp->declBit (c+461,"dut VexRiscv MmuPlugin_ports_0_cacheLine_allowWrite",-1); vcdp->declBit (c+462,"dut VexRiscv MmuPlugin_ports_0_cacheLine_allowExecute",-1); vcdp->declBit (c+463,"dut VexRiscv MmuPlugin_ports_0_cacheLine_allowUser",-1); vcdp->declBit (c+464,"dut VexRiscv MmuPlugin_ports_0_entryToReplace_willIncrement",-1); vcdp->declBit (c+1128,"dut VexRiscv MmuPlugin_ports_0_entryToReplace_willClear",-1); vcdp->declBus (c+465,"dut VexRiscv MmuPlugin_ports_0_entryToReplace_valueNext",-1,1,0); vcdp->declBus (c+845,"dut VexRiscv MmuPlugin_ports_0_entryToReplace_value",-1,1,0); vcdp->declBit (c+846,"dut VexRiscv MmuPlugin_ports_0_entryToReplace_willOverflowIfInc",-1); vcdp->declBit (c+466,"dut VexRiscv MmuPlugin_ports_0_entryToReplace_willOverflow",-1); vcdp->declBit (c+467,"dut VexRiscv MmuPlugin_ports_0_requireMmuLockup",-1); vcdp->declBit (c+847,"dut VexRiscv MmuPlugin_ports_1_cache_0_valid",-1); vcdp->declBit (c+848,"dut VexRiscv MmuPlugin_ports_1_cache_0_exception",-1); vcdp->declBit (c+849,"dut VexRiscv MmuPlugin_ports_1_cache_0_superPage",-1); vcdp->declBus (c+850,"dut VexRiscv MmuPlugin_ports_1_cache_0_virtualAddress_0",-1,9,0); vcdp->declBus (c+851,"dut VexRiscv MmuPlugin_ports_1_cache_0_virtualAddress_1",-1,9,0); vcdp->declBus (c+852,"dut VexRiscv MmuPlugin_ports_1_cache_0_physicalAddress_0",-1,9,0); vcdp->declBus (c+853,"dut VexRiscv MmuPlugin_ports_1_cache_0_physicalAddress_1",-1,9,0); vcdp->declBit (c+854,"dut VexRiscv MmuPlugin_ports_1_cache_0_allowRead",-1); vcdp->declBit (c+855,"dut VexRiscv MmuPlugin_ports_1_cache_0_allowWrite",-1); vcdp->declBit (c+856,"dut VexRiscv MmuPlugin_ports_1_cache_0_allowExecute",-1); vcdp->declBit (c+857,"dut VexRiscv MmuPlugin_ports_1_cache_0_allowUser",-1); vcdp->declBit (c+858,"dut VexRiscv MmuPlugin_ports_1_cache_1_valid",-1); vcdp->declBit (c+859,"dut VexRiscv MmuPlugin_ports_1_cache_1_exception",-1); vcdp->declBit (c+860,"dut VexRiscv MmuPlugin_ports_1_cache_1_superPage",-1); vcdp->declBus (c+861,"dut VexRiscv MmuPlugin_ports_1_cache_1_virtualAddress_0",-1,9,0); vcdp->declBus (c+862,"dut VexRiscv MmuPlugin_ports_1_cache_1_virtualAddress_1",-1,9,0); vcdp->declBus (c+863,"dut VexRiscv MmuPlugin_ports_1_cache_1_physicalAddress_0",-1,9,0); vcdp->declBus (c+864,"dut VexRiscv MmuPlugin_ports_1_cache_1_physicalAddress_1",-1,9,0); vcdp->declBit (c+865,"dut VexRiscv MmuPlugin_ports_1_cache_1_allowRead",-1); vcdp->declBit (c+866,"dut VexRiscv MmuPlugin_ports_1_cache_1_allowWrite",-1); vcdp->declBit (c+867,"dut VexRiscv MmuPlugin_ports_1_cache_1_allowExecute",-1); vcdp->declBit (c+868,"dut VexRiscv MmuPlugin_ports_1_cache_1_allowUser",-1); vcdp->declBit (c+869,"dut VexRiscv MmuPlugin_ports_1_cache_2_valid",-1); vcdp->declBit (c+870,"dut VexRiscv MmuPlugin_ports_1_cache_2_exception",-1); vcdp->declBit (c+871,"dut VexRiscv MmuPlugin_ports_1_cache_2_superPage",-1); vcdp->declBus (c+872,"dut VexRiscv MmuPlugin_ports_1_cache_2_virtualAddress_0",-1,9,0); vcdp->declBus (c+873,"dut VexRiscv MmuPlugin_ports_1_cache_2_virtualAddress_1",-1,9,0); vcdp->declBus (c+874,"dut VexRiscv MmuPlugin_ports_1_cache_2_physicalAddress_0",-1,9,0); vcdp->declBus (c+875,"dut VexRiscv MmuPlugin_ports_1_cache_2_physicalAddress_1",-1,9,0); vcdp->declBit (c+876,"dut VexRiscv MmuPlugin_ports_1_cache_2_allowRead",-1); vcdp->declBit (c+877,"dut VexRiscv MmuPlugin_ports_1_cache_2_allowWrite",-1); vcdp->declBit (c+878,"dut VexRiscv MmuPlugin_ports_1_cache_2_allowExecute",-1); vcdp->declBit (c+879,"dut VexRiscv MmuPlugin_ports_1_cache_2_allowUser",-1); vcdp->declBit (c+880,"dut VexRiscv MmuPlugin_ports_1_cache_3_valid",-1); vcdp->declBit (c+881,"dut VexRiscv MmuPlugin_ports_1_cache_3_exception",-1); vcdp->declBit (c+882,"dut VexRiscv MmuPlugin_ports_1_cache_3_superPage",-1); vcdp->declBus (c+883,"dut VexRiscv MmuPlugin_ports_1_cache_3_virtualAddress_0",-1,9,0); vcdp->declBus (c+884,"dut VexRiscv MmuPlugin_ports_1_cache_3_virtualAddress_1",-1,9,0); vcdp->declBus (c+885,"dut VexRiscv MmuPlugin_ports_1_cache_3_physicalAddress_0",-1,9,0); vcdp->declBus (c+886,"dut VexRiscv MmuPlugin_ports_1_cache_3_physicalAddress_1",-1,9,0); vcdp->declBit (c+887,"dut VexRiscv MmuPlugin_ports_1_cache_3_allowRead",-1); vcdp->declBit (c+888,"dut VexRiscv MmuPlugin_ports_1_cache_3_allowWrite",-1); vcdp->declBit (c+889,"dut VexRiscv MmuPlugin_ports_1_cache_3_allowExecute",-1); vcdp->declBit (c+890,"dut VexRiscv MmuPlugin_ports_1_cache_3_allowUser",-1); vcdp->declBit (c+1087,"dut VexRiscv MmuPlugin_ports_1_cacheHits_0",-1); vcdp->declBit (c+468,"dut VexRiscv MmuPlugin_ports_1_cacheHits_1",-1); vcdp->declBit (c+469,"dut VexRiscv MmuPlugin_ports_1_cacheHits_2",-1); vcdp->declBit (c+470,"dut VexRiscv MmuPlugin_ports_1_cacheHits_3",-1); vcdp->declBit (c+471,"dut VexRiscv MmuPlugin_ports_1_cacheHit",-1); // Tracing: dut VexRiscv _zz_177_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2384 // Tracing: dut VexRiscv _zz_178_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2385 // Tracing: dut VexRiscv _zz_179_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2386 vcdp->declBit (c+472,"dut VexRiscv MmuPlugin_ports_1_cacheLine_valid",-1); vcdp->declBit (c+473,"dut VexRiscv MmuPlugin_ports_1_cacheLine_exception",-1); vcdp->declBit (c+474,"dut VexRiscv MmuPlugin_ports_1_cacheLine_superPage",-1); vcdp->declBus (c+475,"dut VexRiscv MmuPlugin_ports_1_cacheLine_virtualAddress_0",-1,9,0); vcdp->declBus (c+476,"dut VexRiscv MmuPlugin_ports_1_cacheLine_virtualAddress_1",-1,9,0); vcdp->declBus (c+477,"dut VexRiscv MmuPlugin_ports_1_cacheLine_physicalAddress_0",-1,9,0); vcdp->declBus (c+478,"dut VexRiscv MmuPlugin_ports_1_cacheLine_physicalAddress_1",-1,9,0); vcdp->declBit (c+479,"dut VexRiscv MmuPlugin_ports_1_cacheLine_allowRead",-1); vcdp->declBit (c+480,"dut VexRiscv MmuPlugin_ports_1_cacheLine_allowWrite",-1); vcdp->declBit (c+481,"dut VexRiscv MmuPlugin_ports_1_cacheLine_allowExecute",-1); vcdp->declBit (c+482,"dut VexRiscv MmuPlugin_ports_1_cacheLine_allowUser",-1); vcdp->declBit (c+483,"dut VexRiscv MmuPlugin_ports_1_entryToReplace_willIncrement",-1); vcdp->declBit (c+1128,"dut VexRiscv MmuPlugin_ports_1_entryToReplace_willClear",-1); vcdp->declBus (c+484,"dut VexRiscv MmuPlugin_ports_1_entryToReplace_valueNext",-1,1,0); vcdp->declBus (c+891,"dut VexRiscv MmuPlugin_ports_1_entryToReplace_value",-1,1,0); vcdp->declBit (c+892,"dut VexRiscv MmuPlugin_ports_1_entryToReplace_willOverflowIfInc",-1); vcdp->declBit (c+485,"dut VexRiscv MmuPlugin_ports_1_entryToReplace_willOverflow",-1); vcdp->declBit (c+486,"dut VexRiscv MmuPlugin_ports_1_requireMmuLockup",-1); vcdp->declBus (c+893,"dut VexRiscv MmuPlugin_shared_state_1_",-1,2,0); vcdp->declBus (c+894,"dut VexRiscv MmuPlugin_shared_vpn_0",-1,9,0); vcdp->declBus (c+895,"dut VexRiscv MmuPlugin_shared_vpn_1",-1,9,0); vcdp->declBus (c+896,"dut VexRiscv MmuPlugin_shared_portId",-1,0,0); vcdp->declBit (c+487,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_V",-1); vcdp->declBit (c+488,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_R",-1); vcdp->declBit (c+489,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_W",-1); vcdp->declBit (c+490,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_X",-1); vcdp->declBit (c+491,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_U",-1); vcdp->declBit (c+492,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_G",-1); vcdp->declBit (c+493,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_A",-1); vcdp->declBit (c+494,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_D",-1); vcdp->declBus (c+495,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_RSW",-1,1,0); vcdp->declBus (c+496,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_PPN0",-1,9,0); vcdp->declBus (c+497,"dut VexRiscv MmuPlugin_shared_dBusRsp_pte_PPN1",-1,11,0); vcdp->declBit (c+498,"dut VexRiscv MmuPlugin_shared_dBusRsp_exception",-1); vcdp->declBit (c+499,"dut VexRiscv MmuPlugin_shared_dBusRsp_leaf",-1); vcdp->declBit (c+897,"dut VexRiscv MmuPlugin_shared_pteBuffer_V",-1); vcdp->declBit (c+898,"dut VexRiscv MmuPlugin_shared_pteBuffer_R",-1); vcdp->declBit (c+899,"dut VexRiscv MmuPlugin_shared_pteBuffer_W",-1); vcdp->declBit (c+900,"dut VexRiscv MmuPlugin_shared_pteBuffer_X",-1); vcdp->declBit (c+901,"dut VexRiscv MmuPlugin_shared_pteBuffer_U",-1); vcdp->declBit (c+902,"dut VexRiscv MmuPlugin_shared_pteBuffer_G",-1); vcdp->declBit (c+903,"dut VexRiscv MmuPlugin_shared_pteBuffer_A",-1); vcdp->declBit (c+904,"dut VexRiscv MmuPlugin_shared_pteBuffer_D",-1); vcdp->declBus (c+905,"dut VexRiscv MmuPlugin_shared_pteBuffer_RSW",-1,1,0); vcdp->declBus (c+906,"dut VexRiscv MmuPlugin_shared_pteBuffer_PPN0",-1,9,0); vcdp->declBus (c+907,"dut VexRiscv MmuPlugin_shared_pteBuffer_PPN1",-1,11,0); // Tracing: dut VexRiscv _zz_180_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2433 // Tracing: dut VexRiscv _zz_181_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2434 // Tracing: dut VexRiscv _zz_182_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2435 // Tracing: dut VexRiscv _zz_183_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2436 // Tracing: dut VexRiscv _zz_184_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2437 // Tracing: dut VexRiscv _zz_185_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2438 // Tracing: dut VexRiscv _zz_186_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2439 // Tracing: dut VexRiscv _zz_187_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2440 // Tracing: dut VexRiscv _zz_188_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2441 // Tracing: dut VexRiscv _zz_189_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2442 // Tracing: dut VexRiscv _zz_190_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2443 // Tracing: dut VexRiscv _zz_191_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2444 // Tracing: dut VexRiscv _zz_192_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2445 // Tracing: dut VexRiscv _zz_193_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2446 vcdp->declBus (c+500,"dut VexRiscv decode_RegFilePlugin_regFileReadAddress1",-1,4,0); vcdp->declBus (c+501,"dut VexRiscv decode_RegFilePlugin_regFileReadAddress2",-1,4,0); vcdp->declBus (c+1088,"dut VexRiscv decode_RegFilePlugin_rs1Data",-1,31,0); vcdp->declBus (c+1089,"dut VexRiscv decode_RegFilePlugin_rs2Data",-1,31,0); vcdp->declBit (c+1090,"dut VexRiscv lastStageRegFileWrite_valid",-1); vcdp->declBus (c+1091,"dut VexRiscv lastStageRegFileWrite_payload_address",-1,4,0); vcdp->declBus (c+1092,"dut VexRiscv lastStageRegFileWrite_payload_data",-1,31,0); // Tracing: dut VexRiscv _zz_194_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2454 vcdp->declBus (c+502,"dut VexRiscv execute_IntAluPlugin_bitwise",-1,31,0); // Tracing: dut VexRiscv _zz_195_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2456 // Tracing: dut VexRiscv _zz_196_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2457 // Tracing: dut VexRiscv _zz_197_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2458 // Tracing: dut VexRiscv _zz_198_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2459 // Tracing: dut VexRiscv _zz_199_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2460 // Tracing: dut VexRiscv _zz_200_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2461 // Tracing: dut VexRiscv _zz_201_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2462 vcdp->declBus (c+334,"dut VexRiscv execute_SrcPlugin_addSub",-1,31,0); vcdp->declBit (c+335,"dut VexRiscv execute_SrcPlugin_less",-1); vcdp->declBus (c+503,"dut VexRiscv execute_FullBarrelShifterPlugin_amplitude",-1,4,0); // Tracing: dut VexRiscv _zz_202_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2466 vcdp->declBus (c+504,"dut VexRiscv execute_FullBarrelShifterPlugin_reversed",-1,31,0); // Tracing: dut VexRiscv _zz_203_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2468 // Tracing: dut VexRiscv _zz_204_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2469 // Tracing: dut VexRiscv _zz_205_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2470 // Tracing: dut VexRiscv _zz_206_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2471 // Tracing: dut VexRiscv _zz_207_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2472 // Tracing: dut VexRiscv _zz_208_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2473 // Tracing: dut VexRiscv _zz_209_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2474 // Tracing: dut VexRiscv _zz_210_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2475 // Tracing: dut VexRiscv _zz_211_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2476 // Tracing: dut VexRiscv _zz_212_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2477 // Tracing: dut VexRiscv _zz_213_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2478 // Tracing: dut VexRiscv _zz_214_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2479 // Tracing: dut VexRiscv _zz_215_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2480 vcdp->declBit (c+505,"dut VexRiscv execute_BranchPlugin_eq",-1); // Tracing: dut VexRiscv _zz_216_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2482 // Tracing: dut VexRiscv _zz_217_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2483 // Tracing: dut VexRiscv _zz_218_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2484 vcdp->declBit (c+1128,"dut VexRiscv execute_BranchPlugin_missAlignedTarget",-1); vcdp->declBus (c+908,"dut VexRiscv execute_BranchPlugin_branch_src1",-1,31,0); vcdp->declBus (c+506,"dut VexRiscv execute_BranchPlugin_branch_src2",-1,31,0); // Tracing: dut VexRiscv _zz_219_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2488 // Tracing: dut VexRiscv _zz_220_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2489 // Tracing: dut VexRiscv _zz_221_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2490 // Tracing: dut VexRiscv _zz_222_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2491 // Tracing: dut VexRiscv _zz_223_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2492 // Tracing: dut VexRiscv _zz_224_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2493 vcdp->declBus (c+507,"dut VexRiscv execute_BranchPlugin_branchAdder",-1,31,0); // Tracing: dut VexRiscv _zz_225_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2495 vcdp->declBus (c+1142,"dut VexRiscv CsrPlugin_misa_base",-1,1,0); vcdp->declBus (c+1143,"dut VexRiscv CsrPlugin_misa_extensions",-1,25,0); vcdp->declBus (c+909,"dut VexRiscv CsrPlugin_mtvec_mode",-1,1,0); vcdp->declBus (c+910,"dut VexRiscv CsrPlugin_mtvec_base",-1,29,0); vcdp->declBus (c+911,"dut VexRiscv CsrPlugin_mepc",-1,31,0); vcdp->declBit (c+912,"dut VexRiscv CsrPlugin_mstatus_MIE",-1); vcdp->declBit (c+913,"dut VexRiscv CsrPlugin_mstatus_MPIE",-1); vcdp->declBus (c+914,"dut VexRiscv CsrPlugin_mstatus_MPP",-1,1,0); vcdp->declBit (c+915,"dut VexRiscv CsrPlugin_mip_MEIP",-1); vcdp->declBit (c+916,"dut VexRiscv CsrPlugin_mip_MTIP",-1); vcdp->declBit (c+917,"dut VexRiscv CsrPlugin_mip_MSIP",-1); vcdp->declBit (c+918,"dut VexRiscv CsrPlugin_mie_MEIE",-1); vcdp->declBit (c+919,"dut VexRiscv CsrPlugin_mie_MTIE",-1); vcdp->declBit (c+920,"dut VexRiscv CsrPlugin_mie_MSIE",-1); vcdp->declBus (c+921,"dut VexRiscv CsrPlugin_mscratch",-1,31,0); vcdp->declBit (c+922,"dut VexRiscv CsrPlugin_mcause_interrupt",-1); vcdp->declBus (c+923,"dut VexRiscv CsrPlugin_mcause_exceptionCode",-1,3,0); vcdp->declBus (c+924,"dut VexRiscv CsrPlugin_mtval",-1,31,0); vcdp->declQuad (c+508,"dut VexRiscv CsrPlugin_mcycle",-1,63,0); vcdp->declQuad (c+510,"dut VexRiscv CsrPlugin_minstret",-1,63,0); vcdp->declBit (c+925,"dut VexRiscv CsrPlugin_medeleg_IAM",-1); vcdp->declBit (c+926,"dut VexRiscv CsrPlugin_medeleg_IAF",-1); vcdp->declBit (c+927,"dut VexRiscv CsrPlugin_medeleg_II",-1); vcdp->declBit (c+928,"dut VexRiscv CsrPlugin_medeleg_LAM",-1); vcdp->declBit (c+929,"dut VexRiscv CsrPlugin_medeleg_LAF",-1); vcdp->declBit (c+930,"dut VexRiscv CsrPlugin_medeleg_SAM",-1); vcdp->declBit (c+931,"dut VexRiscv CsrPlugin_medeleg_SAF",-1); vcdp->declBit (c+932,"dut VexRiscv CsrPlugin_medeleg_EU",-1); vcdp->declBit (c+933,"dut VexRiscv CsrPlugin_medeleg_ES",-1); vcdp->declBit (c+934,"dut VexRiscv CsrPlugin_medeleg_IPF",-1); vcdp->declBit (c+935,"dut VexRiscv CsrPlugin_medeleg_LPF",-1); vcdp->declBit (c+936,"dut VexRiscv CsrPlugin_medeleg_SPF",-1); vcdp->declBit (c+937,"dut VexRiscv CsrPlugin_mideleg_ST",-1); vcdp->declBit (c+938,"dut VexRiscv CsrPlugin_mideleg_SE",-1); vcdp->declBit (c+939,"dut VexRiscv CsrPlugin_mideleg_SS",-1); vcdp->declBit (c+940,"dut VexRiscv CsrPlugin_sstatus_SIE",-1); vcdp->declBit (c+941,"dut VexRiscv CsrPlugin_sstatus_SPIE",-1); vcdp->declBus (c+942,"dut VexRiscv CsrPlugin_sstatus_SPP",-1,0,0); vcdp->declBit (c+943,"dut VexRiscv CsrPlugin_sip_SEIP_SOFT",-1); vcdp->declBit (c+944,"dut VexRiscv CsrPlugin_sip_SEIP_INPUT",-1); vcdp->declBit (c+512,"dut VexRiscv CsrPlugin_sip_SEIP_OR",-1); vcdp->declBit (c+945,"dut VexRiscv CsrPlugin_sip_STIP",-1); vcdp->declBit (c+946,"dut VexRiscv CsrPlugin_sip_SSIP",-1); vcdp->declBit (c+947,"dut VexRiscv CsrPlugin_sie_SEIE",-1); vcdp->declBit (c+948,"dut VexRiscv CsrPlugin_sie_STIE",-1); vcdp->declBit (c+949,"dut VexRiscv CsrPlugin_sie_SSIE",-1); vcdp->declBus (c+950,"dut VexRiscv CsrPlugin_stvec_mode",-1,1,0); vcdp->declBus (c+951,"dut VexRiscv CsrPlugin_stvec_base",-1,29,0); vcdp->declBus (c+952,"dut VexRiscv CsrPlugin_sscratch",-1,31,0); vcdp->declBit (c+953,"dut VexRiscv CsrPlugin_scause_interrupt",-1); vcdp->declBus (c+954,"dut VexRiscv CsrPlugin_scause_exceptionCode",-1,3,0); vcdp->declBus (c+955,"dut VexRiscv CsrPlugin_stval",-1,31,0); vcdp->declBus (c+956,"dut VexRiscv CsrPlugin_sepc",-1,31,0); vcdp->declBus (c+1144,"dut VexRiscv CsrPlugin_satp_PPN",-1,21,0); vcdp->declBus (c+1145,"dut VexRiscv CsrPlugin_satp_ASID",-1,8,0); vcdp->declBus (c+1146,"dut VexRiscv CsrPlugin_satp_MODE",-1,0,0); // Tracing: dut VexRiscv _zz_226_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2552 // Tracing: dut VexRiscv _zz_227_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2553 // Tracing: dut VexRiscv _zz_228_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2554 // Tracing: dut VexRiscv _zz_229_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2555 // Tracing: dut VexRiscv _zz_230_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2556 // Tracing: dut VexRiscv _zz_231_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2557 vcdp->declBit (c+513,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValids_decode",-1); vcdp->declBit (c+514,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValids_execute",-1); vcdp->declBit (c+515,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValids_memory",-1); vcdp->declBit (c+516,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack",-1); vcdp->declBit (c+768,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode",-1); vcdp->declBit (c+769,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute",-1); vcdp->declBit (c+770,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory",-1); vcdp->declBit (c+771,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack",-1); vcdp->declBus (c+957,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionContext_code",-1,3,0); vcdp->declBus (c+958,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr",-1,31,0); vcdp->declBus (c+517,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped",-1,1,0); vcdp->declBus (c+518,"dut VexRiscv CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege",-1,1,0); // Tracing: dut VexRiscv _zz_232_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2570 // Tracing: dut VexRiscv _zz_233_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2571 vcdp->declBit (c+959,"dut VexRiscv CsrPlugin_interrupt_valid",-1); vcdp->declBus (c+1093,"dut VexRiscv CsrPlugin_interrupt_code",-1,3,0); vcdp->declBus (c+960,"dut VexRiscv CsrPlugin_interrupt_targetPrivilege",-1,1,0); vcdp->declBit (c+516,"dut VexRiscv CsrPlugin_exception",-1); vcdp->declBit (c+961,"dut VexRiscv CsrPlugin_lastStageWasWfi",-1); vcdp->declBit (c+519,"dut VexRiscv CsrPlugin_pipelineLiberator_done",-1); vcdp->declBit (c+1094,"dut VexRiscv CsrPlugin_interruptJump",-1); vcdp->declBit (c+962,"dut VexRiscv CsrPlugin_hadException",-1); vcdp->declBus (c+520,"dut VexRiscv CsrPlugin_targetPrivilege",-1,1,0); vcdp->declBus (c+521,"dut VexRiscv CsrPlugin_trapCause",-1,3,0); vcdp->declBus (c+522,"dut VexRiscv CsrPlugin_xtvec_mode",-1,1,0); vcdp->declBus (c+523,"dut VexRiscv CsrPlugin_xtvec_base",-1,29,0); vcdp->declBit (c+1095,"dut VexRiscv execute_CsrPlugin_inWfi",-1); vcdp->declBit (c+963,"dut VexRiscv execute_CsrPlugin_wfiWake",-1); vcdp->declBit (c+524,"dut VexRiscv execute_CsrPlugin_blockedBySideEffects",-1); vcdp->declBit (c+525,"dut VexRiscv execute_CsrPlugin_illegalAccess",-1); vcdp->declBit (c+526,"dut VexRiscv execute_CsrPlugin_illegalInstruction",-1); vcdp->declBus (c+527,"dut VexRiscv execute_CsrPlugin_readData",-1,31,0); vcdp->declBit (c+964,"dut VexRiscv execute_CsrPlugin_writeInstruction",-1); vcdp->declBit (c+965,"dut VexRiscv execute_CsrPlugin_readInstruction",-1); vcdp->declBit (c+528,"dut VexRiscv execute_CsrPlugin_writeEnable",-1); vcdp->declBit (c+529,"dut VexRiscv execute_CsrPlugin_readEnable",-1); vcdp->declBus (c+530,"dut VexRiscv execute_CsrPlugin_readToWriteData",-1,31,0); vcdp->declBus (c+531,"dut VexRiscv execute_CsrPlugin_writeData",-1,31,0); vcdp->declBus (c+966,"dut VexRiscv execute_CsrPlugin_csrAddress",-1,11,0); vcdp->declBit (c+967,"dut VexRiscv execute_MulPlugin_aSigned",-1); vcdp->declBit (c+968,"dut VexRiscv execute_MulPlugin_bSigned",-1); vcdp->declBus (c+337,"dut VexRiscv execute_MulPlugin_a",-1,31,0); vcdp->declBus (c+336,"dut VexRiscv execute_MulPlugin_b",-1,31,0); vcdp->declBus (c+532,"dut VexRiscv execute_MulPlugin_aULow",-1,15,0); vcdp->declBus (c+533,"dut VexRiscv execute_MulPlugin_bULow",-1,15,0); vcdp->declBus (c+534,"dut VexRiscv execute_MulPlugin_aSLow",-1,16,0); vcdp->declBus (c+535,"dut VexRiscv execute_MulPlugin_bSLow",-1,16,0); vcdp->declBus (c+536,"dut VexRiscv execute_MulPlugin_aHigh",-1,16,0); vcdp->declBus (c+537,"dut VexRiscv execute_MulPlugin_bHigh",-1,16,0); vcdp->declArray(c+969,"dut VexRiscv writeBack_MulPlugin_result",-1,65,0); vcdp->declQuad (c+972,"dut VexRiscv memory_DivPlugin_rs1",-1,32,0); vcdp->declBus (c+974,"dut VexRiscv memory_DivPlugin_rs2",-1,31,0); vcdp->declArray(c+975,"dut VexRiscv memory_DivPlugin_accumulator",-1,64,0); vcdp->declBit (c+978,"dut VexRiscv memory_DivPlugin_div_needRevert",-1); vcdp->declBit (c+538,"dut VexRiscv memory_DivPlugin_div_counter_willIncrement",-1); vcdp->declBit (c+539,"dut VexRiscv memory_DivPlugin_div_counter_willClear",-1); vcdp->declBus (c+540,"dut VexRiscv memory_DivPlugin_div_counter_valueNext",-1,5,0); vcdp->declBus (c+979,"dut VexRiscv memory_DivPlugin_div_counter_value",-1,5,0); vcdp->declBit (c+980,"dut VexRiscv memory_DivPlugin_div_counter_willOverflowIfInc",-1); vcdp->declBit (c+541,"dut VexRiscv memory_DivPlugin_div_counter_willOverflow",-1); vcdp->declBit (c+981,"dut VexRiscv memory_DivPlugin_div_done",-1); vcdp->declBus (c+982,"dut VexRiscv memory_DivPlugin_div_result",-1,31,0); // Tracing: dut VexRiscv _zz_234_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2620 // Tracing: dut VexRiscv _zz_235_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2621 // Tracing: dut VexRiscv _zz_236_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2622 // Tracing: dut VexRiscv _zz_237_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2623 // Tracing: dut VexRiscv _zz_238_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2624 // Tracing: dut VexRiscv _zz_239_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2625 // Tracing: dut VexRiscv _zz_240_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2626 vcdp->declBus (c+983,"dut VexRiscv externalInterruptArray_regNext",-1,31,0); // Tracing: dut VexRiscv _zz_241_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2628 // Tracing: dut VexRiscv _zz_242_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2629 // Tracing: dut VexRiscv _zz_243_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2630 // Tracing: dut VexRiscv _zz_244_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2631 vcdp->declBit (c+723,"dut VexRiscv decode_to_execute_PREDICTION_HAD_BRANCHED2",-1); vcdp->declBit (c+751,"dut VexRiscv decode_to_execute_MEMORY_LRSC",-1); vcdp->declBit (c+726,"dut VexRiscv decode_to_execute_BYPASSABLE_EXECUTE_STAGE",-1); vcdp->declBit (c+714,"dut VexRiscv decode_to_execute_CSR_WRITE_OPCODE",-1); vcdp->declBus (c+731,"dut VexRiscv execute_to_memory_SHIFT_RIGHT",-1,31,0); vcdp->declBit (c+715,"dut VexRiscv decode_to_execute_IS_CSR",-1); vcdp->declBit (c+738,"dut VexRiscv decode_to_execute_IS_RVC",-1); vcdp->declBus (c+733,"dut VexRiscv decode_to_execute_SHIFT_CTRL",-1,1,0); vcdp->declBus (c+732,"dut VexRiscv execute_to_memory_SHIFT_CTRL",-1,1,0); vcdp->declBus (c+739,"dut VexRiscv decode_to_execute_SRC1_CTRL",-1,1,0); vcdp->declBit (c+701,"dut VexRiscv decode_to_execute_IS_RS2_SIGNED",-1); vcdp->declBit (c+735,"dut VexRiscv decode_to_execute_SRC2_FORCE_ZERO",-1); vcdp->declBit (c+725,"dut VexRiscv decode_to_execute_REGFILE_WRITE_VALID",-1); vcdp->declBit (c+727,"dut VexRiscv execute_to_memory_REGFILE_WRITE_VALID",-1); vcdp->declBit (c+730,"dut VexRiscv memory_to_writeBack_REGFILE_WRITE_VALID",-1); vcdp->declBit (c+754,"dut VexRiscv decode_to_execute_MEMORY_WR",-1); vcdp->declBit (c+698,"dut VexRiscv execute_to_memory_MEMORY_WR",-1); vcdp->declBit (c+746,"dut VexRiscv memory_to_writeBack_MEMORY_WR",-1); vcdp->declBit (c+697,"dut VexRiscv decode_to_execute_IS_SFENCE_VMA",-1); vcdp->declBit (c+696,"dut VexRiscv execute_to_memory_IS_SFENCE_VMA",-1); vcdp->declBit (c+742,"dut VexRiscv memory_to_writeBack_IS_SFENCE_VMA",-1); vcdp->declBus (c+724,"dut VexRiscv decode_to_execute_BRANCH_CTRL",-1,1,0); vcdp->declBus (c+753,"dut VexRiscv decode_to_execute_RS2",-1,31,0); vcdp->declBus (c+695,"dut VexRiscv execute_to_memory_MEMORY_ADDRESS_LOW",-1,1,0); vcdp->declBus (c+745,"dut VexRiscv memory_to_writeBack_MEMORY_ADDRESS_LOW",-1,1,0); vcdp->declQuad (c+708,"dut VexRiscv execute_to_memory_MUL_HL",-1,33,0); vcdp->declBus (c+694,"dut VexRiscv decode_to_execute_FORMAL_PC_NEXT",-1,31,0); vcdp->declBus (c+693,"dut VexRiscv execute_to_memory_FORMAL_PC_NEXT",-1,31,0); vcdp->declBus (c+692,"dut VexRiscv memory_to_writeBack_FORMAL_PC_NEXT",-1,31,0); vcdp->declBit (c+736,"dut VexRiscv decode_to_execute_SRC_USE_SUB_LESS",-1); vcdp->declBit (c+755,"dut VexRiscv decode_to_execute_MEMORY_ENABLE",-1); vcdp->declBit (c+749,"dut VexRiscv execute_to_memory_MEMORY_ENABLE",-1); vcdp->declBit (c+748,"dut VexRiscv memory_to_writeBack_MEMORY_ENABLE",-1); vcdp->declBit (c+699,"dut VexRiscv decode_to_execute_IS_RS1_SIGNED",-1); vcdp->declBus (c+712,"dut VexRiscv execute_to_memory_MUL_LL",-1,31,0); vcdp->declBit (c+691,"dut VexRiscv decode_to_execute_IS_MUL",-1); vcdp->declBit (c+690,"dut VexRiscv execute_to_memory_IS_MUL",-1); vcdp->declBit (c+703,"dut VexRiscv memory_to_writeBack_IS_MUL",-1); vcdp->declBit (c+689,"dut VexRiscv decode_to_execute_BYPASSABLE_MEMORY_STAGE",-1); vcdp->declBit (c+729,"dut VexRiscv execute_to_memory_BYPASSABLE_MEMORY_STAGE",-1); vcdp->declBus (c+681,"dut VexRiscv execute_to_memory_REGFILE_WRITE_DATA",-1,31,0); vcdp->declBus (c+747,"dut VexRiscv memory_to_writeBack_REGFILE_WRITE_DATA",-1,31,0); vcdp->declBus (c+722,"dut VexRiscv decode_to_execute_RS1",-1,31,0); vcdp->declBit (c+713,"dut VexRiscv decode_to_execute_CSR_READ_OPCODE",-1); vcdp->declBit (c+744,"dut VexRiscv execute_to_memory_IS_DBUS_SHARING",-1); vcdp->declBit (c+743,"dut VexRiscv memory_to_writeBack_IS_DBUS_SHARING",-1); vcdp->declBus (c+737,"dut VexRiscv decode_to_execute_SRC2_CTRL",-1,1,0); vcdp->declBus (c+756,"dut VexRiscv decode_to_execute_INSTRUCTION",-1,31,0); vcdp->declBus (c+728,"dut VexRiscv execute_to_memory_INSTRUCTION",-1,31,0); vcdp->declBus (c+758,"dut VexRiscv memory_to_writeBack_INSTRUCTION",-1,31,0); vcdp->declBus (c+719,"dut VexRiscv execute_to_memory_BRANCH_CALC",-1,31,0); vcdp->declQuad (c+706,"dut VexRiscv memory_to_writeBack_MUL_LOW",-1,51,0); vcdp->declBit (c+720,"dut VexRiscv execute_to_memory_BRANCH_DO",-1); vcdp->declBit (c+750,"dut VexRiscv decode_to_execute_MEMORY_AMO",-1); vcdp->declQuad (c+685,"dut VexRiscv execute_to_memory_MUL_HH",-1,33,0); vcdp->declQuad (c+704,"dut VexRiscv memory_to_writeBack_MUL_HH",-1,33,0); vcdp->declBit (c+734,"dut VexRiscv decode_to_execute_SRC_LESS_UNSIGNED",-1); vcdp->declBus (c+721,"dut VexRiscv decode_to_execute_PC",-1,31,0); vcdp->declBus (c+684,"dut VexRiscv execute_to_memory_PC",-1,31,0); vcdp->declBus (c+757,"dut VexRiscv memory_to_writeBack_PC",-1,31,0); vcdp->declBus (c+717,"dut VexRiscv decode_to_execute_ENV_CTRL",-1,1,0); vcdp->declBus (c+716,"dut VexRiscv execute_to_memory_ENV_CTRL",-1,1,0); vcdp->declBus (c+718,"dut VexRiscv memory_to_writeBack_ENV_CTRL",-1,1,0); vcdp->declBit (c+752,"dut VexRiscv decode_to_execute_MEMORY_MANAGMENT",-1); vcdp->declBus (c+740,"dut VexRiscv decode_to_execute_ALU_CTRL",-1,1,0); vcdp->declBus (c+741,"dut VexRiscv decode_to_execute_ALU_BITWISE_CTRL",-1,1,0); vcdp->declBit (c+700,"dut VexRiscv decode_to_execute_IS_DIV",-1); vcdp->declBit (c+702,"dut VexRiscv execute_to_memory_IS_DIV",-1); vcdp->declQuad (c+710,"dut VexRiscv execute_to_memory_MUL_LH",-1,33,0); // Tracing: dut VexRiscv _zz_245_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2701 // Tracing: dut VexRiscv _zz_246_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2702 vcdp->declBus (c+782,"dut VexRiscv iBusWishbone_DAT_MISO_regNext",-1,31,0); // Tracing: dut VexRiscv _zz_247_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2704 // Tracing: dut VexRiscv _zz_248_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2705 // Tracing: dut VexRiscv _zz_249_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2706 // Tracing: dut VexRiscv _zz_250_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2707 // Tracing: dut VexRiscv _zz_251_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2708 // Tracing: dut VexRiscv _zz_252_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2709 // Tracing: dut VexRiscv _zz_253_ // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2710 vcdp->declBus (c+791,"dut VexRiscv dBusWishbone_DAT_MISO_regNext",-1,31,0); vcdp->declQuad (c+542,"dut VexRiscv decode_ALU_BITWISE_CTRL_string",-1,39,0); // Tracing: dut VexRiscv _zz_1__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2714 // Tracing: dut VexRiscv _zz_2__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2715 // Tracing: dut VexRiscv _zz_3__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2716 vcdp->declQuad (c+544,"dut VexRiscv decode_ALU_CTRL_string",-1,63,0); // Tracing: dut VexRiscv _zz_4__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2718 // Tracing: dut VexRiscv _zz_5__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2719 // Tracing: dut VexRiscv _zz_6__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2720 // Tracing: dut VexRiscv _zz_7__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2721 // Tracing: dut VexRiscv _zz_8__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2722 // Tracing: dut VexRiscv _zz_9__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2723 // Tracing: dut VexRiscv _zz_10__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2724 vcdp->declQuad (c+546,"dut VexRiscv decode_ENV_CTRL_string",-1,39,0); // Tracing: dut VexRiscv _zz_11__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2726 // Tracing: dut VexRiscv _zz_12__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2727 // Tracing: dut VexRiscv _zz_13__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2728 vcdp->declBus (c+548,"dut VexRiscv decode_SRC2_CTRL_string",-1,23,0); // Tracing: dut VexRiscv _zz_14__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2730 // Tracing: dut VexRiscv _zz_15__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2731 // Tracing: dut VexRiscv _zz_16__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2732 // Tracing: dut VexRiscv _zz_17__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2733 // Tracing: dut VexRiscv _zz_18__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2734 vcdp->declArray(c+549,"dut VexRiscv decode_SRC1_CTRL_string",-1,95,0); // Tracing: dut VexRiscv _zz_19__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2736 // Tracing: dut VexRiscv _zz_20__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2737 // Tracing: dut VexRiscv _zz_21__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2738 // Tracing: dut VexRiscv _zz_22__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2739 // Tracing: dut VexRiscv _zz_23__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2740 vcdp->declArray(c+552,"dut VexRiscv decode_SHIFT_CTRL_string",-1,71,0); // Tracing: dut VexRiscv _zz_24__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2742 // Tracing: dut VexRiscv _zz_25__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2743 // Tracing: dut VexRiscv _zz_26__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2744 vcdp->declQuad (c+984,"dut VexRiscv memory_ENV_CTRL_string",-1,39,0); // Tracing: dut VexRiscv _zz_32__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2746 vcdp->declQuad (c+986,"dut VexRiscv execute_ENV_CTRL_string",-1,39,0); // Tracing: dut VexRiscv _zz_33__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2748 vcdp->declQuad (c+988,"dut VexRiscv writeBack_ENV_CTRL_string",-1,39,0); // Tracing: dut VexRiscv _zz_36__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2750 vcdp->declBus (c+990,"dut VexRiscv execute_BRANCH_CTRL_string",-1,31,0); // Tracing: dut VexRiscv _zz_39__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2752 vcdp->declArray(c+555,"dut VexRiscv memory_SHIFT_CTRL_string",-1,71,0); // Tracing: dut VexRiscv _zz_44__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2754 vcdp->declArray(c+558,"dut VexRiscv execute_SHIFT_CTRL_string",-1,71,0); // Tracing: dut VexRiscv _zz_46__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2756 vcdp->declBus (c+991,"dut VexRiscv execute_SRC2_CTRL_string",-1,23,0); // Tracing: dut VexRiscv _zz_51__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2758 vcdp->declArray(c+561,"dut VexRiscv execute_SRC1_CTRL_string",-1,95,0); // Tracing: dut VexRiscv _zz_53__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2760 vcdp->declQuad (c+992,"dut VexRiscv execute_ALU_CTRL_string",-1,63,0); // Tracing: dut VexRiscv _zz_56__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2762 vcdp->declQuad (c+994,"dut VexRiscv execute_ALU_BITWISE_CTRL_string",-1,39,0); // Tracing: dut VexRiscv _zz_58__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2764 // Tracing: dut VexRiscv _zz_69__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2765 // Tracing: dut VexRiscv _zz_74__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2766 // Tracing: dut VexRiscv _zz_77__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2767 // Tracing: dut VexRiscv _zz_78__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2768 // Tracing: dut VexRiscv _zz_80__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2769 // Tracing: dut VexRiscv _zz_83__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2770 // Tracing: dut VexRiscv _zz_87__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2771 vcdp->declBus (c+564,"dut VexRiscv decode_BRANCH_CTRL_string",-1,31,0); // Tracing: dut VexRiscv _zz_98__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2773 vcdp->declQuad (c+565,"dut VexRiscv MmuPlugin_shared_state_1__string",-1,47,0); // Tracing: dut VexRiscv _zz_187__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2775 // Tracing: dut VexRiscv _zz_188__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2776 // Tracing: dut VexRiscv _zz_189__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2777 // Tracing: dut VexRiscv _zz_190__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2778 // Tracing: dut VexRiscv _zz_191__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2779 // Tracing: dut VexRiscv _zz_192__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2780 // Tracing: dut VexRiscv _zz_193__string // Ignored: Leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:2781 vcdp->declArray(c+567,"dut VexRiscv decode_to_execute_SHIFT_CTRL_string",-1,71,0); vcdp->declArray(c+570,"dut VexRiscv execute_to_memory_SHIFT_CTRL_string",-1,71,0); vcdp->declArray(c+573,"dut VexRiscv decode_to_execute_SRC1_CTRL_string",-1,95,0); vcdp->declBus (c+990,"dut VexRiscv decode_to_execute_BRANCH_CTRL_string",-1,31,0); vcdp->declBus (c+991,"dut VexRiscv decode_to_execute_SRC2_CTRL_string",-1,23,0); vcdp->declQuad (c+986,"dut VexRiscv decode_to_execute_ENV_CTRL_string",-1,39,0); vcdp->declQuad (c+984,"dut VexRiscv execute_to_memory_ENV_CTRL_string",-1,39,0); vcdp->declQuad (c+988,"dut VexRiscv memory_to_writeBack_ENV_CTRL_string",-1,39,0); vcdp->declQuad (c+992,"dut VexRiscv decode_to_execute_ALU_CTRL_string",-1,63,0); vcdp->declQuad (c+994,"dut VexRiscv decode_to_execute_ALU_BITWISE_CTRL_string",-1,39,0); {int i; for (i=0; i<32; i++) { vcdp->declBus (c+1096+i*1,"dut VexRiscv RegFilePlugin_regFile",(i+0),31,0);}} vcdp->declBit (c+576,"dut VexRiscv IBusCachedPlugin_cache io_flush",-1); vcdp->declBit (c+417,"dut VexRiscv IBusCachedPlugin_cache io_cpu_prefetch_isValid",-1); vcdp->declBit (c+271,"dut VexRiscv IBusCachedPlugin_cache io_cpu_prefetch_haltIt",-1); vcdp->declBus (c+419,"dut VexRiscv IBusCachedPlugin_cache io_cpu_prefetch_pc",-1,31,0); vcdp->declBit (c+273,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_isValid",-1); vcdp->declBit (c+577,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_isStuck",-1); vcdp->declBit (c+378,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_isRemoved",-1); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_pc",-1,31,0); vcdp->declBus (c+671,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_data",-1,31,0); vcdp->declBit (c+784,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_dataBypassValid",-1); vcdp->declBus (c+1129,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_dataBypass",-1,31,0); vcdp->declBit (c+273,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_cmd_isValid",-1); vcdp->declBus (c+1080,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_cmd_virtualAddress",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_cmd_bypassTranslation",-1); vcdp->declBus (c+272,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_physicalAddress",-1,31,0); vcdp->declBit (c+386,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_isIoAccess",-1); vcdp->declBit (c+387,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_allowRead",-1); vcdp->declBit (c+388,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_allowWrite",-1); vcdp->declBit (c+389,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_allowExecute",-1); vcdp->declBit (c+390,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_exception",-1); vcdp->declBit (c+391,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_rsp_refilling",-1); vcdp->declBit (c+274,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_end",-1); vcdp->declBit (c+672,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_mmuBus_busy",-1); vcdp->declBus (c+272,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_physicalAddress",-1,31,0); vcdp->declBit (c+672,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_haltIt",-1); vcdp->declBit (c+578,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_isValid",-1); vcdp->declBit (c+579,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_isStuck",-1); vcdp->declBus (c+777,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_pc",-1,31,0); vcdp->declBus (c+678,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_physicalAddress",-1,31,0); vcdp->declBus (c+676,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_data",-1,31,0); vcdp->declBit (c+677,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_cacheMiss",-1); vcdp->declBit (c+673,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_error",-1); vcdp->declBit (c+674,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_mmuRefilling",-1); vcdp->declBit (c+675,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_mmuException",-1); vcdp->declBit (c+996,"dut VexRiscv IBusCachedPlugin_cache io_cpu_decode_isUser",-1); vcdp->declBit (c+580,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fill_valid",-1); vcdp->declBus (c+678,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fill_payload",-1,31,0); vcdp->declBit (c+275,"dut VexRiscv IBusCachedPlugin_cache io_mem_cmd_valid",-1); vcdp->declBit (c+437,"dut VexRiscv IBusCachedPlugin_cache io_mem_cmd_ready",-1); vcdp->declBus (c+679,"dut VexRiscv IBusCachedPlugin_cache io_mem_cmd_payload_address",-1,31,0); vcdp->declBus (c+1132,"dut VexRiscv IBusCachedPlugin_cache io_mem_cmd_payload_size",-1,2,0); vcdp->declBit (c+781,"dut VexRiscv IBusCachedPlugin_cache io_mem_rsp_valid",-1); vcdp->declBus (c+782,"dut VexRiscv IBusCachedPlugin_cache io_mem_rsp_payload_data",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_cache io_mem_rsp_payload_error",-1); vcdp->declBit (c+1071,"dut VexRiscv IBusCachedPlugin_cache clk",-1); vcdp->declBit (c+270,"dut VexRiscv IBusCachedPlugin_cache reset",-1); // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_10_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:100 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_11_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:101 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_12_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:102 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_13_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:103 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_14_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:104 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_15_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:105 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_16_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:106 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_1_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:107 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_2_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:108 vcdp->declBit (c+581,"dut VexRiscv IBusCachedPlugin_cache lineLoader_fire",-1); vcdp->declBit (c+997,"dut VexRiscv IBusCachedPlugin_cache lineLoader_valid",-1); vcdp->declBus (c+998,"dut VexRiscv IBusCachedPlugin_cache lineLoader_address",-1,31,0); vcdp->declBit (c+999,"dut VexRiscv IBusCachedPlugin_cache lineLoader_hadError",-1); vcdp->declBit (c+1000,"dut VexRiscv IBusCachedPlugin_cache lineLoader_flushPending",-1); vcdp->declBus (c+1001,"dut VexRiscv IBusCachedPlugin_cache lineLoader_flushCounter",-1,7,0); // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_3_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:115 vcdp->declBit (c+1002,"dut VexRiscv IBusCachedPlugin_cache lineLoader_cmdSent",-1); vcdp->declBit (c+582,"dut VexRiscv IBusCachedPlugin_cache lineLoader_wayToAllocate_willIncrement",-1); vcdp->declBit (c+1128,"dut VexRiscv IBusCachedPlugin_cache lineLoader_wayToAllocate_willClear",-1); vcdp->declBit (c+1133,"dut VexRiscv IBusCachedPlugin_cache lineLoader_wayToAllocate_willOverflowIfInc",-1); vcdp->declBit (c+582,"dut VexRiscv IBusCachedPlugin_cache lineLoader_wayToAllocate_willOverflow",-1); vcdp->declBus (c+1003,"dut VexRiscv IBusCachedPlugin_cache lineLoader_wordIndex",-1,2,0); vcdp->declBit (c+583,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_tag_0_valid",-1); vcdp->declBus (c+1004,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_tag_0_payload_address",-1,6,0); vcdp->declBit (c+1005,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_tag_0_payload_data_valid",-1); vcdp->declBit (c+999,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_tag_0_payload_data_error",-1); vcdp->declBus (c+1006,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_tag_0_payload_data_address",-1,19,0); vcdp->declBit (c+781,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_data_0_valid",-1); vcdp->declBus (c+1007,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_data_0_payload_address",-1,9,0); vcdp->declBus (c+782,"dut VexRiscv IBusCachedPlugin_cache lineLoader_write_data_0_payload_data",-1,31,0); // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_4_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:130 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_5_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:131 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_6_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:132 vcdp->declBit (c+1008,"dut VexRiscv IBusCachedPlugin_cache fetchStage_read_waysValues_0_tag_valid",-1); vcdp->declBit (c+1009,"dut VexRiscv IBusCachedPlugin_cache fetchStage_read_waysValues_0_tag_error",-1); vcdp->declBus (c+1010,"dut VexRiscv IBusCachedPlugin_cache fetchStage_read_waysValues_0_tag_address",-1,19,0); // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_7_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:136 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_8_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:137 // Tracing: dut VexRiscv IBusCachedPlugin_cache _zz_9_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:138 vcdp->declBus (c+1011,"dut VexRiscv IBusCachedPlugin_cache fetchStage_read_waysValues_0_data",-1,31,0); vcdp->declBit (c+584,"dut VexRiscv IBusCachedPlugin_cache fetchStage_hit_hits_0",-1); vcdp->declBit (c+584,"dut VexRiscv IBusCachedPlugin_cache fetchStage_hit_valid",-1); vcdp->declBit (c+1009,"dut VexRiscv IBusCachedPlugin_cache fetchStage_hit_error",-1); vcdp->declBus (c+1011,"dut VexRiscv IBusCachedPlugin_cache fetchStage_hit_data",-1,31,0); vcdp->declBus (c+1011,"dut VexRiscv IBusCachedPlugin_cache fetchStage_hit_word",-1,31,0); vcdp->declBus (c+676,"dut VexRiscv IBusCachedPlugin_cache io_cpu_fetch_data_regNextWhen",-1,31,0); vcdp->declBus (c+678,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_physicalAddress",-1,31,0); vcdp->declBit (c+1012,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_isIoAccess",-1); vcdp->declBit (c+1013,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_allowRead",-1); vcdp->declBit (c+1014,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_allowWrite",-1); vcdp->declBit (c+1015,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_allowExecute",-1); vcdp->declBit (c+1016,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_exception",-1); vcdp->declBit (c+674,"dut VexRiscv IBusCachedPlugin_cache decodeStage_mmuRsp_refilling",-1); vcdp->declBit (c+1017,"dut VexRiscv IBusCachedPlugin_cache decodeStage_hit_valid",-1); vcdp->declBit (c+673,"dut VexRiscv IBusCachedPlugin_cache decodeStage_hit_error",-1); // Tracing: dut VexRiscv IBusCachedPlugin_cache ways_0_tags // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:155 // Tracing: dut VexRiscv IBusCachedPlugin_cache ways_0_datas // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:156 vcdp->declBit (c+585,"dut VexRiscv dataCache_1_ io_cpu_execute_isValid",-1); vcdp->declBus (c+586,"dut VexRiscv dataCache_1_ io_cpu_execute_address",-1,31,0); vcdp->declBit (c+587,"dut VexRiscv dataCache_1_ io_cpu_execute_args_wr",-1); vcdp->declBus (c+588,"dut VexRiscv dataCache_1_ io_cpu_execute_args_data",-1,31,0); vcdp->declBus (c+589,"dut VexRiscv dataCache_1_ io_cpu_execute_args_size",-1,1,0); vcdp->declBit (c+590,"dut VexRiscv dataCache_1_ io_cpu_execute_args_isLrsc",-1); vcdp->declBit (c+591,"dut VexRiscv dataCache_1_ io_cpu_execute_args_isAmo",-1); vcdp->declBit (c+1018,"dut VexRiscv dataCache_1_ io_cpu_execute_args_amoCtrl_swap",-1); vcdp->declBus (c+1019,"dut VexRiscv dataCache_1_ io_cpu_execute_args_amoCtrl_alu",-1,2,0); vcdp->declBit (c+276,"dut VexRiscv dataCache_1_ io_cpu_memory_isValid",-1); vcdp->declBit (c+367,"dut VexRiscv dataCache_1_ io_cpu_memory_isStuck",-1); vcdp->declBit (c+365,"dut VexRiscv dataCache_1_ io_cpu_memory_isRemoved",-1); vcdp->declBit (c+680,"dut VexRiscv dataCache_1_ io_cpu_memory_isWrite",-1); vcdp->declBus (c+681,"dut VexRiscv dataCache_1_ io_cpu_memory_address",-1,31,0); vcdp->declBit (c+276,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_cmd_isValid",-1); vcdp->declBus (c+681,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_cmd_virtualAddress",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_cmd_bypassTranslation",-1); vcdp->declBus (c+393,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_physicalAddress",-1,31,0); vcdp->declBit (c+394,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_isIoAccess",-1); vcdp->declBit (c+395,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_allowRead",-1); vcdp->declBit (c+396,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_allowWrite",-1); vcdp->declBit (c+397,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_allowExecute",-1); vcdp->declBit (c+398,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_exception",-1); vcdp->declBit (c+399,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_rsp_refilling",-1); vcdp->declBit (c+277,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_end",-1); vcdp->declBit (c+767,"dut VexRiscv dataCache_1_ io_cpu_memory_mmuBus_busy",-1); vcdp->declBit (c+592,"dut VexRiscv dataCache_1_ io_cpu_writeBack_isValid",-1); vcdp->declBit (c+368,"dut VexRiscv dataCache_1_ io_cpu_writeBack_isStuck",-1); vcdp->declBit (c+996,"dut VexRiscv dataCache_1_ io_cpu_writeBack_isUser",-1); vcdp->declBit (c+278,"dut VexRiscv dataCache_1_ io_cpu_writeBack_haltIt",-1); vcdp->declBit (c+682,"dut VexRiscv dataCache_1_ io_cpu_writeBack_isWrite",-1); vcdp->declBus (c+279,"dut VexRiscv dataCache_1_ io_cpu_writeBack_data",-1,31,0); vcdp->declBus (c+747,"dut VexRiscv dataCache_1_ io_cpu_writeBack_address",-1,31,0); vcdp->declBit (c+280,"dut VexRiscv dataCache_1_ io_cpu_writeBack_mmuException",-1); vcdp->declBit (c+281,"dut VexRiscv dataCache_1_ io_cpu_writeBack_unalignedAccess",-1); vcdp->declBit (c+282,"dut VexRiscv dataCache_1_ io_cpu_writeBack_accessError",-1); vcdp->declBit (c+409,"dut VexRiscv dataCache_1_ io_cpu_writeBack_clearLrsc",-1); vcdp->declBit (c+284,"dut VexRiscv dataCache_1_ io_cpu_redo",-1); vcdp->declBit (c+593,"dut VexRiscv dataCache_1_ io_cpu_flush_valid",-1); vcdp->declBit (c+283,"dut VexRiscv dataCache_1_ io_cpu_flush_ready",-1); vcdp->declBit (c+285,"dut VexRiscv dataCache_1_ io_mem_cmd_valid",-1); vcdp->declBit (c+1020,"dut VexRiscv dataCache_1_ io_mem_cmd_ready",-1); vcdp->declBit (c+286,"dut VexRiscv dataCache_1_ io_mem_cmd_payload_wr",-1); vcdp->declBus (c+287,"dut VexRiscv dataCache_1_ io_mem_cmd_payload_address",-1,31,0); vcdp->declBus (c+288,"dut VexRiscv dataCache_1_ io_mem_cmd_payload_data",-1,31,0); vcdp->declBus (c+683,"dut VexRiscv dataCache_1_ io_mem_cmd_payload_mask",-1,3,0); vcdp->declBus (c+289,"dut VexRiscv dataCache_1_ io_mem_cmd_payload_length",-1,2,0); vcdp->declBit (c+290,"dut VexRiscv dataCache_1_ io_mem_cmd_payload_last",-1); vcdp->declBit (c+790,"dut VexRiscv dataCache_1_ io_mem_rsp_valid",-1); vcdp->declBus (c+791,"dut VexRiscv dataCache_1_ io_mem_rsp_payload_data",-1,31,0); vcdp->declBit (c+1128,"dut VexRiscv dataCache_1_ io_mem_rsp_payload_error",-1); vcdp->declBit (c+1071,"dut VexRiscv dataCache_1_ clk",-1); vcdp->declBit (c+270,"dut VexRiscv dataCache_1_ reset",-1); // Tracing: dut VexRiscv dataCache_1_ _zz_10_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:396 // Tracing: dut VexRiscv dataCache_1_ _zz_11_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:397 // Tracing: dut VexRiscv dataCache_1_ _zz_12_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:398 // Tracing: dut VexRiscv dataCache_1_ _zz_13_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:399 // Tracing: dut VexRiscv dataCache_1_ _zz_14_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:400 // Tracing: dut VexRiscv dataCache_1_ _zz_15_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:401 // Tracing: dut VexRiscv dataCache_1_ _zz_16_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:402 // Tracing: dut VexRiscv dataCache_1_ _zz_17_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:403 // Tracing: dut VexRiscv dataCache_1_ _zz_18_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:404 // Tracing: dut VexRiscv dataCache_1_ _zz_19_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:405 // Tracing: dut VexRiscv dataCache_1_ _zz_20_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:406 // Tracing: dut VexRiscv dataCache_1_ _zz_21_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:407 // Tracing: dut VexRiscv dataCache_1_ _zz_22_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:408 // Tracing: dut VexRiscv dataCache_1_ _zz_23_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:409 // Tracing: dut VexRiscv dataCache_1_ _zz_24_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:410 // Tracing: dut VexRiscv dataCache_1_ _zz_25_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:411 // Tracing: dut VexRiscv dataCache_1_ _zz_26_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:412 // Tracing: dut VexRiscv dataCache_1_ _zz_27_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:413 // Tracing: dut VexRiscv dataCache_1_ _zz_28_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:414 // Tracing: dut VexRiscv dataCache_1_ _zz_29_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:415 // Tracing: dut VexRiscv dataCache_1_ _zz_30_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:416 // Tracing: dut VexRiscv dataCache_1_ _zz_31_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:417 // Tracing: dut VexRiscv dataCache_1_ _zz_32_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:418 // Tracing: dut VexRiscv dataCache_1_ _zz_33_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:419 // Tracing: dut VexRiscv dataCache_1_ _zz_34_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:420 // Tracing: dut VexRiscv dataCache_1_ _zz_35_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:421 // Tracing: dut VexRiscv dataCache_1_ _zz_36_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:422 // Tracing: dut VexRiscv dataCache_1_ _zz_37_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:423 // Tracing: dut VexRiscv dataCache_1_ _zz_1_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:424 // Tracing: dut VexRiscv dataCache_1_ _zz_2_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:425 vcdp->declBit (c+1128,"dut VexRiscv dataCache_1_ haltCpu",-1); vcdp->declBit (c+594,"dut VexRiscv dataCache_1_ tagsReadCmd_valid",-1); vcdp->declBus (c+595,"dut VexRiscv dataCache_1_ tagsReadCmd_payload",-1,6,0); vcdp->declBit (c+596,"dut VexRiscv dataCache_1_ tagsWriteCmd_valid",-1); vcdp->declBus (c+597,"dut VexRiscv dataCache_1_ tagsWriteCmd_payload_way",-1,0,0); vcdp->declBus (c+598,"dut VexRiscv dataCache_1_ tagsWriteCmd_payload_address",-1,6,0); vcdp->declBit (c+599,"dut VexRiscv dataCache_1_ tagsWriteCmd_payload_data_valid",-1); vcdp->declBit (c+600,"dut VexRiscv dataCache_1_ tagsWriteCmd_payload_data_error",-1); vcdp->declBus (c+601,"dut VexRiscv dataCache_1_ tagsWriteCmd_payload_data_address",-1,19,0); vcdp->declBit (c+1021,"dut VexRiscv dataCache_1_ tagsWriteLastCmd_valid",-1); vcdp->declBus (c+1022,"dut VexRiscv dataCache_1_ tagsWriteLastCmd_payload_way",-1,0,0); vcdp->declBus (c+1023,"dut VexRiscv dataCache_1_ tagsWriteLastCmd_payload_address",-1,6,0); vcdp->declBit (c+1024,"dut VexRiscv dataCache_1_ tagsWriteLastCmd_payload_data_valid",-1); vcdp->declBit (c+1025,"dut VexRiscv dataCache_1_ tagsWriteLastCmd_payload_data_error",-1); vcdp->declBus (c+1026,"dut VexRiscv dataCache_1_ tagsWriteLastCmd_payload_data_address",-1,19,0); vcdp->declBit (c+602,"dut VexRiscv dataCache_1_ dataReadCmd_valid",-1); vcdp->declBus (c+603,"dut VexRiscv dataCache_1_ dataReadCmd_payload",-1,9,0); vcdp->declBit (c+604,"dut VexRiscv dataCache_1_ dataWriteCmd_valid",-1); vcdp->declBus (c+605,"dut VexRiscv dataCache_1_ dataWriteCmd_payload_way",-1,0,0); vcdp->declBus (c+606,"dut VexRiscv dataCache_1_ dataWriteCmd_payload_address",-1,9,0); vcdp->declBus (c+607,"dut VexRiscv dataCache_1_ dataWriteCmd_payload_data",-1,31,0); vcdp->declBus (c+608,"dut VexRiscv dataCache_1_ dataWriteCmd_payload_mask",-1,3,0); // Tracing: dut VexRiscv dataCache_1_ _zz_3_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:448 vcdp->declBit (c+1027,"dut VexRiscv dataCache_1_ ways_0_tagsReadRsp_valid",-1); vcdp->declBit (c+1028,"dut VexRiscv dataCache_1_ ways_0_tagsReadRsp_error",-1); vcdp->declBus (c+1029,"dut VexRiscv dataCache_1_ ways_0_tagsReadRsp_address",-1,19,0); // Tracing: dut VexRiscv dataCache_1_ _zz_4_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:452 // Tracing: dut VexRiscv dataCache_1_ _zz_5_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:453 vcdp->declBus (c+1030,"dut VexRiscv dataCache_1_ ways_0_dataReadRsp",-1,31,0); // Tracing: dut VexRiscv dataCache_1_ _zz_6_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:455 vcdp->declBus (c+609,"dut VexRiscv dataCache_1_ stage0_mask",-1,3,0); vcdp->declBus (c+610,"dut VexRiscv dataCache_1_ stage0_colisions",-1,0,0); vcdp->declBit (c+680,"dut VexRiscv dataCache_1_ stageA_request_wr",-1); vcdp->declBus (c+1031,"dut VexRiscv dataCache_1_ stageA_request_data",-1,31,0); vcdp->declBus (c+1032,"dut VexRiscv dataCache_1_ stageA_request_size",-1,1,0); vcdp->declBit (c+1033,"dut VexRiscv dataCache_1_ stageA_request_isLrsc",-1); vcdp->declBit (c+1034,"dut VexRiscv dataCache_1_ stageA_request_isAmo",-1); vcdp->declBit (c+1035,"dut VexRiscv dataCache_1_ stageA_request_amoCtrl_swap",-1); vcdp->declBus (c+1036,"dut VexRiscv dataCache_1_ stageA_request_amoCtrl_alu",-1,2,0); vcdp->declBus (c+1037,"dut VexRiscv dataCache_1_ stageA_mask",-1,3,0); vcdp->declBit (c+611,"dut VexRiscv dataCache_1_ stageA_wayHits_0",-1); vcdp->declBus (c+1038,"dut VexRiscv dataCache_1_ stage0_colisions_regNextWhen",-1,0,0); // Tracing: dut VexRiscv dataCache_1_ _zz_7_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:468 vcdp->declBus (c+612,"dut VexRiscv dataCache_1_ stageA_colisions",-1,0,0); vcdp->declBit (c+682,"dut VexRiscv dataCache_1_ stageB_request_wr",-1); vcdp->declBus (c+1039,"dut VexRiscv dataCache_1_ stageB_request_data",-1,31,0); vcdp->declBus (c+1040,"dut VexRiscv dataCache_1_ stageB_request_size",-1,1,0); vcdp->declBit (c+1041,"dut VexRiscv dataCache_1_ stageB_request_isLrsc",-1); vcdp->declBit (c+1042,"dut VexRiscv dataCache_1_ stageB_isAmo",-1); vcdp->declBit (c+1043,"dut VexRiscv dataCache_1_ stageB_request_amoCtrl_swap",-1); vcdp->declBus (c+1044,"dut VexRiscv dataCache_1_ stageB_request_amoCtrl_alu",-1,2,0); vcdp->declBit (c+613,"dut VexRiscv dataCache_1_ stageB_mmuRspFreeze",-1); vcdp->declBus (c+1045,"dut VexRiscv dataCache_1_ stageB_mmuRsp_physicalAddress",-1,31,0); vcdp->declBit (c+1046,"dut VexRiscv dataCache_1_ stageB_mmuRsp_isIoAccess",-1); vcdp->declBit (c+1047,"dut VexRiscv dataCache_1_ stageB_mmuRsp_allowRead",-1); vcdp->declBit (c+1048,"dut VexRiscv dataCache_1_ stageB_mmuRsp_allowWrite",-1); vcdp->declBit (c+1049,"dut VexRiscv dataCache_1_ stageB_mmuRsp_allowExecute",-1); vcdp->declBit (c+1050,"dut VexRiscv dataCache_1_ stageB_mmuRsp_exception",-1); vcdp->declBit (c+1051,"dut VexRiscv dataCache_1_ stageB_mmuRsp_refilling",-1); vcdp->declBit (c+1052,"dut VexRiscv dataCache_1_ stageB_tagsReadRsp_0_valid",-1); vcdp->declBit (c+1053,"dut VexRiscv dataCache_1_ stageB_tagsReadRsp_0_error",-1); vcdp->declBus (c+1054,"dut VexRiscv dataCache_1_ stageB_tagsReadRsp_0_address",-1,19,0); vcdp->declBus (c+1055,"dut VexRiscv dataCache_1_ stageB_dataReadRsp_0",-1,31,0); // Tracing: dut VexRiscv dataCache_1_ _zz_8_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:489 vcdp->declBus (c+1056,"dut VexRiscv dataCache_1_ stageB_waysHits",-1,0,0); vcdp->declBit (c+1057,"dut VexRiscv dataCache_1_ stageB_waysHit",-1); vcdp->declBus (c+1055,"dut VexRiscv dataCache_1_ stageB_dataMux",-1,31,0); vcdp->declBus (c+683,"dut VexRiscv dataCache_1_ stageB_mask",-1,3,0); vcdp->declBus (c+1058,"dut VexRiscv dataCache_1_ stageB_colisions",-1,0,0); vcdp->declBit (c+614,"dut VexRiscv dataCache_1_ stageB_loaderValid",-1); vcdp->declBit (c+1059,"dut VexRiscv dataCache_1_ stageB_flusher_valid",-1); vcdp->declBit (c+1060,"dut VexRiscv dataCache_1_ stageB_lrsc_reserved",-1); vcdp->declBus (c+288,"dut VexRiscv dataCache_1_ stageB_requestDataBypass",-1,31,0); vcdp->declBit (c+1061,"dut VexRiscv dataCache_1_ stageB_amo_compare",-1); vcdp->declBit (c+1062,"dut VexRiscv dataCache_1_ stageB_amo_unsigned",-1); vcdp->declBus (c+615,"dut VexRiscv dataCache_1_ stageB_amo_addSub",-1,31,0); vcdp->declBit (c+616,"dut VexRiscv dataCache_1_ stageB_amo_less",-1); vcdp->declBit (c+617,"dut VexRiscv dataCache_1_ stageB_amo_selectRf",-1); vcdp->declBus (c+618,"dut VexRiscv dataCache_1_ stageB_amo_result",-1,31,0); vcdp->declBit (c+1063,"dut VexRiscv dataCache_1_ stageB_amo_resultRegValid",-1); vcdp->declBus (c+1064,"dut VexRiscv dataCache_1_ stageB_amo_resultReg",-1,31,0); vcdp->declBit (c+1065,"dut VexRiscv dataCache_1_ stageB_memCmdSent",-1); // Tracing: dut VexRiscv dataCache_1_ _zz_9_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:508 vcdp->declBit (c+1066,"dut VexRiscv dataCache_1_ loader_valid",-1); vcdp->declBit (c+619,"dut VexRiscv dataCache_1_ loader_counter_willIncrement",-1); vcdp->declBit (c+1128,"dut VexRiscv dataCache_1_ loader_counter_willClear",-1); vcdp->declBus (c+620,"dut VexRiscv dataCache_1_ loader_counter_valueNext",-1,2,0); vcdp->declBus (c+1067,"dut VexRiscv dataCache_1_ loader_counter_value",-1,2,0); vcdp->declBit (c+1068,"dut VexRiscv dataCache_1_ loader_counter_willOverflowIfInc",-1); vcdp->declBit (c+621,"dut VexRiscv dataCache_1_ loader_counter_willOverflow",-1); vcdp->declBus (c+1069,"dut VexRiscv dataCache_1_ loader_waysAllocator",-1,0,0); vcdp->declBit (c+1070,"dut VexRiscv dataCache_1_ loader_error",-1); // Tracing: dut VexRiscv dataCache_1_ ways_0_tags // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:518 // Tracing: dut VexRiscv dataCache_1_ ways_0_data_symbol0 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:519 // Tracing: dut VexRiscv dataCache_1_ ways_0_data_symbol1 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:520 // Tracing: dut VexRiscv dataCache_1_ ways_0_data_symbol2 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:521 // Tracing: dut VexRiscv dataCache_1_ ways_0_data_symbol3 // Ignored: Wide memory > --trace-max-array ents at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:522 // Tracing: dut VexRiscv dataCache_1_ _zz_38_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:523 // Tracing: dut VexRiscv dataCache_1_ _zz_39_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:524 // Tracing: dut VexRiscv dataCache_1_ _zz_40_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:525 // Tracing: dut VexRiscv dataCache_1_ _zz_41_ // Ignored: Inlined leading underscore at /home/tom/src/litex/litex/soc/cores/cpu/vexriscv/verilog/VexRiscv_Linux.v:526 } } void Vdut::traceFullThis__1(Vdut__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { Vdut* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; int c=code; if (0 && vcdp && c) {} // Prevent unused // Variables VL_SIGW(__Vtemp2,95,0,3); VL_SIGW(__Vtemp3,95,0,3); VL_SIGW(__Vtemp4,95,0,3); VL_SIGW(__Vtemp5,95,0,3); VL_SIGW(__Vtemp6,95,0,3); // Body { vcdp->fullBus (c+1,(vlSymsp->TOP__dut.__PVT__builder_array_muxed7),2); vcdp->fullBit (c+2,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_readable)); vcdp->fullBus (c+3,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_fifo_out_payload_data),8); vcdp->fullBit (c+4,((0x10U != (IData)(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_level0)))); vcdp->fullBit (c+5,((((0U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (0U == (0xfU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+6,((1U & vlSymsp->TOP__dut.__PVT__builder_array_muxed1))); vcdp->fullBit (c+7,((((0U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0U == (0xfU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+8,(vlSymsp->TOP__dut.__PVT__main_soclinux_ctrl_storage),32); vcdp->fullBit (c+9,(vlSymsp->TOP__dut.__PVT__main_soclinux_ctrl_re)); vcdp->fullBus (c+10,(vlSymsp->TOP__dut.__PVT__main_soclinux_ctrl_bus_errors),32); vcdp->fullBit (c+11,((((0U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (8U == (0xfU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+12,(vlSymsp->TOP__dut.__PVT__builder_error)); vcdp->fullBus (c+13,(vlSymsp->TOP__dut.__PVT__builder_shared_dat_r),32); vcdp->fullBit (c+14,(vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_CYC)); vcdp->fullBit (c+15,(vlSymsp->TOP__dut__VexRiscv.__PVT__iBusWishbone_STB)); vcdp->fullBit (c+16,(vlSymsp->TOP__dut.__PVT__main_soclinux_interface0_soc_bus_ack)); vcdp->fullBit (c+17,(vlSymsp->TOP__dut.__PVT__main_soclinux_interface1_soc_bus_ack)); vcdp->fullBus (c+18,(((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_166_)) ? ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_) ? 7U : 2U) : 0U)),3); vcdp->fullBus (c+19,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_interrupt0),32); vcdp->fullBit (c+20,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_latch_re)); vcdp->fullBit (c+21,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullQuad (c+22,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status),64); vcdp->fullBit (c+24,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (8U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullQuad (c+25,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_cmp_storage),64); vcdp->fullBit (c+27,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_cmp_re)); vcdp->fullBit (c+28,((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time >= vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_cmp))); vcdp->fullQuad (c+29,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time),64); vcdp->fullQuad (c+31,(vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_cmp),64); vcdp->fullBus (c+33,(vlSymsp->TOP__dut.__PVT__builder_array_muxed0),30); vcdp->fullBus (c+34,(vlSymsp->TOP__dut.__PVT__builder_array_muxed1),32); vcdp->fullBus (c+35,(vlSymsp->TOP__dut.__PVT__builder_array_muxed2),4); vcdp->fullBit (c+36,(((IData)(vlSymsp->TOP__dut.__PVT__builder_array_muxed3) & (IData)(vlSymsp->TOP__dut.__PVT__builder_slave_sel)))); vcdp->fullBit (c+37,(vlSymsp->TOP__dut.__PVT__builder_array_muxed4)); vcdp->fullBit (c+38,(vlSymsp->TOP__dut.__PVT__main_soclinux_rom_bus_ack)); vcdp->fullBit (c+39,(vlSymsp->TOP__dut.__PVT__builder_array_muxed5)); vcdp->fullBus (c+40,(vlSymsp->TOP__dut.__PVT__builder_array_muxed6),3); vcdp->fullBus (c+41,((0x1fffU & vlSymsp->TOP__dut.__PVT__builder_array_muxed0)),13); vcdp->fullBus (c+42,(vlSymsp->TOP__dut.__PVT__mem_1 [vlSymsp->TOP__dut.__PVT__memadr]),32); vcdp->fullBit (c+43,(vlSymsp->TOP__dut.__PVT__main_soclinux_sram_bus_cyc)); vcdp->fullBit (c+44,(vlSymsp->TOP__dut.__PVT__main_soclinux_sram_bus_ack)); vcdp->fullBus (c+45,((0x3ffU & vlSymsp->TOP__dut.__PVT__builder_array_muxed0)),10); vcdp->fullBus (c+46,(vlSymsp->TOP__dut.__PVT__main_soclinux_sram_we),4); vcdp->fullBus (c+47,(vlSymsp->TOP__dut.__PVT__mem_2 [vlSymsp->TOP__dut.__PVT__memadr_1]),32); vcdp->fullBit (c+48,(vlSymsp->TOP__dut.__PVT__main_soclinux_main_ram_bus_cyc)); vcdp->fullBit (c+49,(vlSymsp->TOP__dut.__PVT__main_soclinux_main_ram_bus_ack)); vcdp->fullBus (c+50,((0x7fffffU & vlSymsp->TOP__dut.__PVT__builder_array_muxed0)),23); vcdp->fullBus (c+51,(vlSymsp->TOP__dut.__PVT__main_soclinux_main_ram_we),4); vcdp->fullBus (c+52,(vlSymsp->TOP__dut.__PVT__main_soclinux_load_storage),32); vcdp->fullBit (c+53,(vlSymsp->TOP__dut.__PVT__main_soclinux_load_re)); vcdp->fullBus (c+54,(vlSymsp->TOP__dut.__PVT__main_soclinux_reload_storage),32); vcdp->fullBit (c+55,(vlSymsp->TOP__dut.__PVT__main_soclinux_reload_re)); vcdp->fullBit (c+56,(vlSymsp->TOP__dut.__PVT__main_soclinux_en_storage)); vcdp->fullBit (c+57,(vlSymsp->TOP__dut.__PVT__main_soclinux_en_re)); vcdp->fullBit (c+58,(vlSymsp->TOP__dut.__PVT__main_soclinux_update_value_storage)); vcdp->fullBit (c+59,(vlSymsp->TOP__dut.__PVT__main_soclinux_update_value_re)); vcdp->fullBus (c+60,(vlSymsp->TOP__dut.__PVT__main_soclinux_value_status),32); vcdp->fullBit (c+61,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0xdU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+62,(((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_zero_pending) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_eventmanager_storage)))); vcdp->fullBit (c+63,((0U != vlSymsp->TOP__dut.__PVT__main_soclinux_value))); vcdp->fullBit (c+64,(vlSymsp->TOP__dut.__PVT__main_soclinux_zero_pending)); vcdp->fullBit (c+65,(vlSymsp->TOP__dut.__PVT__main_soclinux_zero_clear)); vcdp->fullBit (c+66,(vlSymsp->TOP__dut.__PVT__main_soclinux_zero_old_trigger)); vcdp->fullBit (c+67,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (0xeU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+68,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0xeU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+69,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (0xfU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+70,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0xfU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+71,(vlSymsp->TOP__dut.__PVT__main_soclinux_eventmanager_storage)); vcdp->fullBit (c+72,(vlSymsp->TOP__dut.__PVT__main_soclinux_eventmanager_re)); vcdp->fullBus (c+73,(vlSymsp->TOP__dut.__PVT__main_soclinux_value),32); vcdp->fullBus (c+74,(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr),14); vcdp->fullBit (c+75,(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)); vcdp->fullBus (c+76,((0xffU & vlSymsp->TOP__dut.__PVT__builder_array_muxed1)),8); vcdp->fullBus (c+77,((((((IData)(vlSymsp->TOP__dut.__PVT__builder_interface0_bank_bus_dat_r) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface1_bank_bus_dat_r)) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface2_bank_bus_dat_r)) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface3_bank_bus_dat_r)) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface4_bank_bus_dat_r))),8); vcdp->fullBus (c+78,((((((IData)(vlSymsp->TOP__dut.__PVT__builder_interface0_bank_bus_dat_r) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface1_bank_bus_dat_r)) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface2_bank_bus_dat_r)) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface3_bank_bus_dat_r)) | (IData)(vlSymsp->TOP__dut.__PVT__builder_interface4_bank_bus_dat_r))),32); vcdp->fullBit (c+79,(vlSymsp->TOP__dut.__PVT__main_soclinux_bus_wishbone_cyc)); vcdp->fullBit (c+80,(vlSymsp->TOP__dut.__PVT__main_soclinux_bus_wishbone_ack)); vcdp->fullBit (c+81,((((4U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr))))); vcdp->fullBit (c+82,((((4U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr))))); vcdp->fullBit (c+83,(vlSymsp->TOP__dut.__PVT__main_int_rst)); vcdp->fullBus (c+84,(vlSymsp->TOP__dut.__PVT__mem_3 [vlSymsp->TOP__dut.__PVT__memadr_2]),32); vcdp->fullBit (c+85,(vlSymsp->TOP__dut.__PVT__main_bus_cyc)); vcdp->fullBit (c+86,(vlSymsp->TOP__dut.__PVT__main_bus_ack)); vcdp->fullBus (c+87,((0xfffU & vlSymsp->TOP__dut.__PVT__builder_array_muxed0)),12); vcdp->fullBus (c+88,(vlSymsp->TOP__dut.__PVT__main_we),4); vcdp->fullBit (c+89,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_fifo_out_first)); vcdp->fullBit (c+90,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_fifo_out_last)); vcdp->fullBit (c+91,(vlSymsp->TOP__dut.__PVT__main_uart_rxtx_re)); vcdp->fullBit (c+92,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+93,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_fifo_out_payload_data),8); vcdp->fullBit (c+94,((0x10U == (IData)(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_level0)))); vcdp->fullBit (c+95,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (1U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+96,((1U & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_readable))))); vcdp->fullBit (c+97,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (2U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+98,((1U & (((IData)(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_pending_w) & (IData)(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_storage)) | (((IData)(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_pending_w) & (IData)(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_storage)) >> 1U))))); vcdp->fullBit (c+99,(vlSymsp->TOP__dut.__PVT__main_uart_tx_pending)); vcdp->fullBit (c+100,(vlSymsp->TOP__dut.__PVT__main_uart_tx_clear)); vcdp->fullBit (c+101,(vlSymsp->TOP__dut.__PVT__main_uart_tx_old_trigger)); vcdp->fullBit (c+102,(vlSymsp->TOP__dut.__PVT__main_uart_rx_pending)); vcdp->fullBit (c+103,(vlSymsp->TOP__dut.__PVT__main_uart_rx_clear)); vcdp->fullBit (c+104,(vlSymsp->TOP__dut.__PVT__main_uart_rx_old_trigger)); vcdp->fullBit (c+105,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (3U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+106,((3U & vlSymsp->TOP__dut.__PVT__builder_array_muxed1)),2); vcdp->fullBit (c+107,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (3U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+108,(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_status_w),2); vcdp->fullBit (c+109,(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_pending_re)); vcdp->fullBit (c+110,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (4U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+111,(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_pending_w),2); vcdp->fullBus (c+112,(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_storage),2); vcdp->fullBit (c+113,(vlSymsp->TOP__dut.__PVT__main_uart_eventmanager_re)); vcdp->fullBit (c+114,((0x10U != (IData)(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_level0)))); vcdp->fullBit (c+115,((0U != (IData)(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_level0)))); vcdp->fullBus (c+116,((0xffU & vlSymsp->TOP__dut.__PVT__builder_array_muxed1)),10); vcdp->fullBus (c+117,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_level0),5); vcdp->fullBus (c+118,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_produce),4); vcdp->fullBus (c+119,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_consume),4); vcdp->fullBus (c+120,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_wrport_adr),4); vcdp->fullBit (c+121,(((IData)(vlSymsp->TOP__dut.__PVT__main_uart_rxtx_re) & (0x10U != (IData)(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_level0))))); vcdp->fullBus (c+122,((0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_level0) + (IData)(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_readable)))),5); vcdp->fullBit (c+123,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_readable)); vcdp->fullBit (c+124,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_fifo_out_first)); vcdp->fullBit (c+125,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_fifo_out_last)); vcdp->fullBit (c+126,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_syncfifo_re)); vcdp->fullBit (c+127,((0U != (IData)(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_level0)))); vcdp->fullBus (c+128,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_level0),5); vcdp->fullBus (c+129,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_produce),4); vcdp->fullBus (c+130,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_consume),4); vcdp->fullBus (c+131,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_wrport_adr),4); vcdp->fullBit (c+132,(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_do_read)); vcdp->fullBus (c+133,((0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_level0) + (IData)(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_readable)))),5); vcdp->fullBit (c+134,(vlSymsp->TOP__dut.__PVT__builder_state)); vcdp->fullBit (c+135,(vlSymsp->TOP__dut.__PVT__builder_next_state)); vcdp->fullBit (c+136,(vlSymsp->TOP__dut.__PVT__builder_array_muxed3)); vcdp->fullBit (c+137,(vlSymsp->TOP__dut.__PVT__builder_shared_ack)); vcdp->fullBus (c+138,(vlSymsp->TOP__dut.__PVT__builder_request),2); vcdp->fullBit (c+139,(vlSymsp->TOP__dut.__PVT__builder_grant)); vcdp->fullBus (c+140,(vlSymsp->TOP__dut.__PVT__builder_slave_sel),5); vcdp->fullBus (c+141,(vlSymsp->TOP__dut.__PVT__builder_slave_sel_r),5); vcdp->fullBit (c+142,((((IData)(vlSymsp->TOP__dut.__PVT__builder_array_muxed4) & (IData)(vlSymsp->TOP__dut.__PVT__builder_array_muxed3)) & (~ (IData)(vlSymsp->TOP__dut.__PVT__builder_shared_ack))))); vcdp->fullBit (c+143,((0U == vlSymsp->TOP__dut.__PVT__builder_count))); vcdp->fullBus (c+144,(vlSymsp->TOP__dut.__PVT__builder_count),20); vcdp->fullBus (c+145,(vlSymsp->TOP__dut.__PVT__builder_interface0_bank_bus_dat_r),8); vcdp->fullBit (c+146,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (1U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+147,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (1U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+148,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 0x38U)))),8); vcdp->fullBit (c+149,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (2U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+150,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (2U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+151,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 0x30U)))),8); vcdp->fullBit (c+152,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (3U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+153,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (3U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+154,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 0x28U)))),8); vcdp->fullBit (c+155,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (4U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+156,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (4U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+157,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 0x20U)))),8); vcdp->fullBit (c+158,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (5U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+159,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (5U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+160,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 0x18U)))),8); vcdp->fullBit (c+161,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (6U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+162,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (6U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+163,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 0x10U)))),8); vcdp->fullBit (c+164,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (7U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+165,((((1U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (7U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+166,((0xffU & (IData)((vlSymsp->TOP__dut.__PVT__main_soclinux_cpu_time_status >> 8U)))),8); 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vcdp->fullBus (c+255,((0xffU & (vlSymsp->TOP__dut.__PVT__main_soclinux_value_status >> 0x10U))),8); vcdp->fullBit (c+256,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (0xcU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+257,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0xcU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+258,((0xffU & (vlSymsp->TOP__dut.__PVT__main_soclinux_value_status >> 8U))),8); vcdp->fullBit (c+259,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (0xdU == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBus (c+260,((0xffU & vlSymsp->TOP__dut.__PVT__main_soclinux_value_status)),8); vcdp->fullBit (c+261,(vlSymsp->TOP__dut.__PVT__builder_csrbank3_ev_enable0_re)); vcdp->fullBit (c+262,((((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (0x10U == (0x1fU & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+263,((3U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))))); vcdp->fullBus (c+264,(vlSymsp->TOP__dut.__PVT__builder_interface4_bank_bus_dat_r),8); vcdp->fullBit (c+265,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (1U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+266,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we)) & (2U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+267,(vlSymsp->TOP__dut.__PVT__builder_csrbank4_ev_enable0_re)); vcdp->fullBit (c+268,((((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))) & (~ (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_we))) & (5U == (7U & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr)))))); vcdp->fullBit (c+269,((2U == (0x1fU & ((IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface_adr) >> 9U))))); vcdp->fullBit (c+270,(vlSymsp->TOP__dut.__Vcellinp__VexRiscv__reset)); vcdp->fullBit (c+271,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)); vcdp->fullBus (c+272,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress),32); vcdp->fullBit (c+273,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_256_)); vcdp->fullBit (c+274,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_fetcherflushIt)))); vcdp->fullBit (c+275,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid)); vcdp->fullBit (c+276,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_272_)); vcdp->fullBit (c+277,((1U & ((~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_isStuck)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_arbitration_removeIt))))); vcdp->fullBit (c+278,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_haltIt)); vcdp->fullBus (c+279,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data),32); vcdp->fullBit (c+280,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_mmuException)); vcdp->fullBit (c+281,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_unalignedAccess)); vcdp->fullBit (c+282,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_accessError)); vcdp->fullBit (c+283,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_flush_ready)); vcdp->fullBit (c+284,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_redo)); vcdp->fullBit (c+285,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid)); vcdp->fullBit (c+286,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_wr)); vcdp->fullBus (c+287,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_address),32); vcdp->fullBus (c+288,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_requestDataBypass),32); vcdp->fullBus (c+289,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_length),3); vcdp->fullBit (c+290,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last)); vcdp->fullQuad (c+291,((VL_ULL(0x3ffffffff) & VL_MULS_QQQ(34,34,34, (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_))), (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh))))),34); vcdp->fullBit (c+293,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x14U))))); vcdp->fullBus (c+294,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1cU)))),2); vcdp->fullBus (c+295,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 4U)))),2); vcdp->fullBit (c+296,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1bU))))); vcdp->fullBus (c+297,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x12U)))),2); vcdp->fullBit (c+298,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x21U))))); vcdp->fullQuad (c+299,((VL_ULL(0x3ffffffff) & VL_MULS_QQQ(34,34,34, (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh)), (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh))))),34); vcdp->fullBit (c+301,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xfU))))); vcdp->fullBit (c+302,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PREDICTION_HAD_BRANCHED2) != ((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) & ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) | ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) | ((0U == (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq) : ((1U == (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq)) : ((5U == (5U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less)) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less)))))))))); vcdp->fullBus (c+303,((0xfffffffeU & (((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC) + vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2))),32); vcdp->fullBus (c+304,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 9U)))),2); vcdp->fullBit (c+305,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_dBusAccess_cmd_ready)))); vcdp->fullBit (c+306,((0x20U != (0x7fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 7U))))); vcdp->fullBus (c+307,(((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ ^ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_))) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_less) : vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SrcPlugin_addSub))),32); vcdp->fullBit (c+308,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 3U))))); vcdp->fullBit (c+309,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x19U))))); vcdp->fullBus (c+310,(((0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_) * (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_))),32); vcdp->fullBit (c+311,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x15U))))); vcdp->fullQuad (c+312,((VL_ULL(0x3ffffffff) & VL_MULS_QQQ(34,34,34, (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh)), (VL_ULL(0x3ffffffff) & VL_EXTENDS_QI(34,17, (0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)))))),34); vcdp->fullBus (c+314,((3U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_)),2); vcdp->fullBit (c+315,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x18U))))); vcdp->fullBit (c+316,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1aU))))); vcdp->fullBit (c+317,((1U & ((IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xcU)) & (~ (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x20U))))))); vcdp->fullBit (c+318,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 6U))))); vcdp->fullBus (c+319,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x16U)))),2); vcdp->fullBus (c+320,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x10U)))),2); vcdp->fullBit (c+321,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xbU))))); vcdp->fullBus (c+322,((IData)((VL_ULL(0x1ffffffff) & VL_SHIFTRS_QQI(33,33,5, (((QData)((IData)( ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL)) & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed >> 0x1fU)))) << 0x20U) | (QData)((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed))), (0x1fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_))))),32); vcdp->fullBit (c+323,((1U & (~ (((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))) & (0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU)))) | ((3U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xdU))) & (0U == (0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))))))))); vcdp->fullBit (c+324,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 2U))))); vcdp->fullBit (c+325,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1fU))))); vcdp->fullBit (c+326,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decodePrediction_cmd_hadBranch)); vcdp->fullBit (c+327,(((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) & ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) | ((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) | ((0U == (7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) ? 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vcdp->fullBit (c+340,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 8U))))); vcdp->fullBit (c+341,((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 7U))))); vcdp->fullBit (c+342,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_rsp_issueDetected)); vcdp->fullBus (c+343,((3U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU)))),2); vcdp->fullBus (c+344,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst),32); vcdp->fullBit (c+345,((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)))); vcdp->fullBit (c+346,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltItself)); vcdp->fullBit (c+347,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_haltByOther)); vcdp->fullBit (c+348,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_removeIt)); vcdp->fullBit (c+349,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_flushNext)); vcdp->fullBit (c+350,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isValid)); 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vcdp->fullBit (c+430,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt)); vcdp->fullBit (c+431,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_readyForError)); vcdp->fullBit (c+432,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_valid)); vcdp->fullBit (c+433,((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_arbitration_isStuck))))); vcdp->fullBus (c+434,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode),32); vcdp->fullBus (c+435,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decompressed),32); vcdp->fullBit (c+436,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_bufferFill)); vcdp->fullBit (c+437,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache_io_mem_cmd_valid) & (IData)(vlSymsp->TOP__dut.__PVT__main_soclinux_interface0_soc_bus_ack)))); vcdp->fullBit (c+438,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_249_) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_251_))))); vcdp->fullBit (c+439,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_valid) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_)))); vcdp->fullBit (c+440,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_s2mPipe_ready)); vcdp->fullBit (c+441,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_) ? 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(IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_160_) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_mem_cmd_payload_last)))); vcdp->fullBus (c+446,(vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted),32); vcdp->fullBus (c+447,(((0U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_171_ : ((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_INSTRUCTION >> 0xcU))) ? vlSymsp->TOP__dut__VexRiscv.__PVT___zz_173_ : vlSymsp->TOP__dut__VexRiscv.__PVT__writeBack_DBusCachedPlugin_rspShifted))),32); vcdp->fullBit (c+448,(vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_forceDatapath)); vcdp->fullBit (c+449,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_1)); vcdp->fullBit (c+450,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_2)); vcdp->fullBit (c+451,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHits_3)); vcdp->fullBit (c+452,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_cacheHit)); vcdp->fullBit (c+453,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_283_)); vcdp->fullBit (c+454,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_284_)); vcdp->fullBit (c+455,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_285_)); vcdp->fullBus (c+456,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_286_),10); vcdp->fullBus (c+457,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_287_),10); vcdp->fullBus (c+458,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_288_),10); vcdp->fullBus (c+459,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_289_),10); vcdp->fullBit (c+460,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_290_)); vcdp->fullBit (c+461,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_291_)); vcdp->fullBit (c+462,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_292_)); vcdp->fullBit (c+463,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_293_)); vcdp->fullBit (c+464,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement)); vcdp->fullBus (c+465,((3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement)))),2); vcdp->fullBit (c+466,(((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_entryToReplace_willIncrement)))); vcdp->fullBit (c+467,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_0_requireMmuLockup)); vcdp->fullBit (c+468,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_1)); vcdp->fullBit (c+469,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_2)); vcdp->fullBit (c+470,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHits_3)); vcdp->fullBit (c+471,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cacheHit)); vcdp->fullBit (c+472,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_294_)); vcdp->fullBit (c+473,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_295_)); vcdp->fullBit (c+474,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_296_)); vcdp->fullBus (c+475,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_297_),10); vcdp->fullBus (c+476,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_298_),10); vcdp->fullBus (c+477,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_299_),10); vcdp->fullBus (c+478,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_300_),10); vcdp->fullBit (c+479,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_301_)); vcdp->fullBit (c+480,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_302_)); vcdp->fullBit (c+481,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_303_)); vcdp->fullBit (c+482,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_304_)); vcdp->fullBit (c+483,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement)); vcdp->fullBus (c+484,((3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement)))),2); vcdp->fullBit (c+485,(((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_entryToReplace_willIncrement)))); vcdp->fullBit (c+486,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_requireMmuLockup)); vcdp->fullBit (c+487,((1U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data))); vcdp->fullBit (c+488,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 1U)))); vcdp->fullBit (c+489,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 2U)))); vcdp->fullBit (c+490,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 3U)))); vcdp->fullBit (c+491,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 4U)))); vcdp->fullBit (c+492,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 5U)))); vcdp->fullBit (c+493,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 6U)))); vcdp->fullBit (c+494,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 7U)))); vcdp->fullBus (c+495,((3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 8U))),2); vcdp->fullBus (c+496,((0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0xaU))),10); vcdp->fullBus (c+497,((0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___05Fio_cpu_writeBack_data >> 0x14U))),12); vcdp->fullBit (c+498,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_exception)); vcdp->fullBit (c+499,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_dBusRsp_leaf)); vcdp->fullBus (c+500,((0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))),5); vcdp->fullBus (c+501,((0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))),5); vcdp->fullBus (c+502,(((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? 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(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ | vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_) : (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_ ^ vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)))),32); vcdp->fullBus (c+503,((0x1fU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)),5); vcdp->fullBus (c+504,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_FullBarrelShifterPlugin_reversed),32); vcdp->fullBit (c+505,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_eq)); vcdp->fullBus (c+506,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2),32); vcdp->fullBus (c+507,((((3U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_RS1 : vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_PC) + vlSymsp->TOP__dut__VexRiscv.__PVT__execute_BranchPlugin_branch_src2)),32); vcdp->fullQuad (c+508,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_mcycle),64); vcdp->fullQuad (c+510,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_minstret),64); vcdp->fullBit (c+512,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_sip_SEIP_OR)); vcdp->fullBit (c+513,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_decode)); vcdp->fullBit (c+514,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_execute)); vcdp->fullBit (c+515,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_memory)); vcdp->fullBit (c+516,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); vcdp->fullBus (c+517,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped),2); vcdp->fullBus (c+518,((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_) < (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped)) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_))),2); vcdp->fullBit (c+519,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_pipelineLiberator_done)); vcdp->fullBus (c+520,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_targetPrivilege),2); vcdp->fullBus (c+521,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_trapCause),4); vcdp->fullBus (c+522,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_mode),2); vcdp->fullBus (c+523,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_xtvec_base),30); vcdp->fullBit (c+524,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects)); vcdp->fullBit (c+525,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalAccess)); vcdp->fullBit (c+526,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_illegalInstruction)); vcdp->fullBus (c+527,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readData),32); vcdp->fullBit (c+528,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeEnable)); vcdp->fullBit (c+529,((((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE)) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_blockedBySideEffects))) & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isStuckByOthers))))); vcdp->fullBus (c+530,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_readToWriteData),32); vcdp->fullBus (c+531,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_writeData),32); vcdp->fullBus (c+532,((0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_)),16); vcdp->fullBus (c+533,((0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)),16); vcdp->fullBus (c+534,((0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_196_)),17); vcdp->fullBus (c+535,((0xffffU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_201_)),17); vcdp->fullBus (c+536,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_aHigh),17); vcdp->fullBus (c+537,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_MulPlugin_bHigh),17); vcdp->fullBit (c+538,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement)); vcdp->fullBit (c+539,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willClear)); vcdp->fullBus (c+540,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_valueNext),6); vcdp->fullBit (c+541,(((0x21U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_willIncrement)))); vcdp->fullQuad (c+542,(((0U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1cU)))) ? VL_ULL(0x584f525f31) : ((1U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1cU)))) ? VL_ULL(0x4f525f3120) : ((2U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x1cU)))) ? VL_ULL(0x414e445f31) : VL_ULL(0x3f3f3f3f3f))))),40); vcdp->fullQuad (c+544,(((0U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 4U)))) ? VL_ULL(0x4144445f53554220) : ((1U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 4U)))) ? VL_ULL(0x534c545f534c5455) : ((2U == (3U & (IData)( (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 4U)))) ? VL_ULL(0x4249545749534520) : VL_ULL(0x3f3f3f3f3f3f3f3f))))),64); vcdp->fullQuad (c+546,(((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x13U))) ? ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x12U))) ? VL_ULL(0x4543414c4c) : VL_ULL(0x5746492020)) : ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0x12U))) ? VL_ULL(0x5852455420) : VL_ULL(0x4e4f4e4520)))),40); vcdp->fullBus (c+548,(((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xaU))) ? ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 9U))) ? 0x504320U : 0x494d53U) : ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 9U))) ? 0x494d49U : 0x525320U))),24); vcdp->fullArray(c+549,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SRC1_CTRL_string),96); vcdp->fullArray(c+552,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_SHIFT_CTRL_string),72); vcdp->fullArray(c+555,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_SHIFT_CTRL_string),72); vcdp->fullArray(c+558,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SHIFT_CTRL_string),72); vcdp->fullArray(c+561,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_SRC1_CTRL_string),96); vcdp->fullBus (c+564,(((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xeU))) ? ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU))) ? 0x4a414c52U : 0x4a414c20U) : ((1U & (IData)((vlSymsp->TOP__dut__VexRiscv.__PVT___zz_180_ >> 0xdU))) ? 0x42202020U : 0x494e4320U))),32); vcdp->fullQuad (c+565,(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_shared_state_1___05Fstring),48); vcdp->fullArray(c+567,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SHIFT_CTRL_string),72); vcdp->fullArray(c+570,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_SHIFT_CTRL_string),72); vcdp->fullArray(c+573,(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC1_CTRL_string),96); vcdp->fullBit (c+576,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_254_)); vcdp->fullBit (c+577,((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_input_ready))))); vcdp->fullBit (c+578,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_259_)); vcdp->fullBit (c+579,((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))))); vcdp->fullBit (c+580,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_262_)); vcdp->fullBit (c+581,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire)); vcdp->fullBit (c+582,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wayToAllocate_willIncrement)); vcdp->fullBit (c+583,((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_fire) | (~ ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U)))))); vcdp->fullBit (c+584,((vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ & ((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ >> 2U)) == (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0xcU)))))); vcdp->fullBit (c+585,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_263_)); vcdp->fullBus (c+586,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_),32); vcdp->fullBit (c+587,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_265_)); vcdp->fullBus (c+588,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_266_),32); vcdp->fullBus (c+589,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_267_),2); vcdp->fullBit (c+590,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_268_)); vcdp->fullBit (c+591,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_269_)); vcdp->fullBit (c+592,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_275_)); vcdp->fullBit (c+593,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_278_)); vcdp->fullBit (c+594,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_valid)); vcdp->fullBus (c+595,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsReadCmd_payload),7); vcdp->fullBit (c+596,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_valid)); vcdp->fullBus (c+597,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_way),1); vcdp->fullBus (c+598,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_address),7); vcdp->fullBit (c+599,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_valid)); vcdp->fullBit (c+600,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_error)); vcdp->fullBus (c+601,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteCmd_payload_data_address),20); vcdp->fullBit (c+602,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_valid)); vcdp->fullBus (c+603,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataReadCmd_payload),10); vcdp->fullBit (c+604,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid)); vcdp->fullBus (c+605,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way),1); vcdp->fullBus (c+606,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address),10); vcdp->fullBus (c+607,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_data),32); vcdp->fullBus (c+608,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask),4); vcdp->fullBus (c+609,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_mask),4); vcdp->fullBus (c+610,(((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT___zz_264_ >> 2U)))) & (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_mask) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask))))),1); vcdp->fullBit (c+611,((((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__DBusCachedPlugin_mmuBus_rsp_physicalAddress >> 0xcU)) == (0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ >> 2U))) & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_))); vcdp->fullBus (c+612,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_colisions_regNextWhen) | ((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_valid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_way)) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_address) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_REGFILE_WRITE_DATA >> 2U)))) & (0U != ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_mask) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__dataWriteCmd_payload_mask)))))),1); vcdp->fullBit (c+613,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRspFreeze)); vcdp->fullBit (c+614,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_loaderValid)); vcdp->fullBus (c+615,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_),32); vcdp->fullBit (c+616,((1U & (((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)) == (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_ >> 0x1fU) : ((3U == (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) >> 1U))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU) : (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)))))); vcdp->fullBit (c+617,((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) ^ (((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)) == (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_ >> 0x1fU) : ((3U == (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) >> 1U))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU) : (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)))))))); vcdp->fullBus (c+618,(((4U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? ((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) ^ (((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)) == (1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_ >> 0x1fU) : ((3U == (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) >> 1U))) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0 >> 0x1fU) : (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data >> 0x1fU)))))) ? vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : ((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data | vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0)) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_22_)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data ^ vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0) : vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_25_)))),32); vcdp->fullBit (c+619,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement)); vcdp->fullBus (c+620,((7U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value) + (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willIncrement)))),3); vcdp->fullBit (c+621,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_willOverflow)); vcdp->fullBit (c+622,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_syncfifo_re)); vcdp->fullBit (c+623,(vlSymsp->TOP__dut.__PVT__main_uart_tx_fifo_do_read)); vcdp->fullBus (c+624,(((0x3ffffff8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 2U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_))),30); vcdp->fullBus (c+625,(((7U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_245_)) ? 7U : 2U)),3); vcdp->fullBus (c+626,((0x3fffffffU & (((0U != (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_166_)) ? ((0xffffffe0U & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_163_) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_247_) << 2U)) : (0xfffffffcU & vlSymsp->TOP__dut__VexRiscv.__PVT___zz_163_)) >> 2U))),30); vcdp->fullBus (c+627,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_164_),32); vcdp->fullBus (c+628,(((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_) ? (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_165_) : 0xfU)),4); vcdp->fullBit (c+629,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_161_)); vcdp->fullBit (c+630,(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_162_)); vcdp->fullBus (c+631,(vlSymsp->TOP__dut.__PVT__memdat),32); vcdp->fullBus (c+632,(vlSymsp->TOP__dut.__PVT__memdat_2),10); vcdp->fullBus (c+633,(vlSymsp->TOP__dut.__PVT__memdat_1),10); vcdp->fullBus (c+634,(vlSymsp->TOP__dut.__PVT__memdat_4),10); vcdp->fullBus (c+635,(vlSymsp->TOP__dut.__PVT__memdat_3),10); vcdp->fullBus (c+636,(vlSymsp->TOP__dut.__PVT__memadr),10); vcdp->fullBus (c+637,(vlSymsp->TOP__dut.__PVT__memadr_1),23); vcdp->fullBus (c+638,(vlSymsp->TOP__dut.__PVT__memadr_2),12); vcdp->fullBus (c+639,(vlSymsp->TOP__dut.__PVT__storage[0]),10); vcdp->fullBus (c+640,(vlSymsp->TOP__dut.__PVT__storage[1]),10); vcdp->fullBus (c+641,(vlSymsp->TOP__dut.__PVT__storage[2]),10); vcdp->fullBus (c+642,(vlSymsp->TOP__dut.__PVT__storage[3]),10); vcdp->fullBus (c+643,(vlSymsp->TOP__dut.__PVT__storage[4]),10); vcdp->fullBus (c+644,(vlSymsp->TOP__dut.__PVT__storage[5]),10); vcdp->fullBus (c+645,(vlSymsp->TOP__dut.__PVT__storage[6]),10); vcdp->fullBus (c+646,(vlSymsp->TOP__dut.__PVT__storage[7]),10); vcdp->fullBus (c+647,(vlSymsp->TOP__dut.__PVT__storage[8]),10); vcdp->fullBus (c+648,(vlSymsp->TOP__dut.__PVT__storage[9]),10); vcdp->fullBus (c+649,(vlSymsp->TOP__dut.__PVT__storage[10]),10); vcdp->fullBus (c+650,(vlSymsp->TOP__dut.__PVT__storage[11]),10); vcdp->fullBus (c+651,(vlSymsp->TOP__dut.__PVT__storage[12]),10); vcdp->fullBus (c+652,(vlSymsp->TOP__dut.__PVT__storage[13]),10); vcdp->fullBus (c+653,(vlSymsp->TOP__dut.__PVT__storage[14]),10); vcdp->fullBus (c+654,(vlSymsp->TOP__dut.__PVT__storage[15]),10); vcdp->fullBus (c+655,(vlSymsp->TOP__dut.__PVT__storage_1[0]),10); vcdp->fullBus (c+656,(vlSymsp->TOP__dut.__PVT__storage_1[1]),10); vcdp->fullBus (c+657,(vlSymsp->TOP__dut.__PVT__storage_1[2]),10); vcdp->fullBus (c+658,(vlSymsp->TOP__dut.__PVT__storage_1[3]),10); vcdp->fullBus (c+659,(vlSymsp->TOP__dut.__PVT__storage_1[4]),10); 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vcdp->fullBit (c+962,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_hadException)); vcdp->fullBit (c+963,(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_CsrPlugin_wfiWake)); vcdp->fullBit (c+964,((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_WRITE_OPCODE)))); vcdp->fullBit (c+965,((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_arbitration_isValid) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_IS_CSR)) & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_CSR_READ_OPCODE)))); vcdp->fullBus (c+966,((0xfffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x14U))),12); vcdp->fullBit (c+967,(((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))) | (2U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU)))))); vcdp->fullBit (c+968,((1U == (3U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0xcU))))); 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vcdp->fullBit (c+978,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_needRevert)); vcdp->fullBus (c+979,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value),6); vcdp->fullBit (c+980,((0x21U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_counter_value)))); vcdp->fullBit (c+981,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_done)); vcdp->fullBus (c+982,(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_DivPlugin_div_result),32); vcdp->fullBus (c+983,(vlSymsp->TOP__dut__VexRiscv.__PVT__externalInterruptArray_regNext),32); vcdp->fullQuad (c+984,(((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL)) ? VL_ULL(0x4543414c4c) : VL_ULL(0x5746492020)) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__execute_to_memory_ENV_CTRL)) ? VL_ULL(0x5852455420) : VL_ULL(0x4e4f4e4520)))),40); vcdp->fullQuad (c+986,(((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL)) ? VL_ULL(0x4543414c4c) : VL_ULL(0x5746492020)) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ENV_CTRL)) ? VL_ULL(0x5852455420) : VL_ULL(0x4e4f4e4520)))),40); vcdp->fullQuad (c+988,(((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL)) ? VL_ULL(0x4543414c4c) : VL_ULL(0x5746492020)) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__memory_to_writeBack_ENV_CTRL)) ? VL_ULL(0x5852455420) : VL_ULL(0x4e4f4e4520)))),40); vcdp->fullBus (c+990,(((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? 0x4a414c52U : 0x4a414c20U) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_BRANCH_CTRL)) ? 0x42202020U : 0x494e4320U))),32); vcdp->fullBus (c+991,(((2U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? 0x504320U : 0x494d53U) : ((1U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_SRC2_CTRL)) ? 0x494d49U : 0x525320U))),24); vcdp->fullQuad (c+992,(((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? VL_ULL(0x4144445f53554220) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? VL_ULL(0x534c545f534c5455) : ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_CTRL)) ? VL_ULL(0x4249545749534520) : VL_ULL(0x3f3f3f3f3f3f3f3f))))),64); vcdp->fullQuad (c+994,(((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? VL_ULL(0x584f525f31) : ((1U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? VL_ULL(0x4f525f3120) : ((2U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_ALU_BITWISE_CTRL)) ? VL_ULL(0x414e445f31) : VL_ULL(0x3f3f3f3f3f))))),40); vcdp->fullBit (c+996,((0U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_225_)))); vcdp->fullBit (c+997,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_valid)); vcdp->fullBus (c+998,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address),32); vcdp->fullBit (c+999,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_hadError)); vcdp->fullBit (c+1000,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushPending)); vcdp->fullBus (c+1001,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter),8); vcdp->fullBit (c+1002,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_cmdSent)); vcdp->fullBus (c+1003,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex),3); vcdp->fullBus (c+1004,((0x7fU & ((0x80U & (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter)) ? (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 5U) : (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter)))),7); vcdp->fullBit (c+1005,((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_flushCounter) >> 7U)))); vcdp->fullBus (c+1006,((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 0xcU))),20); vcdp->fullBus (c+1007,(((0x3f8U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_address >> 2U)) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__lineLoader_wordIndex))),10); vcdp->fullBit (c+1008,((1U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_))); vcdp->fullBit (c+1009,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ >> 1U)))); vcdp->fullBus (c+1010,((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_10_ >> 2U))),20); vcdp->fullBus (c+1011,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT___zz_11_),32); vcdp->fullBit (c+1012,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_isIoAccess)); vcdp->fullBit (c+1013,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowRead)); vcdp->fullBit (c+1014,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowWrite)); vcdp->fullBit (c+1015,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_allowExecute)); vcdp->fullBit (c+1016,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_mmuRsp_exception)); vcdp->fullBit (c+1017,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_cache__DOT__decodeStage_hit_valid)); vcdp->fullBit (c+1018,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1bU)))); vcdp->fullBus (c+1019,((7U & (vlSymsp->TOP__dut__VexRiscv.__PVT__decode_to_execute_INSTRUCTION >> 0x1dU))),3); vcdp->fullBit (c+1020,((1U & (~ (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT___zz_154_))))); vcdp->fullBit (c+1021,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_valid)); vcdp->fullBus (c+1022,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_way),1); vcdp->fullBus (c+1023,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_address),7); vcdp->fullBit (c+1024,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_valid)); vcdp->fullBit (c+1025,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_error)); vcdp->fullBus (c+1026,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__tagsWriteLastCmd_payload_data_address),20); vcdp->fullBit (c+1027,((1U & vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_))); vcdp->fullBit (c+1028,((1U & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ >> 1U)))); vcdp->fullBus (c+1029,((0xfffffU & (vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_10_ >> 2U))),20); vcdp->fullBus (c+1030,((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_41_) << 0x18U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_40_) << 0x10U) | (((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_39_) << 8U) | (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT___zz_38_))))),32); vcdp->fullBus (c+1031,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_data),32); vcdp->fullBus (c+1032,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_size),2); vcdp->fullBit (c+1033,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_isLrsc)); vcdp->fullBit (c+1034,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_isAmo)); vcdp->fullBit (c+1035,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_amoCtrl_swap)); vcdp->fullBus (c+1036,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_request_amoCtrl_alu),3); vcdp->fullBus (c+1037,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageA_mask),4); vcdp->fullBus (c+1038,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stage0_colisions_regNextWhen),1); vcdp->fullBus (c+1039,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_data),32); vcdp->fullBus (c+1040,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_size),2); vcdp->fullBit (c+1041,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_isLrsc)); vcdp->fullBit (c+1042,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_isAmo)); vcdp->fullBit (c+1043,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_swap)); vcdp->fullBus (c+1044,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu),3); vcdp->fullBus (c+1045,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_physicalAddress),32); vcdp->fullBit (c+1046,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_isIoAccess)); vcdp->fullBit (c+1047,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowRead)); vcdp->fullBit (c+1048,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowWrite)); vcdp->fullBit (c+1049,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_allowExecute)); vcdp->fullBit (c+1050,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_exception)); vcdp->fullBit (c+1051,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_mmuRsp_refilling)); vcdp->fullBit (c+1052,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_valid)); vcdp->fullBit (c+1053,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_error)); vcdp->fullBus (c+1054,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_tagsReadRsp_0_address),20); vcdp->fullBus (c+1055,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_dataReadRsp_0),32); vcdp->fullBus (c+1056,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits),1); vcdp->fullBit (c+1057,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_waysHits)); vcdp->fullBus (c+1058,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_colisions),1); vcdp->fullBit (c+1059,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_flusher_valid)); vcdp->fullBit (c+1060,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_lrsc_reserved)); vcdp->fullBit (c+1061,((1U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) >> 2U)))); vcdp->fullBit (c+1062,((3U == (3U & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_request_amoCtrl_alu) >> 1U))))); vcdp->fullBit (c+1063,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultRegValid)); vcdp->fullBus (c+1064,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_amo_resultReg),32); vcdp->fullBit (c+1065,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__stageB_memCmdSent)); vcdp->fullBit (c+1066,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_valid)); vcdp->fullBus (c+1067,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value),3); vcdp->fullBit (c+1068,((7U == (IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_counter_value)))); vcdp->fullBus (c+1069,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_waysAllocator),1); vcdp->fullBit (c+1070,(vlSymsp->TOP__dut__VexRiscv.__PVT__dataCache_1___DOT__loader_error)); vcdp->fullBit (c+1071,(vlTOPp->sys_clk)); vcdp->fullBit (c+1072,(vlTOPp->serial_source_valid)); vcdp->fullBit (c+1073,(vlTOPp->serial_source_ready)); vcdp->fullBus (c+1074,(vlTOPp->serial_source_data),8); vcdp->fullBit (c+1075,(vlTOPp->serial_sink_valid)); vcdp->fullBit (c+1076,(vlTOPp->serial_sink_ready)); vcdp->fullBus (c+1077,(vlTOPp->serial_sink_data),8); vcdp->fullBus (c+1078,(vlTOPp->serial_sink_data),10); vcdp->fullBit (c+1079,(((IData)(vlTOPp->serial_sink_valid) & (0x10U != (IData)(vlSymsp->TOP__dut.__PVT__main_uart_rx_fifo_level0))))); vcdp->fullBus (c+1080,(vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg),32); vcdp->fullBus (c+1081,((vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg + ((3U != (3U & vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_rawInDecode)) ? 2U : 4U))),32); vcdp->fullBus (c+1082,(vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_decodePc_pcReg),32); vcdp->fullBus (c+1083,(vlSymsp->TOP__dut__VexRiscv.lastStageInstruction),32); vcdp->fullBus (c+1084,(vlSymsp->TOP__dut__VexRiscv.lastStagePc),32); vcdp->fullBit (c+1085,(vlSymsp->TOP__dut__VexRiscv.lastStageIsValid)); vcdp->fullBit (c+1086,(vlSymsp->TOP__dut__VexRiscv.lastStageIsFiring)); vcdp->fullBit (c+1087,((((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_valid) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_1) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0x16U)))) & ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_superPage) | ((IData)(vlSymsp->TOP__dut__VexRiscv.__PVT__MmuPlugin_ports_1_cache_0_virtualAddress_0) == (0x3ffU & (vlSymsp->TOP__dut__VexRiscv.IBusCachedPlugin_fetchPc_pcReg >> 0xcU))))))); vcdp->fullBus (c+1088,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile [(0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0xfU))]),32); vcdp->fullBus (c+1089,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile [(0x1fU & (vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_inst >> 0x14U))]),32); vcdp->fullBit (c+1090,(vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_valid)); vcdp->fullBus (c+1091,(vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_address),5); vcdp->fullBus (c+1092,(vlSymsp->TOP__dut__VexRiscv.lastStageRegFileWrite_payload_data),32); vcdp->fullBus (c+1093,(vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interrupt_code),4); vcdp->fullBit (c+1094,(vlSymsp->TOP__dut__VexRiscv.CsrPlugin_interruptJump)); vcdp->fullBit (c+1095,(vlSymsp->TOP__dut__VexRiscv.execute_CsrPlugin_inWfi)); vcdp->fullBus (c+1096,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[0]),32); vcdp->fullBus (c+1097,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[1]),32); vcdp->fullBus (c+1098,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[2]),32); vcdp->fullBus (c+1099,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[3]),32); vcdp->fullBus (c+1100,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[4]),32); vcdp->fullBus (c+1101,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[5]),32); vcdp->fullBus (c+1102,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[6]),32); vcdp->fullBus (c+1103,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[7]),32); vcdp->fullBus (c+1104,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[8]),32); vcdp->fullBus (c+1105,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[9]),32); vcdp->fullBus (c+1106,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[10]),32); vcdp->fullBus (c+1107,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[11]),32); vcdp->fullBus (c+1108,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[12]),32); vcdp->fullBus (c+1109,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[13]),32); vcdp->fullBus (c+1110,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[14]),32); vcdp->fullBus (c+1111,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[15]),32); vcdp->fullBus (c+1112,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[16]),32); vcdp->fullBus (c+1113,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[17]),32); vcdp->fullBus (c+1114,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[18]),32); vcdp->fullBus (c+1115,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[19]),32); vcdp->fullBus (c+1116,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[20]),32); vcdp->fullBus (c+1117,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[21]),32); vcdp->fullBus (c+1118,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[22]),32); vcdp->fullBus (c+1119,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[23]),32); vcdp->fullBus (c+1120,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[24]),32); vcdp->fullBus (c+1121,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[25]),32); vcdp->fullBus (c+1122,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[26]),32); vcdp->fullBus (c+1123,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[27]),32); vcdp->fullBus (c+1124,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[28]),32); vcdp->fullBus (c+1125,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[29]),32); vcdp->fullBus (c+1126,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[30]),32); vcdp->fullBus (c+1127,(vlSymsp->TOP__dut__VexRiscv.RegFilePlugin_regFile[31]),32); vcdp->fullBit (c+1128,(0U)); vcdp->fullBus (c+1129,(0U),32); vcdp->fullBus (c+1130,(0xfU),4); vcdp->fullBus (c+1131,(0U),2); vcdp->fullBus (c+1132,(5U),3); vcdp->fullBit (c+1133,(1U)); vcdp->fullBus (c+1134,(2U),2); vcdp->fullBus (c+1135,(0U),4); vcdp->fullBus (c+1136,(2U),4); vcdp->fullBit (c+1137,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_stages_1_inputSample)); vcdp->fullBit (c+1138,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample)); vcdp->fullBit (c+1139,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_payload_rsp_error)); vcdp->fullBit (c+1140,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_iBusRsp_output_payload_isRvc)); vcdp->fullBit (c+1141,(vlSymsp->TOP__dut__VexRiscv.__PVT__IBusCachedPlugin_decompressor_decodeInput_payload_rsp_error)); vcdp->fullBus (c+1142,(1U),2); vcdp->fullBus (c+1143,(0U),26); vcdp->fullBus (c+1144,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_satp_PPN),22); vcdp->fullBus (c+1145,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_satp_ASID),9); vcdp->fullBus (c+1146,(vlSymsp->TOP__dut__VexRiscv.__PVT__CsrPlugin_satp_MODE),1); } }