//-------------------------------------------------------------------------------- // Auto-generated by Migen (811d135) & LiteX (5da0bcbd) on 2019-12-29 19:13:38 //-------------------------------------------------------------------------------- #include #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H #include #ifdef CSR_ACCESSORS_DEFINED extern void csr_writeb(uint8_t value, unsigned long addr); extern uint8_t csr_readb(unsigned long addr); extern void csr_writew(uint16_t value, unsigned long addr); extern uint16_t csr_readw(unsigned long addr); extern void csr_writel(uint32_t value, unsigned long addr); extern uint32_t csr_readl(unsigned long addr); #else /* ! CSR_ACCESSORS_DEFINED */ #include #endif /* ! CSR_ACCESSORS_DEFINED */ /* ctrl */ #define CSR_CTRL_BASE 0xf0000000L #define CSR_CTRL_RESET_ADDR 0xf0000000L #define CSR_CTRL_RESET_SIZE 1 static inline unsigned char ctrl_reset_read(void) { unsigned char r = csr_readl(0xf0000000L); return r; } static inline void ctrl_reset_write(unsigned char value) { csr_writel(value, 0xf0000000L); } #define CSR_CTRL_SCRATCH_ADDR 0xf0000004L #define CSR_CTRL_SCRATCH_SIZE 4 static inline unsigned int ctrl_scratch_read(void) { unsigned int r = csr_readl(0xf0000004L); r <<= 8; r |= csr_readl(0xf0000008L); r <<= 8; r |= csr_readl(0xf000000cL); r <<= 8; r |= csr_readl(0xf0000010L); return r; } static inline void ctrl_scratch_write(unsigned int value) { csr_writel(value >> 24, 0xf0000004L); csr_writel(value >> 16, 0xf0000008L); csr_writel(value >> 8, 0xf000000cL); csr_writel(value, 0xf0000010L); } #define CSR_CTRL_BUS_ERRORS_ADDR 0xf0000014L #define CSR_CTRL_BUS_ERRORS_SIZE 4 static inline unsigned int ctrl_bus_errors_read(void) { unsigned int r = csr_readl(0xf0000014L); r <<= 8; r |= csr_readl(0xf0000018L); r <<= 8; r |= csr_readl(0xf000001cL); r <<= 8; r |= csr_readl(0xf0000020L); return r; } /* cpu */ #define CSR_CPU_BASE 0xf0000800L #define CSR_CPU_TIMER_LATCH_ADDR 0xf0000800L #define CSR_CPU_TIMER_LATCH_SIZE 1 static inline unsigned char cpu_timer_latch_read(void) { unsigned char r = csr_readl(0xf0000800L); return r; } static inline void cpu_timer_latch_write(unsigned char value) { csr_writel(value, 0xf0000800L); } #define CSR_CPU_TIMER_TIME_ADDR 0xf0000804L #define CSR_CPU_TIMER_TIME_SIZE 8 static inline unsigned long long int cpu_timer_time_read(void) { unsigned long long int r = csr_readl(0xf0000804L); r <<= 8; r |= csr_readl(0xf0000808L); r <<= 8; r |= csr_readl(0xf000080cL); r <<= 8; r |= csr_readl(0xf0000810L); r <<= 8; r |= csr_readl(0xf0000814L); r <<= 8; r |= csr_readl(0xf0000818L); r <<= 8; r |= csr_readl(0xf000081cL); r <<= 8; r |= csr_readl(0xf0000820L); return r; } #define CSR_CPU_TIMER_TIME_CMP_ADDR 0xf0000824L #define CSR_CPU_TIMER_TIME_CMP_SIZE 8 static inline unsigned long long int cpu_timer_time_cmp_read(void) { unsigned long long int r = csr_readl(0xf0000824L); r <<= 8; r |= csr_readl(0xf0000828L); r <<= 8; r |= csr_readl(0xf000082cL); r <<= 8; r |= csr_readl(0xf0000830L); r <<= 8; r |= csr_readl(0xf0000834L); r <<= 8; r |= csr_readl(0xf0000838L); r <<= 8; r |= csr_readl(0xf000083cL); r <<= 8; r |= csr_readl(0xf0000840L); return r; } static inline void cpu_timer_time_cmp_write(unsigned long long int value) { csr_writel(value >> 56, 0xf0000824L); csr_writel(value >> 48, 0xf0000828L); csr_writel(value >> 40, 0xf000082cL); csr_writel(value >> 32, 0xf0000830L); csr_writel(value >> 24, 0xf0000834L); csr_writel(value >> 16, 0xf0000838L); csr_writel(value >> 8, 0xf000083cL); csr_writel(value, 0xf0000840L); } /* uart */ #define CSR_UART_BASE 0xf0001000L #define CSR_UART_RXTX_ADDR 0xf0001000L #define CSR_UART_RXTX_SIZE 1 static inline unsigned char uart_rxtx_read(void) { unsigned char r = csr_readl(0xf0001000L); return r; } static inline void uart_rxtx_write(unsigned char value) { csr_writel(value, 0xf0001000L); } #define CSR_UART_TXFULL_ADDR 0xf0001004L #define CSR_UART_TXFULL_SIZE 1 static inline unsigned char uart_txfull_read(void) { unsigned char r = csr_readl(0xf0001004L); return r; } #define CSR_UART_RXEMPTY_ADDR 0xf0001008L #define CSR_UART_RXEMPTY_SIZE 1 static inline unsigned char uart_rxempty_read(void) { unsigned char r = csr_readl(0xf0001008L); return r; } #define CSR_UART_EV_STATUS_ADDR 0xf000100cL #define CSR_UART_EV_STATUS_SIZE 1 static inline unsigned char uart_ev_status_read(void) { unsigned char r = csr_readl(0xf000100cL); return r; } static inline void uart_ev_status_write(unsigned char value) { csr_writel(value, 0xf000100cL); } #define CSR_UART_EV_PENDING_ADDR 0xf0001010L #define CSR_UART_EV_PENDING_SIZE 1 static inline unsigned char uart_ev_pending_read(void) { unsigned char r = csr_readl(0xf0001010L); return r; } static inline void uart_ev_pending_write(unsigned char value) { csr_writel(value, 0xf0001010L); } #define CSR_UART_EV_ENABLE_ADDR 0xf0001014L #define CSR_UART_EV_ENABLE_SIZE 1 static inline unsigned char uart_ev_enable_read(void) { unsigned char r = csr_readl(0xf0001014L); return r; } static inline void uart_ev_enable_write(unsigned char value) { csr_writel(value, 0xf0001014L); } /* timer0 */ #define CSR_TIMER0_BASE 0xf0001800L #define CSR_TIMER0_LOAD_ADDR 0xf0001800L #define CSR_TIMER0_LOAD_SIZE 4 static inline unsigned int timer0_load_read(void) { unsigned int r = csr_readl(0xf0001800L); r <<= 8; r |= csr_readl(0xf0001804L); r <<= 8; r |= csr_readl(0xf0001808L); r <<= 8; r |= csr_readl(0xf000180cL); return r; } static inline void timer0_load_write(unsigned int value) { csr_writel(value >> 24, 0xf0001800L); csr_writel(value >> 16, 0xf0001804L); csr_writel(value >> 8, 0xf0001808L); csr_writel(value, 0xf000180cL); } #define CSR_TIMER0_RELOAD_ADDR 0xf0001810L #define CSR_TIMER0_RELOAD_SIZE 4 static inline unsigned int timer0_reload_read(void) { unsigned int r = csr_readl(0xf0001810L); r <<= 8; r |= csr_readl(0xf0001814L); r <<= 8; r |= csr_readl(0xf0001818L); r <<= 8; r |= csr_readl(0xf000181cL); return r; } static inline void timer0_reload_write(unsigned int value) { csr_writel(value >> 24, 0xf0001810L); csr_writel(value >> 16, 0xf0001814L); csr_writel(value >> 8, 0xf0001818L); csr_writel(value, 0xf000181cL); } #define CSR_TIMER0_EN_ADDR 0xf0001820L #define CSR_TIMER0_EN_SIZE 1 static inline unsigned char timer0_en_read(void) { unsigned char r = csr_readl(0xf0001820L); return r; } static inline void timer0_en_write(unsigned char value) { csr_writel(value, 0xf0001820L); } #define CSR_TIMER0_UPDATE_VALUE_ADDR 0xf0001824L #define CSR_TIMER0_UPDATE_VALUE_SIZE 1 static inline unsigned char timer0_update_value_read(void) { unsigned char r = csr_readl(0xf0001824L); return r; } static inline void timer0_update_value_write(unsigned char value) { csr_writel(value, 0xf0001824L); } #define CSR_TIMER0_VALUE_ADDR 0xf0001828L #define CSR_TIMER0_VALUE_SIZE 4 static inline unsigned int timer0_value_read(void) { unsigned int r = csr_readl(0xf0001828L); r <<= 8; r |= csr_readl(0xf000182cL); r <<= 8; r |= csr_readl(0xf0001830L); r <<= 8; r |= csr_readl(0xf0001834L); return r; } #define CSR_TIMER0_EV_STATUS_ADDR 0xf0001838L #define CSR_TIMER0_EV_STATUS_SIZE 1 static inline unsigned char timer0_ev_status_read(void) { unsigned char r = csr_readl(0xf0001838L); return r; } static inline void timer0_ev_status_write(unsigned char value) { csr_writel(value, 0xf0001838L); } #define CSR_TIMER0_EV_PENDING_ADDR 0xf000183cL #define CSR_TIMER0_EV_PENDING_SIZE 1 static inline unsigned char timer0_ev_pending_read(void) { unsigned char r = csr_readl(0xf000183cL); return r; } static inline void timer0_ev_pending_write(unsigned char value) { csr_writel(value, 0xf000183cL); } #define CSR_TIMER0_EV_ENABLE_ADDR 0xf0001840L #define CSR_TIMER0_EV_ENABLE_SIZE 1 static inline unsigned char timer0_ev_enable_read(void) { unsigned char r = csr_readl(0xf0001840L); return r; } static inline void timer0_ev_enable_write(unsigned char value) { csr_writel(value, 0xf0001840L); } /* supervisor */ #define CSR_SUPERVISOR_BASE 0xf0002000L #define CSR_SUPERVISOR_FINISH_ADDR 0xf0002000L #define CSR_SUPERVISOR_FINISH_SIZE 1 static inline unsigned char supervisor_finish_read(void) { unsigned char r = csr_readl(0xf0002000L); return r; } static inline void supervisor_finish_write(unsigned char value) { csr_writel(value, 0xf0002000L); } #endif