LPC11Uxx 7 LPC11Uxx CM0 r0p0 little 0 0 2 0 LPC_ 8 32 32 I2C I2C-bus controller I2C 0x40000000 0 0xFFF registers I2C 15 CONSET I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x000 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AA Assert acknowledge flag. [2:2] SI I2C interrupt flag. [3:3] STO STOP flag. [4:4] STA START flag. [5:5] I2EN I2C interface enable. [6:6] RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] STAT I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. 0x004 read-only 0xF8 0xFFFFFFFF RESERVED These bits are unused and are always 0. [2:0] Status These bits give the actual status information about the I2C interface. [7:3] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DAT I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0x008 read-write 0x00 0xFFFFFFFF Data This register holds data values that have been received or are to be transmitted. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] ADR0 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x00C read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. 0x010 read-write 0x04 0xFFFFFFFF SCLH Count for SCL HIGH time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. 0x014 read-write 0x04 0xFFFFFFFF SCLL Count for SCL low time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] CONCLR I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x018 write-only 0 0x00000000 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AAC Assert acknowledge Clear bit. [2:2] SIC I2C interrupt Clear bit. [3:3] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:4] STAC START flag Clear bit. [5:5] I2ENC I2C interface Disable bit. [6:6] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] MMCTRL Monitor mode control register. 0x01C read-write 0x00 0xFFFFFFFF MM_ENA Monitor mode enable. [0:0] ENUM DISABLED Monitor mode disabled. 0 ENABLED The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 ENA_SCL SCL output enable. [1:1] ENUM HIGH When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 0 NORMAL When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] 1 MATCH_ALL Select interrupt register match. [2:2] ENUM MATCH When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 0 ANYADDRESS When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 1 RESERVED Reserved. The value read from reserved bits is not defined. [31:3] 3 0x4 1-3 ADR%s I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x020 read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DATA_BUFFER Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. 0x02C read-only 0x00 0xFFFFFFFF Data This register holds contents of the 8 MSBs of the DAT shift register. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] 4 0x4 0-3 MASK%s I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x030 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. [0:0] MASK Mask bits. [7:1] RESERVED Reserved. The value read from reserved bits is undefined. [31:8] WWDT Windowed Watchdog Timer (WWDT) WWDT 0x40004000 0 0xFFF registers WDT 25 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [0:0] ENUM STOPPED The watchdog timer is stopped. 0 RUNNING The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [1:1] ENUM INTERRUPT A watchdog timeout will not cause a chip reset. 0 RESET A watchdog timeout will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. [2:2] WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. [3:3] WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. [4:4] ENUM NOT_LOCKED The watchdog time-out value (TC) can be changed at any time. 0 LOCKED The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 1 LOCK A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7). [5:5] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF COUNT Watchdog time-out value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 FEED Feed value should be 0xAA followed by 0x55. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF COUNT Counter timer value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] CLKSEL Watchdog clock select register. 0x010 read-write 0 0xFFFFFFFF CLKSEL Selects source of WDT clock [0:0] ENUM IRC IRC 0 WATCHDOG_OSCILLATOR Watchdog oscillator (WDOSC) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [30:1] LOCK If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0. [31:31] WARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] WINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] USART USART USART 0x40008000 0 0xFFF registers USART 21 RBR Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) 0x000 read-only 0 0x00000000 modify RBR The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO. [7:0] RESERVED Reserved [31:8] THR Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) RBR 0x000 write-only 0 0x00000000 modify THR Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available. [7:0] RESERVED Reserved [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) 0x004 read-write 0 0xFFFFFFFF DLMSB The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) DLM 0x004 read-write 0 0xFFFFFFFF RBRINTEN RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE_THE_RDA_INTE Disable the RDA interrupt. 0 ENABLE_THE_RDA_INTER Enable the RDA interrupt. 1 THREINTEN THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE_THE_THRE_INT Disable the THRE interrupt. 0 ENABLE_THE_THRE_INTE Enable the THRE interrupt. 1 RLSINTEN Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE_THE_RLS_INTE Disable the RLS interrupt. 0 ENABLE_THE_RLS_INTER Enable the RLS interrupt. 1 MSINTEN Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR. [3:3] ENUM DISABLE_THE_MS_INTER Disable the MS interrupt. 0 ENABLE_THE_MS_INTERR Enable the MS interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:4] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLED Disable end of auto-baud Interrupt. 0 ENABLED Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLED Disable auto-baud time-out Interrupt. 0 ENABLED Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM PENDING At least one interrupt is pending. 0 NONE No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved. [3:1] ENUM RECEIVE_LINE_STATUS 1 - Receive Line Status (RLS). 0x3 RECEIVE_DATA_AVAILABLE 2a - Receive Data Available (RDA). 0x2 CHARACTER_TIMEOUT_INDICATOR 2b - Character Time-out Indicator (CTI). 0x6 THRE_INTERRUPT 3 - THRE Interrupt. 0x1 MODEM_STATUS 4 - Modem status 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOEN These bits are equivalent to FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls USART FIFO usage and modes. 0x008 write-only 0 0xFFFFFFFF FIFOEN FIFO enable [0:0] ENUM DISABLED USART FIFOs are disabled. Must not be used in the application. 0 ENABLED Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs. 1 RXFIFORES RX FIFO Reset [1:1] ENUM NO_IMPACT No impact on either of USART FIFOs. 0 CLEAR Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset [2:2] ENUM NO_IMPACT No impact on either of USART FIFOs. 0 CLEAR Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 RESERVED Reserved [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTL RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated. [7:6] ENUM LEVEL0 Trigger level 0 (1 character or 0x01). 0x0 LEVEL1 Trigger level 1 (4 characters or 0x04). 0x1 LEVEL2 Trigger level 2 (8 characters or 0x08). 0x2 LEVEL3 Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0 0xFFFFFFFF WLS Word Length Select [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select [2:2] ENUM 1_STOP_BIT 1 stop bit. 0 2_STOP_BITS_1_5_IF 2 stop bits (1.5 if LCR[1:0]=00). 1 PE Parity Enable [3:3] ENUM DISABLED Disable parity generation and checking. 0 ENABLED Enable parity generation and checking. 1 PS Parity Select [5:4] ENUM ODD Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK Forced 1 stick parity. 0x2 FORCED_0_STICK Forced 0 stick parity. 0x3 BC Break Control [6:6] ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit [7:7] ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 RESERVED Reserved [31:8] MCR Modem Control Register. 0x010 read-write 0 0xFFFFFFFF DTRCTRL Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active. [0:0] RTSCTRL Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:2] LMS Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR. [4:4] ENUM DISABLE_MODEM_LOOPBA Disable modem loopback mode. 0 ENABLE_MODEM_LOOPBAC Enable modem loopback mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:5] RTSEN RTS enable [6:6] ENUM DISABLE_AUTO_RTS_FLO Disable auto-rts flow control. 0 ENABLE_AUTO_RTS_FLOW Enable auto-rts flow control. 1 CTSEN CTS enable [7:7] ENUM DISABLE_AUTO_CTS_FLO Disable auto-cts flow control. 0 ENABLE_AUTO_CTS_FLOW Enable auto-cts flow control. 1 RESERVED Reserved [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty. [0:0] ENUM EMPTY RBR is empty. 0 VALID RBR contains valid data. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost. [1:1] ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO. [2:2] ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO. [3:3] ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO. [4:4] ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write. [5:5] ENUM VALID THR contains valid data. 0 EMPTY THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM VALID THR and/or the TSR contains valid data. 0 EMPTY THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO. [7:7] ENUM NO_ERROR RBR contains no USART RX errors or FCR[0]=0. 0 ERRO USART RBR contains at least one USART RX error. 1 TXERR Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field. [8:8] RESERVED Reserved [31:9] MSR Modem Status Register. 0x018 read-only 0 0xFFFFFFFF modify DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. [0:0] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, CTS. 0 STATE_CHANGE_DETECTE State change detected on modem input, CTS. 1 DDSR Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. [1:1] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DSR. 0 STATE_CHANGE_DETECTE State change detected on modem input, DSR. 1 TERI Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. [2:2] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, RI. 0 LOW_TO_HIGH_TRANSITI Low-to-high transition detected on RI. 1 DDCD Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. [3:3] ENUM NO_CHANGE_DETECTED_O No change detected on modem input, DCD. 0 STATE_CHANGE_DETECTE State change detected on modem input, DCD. 1 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. [4:4] DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. [5:5] RI Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. [6:6] DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. [7:7] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x01C read-write 0 0xFFFFFFFF PAD A readable, writable byte. [7:0] RESERVED Reserved [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0 0xFFFFFFFF START This bit is automatically cleared after auto-baud completion. [0:0] ENUM AUTO_BAUD_STOP_AUTO Auto-baud stop (auto-baud is not running). 0 AUTO_BAUD_START_AUT Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE0 Mode 0. 0 MODE1 Mode 1. 1 AUTORESTART Start mode [2:2] ENUM NO_RESTART No restart 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next USART Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write only accessible). [8:8] ENUM NO_IMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write only accessible). [9:9] ENUM NO_IMPACT Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] ICR IrDA Control Register. Enables and configures the IrDA (remote control) mode. 0x024 read-write 0 0xFFFFFFFF IRDAEN IrDA mode enable [0:0] ENUM DISABLED IrDA mode is disabled, USARTn acts as a standard USART. 0 ENABLED IrDA mode is enabled. 1 IRDAINV Serial input inverter [1:1] ENUM INVERTED The serial input is not inverted. 0 NOT_INVERTED The serial input is inverted. This has no effect on the serial output. 1 FIXPULSEEN IrDA fixed pulse width mode. [2:2] ENUM DISABLED IrDA fixed pulse width mode disabled. 0 ENABLED IrDA fixed pulse width mode enabled. 1 PULSEDIV Configures the pulse width when FixPulseEn = 1. [5:3] ENUM 3_DIV_16_X_BAUD_RATE 3 / (16 x baud rate) 0x0 2_X_TPCLK 2 x TPCLK 0x1 4_X_TPCLK 4 x TPCLK 0x2 8_X_TPCLK 8 x TPCLK 0x3 16_X_TPCLK 16 x TPCLK 0x4 32_X_TPCLK 32 x TPCLK 0x5 64_X_TPCLK 64 x TPCLK 0x6 128_X_TPCLK 128 x TPCLK 0x7 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate. [3:0] MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] OSR Oversampling Register. Controls the degree of oversampling during each bit time. 0x02C read-write 0xF0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] OSFRAC Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875) [3:1] OSINT Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time. [7:4] FDINT In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372. [14:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:15] TER Transmit Enable Register. Turns off USART transmitter for use with software flow control. 0x030 read-write 0x80 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:0] TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. [7:7] RESERVED Reserved [31:8] HDEN Half duplex enable register. 0x040 read-write 0 0xFFFFFFFF HDEN Half-duplex mode enable [0:0] ENUM DISABLED Disable half-duplex mode. 0 ENABLED Enable half-duplex mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] SCICTRL Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. 0x048 read-write 0 0xFFFFFFFF SCIEN Smart Card Interface Enable. [0:0] ENUM SMART_CARD_INTERFACE Smart card interface disabled. 0 ASYNCHRONOUS_HALF_DU Asynchronous half duplex smart card interface is enabled. 1 NACKDIS NACK response disable. Only applicable in T=0. [1:1] ENUM ENABLED A NACK response is enabled. 0 DISABLED A NACK response is inhibited. 1 PROTSEL Protocol selection as defined in the ISO7816-3 standard. [2:2] ENUM T_EQ_0 T = 0 0 T_EQ_1 T = 1 1 RESERVED Reserved. [4:3] TXRETRY When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared. [7:5] XTRAGUARD When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. 1 RXDIS Receiver enable. [1:1] ENUM ENABLED The receiver is enabled. 0 DISABLED The receiver is disabled. 1 AADEN AAD enable. [2:2] ENUM DISABLED Auto Address Detect (AAD) is disabled. 0 ENABLED Auto Address Detect (AAD) is enabled. 1 SEL Select direction control pin [3:3] ENUM RTS If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 DCTRL Auto direction control enable. [4:4] ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 OINV Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. [5:5] ENUM LOW The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0 0xFFFFFFFF DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] SYNCCTRL Synchronous mode control register. 0x058 read-write 0 0xFFFFFFFF SYNC Enables synchronous mode. [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 CSRC Clock source select. [1:1] ENUM SYNCHRONOUS_SLAVE_MO Synchronous slave mode (SCLK in) 0 SYNCHRONOUS_MASTER_M Synchronous master mode (SCLK out) 1 FES Falling edge sampling. [2:2] ENUM RISING RxD is sampled on the rising edge of SCLK 0 FALLING RxD is sampled on the falling edge of SCLK 1 TSBYPASS Transmit synchronization bypass in synchronous slave mode. [3:3] ENUM SYNC The input clock is synchronized prior to being used in clock edge detection logic 0 NOSYNC The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. 1 CSCEN Continuous master clock enable (used only when CSRC is 1) [4:4] ENUM SCLK_CYCLES_ONLY_WHE SCLK cycles only when characters are being sent on TxD 0 SCLK_RUNS_CONTINUOUS SCLK runs continuously (characters can be received on RxD independently from transmission on TxD) 1 SSDIS Start/stop bits [5:5] ENUM SEND_START_STOP Send start and stop bits as in other modes. 0 DONT_SEND_START_STOP Do not send start/stop bits. 1 CCCLR Continuous clock clear [6:6] ENUM SOFTWARE CSCEN is under software control. 0 HARDWARE Hardware clears CSCEN after each character is received. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] CT16B0 16-bit counter/timers CT16B0 CT16B0 0x4000C000 0 0xFFF registers CT16B0 16 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] RESERVED Reserved. [5:5] CR1INT Interrupt flag for capture channel 1 event. [6:6] RESERVED Reserved [31:7] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM THE_COUNTERS_ARE_DIS The counters are disabled. 0 THE_TIMER_COUNTER_AN The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM DO_NOTHING Do nothing. 0 RESET The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [15:0] RESERVED Reserved. [31:16] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescale value. [15:0] RESERVED Reserved. [31:16] PC Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [15:0] RESERVED Reserved. [31:16] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [15:0] RESERVED Reserved. [31:16] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0FE Capture on CT16B0_CAP0 falling edge: a sequence of 1 then 0 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0I Interrupt on CT16B0_CAP0 event: a CR0 load due to a CT16B0_CAP0 event will generate an interrupt. [2:2] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved. [3:3] RESERVED Reserved. [4:4] RESERVED Reserved. [5:5] CAP1RE Capture on CT16B0_CAP1 rising edge: a sequence of 0 then 1 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1. [6:6] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1FE Capture on CT16B0_CAP1 falling edge: a sequence of 1 then 0 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1. [7:7] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1I Interrupt on CT16B0_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt. This bit is reserved for 16-bit timer1 CT16B1. [8:8] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] CR0 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [15:0] RESERVED Reserved. [31:16] CR1 Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B0_CAP1 input. 0x034 read-only 0 0x00000000 CAP Timer counter capture value. [15:0] RESERVED Reserved. [31:16] EMR External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. [2:2] EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits. [5:4] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTH Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved. [3:2] ENUM CT16B0_CAP0 CT16B0_CAP0. 0x0 RESERVED_1 Reserved. 0x1 CT16B0_CAP1 CT16B0_CAP1. 0x2 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. [7:5] ENUM RISING_EDGE_OF_CT16B_CAP0 Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set). 0x0 FALLING_EDGE_OF_CT16_CAP0 Falling Edge of CT16B0_CAP0 clears the timer (if bit 4 is set). 0x1 RESERVED_2 Reserved. 0x2 RESERVED_3 Reserved. 0x3 RISING_EDGE_OF_CT16B_CAP1 Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set). 0x4 FALLING_EDGE_OF_CT16_CAP1 Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set). 0x5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 ENABLED PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT16Bn_MAT01 is controlled by EM1. 0 ENABLED PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT16Bn_MAT2 is controlled by EM2. 0 ENABLED PWM mode is enabled for CT16Bn_MAT2. 1 PWMEN3 PWM mode enable for channel3. [3:3] ENUM EM3 CT16Bn_MAT3 is controlled by EM3. 0 ENABLED PWM mode is enabled for CT16Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT16B1 16-bit counter/timers CT16B1 0x40010000 0 0xFFF registers CT16B1 17 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] RESERVED Reserved. [6:6] RESERVED Reserved [31:7] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM THE_COUNTERS_ARE_DIS The counters are disabled. 0 THE_TIMER_COUNTER_AN The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM DO_NOTHING Do nothing. 0 RESET The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [15:0] RESERVED Reserved. [31:16] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescale value. [15:0] RESERVED Reserved. [31:16] PC Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [15:0] RESERVED Reserved. [31:16] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [15:0] RESERVED Reserved. [31:16] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT16B1_CAP0 rising edge: a sequence of 0 then 1 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0FE Capture on CT16B11_CAP0 falling edge: a sequence of 1 then 0 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0I Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will generate an interrupt. [2:2] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1RE Capture on CT16B1_CAP1 rising edge: a sequence of 0 then 1 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC. [3:3] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1FE Capture on CT16B1_CAP1 falling edge: a sequence of 1 then 0 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC. [4:4] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1I Interrupt on CT16B1_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt. [5:5] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] CR0 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [15:0] RESERVED Reserved. [31:16] CR1 Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B1_CAP1 input. 0x030 read-only 0 0x00000000 CAP Timer counter capture value. [15:0] RESERVED Reserved. [31:16] EMR External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. [2:2] EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits. [5:4] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTH Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x2 to 0x3 are reserved. [3:2] ENUM CT16B1_CAP0 CT16B1_CAP0. 0x0 CT16B1_CAP1 CT16B1_CAP1. 0x1 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SELCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x6 to 0x7 are reserved. [7:5] ENUM RISING_EDGE_OF_CT16B_CAP0 Rising Edge of CT16B1_CAP0 clears the timer (if bit 4 is set). 0x0 FALLING_EDGE_OF_CT16_CAP0 Falling Edge of CT16B1_CAP0 clears the timer (if bit 4 is set). 0x1 RISING_EDGE_OF_CT16B_CAP1 Rising Edge of CT16B1_CAP1 clears the timer (if bit 4 is set). 0x2 FALLING_EDGE_OF_CT16_CAP1 Falling Edge of CT16B1_CAP1 clears the timer (if bit 4 is set). 0x3 RESERVED_4 Reserved. 0x4 RESERVED_5 Reserved. 0x5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 ENABLED PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT16Bn_MAT01 is controlled by EM1. 0 ENABLED PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT16Bn_MAT2 is controlled by EM2. 0 ENABLED PWM mode is enabled for CT16Bn_MAT2. 1 PWMEN3 PWM mode enable for channel3. [3:3] ENUM EM3 CT16Bn_MAT3 is controlled by EM3. 0 ENABLED PWM mode is enabled for CT16Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT32B0 32-bit counter/timers CT32B0 CT32B0 0x40014000 0 0xFFF registers CT32B0 18 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] RESERVED Reserved, [5:5] CR1INT Interrupt flag for capture channel 1 event. [6:6] RESERVED Reserved [31:7] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM THE_COUNTERS_ARE_DIS The counters are disabled. 0 THE_TIMER_COUNTER_AN The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM DO_NOTHING Do nothing. 0 RESET The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescaler value. [31:0] PC Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0FE Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0I Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt. [2:2] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved. [5:3] CAP1RE Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC. [6:6] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1FE Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC. [7:7] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1I Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will generate an interrupt. [8:8] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] CR0 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] CR1 Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B0_CAP1 input. 0x034 read-write 0 0x00000000 CAP Timer counter capture value. [31:0] EMR External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTH Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x1 and0x3 are reserved. [3:2] ENUM CT32B0_CAP0 CT32B0_CAP0 0x0 RESERVED_1 Reserved. 0x1 CT32B0_CAP1 CT32B0_CAP1 0x2 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SElCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. [7:5] ENUM RISING_EDGE_OF_CT32B_CAP0 Rising Edge of CT32B0_CAP0 clears the timer (if bit 4 is set) 0x0 FALLING_EDGE_OF_CT32_CAP0 Falling Edge of CT32B0_CAP0 clears the timer (if bit 4 is set) 0x1 RESERVED_2 Reserved, 0x2 RESERVED_3 Reserved. 0x3 RISING_EDGE_OF_CT32B_CAP1 Rising Edge of CT32B0_CAP1 clears the timer (if bit 4 is set) 0x4 FALLING_EDGE_OF_CT32_CAP1 Falling Edge of CT32B0_CAP1 clears the timer (if bit 4 is set) 0x5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 ENABLED PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT32Bn_MAT01 is controlled by EM1. 0 ENABLED PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 ENABLED PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. [3:3] ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 ENABLED PWM mode is enabled for CT132Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CT32B1 32-bit counter/timers CT32B1 0x40018000 0 0xFFF registers CT32B1 19 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] RESERVED Reserved [31:6] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN Counter enable. [0:0] ENUM THE_COUNTERS_ARE_DIS The counters are disabled. 0 THE_TIMER_COUNTER_AN The Timer Counter and Prescale Counter are enabled for counting. 1 CRST Counter reset. [1:1] ENUM DO_NOTHING Do nothing. 0 RESET The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PCVAL Prescaler value. [31:0] PC Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. [0:0] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0R Reset on MR0: the TC will be reset if MR0 matches it. [1:1] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. [2:2] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. [3:3] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1R Reset on MR1: the TC will be reset if MR1 matches it. [4:4] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. [5:5] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. [6:6] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2R Reset on MR2: the TC will be reset if MR2 matches it. [7:7] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. [8:8] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. [9:9] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3R Reset on MR3: the TC will be reset if MR3 matches it. [10:10] ENUM ENABLED Enabled 1 DISABLED Disabled 0 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. [11:11] ENUM ENABLED Enabled 1 DISABLED Disabled 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CT32B1_CAP0 rising edge: a sequence of 0 then 1 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC. [0:0] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0FE Capture on CT32B1_CAP0 falling edge: a sequence of 1 then 0 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC. [1:1] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP0I Interrupt on CT32B1_CAP0 event: a CR0 load due to a CT32B1_CAP0 event will generate an interrupt. [2:2] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1RE Capture on CT32B1_CAP1 rising edge: a sequence of 0 then 1 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC. [3:3] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1FE Capture on CT32B1_CAP1 falling edge: a sequence of 1 then 0 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC. [4:4] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 CAP1I Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will generate an interrupt. [5:5] ENUM ENABLED Enabled. 1 DISABLED Disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] CR0 Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] CR1 Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B1_CAP1 input. 0x030 read-write 0 0x00000000 CAP Timer counter capture value. [31:0] EMR External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [0:0] EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [1:1] EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [2:2] EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM DO_NOTHING Do Nothing. 0x0 CLEAR Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out). 0x1 SET Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. [1:0] ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTH Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved. [3:2] ENUM CT32B1_CAP0 CT32B1_CAP0 0x0 CT32B1_CAP1 CT32B1_CAP1 0x1 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. [4:4] SElCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved. [7:5] ENUM RISING_EDGE_OF_CT32B_CAP0 Rising Edge of CT32B1_CAP0 clears the timer (if bit 4 is set) 0x0 FALLING_EDGE_OF_CT32_CAP0 Falling Edge of CT32B1_CAP0 clears the timer (if bit 4 is set) 0x1 RISING_EDGE_OF_CT32B_CAP1 Rising Edge of CT32B1_CAP1 clears the timer (if bit 4 is set) 0x2 FALLING_EDGE_OF_CT32_CAP1 Falling Edge of CT32B1_CAP1 clears the timer (if bit 4 is set) 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. 0x074 read-write 0 0xFFFFFFFF PWMEN0 PWM mode enable for channel0. [0:0] ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 ENABLED PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM mode enable for channel1. [1:1] ENUM EM1 CT32Bn_MAT01 is controlled by EM1. 0 ENABLED PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM mode enable for channel2. [2:2] ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 ENABLED PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. [3:3] ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 ENABLED PWM mode is enabled for CT132Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ADC ADC ADC 0x4001C000 0 0xFFF registers ADC 24 CR A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. 0x000 read-write 0x00000000 0xFFFFFFFF SEL Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01). [7:0] CLKDIV The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. [15:8] BURST Burst mode If BURST is set to 1, the ADGINTEN bit in the INTEN register (Table 276) must be set to 0. [16:16] ENUM SOFTWARE_CONTROLLED Software-controlled mode: Conversions are software-controlled and require 11 clocks. 0 HARDWARE_SCAN Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. 1 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). [19:17] ENUM 11_CLOCKS_10_BITS 11 clocks / 10 bits 0x0 10_CLOCKS_9_BITS 10 clocks / 9 bits 0x1 9_CLOCKS_8_BITS 9 clocks / 8 bits 0x2 8_CLOCKS_7_BITS 8 clocks / 7 bits 0x3 7_CLOCKS_6_BITS 7 clocks / 6 bits 0x4 6_CLOCKS_5_BITS 6 clocks / 5 bits 0x5 5_CLOCKS_4_BITS 5 clocks / 4 bits 0x6 4_CLOCKS_3_BITS 4 clocks / 3 bits 0x7 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [23:20] START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: [26:24] ENUM NO_START_THIS_VALUE No start (this value should be used when clearing PDN to 0). 0x0 START_CONVERSION_NOW Start conversion now. 0x1 PIO0_2 Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0. 0x2 PIO1_5 Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0. 0x3 CT32B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]. 0x4 CT32B0_MAT1 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]. 0x5 CT16B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]. 0x6 CT16B0_MAT1 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]. 0x7 EDGE This bit is significant only when the START field contains 010-111. In these cases: [27:27] ENUM RISING Start conversion on a rising edge on the selected CAP/MAT signal. 0 FALLING Start conversion on a falling edge on the selected CAP/MAT signal. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:28] GDR A/D Global Data Register. Contains the result of the most recent A/D conversion. 0x004 read-write 0 0x00000000 RESERVED Reserved. These bits always read as zeros. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF. [15:6] RESERVED Reserved. These bits always read as zeros. [23:16] CHN These bits contain the channel from which the result bits V_VREF were converted. [26:24] RESERVED Reserved. These bits always read as zeros. [29:27] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. [31:31] INTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. 0x00C read-write 0x00000100 0xFFFFFFFF ADINTEN These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. [7:0] ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. This bit must be set to 0 in burst mode (BURST = 1 in the CR register). [8:8] RESERVED Reserved. Unused, always 0. [31:9] 8 0x4 0-7 DR%s A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel N 0x010 read-only 0 0x11111111 RESERVED Reserved. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. [15:6] RESERVED Reserved. [29:16] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. [31:31] STAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. 0x030 read-only 0 0xFFFFFFFF DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel n. [7:0] OVERRUN These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously. [15:8] ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. [16:16] RESERVED Reserved. Unused, always 0. [31:17] PMU Power Management Unit (PMU) PMU 0x40038000 0x0 0xFFF registers PCON Power control register 0x000 read-write 0x0 0xFFFFFFFF PM Power mode [2:0] ENUM DEFAULT Default. The part is in active or sleep mode. 0x0 DEEPSLEEP ARM WFI will enter Deep-sleep mode. 0x1 POWERDOWN ARM WFI will enter Power-down mode. 0x2 DEEPPOWERDOWN ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down). 0x3 NODPD A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. Execution continues after the WFI if this bit is 1. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. [3:3] RESERVED Reserved. Do not write ones to this bit. [7:4] SLEEPFLAG Sleep mode flag [8:8] ENUM NOPOWERDOWN Read: No power-down mode entered. LPC11U1x is in Active mode. Write: No effect. 0 POWERDOWN Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 1 RESERVED Reserved. Do not write ones to this bit. [10:9] DPDFLAG Deep power-down flag [11:11] ENUM DPNOTENTERED Read: Deep power-down mode not entered. Write: No effect. 0 DPENTERED Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 1 RESERVED Reserved. Do not write ones to this bit. [31:12] 4 0x4 0-3 GPREG%s General purpose register 0 0x004 read-write 0x0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. [31:0] GPREG4 General purpose register 4 0x014 read-write 0x0 0xFFFFFFFF RESERVED Reserved. Do not write ones to this bit. [9:0] WAKEUPHYS WAKEUP pin hysteresis enable [10:10] ENUM DISABLED Hysteresis for WAKEUP pin disabled. 0 ENABLED Hysteresis for WAKEUP pin enabled. 1 GPDATA Data retained during Deep power-down mode. [31:11] FLASHCTRL Flash controller FLASHCTRL 0x4003C000 0x0 0xFFF registers FLASH_IRQ 27 EEMSSTART EEPROM BIST start address register 0x09C read-write 0x0 0xFFFFFFFF STARTA BIST start address: Bit 0 is fixed zero since only even addresses are allowed. [13:0] RESERVED Reserved [31:14] EEMSSTOP EEPROM BIST stop address register 0x0A0 read-write 0x0 0xFFFFFFFF STOPA BIST stop address: Bit 0 is fixed zero since only even addresses are allowed. [13:0] RESERVED Reserved [29:14] DEVSEL BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same. [30:30] STRTBIST BIST start bit Setting this bit will start the BIST. This bit is self-clearing. [31:31] EEMSSIG EEPROM 24-bit BIST signature register 0x0A4 read-only 0x0 0xFFFFFFFF DATA_SIG BIST 16-bit signature calculated from only the data bytes [15:0] PARITY_SIG BIST 16-bit signature calculated from only the parity bits of the data bytes [31:16] FLASHCFG Flash memory access time configuration register 0x010 read-write 0 0x00000000 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. [1:0] ENUM 1_SYSTEM_CLOCK_FLASH 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 0x0 2_SYSTEM_CLOCKS_FLAS 2 system clocks flash access time (for system clock frequencies of up to 40 MHz). 0x1 3_SYSTEM_CLOCKS_FLAS 3 system clocks flash access time (for system clock frequencies of up to 50 MHz). 0x2 RESERVED Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. [31:2] FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). [16:0] SIG_START Start control bit for signature generation. [17:17] ENUM SIGNATURE_GENERATION Signature generation is stopped 0 INITIATE_SIGNATURE_G Initiate signature generation 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:18] FMSW0 Word 0 [31:0] 0x02C read-only 0 0x00000000 SW0_31_0 Word 0 of 128-bit signature (bits 31 to 0). [31:0] FMSW1 Word 1 [63:32] 0x030 read-only 0 0x00000000 SW1_63_32 Word 1 of 128-bit signature (bits 63 to 32). [31:0] FMSW2 Word 2 [95:64] 0x034 read-only 0 0x00000000 SW2_95_64 Word 2 of 128-bit signature (bits 95 to 64). [31:0] FMSW3 Word 3 [127:96] 0x038 read-only 0 0x00000000 SW3_127_96 Word 3 of 128-bit signature (bits 127 to 96). [31:0] FMSTAT Signature generation status register 0xFE0 read-only 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] SIG_DONE When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag. [2:2] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] FMSTATCLR Signature generation status clear register 0xFE8 write-only 0 0x00000000 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. [2:2] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] SSP0 SSP/SPI SSP0 0x40040000 0 0xFFF registers SSP0 20 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x000 read-write 0 0xFFFFFFFF DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. [3:0] ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. [5:4] ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 RESERVED This combination is not supported and should not be used. 0x3 CPOL Clock Out Polarity. This bit is only used in SPI mode. [6:6] ENUM LOW SPI controller maintains the bus clock low between frames. 0 HIGH SPI controller maintains the bus clock high between frames. 1 CPHA Clock Out Phase. This bit is only used in SPI mode. [7:7] ENUM FIRSTCLOCK SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECONDCLOCK SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 SCR Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). [15:8] RESERVED Reserved [31:16] CR1 Control Register 1. Selects master/slave and other modes. 0x004 read-write 0 0xFFFFFFFF LBM Loop Back Mode. [0:0] ENUM NORMAL_OPERATION During normal operation. 0 SERIAL_OUTPUT Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 SSE SPI Enable. [1:1] ENUM DISABLED The SPI controller is disabled. 0 ENABLED The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit. 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. [2:2] ENUM MASTER The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x008 read-write 0 0xFFFFFFFF modify DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. [15:0] RESERVED Reserved. [31:16] SR Status Register 0x00C read-only 0x00000003 0xFFFFFFFF TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. [0:0] TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. [1:1] RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. [2:2] RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. [3:3] BSY Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CPSR Clock Prescale Register 0x010 read-write 0 0xFFFFFFFF CPSDVSR This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. [7:0] RESERVED Reserved. [31:8] IMSC Interrupt Mask Set and Clear Register 0x014 read-write 0 0xFFFFFFFF RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. [2:2] TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RIS Raw Interrupt Status Register 0x018 read-only 0x00000008 0xFFFFFFFF RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXRIS This bit is 1 if the Rx FIFO is at least half full. [2:2] TXRIS This bit is 1 if the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] MIS Masked Interrupt Status Register 0x01C read-only 0 0xFFFFFFFF RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. [0:0] RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. [2:2] TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ICR SSPICR Interrupt Clear Register 0x020 write-only 0 0x00000000 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. [0:0] RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] IOCON I/O configuration Modification IOCON 0x40044000 0x0 0xFFF registers RESET_PIO0_0 I/O configuration for pin RESET/PIO0_0 0x000 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM RESET RESET. 0x0 PIO0_0 PIO0_0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_1 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE 0x004 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM PIO0_1 PIO0_1. 0x0 CLKOUT CLKOUT. 0x1 CT32B0_MAT2 CT32B0_MAT2. 0x2 USB_FTOGGLE USB_FTOGGLE. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_2 I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 0x008 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_2 PIO0_2. 0x0 SSEL0 SSEL0. 0x1 CT16B0_CAP0 CT16B0_CAP0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_3 I/O configuration for pin PIO0_3/USB_VBUS 0x00C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO0_3 PIO0_3. 0x0 USB_VBUS USB_VBUS. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_4 I/O configuration for pin PIO0_4/SCL 0x010 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO0_4 PIO0_4 (open-drain pin). 0x0 I2C_SCL I2C SCL (open-drain pin). 0x1 RESERVED Reserved. [7:3] I2CMODE Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO Standard I/O functionality 0x1 FAST_MODE_PLUS Fast-mode Plus I2C 0x2 RESERVED Reserved. 0x3 RESERVED Reserved. [31:10] PIO0_5 I/O configuration for pin PIO0_5/SDA 0x014 read-write 0x00000080 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO0_5 PIO0_5 (open-drain pin). 0x0 I2C_SDA I2C SDA (open-drain pin). 0x1 RESERVED Reserved. [7:3] I2CMODE Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO Standard I/O functionality 0x1 FAST_MODE_PLUS Fast-mode Plus I2C 0x2 RESERVED Reserved. 0x3 RESERVED Reserved. [31:10] PIO0_6 I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 0x018 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_6 PIO0_6. 0x0 USB_CONNECT USB_CONNECT. 0x1 SCK0 SCK0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_7 I/O configuration for pin PIO0_7/CTS 0x01C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO0_7 PIO0_7. 0x0 CTS CTS. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_8 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 0x020 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_8 PIO0_8. 0x0 MISO0 MISO0. 0x1 CT16B0_MAT0 CT16B0_MAT0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_9 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 0x024 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_9 PIO0_9. 0x0 MOSI0 MOSI0. 0x1 CT16B0_MAT1 CT16B0_MAT1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] SWCLK_PIO0_10 I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 0x028 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM SWCLK SWCLK. 0x0 PIO0_10 PIO0_10. 0x1 SCK0 SCK0. 0x2 CT16B0_MAT2 CT16B0_MAT2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TDI_PIO0_11 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 0x02C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM TDI TDI. 0x0 PIO0_11 PIO0_11. 0x1 AD0 AD0. 0x2 CT32B0_MAT3 CT32B0_MAT3. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TMS_PIO0_12 I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 0x030 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM TMS TMS. 0x0 PIO0_12 PIO0_12. 0x1 AD1 AD1. 0x2 CT32B1_CAP0 CT32B1_CAP0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TDO_PIO0_13 I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 0x034 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM TDO TDO. 0x0 PIO0_13 PIO0_13. 0x1 AD2 AD2. 0x2 CT32B1_MAT0 CT32B1_MAT0. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] TRST_PIO0_14 I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 0x038 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM TRST TRST. 0x0 PIO0_14 PIO0_14. 0x1 AD3 AD3. 0x2 CT32B1_MAT1 CT32B1_MAT1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] SWDIO_PIO0_15 I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 0x03C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM SWDIO SWDIO. 0x0 PIO0_15 PIO0_15. 0x1 AD4 AD4. 0x2 CT32B1_MAT2 CT32B1_MAT2. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_16 I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP 0x040 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. This pin functions as WAKEUP pin if the LPC11Uxx is in Deep power-down mode regardless of the value of FUNC. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_16 PIO0_16. 0x0 AD5 AD5. 0x1 CT32B1_MAT3 CT32B1_MAT3. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_17 I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK 0x044 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM PIO0_17 PIO0_17. 0x0 RTS RTS. 0x1 CT32B0_CAP0 CT32B0_CAP0. 0x2 SCLK_UART_SYNCHRONO SCLK (UART synchronous clock). 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_18 I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 0x048 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_18 PIO0_18. 0x0 RXD RXD. 0x1 CT32B0_MAT0 CT32B0_MAT0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_19 I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 0x04C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_19 PIO0_19. 0x0 TXD TXD. 0x1 CT32B0_MAT1 CT32B0_MAT1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_20 I/O configuration for pin PIO0_20/CT16B1_CAP0 0x050 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO0_20 PIO0_20. 0x0 CT16B1_CAP0 CT16B1_CAP0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_21 I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 0x054 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO0_21 PIO0_21. 0x0 CT16B1_MAT0 CT16B1_MAT0. 0x1 MOSI1 MOSI1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_22 I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 0x058 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM PIO0_22 PIO0_22. 0x0 AD6 AD6. 0x1 CT16B1_MAT1 CT16B1_MAT1. 0x2 MISO1 MISO1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO0_23 I/O configuration for pin PIO0_23/AD7 0x05C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO0_23 PIO0_23. 0x0 AD7 AD7. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 ADMODE Selects Analog/Digital mode. [7:7] ENUM ANALOG Analog input mode. 0 DIGITAL Digital functional mode. 1 FILTR Selects 10 ns input glitch filter. [8:8] ENUM ENABLED Filter enabled. 0 DISABLED Filter disabled. 1 RESERVED Reserved. [9:9] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_0 I/O configuration for pin PIO1_0/CT32B1_MAT0 0x060 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_0 PIO1_0. 0x0 CT32B1_MAT1 CT32B1_MAT1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_1 I/O configuration for pin PIO1_1/CT32B1_MAT1 0x064 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_1 PIO1_1. 0x0 CT32B1_MAT1 CT32B1_MAT1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_2 I/O configuration for pin PIO1_2/CT32B1_MAT2 0x068 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_2 PIO1_2. 0x0 CT32B1_MAT2 CT32B1_MAT2. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_3 I/O configuration for pin PIO1_3/CT32B1_MAT3 0x06C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_3 PIO1_3. 0x0 CT32B1_MAT3 CT32B1_MAT3. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_4 I/O configuration for pin PIO1_4/CT32B1_CAP0 0x070 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_4 PIO1_4. 0x0 CT32B1_CAP0 CT32B1_CAP0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_5 I/O configuration for pin PIO1_5/CT32B1_CAP1 0x074 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_5 PIO1_5. 0x0 CT32B1_CAP1 CT32B1_CAP1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_6 I/O configuration for pin PIO1_6 0x078 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_6 PIO1_6. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_7 I/O configuration for pin PIO1_7 0x07C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_7 PIO1_7. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_8 I/O configuration for pin PIO1_8 0x080 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x1 to 0x7 are reserved. [2:0] ENUM PIO1_8 PIO1_8. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_9 I/O configuration for pin PIO1_9 0x084 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x1 to 0x7 are reserved. [2:0] ENUM PIO1_9 PIO1_9. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_10 I/O configuration for pin PIO1_10 0x088 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x1 to 0x7 are reserved. [2:0] ENUM PIO1_10 PIO1_10. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_11 I/O configuration for pin PIO1_11 0x08C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x1 to 0x7 are reserved. [2:0] ENUM PIO1_11 PIO1_11. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_12 I/O configuration for pin PIO1_12 0x090 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x1 to 0x7 are reserved. [2:0] ENUM PIO1_12 PIO1_12. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_13 I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD 0x094 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM PIO1_13 PIO1_13. 0x0 DTR DTR. 0x1 CT16B0_MAT0 CT16B0_MAT0. 0x2 TXD TXD. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_14 I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD 0x098 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM PIO1_14 PIO1_14. 0x0 DSR DSR. 0x1 CT16B0_MAT1 CT16B0_MAT1. 0x2 RXD RXD. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_15 I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 0x09C read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x4 to 0x7 are reserved. [2:0] ENUM PIO1_15 PIO1_15. 0x0 DCD DCD. 0x1 CT16B0_MAT2 CT16B0_MAT2. 0x2 SCK1 SCK1. 0x3 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_16 I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 0x0A0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_16 PIO1_16. 0x0 RI RI. 0x1 CT16B0_CAP0 CT16B0_CAP0. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_17 I/O configuration for PIO1_17/CT16B0_CAP1/RXD 0x0A4 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_17 PIO1_17. 0x0 CT16B0_CAP1 CT16B0_CAP1 0x1 RXD RXD 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_18 I/O configuration for PIO1_18/CT16B1_CAP1/TXD 0x0A8 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_18 PIO1_18 0x0 CT16B1_CAP1 CT16B1_CAP1 0x1 TXD TXD 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD. 1 RESERVED Reserved. [31:11] PIO1_19 I/O configuration for pin PIO1_19/DTR/SSEL1 0x0AC read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_19 PIO1_19. 0x0 DTR DTR. 0x1 SSEL1 SSEL1. 0x2 MODE mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_20 I/O configuration for pin PIO1_20/DSR/SCK1 0x0B0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_20 PIO1_20. 0x0 DSR DSR. 0x1 SCK1 SCK1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_21 I/O configuration for pin PIO1_21/DCD/MISO1 0x0B4 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_21 PIO1_21. 0x0 DCD DCD. 0x1 MISO1 MISO1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_22 I/O configuration for pin PIO1_22/RI/MOSI1 0x0B8 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_22 PIO1_22. 0x0 RI RI. 0x1 MOSI1 MOSI1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_23 I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 0x0BC read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_23 PIO1_23. 0x0 CT16B1_MAT1 CT16B1_MAT1. 0x1 SSEL1 SSEL1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_24 I/O configuration for pin PIO1_24/ CT32B0_MAT0 0x0C0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_24 PIO1_24. 0x0 CT32B0_MAT0 CT32B0_MAT0. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_25 I/O configuration for pin PIO1_25/CT32B0_MAT1 0x0C4 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x2 to 0x7 are reserved. [2:0] ENUM PIO1_25 PIO1_25. 0x0 CT32B0_MAT1 CT32B0_MAT1. 0x1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_26 I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD 0x0C8 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_26 PIO1_26. 0x0 CT32B0_MAT2 CT32B0_MAT2 0x1 RXD RXD. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_27 I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD 0x0CC read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_27 PIO1_27. 0x0 CT32B0_MAT3 CT32B0_MAT3. 0x1 TXD TXD. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_28 I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK 0x0D0 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_28 PIO1_28. 0x0 CT32B0_CAP0 CT32B0_CAP0. 0x1 SCLK SCLK. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_29 I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 0x0D4 read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x3 to 0x7 are reserved. [2:0] ENUM PIO1_29 PIO1_29. 0x0 SCK0 SCK0. 0x1 CT32B0_CAP1 CT32B0_CAP1. 0x2 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] PIO1_31 I/O configuration for pin PIO1_31 0x0DC read-write 0x00000090 0xFFFFFFFF FUNC Selects pin function. Values 0x1 to 0x7 are reserved. [2:0] ENUM PIO1_31 PIO1_31. 0x0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN Pull-down resistor enabled. 0x1 PULL_UP Pull-up resistor enabled. 0x2 REPEATER Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLED Disable. 0 ENABLED Enable. 1 INV Invert input [6:6] ENUM NOT_INVERTED Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0). 0 INVERTED Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLED Disable. 0 OPEN_DRAIN Open-drain mode enabled. This is not a true open-drain mode. 1 RESERVED Reserved. [31:11] SYSCON System control block SYSCON 0x40048000 0x0 0xFFF registers BOD_IRQ 26 SYSMEMREMAP System memory remap 0x000 read-write 0x02 0xFFFFFFFF MAP System memory remap. Value 0x3 is reserved. [1:0] ENUM BOOT_LOADER_MODE_IN Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x0 USER_RAM_MODE_INTER User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x1 USER_FLASH_MODE_INT User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x2 RESERVED Reserved [31:2] PRESETCTRL Peripheral reset control 0x004 read-write 0 0xFFFFFFFF SSP0_RST_N SSP0 reset control [0:0] ENUM RESETS_THE_SSP0_PERI Resets the SSP0 peripheral. 0 SSP0_RESET_DE_ASSERT SSP0 reset de-asserted. 1 I2C_RST_N I2C reset control [1:1] ENUM RESETS_THE_I2C_PERIP Resets the I2C peripheral. 0 I2C_RESET_DE_ASSERTE I2C reset de-asserted. 1 SSP1_RST_N SSP1 reset control [2:2] ENUM RESETS_THE_SSP1_PERI Resets the SSP1 peripheral. 0 SSP1_RESET_DE_ASSERT SSP1 reset de-asserted. 1 RESERVED Reserved [3:3] RESERVED Reserved [31:4] SYSPLLCTRL System PLL control 0x008 read-write 0 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 [4:0] PSEL Post divider ratio P. The division ratio is 2 x P. [6:5] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:7] SYSPLLSTAT System PLL status 0x00C read-only 0 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] USBPLLCTRL USB PLL control 0x010 read-write 0 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 [4:0] PSEL Post divider ratio P. The division ratio is 2 x P. [6:5] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:7] USBPLLSTAT USB PLL status 0x014 read-only 0 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] SYSOSCCTRL System oscillator control 0x020 read-write 0x000 0xFFFFFFFF BYPASS Bypass system oscillator [0:0] ENUM DISABLED Oscillator is not bypassed. 0 ENABLED Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. 1 FREQRANGE Determines frequency range for Low-power oscillator. [1:1] ENUM 1_20_MHZ_FREQUENCY 1 - 20 MHz frequency range. 0 15_25_MHZ_FREQUENC 15 - 25 MHz frequency range 1 RESERVED Reserved [31:2] WDTOSCCTRL Watchdog oscillator control 0x024 read-write 0x0 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 [4:0] FREQSEL Select watchdog oscillator analog output frequency (Fclkana). [8:5] ENUM 0_6_MHZ 0.6 MHz 0x1 1_05_MHZ 1.05 MHz 0x2 1_4_MHZ 1.4 MHz 0x3 1_75_MHZ 1.75 MHz 0x4 2_1_MHZ 2.1 MHz 0x5 2_4_MHZ 2.4 MHz 0x6 2_7_MHZ 2.7 MHz 0x7 3_0_MHZ 3.0 MHz 0x8 3_25_MHZ 3.25 MHz 0x9 3_5_MHZ 3.5 MHz 0xA 3_75_MHZ 3.75 MHz 0xB 4_0_MHZ 4.0 MHz 0xC 4_2_MHZ 4.2 MHz 0xD 4_4_MHZ 4.4 MHz 0xE 4_6_MHZ 4.6 MHz 0xF RESERVED Reserved [31:9] SYSRSTSTAT System reset status register 0x030 read-write 0x3 0xFFFFFFFF POR POR reset status [0:0] ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED_WRITIN POR detected. Writing a one clears this reset. 1 EXTRST External reset status [1:1] ENUM NO_RESET_EVENT_DETEC No reset event detected. 0 RESET_DETECTED_WRIT Reset detected. Writing a one clears this reset. 1 WDT Status of the Watchdog reset [2:2] ENUM NO_RESET No WDT reset detected 0 RESET_CLEAR WDT reset detected. Writing a one clears this reset. 1 BOD Status of the Brown-out detect reset [3:3] ENUM NO_RESET No BOD reset detected 0 RESET_CLEAR BOD reset detected. Writing a one clears this reset. 1 SYSRST Status of the software system reset [4:4] ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected. Writing a one clears this reset. 1 RESERVED Reserved [31:5] SYSPLLCLKSEL System PLL clock source select 0x040 read-write 0x1 0xFFFFFFFF SEL System PLL clock source [1:0] ENUM IRC IRC 0x0 CRYSTAL_OSCILLATOR Crystal Oscillator (SYSOSC) 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] SYSPLLCLKUEN System PLL clock source update enable 0x044 read-write 0x1 0xFFFFFFFF ENA Enable system PLL clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] USBPLLCLKSEL USB PLL clock source select 0x048 read-write 0 0xFFFFFFFF SEL USB PLL clock source [1:0] ENUM IRC_THE_USB_PLL_CLO IRC. The USB PLL clock source must be switched to system oscillator for correct full-speed USB operation. The IRC is suitable for low-speed USB operation. 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:2] USBPLLCLKUEN USB PLL clock source update enable 0x04C read-write 0 0xFFFFFFFF ENA Enable USB PLL clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] MAINCLKSEL Main clock source select 0x070 read-write 0x0 0xFFFFFFFF SEL Clock source for main clock [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 PLL_INPUT PLL input 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 PLL_OUTPUT PLL output 0x3 RESERVED Reserved [31:2] MAINCLKUEN Main clock source update enable 0x074 read-write 0x1 0xFFFFFFFF ENA Enable main clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] SYSAHBCLKDIV System clock divider 0x078 read-write 0x001 0xFFFFFFFF DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SYSAHBCLKCTRL System clock control 0x080 read-write 0x0000003F 0xFFFFFFFF SYS Enables the clock for the AHB, the APB bridge, the Cortex-M0 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1. [0:0] ENUM RESERVED Reserved 0 ENABLED Enable 1 ROM Enables clock for ROM. [1:1] ENUM DISABLED Disable 0 ENABLED Enable 1 RAM0 Enables clock for RAM. [2:2] ENUM DISABLED Disable 0 ENABLED Enable 1 FLASHREG Enables clock for flash register interface. [3:3] ENUM DISABLED Disable 0 ENABLED Enable 1 FLASHARRAY Enables clock for flash array access. [4:4] ENUM DISABLED Disable 0 ENABLED Enable 1 I2C Enables clock for I2C. [5:5] ENUM DISABLED Disable 0 ENABLED Enable 1 GPIO Enables clock for GPIO port registers. [6:6] ENUM DISABLED Disable 0 ENABLED Enable 1 CT16B0 Enables clock for 16-bit counter/timer 0. [7:7] ENUM DISABLED Disable 0 ENABLED Enable 1 CT16B1 Enables clock for 16-bit counter/timer 1. [8:8] ENUM DISABLED Disable 0 ENABLED Enable 1 CT32B0 Enables clock for 32-bit counter/timer 0. [9:9] ENUM DISABLED Disable 0 ENABLED Enable 1 CT32B1 Enables clock for 32-bit counter/timer 1. [10:10] ENUM DISABLED Disable 0 ENABLED Enable 1 SSP0 Enables clock for SSP0. [11:11] ENUM DISABLED Disable 0 ENABLED Enable 1 USART Enables clock for UART. [12:12] ENUM DISABLED Disable 0 ENABLED Enable 1 ADC Enables clock for ADC. [13:13] ENUM DISABLED Disable 0 ENABLED Enable 1 USB Enables clock to the USB register interface. [14:14] ENUM DISABLED Disable 0 ENABLED Enable 1 WWDT Enables clock for WWDT. [15:15] ENUM DISABLED Disable 0 ENABLED Enable 1 IOCON Enables clock for I/O configuration block. [16:16] ENUM DISABLED Disable 0 ENABLED Enable 1 RESERVED Reserved [17:17] SSP1 Enables clock for SSP1. [18:18] ENUM DISABLED Disable 0 ENABLED Enable 1 PINT Enables clock to GPIO Pin interrupts register interface. [19:19] ENUM DISABLED Disable 0 ENABLED Enable 1 RESERVED Reserved [22:20] GROUP0INT Enables clock to GPIO GROUP0 interrupt register interface. [23:23] ENUM DISABLED Disable 0 ENABLED Enable 1 GROUP1INT Enables clock to GPIO GROUP1 interrupt register interface. [24:24] ENUM DISABLED Disable 0 ENABLED Enable 1 RESERVED Reserved [25:25] RAM1 Enables SRAM1 block at address 0x2000 0000. See Section 3.1 for availability of this bit. [26:26] ENUM DISABLED Disable 0 ENABLED Enable 1 USBRAM Enables USB SRAM block at address 0x2000 4000. [27:27] ENUM DISABLED Disable 0 ENABLED Enable 1 RESERVED Reserved [31:28] SSP0CLKDIV SSP0 clock divider 0x094 read-write 0x1 0xFFFFFFFF DIV SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] UARTCLKDIV UART clock divider 0x098 read-write 0 0xFFFFFFFF DIV UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SSP1CLKDIV SSP1 clock divider 0x09C read-write 0 0xFFFFFFFF DIV SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] USBCLKSEL USB clock source select 0x0C0 read-write 0 0xFFFFFFFF SEL USB clock source. Values 0x2 and 0x3 are reserved. [1:0] ENUM USB_PLL_OUT USB PLL out 0x0 MAIN_CLOCK Main clock 0x1 RESERVED Reserved [31:2] USBCLKUEN USB clock source update enable 0x0C4 read-write 0 0xFFFFFFFF ENA Enable USB clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] USBCLKDIV USB clock source divider 0x0C8 read-write 0x1 0xFFFFFFFF DIV USB clock divider values 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] CLKOUTSEL CLKOUT clock source select 0x0E0 read-write 0 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 CRYSTAL_OSCILLATOR Crystal oscillator (SYSOSC) 0x1 LF_OSCILLATOR_WATCH LF oscillator (watchdog oscillator) 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] CLKOUTUEN CLKOUT clock source update enable 0x0E4 read-write 0 0xFFFFFFFF ENA Enable CLKOUT clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] CLKOUTDIV CLKOUT clock divider 0x0E8 read-write 0 0xFFFFFFFF DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] PIOPORCAP0 POR captured PIO status 0 0x100 read-only 0 0x00000000 PIOSTAT State of PIO0_23 through PIO0_0 at power-on reset [23:0] RESERVED Reserved. [31:24] PIOPORCAP1 POR captured PIO status 1 0x104 read-only 0 0x00000000 PIOSTAT State of PIO1_31 through PIO1_0 at power-on reset [31:0] BODCTRL Brown-Out Detect 0x150 read-write 0 0xFFFFFFFF BODRSTLEV BOD reset level [1:0] ENUM LEVEL_0_THE_RESET_A Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V. 0x0 LEVEL_1_THE_RESET_A Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V. 0x1 LEVEL_2_THE_RESET_A Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V. 0x2 LEVEL_3_THE_RESET_A Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V. 0x3 BODINTVAL BOD interrupt level [3:2] ENUM LEVEL_0_RESERVED Level 0: Reserved. 0x0 LEVEL_1THE_INTERRUP Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V. 0x1 LEVEL_2_THE_INTERRU Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V. 0x2 LEVEL_3_THE_INTERRU Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V. 0x3 BODRSTENA BOD reset enable [4:4] ENUM DISABLE_RESET_FUNCTI Disable reset function. 0 ENABLE_RESET_FUNCTIO Enable reset function. 1 RESERVED Reserved [31:5] SYSTCKCAL System tick counter calibration 0x154 read-write 0x4 0xFFFFFFFF CAL System tick timer calibration value [25:0] RESERVED Reserved [31:26] IRQLATENCY IQR delay. Allows trade-off between interrupt latency and determinism. 0x170 read-write 0x00000010 0xFFFFFFFF LATENCY 8-bit latency value [7:0] RESERVED Reserved [31:8] NMISRC NMI Source Control 0x174 read-write 0 0xFFFFFFFF IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 58 for the list of interrupt sources and their IRQ numbers. [4:0] RESERVED Reserved [30:5] NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. [31:31] 8 0x4 0-7 PINTSEL%s GPIO Pin Interrupt Select register 0 0x178 read-write 0 0xFFFFFFFF INTPIN Pin number select for pin interrupt. (PIO0_0 to PIO0_23 correspond to numbers 0 to 23 and PIO1_0 to PIO1_31 correspond to numbers 24 to 55). [5:0] RESERVED Reserved [31:6] USBCLKCTRL USB clock control 0x198 read-write 0x0 0xFFFFFFFF AP_CLK USB need_clock signal control [0:0] ENUM UNDER_HARDWARE_CONTROL Under hardware control. 0 FORCED_HIGH Forced HIGH. 1 POL_CLK USB need_clock polarity for triggering the USB wake-up interrupt [1:1] ENUM FALLING_EDGE Falling edge of the USB need_clock triggers the USB wake-up (default). 0 RISING_EDGE Rising edge of the USB need_clock triggers the USB wake-up. 1 RESERVED Reserved [31:2] USBCLKST USB clock status 0x19C read-only 0x1 0xFFFFFFFF NEED_CLKST USB need_clock signal status [0:0] ENUM LOW LOW 0 HIGH HIGH 1 RESERVED Reserved [31:1] STARTERP0 Start logic 0 interrupt wake-up enable register 0 0x204 read-write 0 0xFFFFFFFF PINT0 Pin interrupt 0 wake-up [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT1 Pin interrupt 1 wake-up [1:1] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT2 Pin interrupt 2 wake-up [2:2] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT3 Pin interrupt 3 wake-up [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT4 Pin interrupt 4 wake-up [4:4] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT5 Pin interrupt 5 wake-up [5:5] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT6 Pin interrupt 6 wake-up [6:6] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT7 Pin interrupt 7 wake-up [7:7] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [31:8] STARTERP1 Start logic 1 interrupt wake-up enable register 1 0x214 read-write 0 0xFFFFFFFF WWDTINT WWDT interrupt wake-up [12:12] ENUM DISABLED Disabled 0 ENABLED Enabled 1 BODINT Brown Out Detect (BOD) interrupt wake-up [13:13] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [18:14] USB_WAKEUP USB need_clock signal wake-up [19:19] ENUM DISABLED Disabled 0 ENABLED Enabled 1 GPIOINT0 GPIO GROUP0 interrupt wake-up [20:20] ENUM DISABLED Disabled 0 ENABLED Enabled 1 GPIOINT1 GPIO GROUP1 interrupt wake-up [21:21] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PDSLEEPCFG Power-down states in deep-sleep mode 0x230 read-write 0xFFFF 0xFFFFFFFF BOD_PD BOD power-down control for Deep-sleep and Power-down mode [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down control for Deep-sleep and Power-down mode [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [31:7] PDAWAKECFG Power-down states for wake-up from deep-sleep 0x234 read-write 0xEDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output wake-up configuration [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down wake-up configuration [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash wake-up configuration [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD wake-up configuration [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC_PD ADC wake-up configuration [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD Crystal oscillator wake-up configuration [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator wake-up configuration [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL wake-up configuration [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPLL_PD USB PLL wake-up configuration [8:8] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. [9:9] USBPAD_PD USB transceiver wake-up configuration [10:10] ENUM USB_TRANSCEIVER_POWERED USB transceiver powered 0 USB_TRANSCEIVER_POWERED_DOWN USB transceiver powered down 1 RESERVED_11 Reserved. Always write this bit as 1. [11:11] RESERVED_12 Reserved. Always write this bit as 0. [12:12] RESERVED_13_15 Reserved. Always write these bits as 111. [15:13] RESERVED_16_31 Reserved [31:16] PDRUNCFG Power configuration register 0x238 read-write 0xEDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output power-down [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash power-down [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD power-down [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 ADC_PD ADC power-down [4:4] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSOSC_PD Crystal oscillator power-down [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL power-down [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPLL_PD USB PLL power-down [8:8] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write this bit as 0. [9:9] USBPAD_PD USB transceiver power-down configuration [10:10] ENUM USB_TRANSCEIVER_POWEERED USB transceiver powered 0 USB_TRANSCEIVER_POWEERED_DOWN USB transceiver powered down (suspend mode) 1 RESERVED Reserved. Always write this bit as 1. [11:11] RESERVED Reserved. Always write this bit as 0. [12:12] RESERVED Reserved. Always write these bits as 111. [15:13] RESERVED Reserved [31:16] DEVICE_ID Device ID 0x3F4 read-only 0 0x00000000 DEVICEID Device ID numbers for LPC11Uxx parts LPC11U12FHN33/201 = 0x095C 802B/0x295C 802B LPC11U12FBD48/201 = 0x095C 802B/0x295C 802B LPC11U13FBD48/201 = 0x097A 802B/0x297A 802B LPC11U14FHN33/201 = 0x0998 802B/0x2998 802B LPC11U14FHI33/201 = 0x2998 802B LPC11U14FBD48/201 = 0x0998 802B/0x2998 802B LPC11U14FET48/201 = 0x0998 802B/0x2998 802B LPC11U23FBD48/301 = 0x2972 402B LPC11U24FHI33/301 = 0x2988 402B LPC11U24FBD48/301 = 0x2988 402B LPC11U24FET48/301 = 0x2988 402B LPC11U24FHN33/401 = 0x2980 002B LPC11U24FBD48/401 = 0x2980 002B LPC11U24FBD64/401 = 0x2980 002B [31:0] GPIO_PIN_INT GPIO pin interrupt GPIO_PIN_INT 0x4004C000 0 0xFFF registers PIN_INT0 0 PIN_INT1 1 PIN_INT2 2 PIN_INT3 3 PIN_INT4 4 PIN_INT5 5 PIN_INT6 6 PIN_INT7 7 ISEL Pin Interrupt Mode register 0x000 read-write 0 0xFFFFFFFF PMODE0 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [0:0] PMODE1 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [1:1] PMODE2 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [2:2] PMODE3 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [3:3] PMODE4 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [4:4] PMODE5 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [5:5] PMODE6 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [6:6] PMODE7 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [7:7] RESERVED Reserved. [31:8] IENR Pin Interrupt Enable (Rising) register 0x004 read-write 0 0xFFFFFFFF ENRL0 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [0:0] ENRL1 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [1:1] ENRL2 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [2:2] ENRL3 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [3:3] ENRL4 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [4:4] ENRL5 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [5:5] ENRL6 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [6:6] ENRL7 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] SIENR Set Pin Interrupt Enable (Rising) register 0x008 write-only 0 0x00000000 SETENRL0 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [0:0] SETENRL1 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [1:1] SETENRL2 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [2:2] SETENRL3 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [3:3] SETENRL4 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [4:4] SETENRL5 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [5:5] SETENRL6 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [6:6] SETENRL7 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] CIENR Clear Pin Interrupt Enable (Rising) register 0x00C write-only 0 0x00000000 CENRL0 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [0:0] CENRL1 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [1:1] CENRL2 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [2:2] CENRL3 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [3:3] CENRL4 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [4:4] CENRL5 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [5:5] CENRL6 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [6:6] CENRL7 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] IENF Pin Interrupt Enable Falling Edge / Active Level register 0x010 read-write 0 0xFFFFFFFF ENAF0 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [0:0] ENAF1 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [1:1] ENAF2 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [2:2] ENAF3 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [3:3] ENAF4 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [4:4] ENAF5 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [5:5] ENAF6 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [6:6] ENAF7 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [7:7] RESERVED Reserved. [31:8] SIENF Set Pin Interrupt Enable Falling Edge / Active Level register 0x014 write-only 0 0x00000000 SETENAF0 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [0:0] SETENAF1 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [1:1] SETENAF2 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [2:2] SETENAF3 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [3:3] SETENAF4 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [4:4] SETENAF5 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [5:5] SETENAF6 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [6:6] SETENAF7 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [7:7] RESERVED Reserved. [31:8] CIENF Clear Pin Interrupt Enable Falling Edge / Active Level address 0x018 write-only 0 0x00000000 CENAF0 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [0:0] CENAF1 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [1:1] CENAF2 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [2:2] CENAF3 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [3:3] CENAF4 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [4:4] CENAF5 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [5:5] CENAF6 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [6:6] CENAF7 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [7:7] RESERVED Reserved. [31:8] RISE Pin Interrupt Rising Edge register 0x01C read-write 0 0xFFFFFFFF RDET0 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [0:0] RDET1 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [1:1] RDET2 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [2:2] RDET3 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [3:3] RDET4 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [4:4] RDET5 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [5:5] RDET6 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [6:6] RDET7 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [7:7] RESERVED Reserved. [31:8] FALL Pin Interrupt Falling Edge register 0x020 read-write 0 0xFFFFFFFF FDET0 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [0:0] FDET1 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [1:1] FDET2 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [2:2] FDET3 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [3:3] FDET4 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [4:4] FDET5 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [5:5] FDET6 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [6:6] FDET7 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [7:7] RESERVED Reserved. [31:8] IST Pin Interrupt Status register 0x024 read-write 0 0xFFFFFFFF PSTAT0 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [0:0] PSTAT1 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [1:1] PSTAT2 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [2:2] PSTAT3 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [3:3] PSTAT4 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [4:4] PSTAT5 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [5:5] PSTAT6 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [6:6] PSTAT7 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [7:7] RESERVED Reserved. [31:8] SSP1 0x40058000 0 0xFFF registers SSP1 14 GPIO_GROUP_INT0 GPIO group interrupt GPIO_GROUP_INT0 0x4005C000 0 0xFFF registers GINT0 8 CTRL GPIO grouped interrupt control register 0x000 read-write 0 0xFFFFFFFF INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. [0:0] ENUM NO_INTERRUPT_REQUEST No interrupt request is pending. 0 INTERRUPT_REQUEST_IS Interrupt request is active. 1 COMB Combine enabled inputs for group interrupt [1:1] ENUM OR OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 1 TRIG Group interrupt trigger [2:2] ENUM EDGE_TRIGGERED Edge-triggered 0 LEVEL_TRIGGERED Level-triggered 1 RESERVED Reserved [31:3] 2 0x4 0-1 PORT_POL%s GPIO grouped interrupt port 0 polarity register 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF POL_0 Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [0:0] POL_1 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [1:1] POL_2 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [2:2] POL_3 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [3:3] POL_4 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [4:4] POL_5 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [5:5] POL_6 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [6:6] POL_7 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [7:7] POL_8 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [8:8] POL_9 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [9:9] POL_10 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [10:10] POL_11 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [11:11] POL_12 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [12:12] POL_13 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [13:13] POL_14 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [14:14] POL_15 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [15:15] POL_16 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [16:16] POL_17 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [17:17] POL_18 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [18:18] POL_19 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [19:19] POL_20 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [20:20] POL_21 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [21:21] POL_22 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [22:22] POL_23 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [23:23] POL_24 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [24:24] POL_25 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [25:25] POL_26 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [26:26] POL_27 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [27:27] POL_28 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [28:28] POL_29 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [29:29] POL_30 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [30:30] POL_31 Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [31:31] 2 0x4 0-1 PORT_ENA%s GPIO grouped interrupt port 0/1 enable register 0x040 read-write 0 0xFFFFFFFF ENA_0 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [0:0] ENA_1 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [1:1] ENA_2 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [2:2] ENA_3 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [3:3] ENA_4 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [4:4] ENA_5 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [5:5] ENA_6 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [6:6] ENA_7 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [7:7] ENA_8 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [8:8] ENA_9 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [9:9] ENA_10 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [10:10] ENA_11 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [11:11] ENA_12 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [12:12] ENA_13 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [13:13] ENA_14 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [14:14] ENA_15 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [15:15] ENA_16 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [16:16] ENA_17 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [17:17] ENA_18 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [18:18] ENA_19 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [19:19] ENA_20 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [20:20] ENA_21 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [21:21] ENA_22 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [22:22] ENA_23 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [23:23] ENA_24 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [24:24] ENA_25 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [25:25] ENA_26 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [26:26] ENA_27 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [27:27] ENA_28 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [28:28] ENA_29 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [29:29] ENA_30 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [30:30] ENA_31 Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt. [31:31] GPIO_GROUP_INT1 0x40060000 0 0xFFF registers GINT1 9 USB USB2.0 device controller USB 0x40080000 0x0 0xFFF registers USB_IRQ 22 USB_FIQ 23 USBWAKEUP 30 DEVCMDSTAT USB Device Command/Status register 0x000 read-write 0x00000800 0xFFFFFFFF DEV_ADDR USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. [6:0] DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. [7:7] SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. [8:8] PLL_ON Always PLL Clock on: [9:9] ENUM USB_NEEDCLK_FUNCTION USB_NeedClk functional 0 USB_NEEDCLK_ALWAYS_1 USB_NeedClk always 1. Clock will not be stopped in case of suspend. 1 RESERVED Reserved. [10:10] LPM_SUP LPM Supported: [11:11] ENUM NOT_SUPPORTED LPM not supported. 0 SUPPORTED LPM supported. 1 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP [12:12] ENUM ACKNOW Only acknowledged packets generate an interrupt 0 ACKNOW_NAK Both acknowledged and NAKed packets generate interrupts. 1 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP [13:13] ENUM ACKNOW Only acknowledged packets generate an interrupt 0 ACKNOW_NAK Both acknowledged and NAKed packets generate interrupts. 1 INTONNAK_CO Interrupt on NAK for control OUT EP [14:14] ENUM ACKNOW Only acknowledged packets generate an interrupt 0 ACKNOW_NAK Both acknowledged and NAKed packets generate interrupts. 1 INTONNAK_CI Interrupt on NAK for control IN EP [15:15] ENUM ACKNOW Only acknowledged packets generate an interrupt 0 ACKNOW_NAK Both acknowledged and NAKed packets generate interrupts. 1 DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one. [16:16] DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. [17:17] RESERVED Reserved. [18:18] LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. [19:19] LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. [20:20] RESERVED Reserved. [23:21] DCON_C Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. [24:24] DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. [25:25] DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. [26:26] RESERVED Reserved. [27:27] VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. [28:28] RESERVED Reserved. [31:29] INFO USB Info register 0x004 read-write 0 0xFFFFFFFF FRAME_NR Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. [10:0] ERR_CODE The error code which last occurred: [14:11] ENUM NO_ERROR No error 0x0 PID_ENCODING_ERROR PID encoding error 0x1 PID_UNKNOWN PID unknown 0x2 PACKET_UNEXPECTED Packet unexpected 0x3 TOKEN_CRC_ERROR Token CRC error 0x4 DATA_CRC_ERROR Data CRC error 0x5 TIME_OUT Time out 0x6 BABBLE Babble 0x7 TRUNCATED_EOP Truncated EOP 0x8 SENTRECEIVED_NAK Sent/Received NAK 0x9 SENT_STALL Sent Stall 0xA OVERRUN Overrun 0xB SENT_EMPTY_PACKET Sent empty packet 0xC BITSTUFF_ERROR Bitstuff error 0xD SYNC_ERROR Sync error 0xE WRONG_DATA_TOGGLE Wrong data toggle 0xF RESERVED Reserved. [15:15] RESERVED Reserved [31:16] EPLISTSTART USB EP Command/Status List start address 0x008 read-write 0 0xFFFFFFFF RESERVED Reserved [7:0] EP_LIST Start address of the USB EP Command/Status List. [31:8] DATABUFSTART USB Data buffer start address 0x00C read-write 0 0xFFFFFFFF RESERVED Reserved [21:0] DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. [31:22] LPM Link Power Management register 0x010 read-write 0 0xFFFFFFFF HIRD_HW Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token [3:0] HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. [7:4] DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. [8:8] RESERVED Reserved [31:9] EPSKIP USB Endpoint skip 0x014 read-write 0 0xFFFFFFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. [29:0] RESERVED Reserved [31:30] EPINUSE USB Endpoint Buffer in use 0x018 read-write 0 0xFFFFFFFF RESERVED Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint. [1:0] BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. [9:2] RESERVED Reserved [31:10] EPBUFCFG USB Endpoint Buffer Configuration register 0x01C read-write 0 0xFFFFFFFF RESERVED Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint. [1:0] BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. [9:2] RESERVED Reserved [31:10] INTSTAT USB interrupt status register 0x020 read-write 0 0xFFFFFFFF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. [0:0] EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. [1:1] EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. [2:2] EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. [3:3] EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. [4:4] EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. [5:5] EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. [6:6] EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. [7:7] EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. [8:8] EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. [9:9] RESERVED Reserved [29:10] FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. [30:30] DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. [31:31] INTEN USB interrupt enable register 0x024 read-write 0 0xFFFFFFFF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. [9:0] RESERVED Reserved [29:10] FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. [30:30] DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. [31:31] INTSETSTAT USB set interrupt status register 0x028 read-write 0 0xFFFFFFFF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. [9:0] RESERVED Reserved [29:10] FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. [30:30] DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. [31:31] INTROUTING USB interrupt routing register 0x02C read-write 0 0xFFFFFFFF ROUTE_INT9_0 This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit [9:0] RESERVED Reserved [29:10] ROUTE_INT30 This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit [30:30] ROUTE_INT31 This bit can control on which hardware interrupt line the interrupt will be generated: 0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit [31:31] EPTOGGLE USB Endpoint toggle register 0x034 read-only 0 0xFFFFFFFF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. [9:0] RESERVED Reserved [31:10] GPIO_PORT GPIO port GPIO_PORT 0x50000000 0 0xFfFFF registers 32 0x1 0-31 B0%s Byte pin registers port 0; pins PIO0_0 to PIO0_31 0x0000 8 read-write 0 0xFF PBYTE Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit. [0:0] 32 0x1 32-63 B1%s Byte pin registers port 1 0x0020 8 read-write 0 0xFF PBYTE Read: state of the pin P1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit. [0:0] 32 0x4 0-31 W_0%s Word pin registers port 0 0x1000 read-write 0 0xFFFFFFFF PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. [31:0] 32 0x4 32-63 W_1%s Word pin registers port 1 0x1080 read-write 0 0xFFFFFFFF PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. [31:0] 2 0x4 0-1 DIR%s Direction registers port 0/1 0x2000 read-write 0 0xFFFFFFFF DIRP0 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [0:0] DIRP1 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [1:1] DIRP2 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [2:2] DIRP3 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [3:3] DIRP4 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [4:4] DIRP5 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [5:5] DIRP6 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [6:6] DIRP7 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [7:7] DIRP8 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [8:8] DIRP9 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [9:9] DIRP10 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [10:10] DIRP11 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [11:11] DIRP12 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [12:12] DIRP13 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [13:13] DIRP14 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [14:14] DIRP15 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [15:15] DIRP16 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [16:16] DIRP17 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [17:17] DIRP18 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [18:18] DIRP19 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [19:19] DIRP20 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [20:20] DIRP21 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [21:21] DIRP22 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [22:22] DIRP23 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [23:23] DIRP24 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [24:24] DIRP25 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [25:25] DIRP26 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [26:26] DIRP27 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [27:27] DIRP28 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [28:28] DIRP29 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [29:29] DIRP30 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [30:30] DIRP31 Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output. [31:31] 2 0x4 0-1 MASK%s Mask register port 0/1 0x2080 read-write 0 0xFFFFFFFF MASKP0 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [0:0] MASKP1 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [1:1] MASKP2 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [2:2] MASKP3 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [3:3] MASKP4 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [4:4] MASKP5 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [5:5] MASKP6 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [6:6] MASKP7 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [7:7] MASKP8 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [8:8] MASKP9 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [9:9] MASKP10 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [10:10] MASKP11 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [11:11] MASKP12 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [12:12] MASKP13 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [13:13] MASKP14 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [14:14] MASKP15 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [15:15] MASKP16 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [16:16] MASKP17 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [17:17] MASKP18 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [18:18] MASKP19 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [19:19] MASKP20 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [20:20] MASKP21 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [21:21] MASKP22 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [22:22] MASKP23 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [23:23] MASKP24 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [24:24] MASKP25 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [25:25] MASKP26 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [26:26] MASKP27 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [27:27] MASKP28 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [28:28] MASKP29 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [29:29] MASKP30 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [30:30] MASKP31 Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [31:31] 2 0x4 0-1 PIN%s Portpin register port 0 0x2100 read-write 0 0xFFFFFFFF PORT0 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [0:0] PORT1 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [1:1] PORT2 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [2:2] PORT3 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [3:3] PORT4 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [4:4] PORT5 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [5:5] PORT6 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [6:6] PORT7 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [7:7] PORT8 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [8:8] PORT9 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [9:9] PORT10 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [10:10] PORT11 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [11:11] PORT12 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [12:12] PORT13 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [13:13] PORT14 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [14:14] PORT15 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [15:15] PORT16 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [16:16] PORT17 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [17:17] PORT18 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [18:18] PORT19 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [19:19] PORT20 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [20:20] PORT21 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [21:21] PORT22 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [22:22] PORT23 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [23:23] PORT24 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [24:24] PORT25 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [25:25] PORT26 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [26:26] PORT27 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [27:27] PORT28 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [28:28] PORT29 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [29:29] PORT30 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [30:30] PORT31 Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [31:31] 2 0x4 0-1 MPIN%s Masked port register port 0/1 0x2180 read-write 0 0xFFFFFFFF MPORTP0 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [0:0] MPORTP1 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [1:1] MPORTP2 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [2:2] MPORTP3 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [3:3] MPORTP4 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [4:4] MPORTP5 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [5:5] MPORTP6 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [6:6] MPORTP7 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [7:7] MPORTP8 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [8:8] MPORTP9 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [9:9] MPORTP10 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [10:10] MPORTP11 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [11:11] MPORTP12 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [12:12] MPORTP13 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [13:13] MPORTP14 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [14:14] MPORTP15 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [15:15] MPORTP16 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [16:16] MPORTP17 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [17:17] MPORTP18 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [18:18] MPORTP19 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [19:19] MPORTP20 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [20:20] MPORTP21 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [21:21] MPORTP22 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [22:22] MPORTP23 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [23:23] MPORTP24 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [24:24] MPORTP25 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [25:25] MPORTP26 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [26:26] MPORTP27 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [27:27] MPORTP28 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [28:28] MPORTP29 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [29:29] MPORTP30 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [30:30] MPORTP31 Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [31:31] 2 0x4 0-1 SET%s Write: Set register for port 0/1 Read: output bits for port 0/1 0x2200 read-write 0 0xFFFFFFFF SETP0 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [0:0] SETP1 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [1:1] SETP2 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [2:2] SETP3 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [3:3] SETP4 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [4:4] SETP5 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [5:5] SETP6 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [6:6] SETP7 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [7:7] SETP8 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [8:8] SETP9 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [9:9] SETP10 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [10:10] SETP11 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [11:11] SETP12 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [12:12] SETP13 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [13:13] SETP14 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [14:14] SETP15 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [15:15] SETP16 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [16:16] SETP17 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [17:17] SETP18 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [18:18] SETP19 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [19:19] SETP20 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [20:20] SETP21 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [21:21] SETP22 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [22:22] SETP23 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [23:23] SETP24 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [24:24] SETP25 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [25:25] SETP26 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [26:26] SETP27 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [27:27] SETP28 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [28:28] SETP29 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [29:29] SETP30 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [30:30] SETP31 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [31:31] 2 0x4 0-1 CLR%s Clear port 0/1 0x2280 write-only 0 0x00000000 CLRP00 Clear output bits: 0 = No operation. 1 = Clear output bit. [0:0] CLRP01 Clear output bits: 0 = No operation. 1 = Clear output bit. [1:1] CLRP02 Clear output bits: 0 = No operation. 1 = Clear output bit. [2:2] CLRP03 Clear output bits: 0 = No operation. 1 = Clear output bit. [3:3] CLRP04 Clear output bits: 0 = No operation. 1 = Clear output bit. [4:4] CLRP05 Clear output bits: 0 = No operation. 1 = Clear output bit. [5:5] CLRP06 Clear output bits: 0 = No operation. 1 = Clear output bit. [6:6] CLRP07 Clear output bits: 0 = No operation. 1 = Clear output bit. [7:7] CLRP08 Clear output bits: 0 = No operation. 1 = Clear output bit. [8:8] CLRP09 Clear output bits: 0 = No operation. 1 = Clear output bit. [9:9] CLRP010 Clear output bits: 0 = No operation. 1 = Clear output bit. [10:10] CLRP011 Clear output bits: 0 = No operation. 1 = Clear output bit. [11:11] CLRP012 Clear output bits: 0 = No operation. 1 = Clear output bit. [12:12] CLRP013 Clear output bits: 0 = No operation. 1 = Clear output bit. [13:13] CLRP014 Clear output bits: 0 = No operation. 1 = Clear output bit. [14:14] CLRP015 Clear output bits: 0 = No operation. 1 = Clear output bit. [15:15] CLRP016 Clear output bits: 0 = No operation. 1 = Clear output bit. [16:16] CLRP017 Clear output bits: 0 = No operation. 1 = Clear output bit. [17:17] CLRP018 Clear output bits: 0 = No operation. 1 = Clear output bit. [18:18] CLRP019 Clear output bits: 0 = No operation. 1 = Clear output bit. [19:19] CLRP020 Clear output bits: 0 = No operation. 1 = Clear output bit. [20:20] CLRP021 Clear output bits: 0 = No operation. 1 = Clear output bit. [21:21] CLRP022 Clear output bits: 0 = No operation. 1 = Clear output bit. [22:22] CLRP023 Clear output bits: 0 = No operation. 1 = Clear output bit. [23:23] CLRP024 Clear output bits: 0 = No operation. 1 = Clear output bit. [24:24] CLRP025 Clear output bits: 0 = No operation. 1 = Clear output bit. [25:25] CLRP026 Clear output bits: 0 = No operation. 1 = Clear output bit. [26:26] CLRP027 Clear output bits: 0 = No operation. 1 = Clear output bit. [27:27] CLRP028 Clear output bits: 0 = No operation. 1 = Clear output bit. [28:28] CLRP029 Clear output bits: 0 = No operation. 1 = Clear output bit. [29:29] CLRP030 Clear output bits: 0 = No operation. 1 = Clear output bit. [30:30] CLRP031 Clear output bits: 0 = No operation. 1 = Clear output bit. [31:31] 2 0x4 0-1 NOT%s Toggle port 0/1 0x2300 write-only 0 0x00000000 NOTP0 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [0:0] NOTP1 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [1:1] NOTP2 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [2:2] NOTP3 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [3:3] NOTP4 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [4:4] NOTP5 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [5:5] NOTP6 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [6:6] NOTP7 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [7:7] NOTP8 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [8:8] NOTP9 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [9:9] NOTP10 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [10:10] NOTP11 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [11:11] NOTP12 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [12:12] NOTP13 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [13:13] NOTP14 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [14:14] NOTP15 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [15:15] NOTP16 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [16:16] NOTP17 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [17:17] NOTP18 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [18:18] NOTP19 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [19:19] NOTP20 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [20:20] NOTP21 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [21:21] NOTP22 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [22:22] NOTP23 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [23:23] NOTP24 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [24:24] NOTP25 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [25:25] NOTP26 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [26:26] NOTP27 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [27:27] NOTP28 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [28:28] NOTP29 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [29:29] NOTP30 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [30:30] NOTP31 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [31:31]