nxp.com LPC55S69_cm33_core0 1.0 LPC55S69JBD100,LPC55S69JBD64,LPC55S69JEV98 Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause CM33 r2p0 little true true true 3 false 8 32 FLASH_CFPA0 FLASH_CFPA FLASH_CFPA FLASH_CFPA 0x9E000 0 0x200 registers HEADER . 0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write VERSION . 0x4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write S_FW_Version Secure firmware version (Monotonic counter) 0x8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write NS_FW_Version Non-Secure firmware version (Monotonic counter) 0xC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write IMAGE_KEY_REVOKE Image key revocation ID (Monotonic counter) 0x10 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write ROTKH_REVOKE . 0x18 32 read-write 0 0xFFFFFFFF RoTK0_EN RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked 0 2 read-write RoTK1_EN RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked 2 2 read-write RoTK2_EN RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked 4 2 read-write VENDOR_USAGE . 0x1C 32 read-write 0 0xFFFFFFFF DBG_VENDOR_USAGE DBG_VENDOR_USAGE. 0 16 read-write INVERSE_VALUE inverse value of bits [15:0] 16 16 read-write DCFG_CC_SOCU_PIN With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. 0x20 32 read-write 0 0xFFFFFFFF NIDEN Non Secure non-invasive debug enable 0 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 DBGEN Non Secure debug enable 1 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 SPNIDEN Secure non-invasive debug enable 2 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 SPIDEN Secure invasive debug enable 3 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 TAPEN JTAG TAP enable 4 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 CPU1_DBGEN CPU1 (Micro cortex M33) invasive debug enable 5 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 ISP_CMD_EN ISP Boot Command enable 6 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 FA_CMD_EN FA Command enable 7 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 ME_CMD_EN Flash Mass Erase Command enable 8 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 CPU1_NIDEN CPU1 (Micro cortex M33) non-invasive debug enable 9 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 UUID_CHECK Enforce UUID match during Debug authentication. 15 1 read-write INVERSE_VALUE inverse value of bits [15:0] 16 16 read-write DCFG_CC_SOCU_DFLT With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. 0x24 32 read-write 0 0xFFFFFFFF NIDEN Non Secure non-invasive debug fixed state 0 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 DBGEN Non Secure debug fixed state 1 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 SPNIDEN Secure non-invasive debug fixed state 2 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 SPIDEN Secure invasive debug fixed state 3 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 TAPEN JTAG TAP fixed state 4 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 CPU1_DBGEN CPU1 (Micro cortex M33) invasive debug fixed state 5 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 ISP_CMD_EN ISP Boot Command fixed state 6 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 FA_CMD_EN FA Command fixed state 7 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 ME_CMD_EN Flash Mass Erase Command fixed state 8 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 CPU1_NIDEN CPU1 (Micro cortex M33) non-invasive debug fixed state 9 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 INVERSE_VALUE inverse value of bits [15:0] 16 16 read-write ENABLE_FA_MODE Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. 0x28 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write CMPA_PROG_IN_PROGRESS CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. 0x2C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE0 . PRINCE_REGION0_IV_CODE 0x30 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_HEADER0 . PRINCE_REGION0_IV_CODE 0x30 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE1 . PRINCE_REGION0_IV_CODE 0x34 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_HEADER1 . PRINCE_REGION0_IV_CODE 0x34 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write PRINCE_REGION0_IV_BODY0 . PRINCE_REGION0_IV_CODE 0x38 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE2 . PRINCE_REGION0_IV_CODE 0x38 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY1 . PRINCE_REGION0_IV_CODE 0x3C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE3 . PRINCE_REGION0_IV_CODE 0x3C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY2 . PRINCE_REGION0_IV_CODE 0x40 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE4 . PRINCE_REGION0_IV_CODE 0x40 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY3 . PRINCE_REGION0_IV_CODE 0x44 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE5 . PRINCE_REGION0_IV_CODE 0x44 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY4 . PRINCE_REGION0_IV_CODE 0x48 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE6 . PRINCE_REGION0_IV_CODE 0x48 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY5 . PRINCE_REGION0_IV_CODE 0x4C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE7 . PRINCE_REGION0_IV_CODE 0x4C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY6 . PRINCE_REGION0_IV_CODE 0x50 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE8 . PRINCE_REGION0_IV_CODE 0x50 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY7 . PRINCE_REGION0_IV_CODE 0x54 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE9 . PRINCE_REGION0_IV_CODE 0x54 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY8 . PRINCE_REGION0_IV_CODE 0x58 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE10 . PRINCE_REGION0_IV_CODE 0x58 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY9 . PRINCE_REGION0_IV_CODE 0x5C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE11 . PRINCE_REGION0_IV_CODE 0x5C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY10 . PRINCE_REGION0_IV_CODE 0x60 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE12 . PRINCE_REGION0_IV_CODE 0x60 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_BODY11 . PRINCE_REGION0_IV_CODE 0x64 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_IV_CODE13 . PRINCE_REGION0_IV_CODE 0x64 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE0 . PRINCE_REGION1_IV_CODE 0x68 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_HEADER0 . PRINCE_REGION1_IV_CODE 0x68 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE1 . PRINCE_REGION1_IV_CODE 0x6C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_HEADER1 . PRINCE_REGION1_IV_CODE 0x6C 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write PRINCE_REGION1_IV_BODY0 . PRINCE_REGION1_IV_CODE 0x70 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE2 . PRINCE_REGION1_IV_CODE 0x70 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY1 . PRINCE_REGION1_IV_CODE 0x74 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE3 . PRINCE_REGION1_IV_CODE 0x74 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY2 . PRINCE_REGION1_IV_CODE 0x78 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE4 . PRINCE_REGION1_IV_CODE 0x78 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY3 . PRINCE_REGION1_IV_CODE 0x7C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE5 . PRINCE_REGION1_IV_CODE 0x7C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY4 . PRINCE_REGION1_IV_CODE 0x80 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE6 . PRINCE_REGION1_IV_CODE 0x80 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY5 . PRINCE_REGION1_IV_CODE 0x84 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE7 . PRINCE_REGION1_IV_CODE 0x84 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY6 . PRINCE_REGION1_IV_CODE 0x88 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE8 . PRINCE_REGION1_IV_CODE 0x88 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY7 . PRINCE_REGION1_IV_CODE 0x8C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE9 . PRINCE_REGION1_IV_CODE 0x8C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY8 . PRINCE_REGION1_IV_CODE 0x90 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE10 . PRINCE_REGION1_IV_CODE 0x90 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY9 . PRINCE_REGION1_IV_CODE 0x94 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE11 . PRINCE_REGION1_IV_CODE 0x94 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY10 . PRINCE_REGION1_IV_CODE 0x98 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE12 . PRINCE_REGION1_IV_CODE 0x98 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_BODY11 . PRINCE_REGION1_IV_CODE 0x9C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_IV_CODE13 . PRINCE_REGION1_IV_CODE 0x9C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE0 . PRINCE_REGION2_IV_CODE 0xA0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_HEADER0 . PRINCE_REGION2_IV_CODE 0xA0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE1 . PRINCE_REGION2_IV_CODE 0xA4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_HEADER1 . PRINCE_REGION2_IV_CODE 0xA4 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write PRINCE_REGION2_IV_BODY0 . PRINCE_REGION2_IV_CODE 0xA8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE2 . PRINCE_REGION2_IV_CODE 0xA8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY1 . PRINCE_REGION2_IV_CODE 0xAC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE3 . PRINCE_REGION2_IV_CODE 0xAC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY2 . PRINCE_REGION2_IV_CODE 0xB0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE4 . PRINCE_REGION2_IV_CODE 0xB0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY3 . PRINCE_REGION2_IV_CODE 0xB4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE5 . PRINCE_REGION2_IV_CODE 0xB4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY4 . PRINCE_REGION2_IV_CODE 0xB8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE6 . PRINCE_REGION2_IV_CODE 0xB8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY5 . PRINCE_REGION2_IV_CODE 0xBC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE7 . PRINCE_REGION2_IV_CODE 0xBC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY6 . PRINCE_REGION2_IV_CODE 0xC0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE8 . PRINCE_REGION2_IV_CODE 0xC0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY7 . PRINCE_REGION2_IV_CODE 0xC4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE9 . PRINCE_REGION2_IV_CODE 0xC4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY8 . PRINCE_REGION2_IV_CODE 0xC8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE10 . PRINCE_REGION2_IV_CODE 0xC8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY9 . PRINCE_REGION2_IV_CODE 0xCC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE11 . PRINCE_REGION2_IV_CODE 0xCC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY10 . PRINCE_REGION2_IV_CODE 0xD0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE12 . PRINCE_REGION2_IV_CODE 0xD0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_BODY11 . PRINCE_REGION2_IV_CODE 0xD4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_IV_CODE13 . PRINCE_REGION2_IV_CODE 0xD4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write 56 0x4 CUSTOMER_DEFINED[%s] Customer Defined (Programable through ROM API) 0x100 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write 8 0x4 SHA256_DIGEST[%s] SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] 0x1E0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write FLASH_CFPA_SCRATCH FLASH_CFPA FLASH_CFPA 0x9DE00 0 0x200 registers FLASH_CFPA1 FLASH_CFPA FLASH_CFPA 0x9E200 0 0x200 registers FLASH_CMPA FLASH_CMPA FLASH_CMPA 0x9E400 0 0x200 registers BOOT_CFG . 0 32 read-write 0 0xFFFFFFFF DEFAULT_ISP_MODE Default ISP mode: 4 3 read-write VALUE_0 Auto ISP 0 VALUE_1 USB_HID_MSC 0x1 VALUE_2 SPI Slave ISP 0x2 VALUE_3 I2C Slave ISP 0x3 VALUE_7 Disable ISP fall through 0x7 BOOT_SPEED Core clock: 7 2 read-write VALUE_0 Defined by NMPA.SYSTEM_SPEED_CODE 0 VALUE_1 48MHz FRO 0x1 VALUE_2 96MHz FRO 0x2 BOOT_FAILURE_PIN GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin 24 8 read-write SPI_FLASH_CFG . 0x4 32 read-write 0 0xFFFFFFFF SPI_RECOVERY_BOOT_EN SPI flash recovery boot is enabled, if non-zero value is written to this field. 0 5 read-write USB_ID . 0x8 32 read-write 0 0xFFFFFFFF USB_VENDOR_ID . 0 16 read-write USB_PRODUCT_ID . 16 16 read-write SDIO_CFG . 0xC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write CC_SOCU_PIN . 0x10 32 read-write 0 0xFFFFFFFF NIDEN Non Secure non-invasive debug enable 0 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 DBGEN Non Secure debug enable 1 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 SPNIDEN Secure non-invasive debug enable 2 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 SPIDEN Secure invasive debug enable 3 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 TAPEN JTAG TAP enable 4 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 CPU1_DBGEN CPU1 (Micro cortex M33) invasive debug enable 5 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 ISP_CMD_EN ISP Boot Command enable 6 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 FA_CMD_EN FA Command enable 7 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 ME_CMD_EN Flash Mass Erase Command enable 8 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 CPU1_NIDEN CPU1 (Micro cortex M33) non-invasive debug enable 9 1 read-write VALUE_0 Use DAP to enable 0 VALUE_1 Fixed state 0x1 UUID_CHECK Enforce UUID match during Debug authentication. 15 1 read-write INVERSE_VALUE inverse value of bits [15:0] 16 16 read-write CC_SOCU_DFLT . 0x14 32 read-write 0 0xFFFFFFFF NIDEN Non Secure non-invasive debug fixed state 0 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 DBGEN Non Secure debug fixed state 1 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 SPNIDEN Secure non-invasive debug fixed state 2 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 SPIDEN Secure invasive debug fixed state 3 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 TAPEN JTAG TAP fixed state 4 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 CPU1_DBGEN CPU1 (Micro cortex M33) invasive debug fixed state 5 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 ISP_CMD_EN ISP Boot Command fixed state 6 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 FA_CMD_EN FA Command fixed state 7 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 ME_CMD_EN Flash Mass Erase Command fixed state 8 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 CPU1_NIDEN CPU1 (Micro cortex M33) non-invasive debug fixed state 9 1 read-write DISABLE Disable 0 ENABLE Enable 0x1 INVERSE_VALUE inverse value of bits [15:0] 16 16 read-write VENDOR_USAGE . 0x18 32 read-write 0 0xFFFFFFFF VENDOR_USAGE Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. 16 16 read-write SECURE_BOOT_CFG . 0x1C 32 read-write 0 0xFFFFFFFF RSA4K Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys 0 2 read-write DICE_ENC_NXP_CFG Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included 2 2 read-write DICE_CUST_CFG Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included 4 2 read-write SKIP_DICE Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE 6 2 read-write TZM_IMAGE_TYPE TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. 8 2 read-write BLOCK_SET_KEY Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation 10 2 read-write BLOCK_ENROLL Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet 12 2 read-write DICE_INC_SEC_EPOCH Include security EPOCH in DICE 14 2 read-write SEC_BOOT_EN Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, 11 - Boot signed images. (internal flash, RSA signed) 30 2 read-write PRINCE_BASE_ADDR . 0x20 32 read-write 0 0xFFFFFFFF ADDR0_PRG Programmable portion of the base address of region 0. 0 4 read-write ADDR1_PRG Programmable portion of the base address of region 1. 4 4 read-write ADDR2_PRG Programmable portion of the base address of region 2. 8 4 read-write LOCK_REG0 Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. 16 2 read-write LOCK_REG1 Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. 18 2 read-write LOCK_REG2 Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. 20 2 read-write REG0_ERASE_CHECK_EN For PRINCE region0 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. 24 2 read-write REG1_ERASE_CHECK_EN For PRINCE region1 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. 26 2 read-write REG2_ERASE_CHECK_EN For PRINCE region2 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. 28 2 read-write PRINCE_SR_0 Region 0, sub-region enable 0x24 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_SR_1 Region 1, sub-region enable 0x28 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_SR_2 Region 2, sub-region enable 0x2C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write XTAL_32KHZ_CAPABANK_TRIM Xtal 32kHz capabank triming. 0x30 32 read-write 0 0xFFFFFFFF TRIM_VALID 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid. 0 1 read-write XTAL_LOAD_CAP_IEC_PF_X100 Load capacitance, pF x 100. For example, 6pF becomes 600. 1 10 read-write PCB_XIN_PARA_CAP_PF_X100 PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. 11 10 read-write PCB_XOUT_PARA_CAP_PF_X100 PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. 21 10 read-write XTAL_16MHZ_CAPABANK_TRIM Xtal 16MHz capabank triming. 0x34 32 read-write 0 0xFFFFFFFF TRIM_VALID 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid. 0 1 read-write XTAL_LOAD_CAP_IEC_PF_X100 Load capacitance, pF x 100. For example, 6pF becomes 600. 1 10 read-write PCB_XIN_PARA_CAP_PF_X100 PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. 11 10 read-write PCB_XOUT_PARA_CAP_PF_X100 PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. 21 10 read-write 8 0x4 ROTKH[%s] ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] 0x50 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write 56 0x4 CUSTOMER_DEFINED[%s] Customer Defined (Programable through ROM API) 0x100 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write 8 0x4 SHA256_DIGEST[%s] SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] 0x1E0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write FLASH_KEY_STORE FLASH_KEY_STORE FLASH_KEY_STORE 0x9E600 0 0x600 registers HEADER Valid Key Sore Header : 0x95959595 0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write puf_discharge_time_in_ms puf discharge time in ms. 0x4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write 298 0x4 ACTIVATION_CODE[%s] . 0x8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_HEADER0 . SBKEY_KEY_CODE 0x4B0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE0 . SBKEY_KEY_CODE 0x4B0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_HEADER1 . SBKEY_KEY_CODE 0x4B4 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write SBKEY_KEY_CODE1 . SBKEY_KEY_CODE 0x4B4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY0 . SBKEY_KEY_CODE 0x4B8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE2 . SBKEY_KEY_CODE 0x4B8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY1 . SBKEY_KEY_CODE 0x4BC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE3 . SBKEY_KEY_CODE 0x4BC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY2 . SBKEY_KEY_CODE 0x4C0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE4 . SBKEY_KEY_CODE 0x4C0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY3 . SBKEY_KEY_CODE 0x4C4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE5 . SBKEY_KEY_CODE 0x4C4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY4 . SBKEY_KEY_CODE 0x4C8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE6 . SBKEY_KEY_CODE 0x4C8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY5 . SBKEY_KEY_CODE 0x4CC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE7 . SBKEY_KEY_CODE 0x4CC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY6 . SBKEY_KEY_CODE 0x4D0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE8 . SBKEY_KEY_CODE 0x4D0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY7 . SBKEY_KEY_CODE 0x4D4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE9 . SBKEY_KEY_CODE 0x4D4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY8 . SBKEY_KEY_CODE 0x4D8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE10 . SBKEY_KEY_CODE 0x4D8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY9 . SBKEY_KEY_CODE 0x4DC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE11 . SBKEY_KEY_CODE 0x4DC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY10 . SBKEY_KEY_CODE 0x4E0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE12 . SBKEY_KEY_CODE 0x4E0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_BODY11 . SBKEY_KEY_CODE 0x4E4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SBKEY_KEY_CODE13 . SBKEY_KEY_CODE 0x4E4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_HEADER0 . USER_KEK_KEY_CODE 0x4E8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE0 . USER_KEK_KEY_CODE 0x4E8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_HEADER1 . USER_KEK_KEY_CODE 0x4EC 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write USER_KEK_KEY_CODE1 . USER_KEK_KEY_CODE 0x4EC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY0 . USER_KEK_KEY_CODE 0x4F0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE2 . USER_KEK_KEY_CODE 0x4F0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY1 . USER_KEK_KEY_CODE 0x4F4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE3 . USER_KEK_KEY_CODE 0x4F4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY2 . USER_KEK_KEY_CODE 0x4F8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE4 . USER_KEK_KEY_CODE 0x4F8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY3 . USER_KEK_KEY_CODE 0x4FC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE5 . USER_KEK_KEY_CODE 0x4FC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY4 . USER_KEK_KEY_CODE 0x500 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE6 . USER_KEK_KEY_CODE 0x500 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY5 . USER_KEK_KEY_CODE 0x504 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE7 . USER_KEK_KEY_CODE 0x504 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY6 . USER_KEK_KEY_CODE 0x508 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE8 . USER_KEK_KEY_CODE 0x508 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY7 . USER_KEK_KEY_CODE 0x50C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE9 . USER_KEK_KEY_CODE 0x50C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY8 . USER_KEK_KEY_CODE 0x510 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE10 . USER_KEK_KEY_CODE 0x510 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY9 . USER_KEK_KEY_CODE 0x514 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE11 . USER_KEK_KEY_CODE 0x514 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY10 . USER_KEK_KEY_CODE 0x518 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE12 . USER_KEK_KEY_CODE 0x518 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_BODY11 . USER_KEK_KEY_CODE 0x51C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write USER_KEK_KEY_CODE13 . USER_KEK_KEY_CODE 0x51C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_HEADER0 . UDS_KEY_CODE 0x520 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE0 . UDS_KEY_CODE 0x520 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_HEADER1 . UDS_KEY_CODE 0x524 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write UDS_KEY_CODE1 . UDS_KEY_CODE 0x524 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY0 . UDS_KEY_CODE 0x528 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE2 . UDS_KEY_CODE 0x528 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY1 . UDS_KEY_CODE 0x52C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE3 . UDS_KEY_CODE 0x52C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY2 . UDS_KEY_CODE 0x530 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE4 . UDS_KEY_CODE 0x530 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY3 . UDS_KEY_CODE 0x534 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE5 . UDS_KEY_CODE 0x534 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY4 . UDS_KEY_CODE 0x538 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE6 . UDS_KEY_CODE 0x538 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY5 . UDS_KEY_CODE 0x53C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE7 . UDS_KEY_CODE 0x53C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY6 . UDS_KEY_CODE 0x540 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE8 . UDS_KEY_CODE 0x540 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY7 . UDS_KEY_CODE 0x544 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE9 . UDS_KEY_CODE 0x544 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY8 . UDS_KEY_CODE 0x548 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE10 . UDS_KEY_CODE 0x548 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY9 . UDS_KEY_CODE 0x54C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE11 . UDS_KEY_CODE 0x54C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY10 . UDS_KEY_CODE 0x550 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE12 . UDS_KEY_CODE 0x550 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_BODY11 . UDS_KEY_CODE 0x554 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write UDS_KEY_CODE13 . UDS_KEY_CODE 0x554 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_HEADER0 . PRINCE_REGION0_KEY_CODE 0x558 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE0 . PRINCE_REGION0_KEY_CODE 0x558 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_HEADER1 . PRINCE_REGION0_KEY_CODE 0x55C 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write PRINCE_REGION0_KEY_CODE1 . PRINCE_REGION0_KEY_CODE 0x55C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY0 . PRINCE_REGION0_KEY_CODE 0x560 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE2 . PRINCE_REGION0_KEY_CODE 0x560 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY1 . PRINCE_REGION0_KEY_CODE 0x564 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE3 . PRINCE_REGION0_KEY_CODE 0x564 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY2 . PRINCE_REGION0_KEY_CODE 0x568 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE4 . PRINCE_REGION0_KEY_CODE 0x568 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY3 . PRINCE_REGION0_KEY_CODE 0x56C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE5 . PRINCE_REGION0_KEY_CODE 0x56C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY4 . PRINCE_REGION0_KEY_CODE 0x570 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE6 . PRINCE_REGION0_KEY_CODE 0x570 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY5 . PRINCE_REGION0_KEY_CODE 0x574 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE7 . PRINCE_REGION0_KEY_CODE 0x574 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY6 . PRINCE_REGION0_KEY_CODE 0x578 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE8 . PRINCE_REGION0_KEY_CODE 0x578 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY7 . PRINCE_REGION0_KEY_CODE 0x57C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE9 . PRINCE_REGION0_KEY_CODE 0x57C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY8 . PRINCE_REGION0_KEY_CODE 0x580 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE10 . PRINCE_REGION0_KEY_CODE 0x580 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY9 . PRINCE_REGION0_KEY_CODE 0x584 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE11 . PRINCE_REGION0_KEY_CODE 0x584 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY10 . PRINCE_REGION0_KEY_CODE 0x588 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE12 . PRINCE_REGION0_KEY_CODE 0x588 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_BODY11 . PRINCE_REGION0_KEY_CODE 0x58C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION0_KEY_CODE13 . PRINCE_REGION0_KEY_CODE 0x58C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_HEADER0 . PRINCE_REGION1_KEY_CODE 0x590 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE0 . PRINCE_REGION1_KEY_CODE 0x590 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_HEADER1 . PRINCE_REGION1_KEY_CODE 0x594 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write PRINCE_REGION1_KEY_CODE1 . PRINCE_REGION1_KEY_CODE 0x594 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY0 . PRINCE_REGION1_KEY_CODE 0x598 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE2 . PRINCE_REGION1_KEY_CODE 0x598 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY1 . PRINCE_REGION1_KEY_CODE 0x59C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE3 . PRINCE_REGION1_KEY_CODE 0x59C 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY2 . PRINCE_REGION1_KEY_CODE 0x5A0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE4 . PRINCE_REGION1_KEY_CODE 0x5A0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY3 . PRINCE_REGION1_KEY_CODE 0x5A4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE5 . PRINCE_REGION1_KEY_CODE 0x5A4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY4 . PRINCE_REGION1_KEY_CODE 0x5A8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE6 . PRINCE_REGION1_KEY_CODE 0x5A8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY5 . PRINCE_REGION1_KEY_CODE 0x5AC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE7 . PRINCE_REGION1_KEY_CODE 0x5AC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY6 . PRINCE_REGION1_KEY_CODE 0x5B0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE8 . PRINCE_REGION1_KEY_CODE 0x5B0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY7 . PRINCE_REGION1_KEY_CODE 0x5B4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE9 . PRINCE_REGION1_KEY_CODE 0x5B4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY8 . PRINCE_REGION1_KEY_CODE 0x5B8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE10 . PRINCE_REGION1_KEY_CODE 0x5B8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY9 . PRINCE_REGION1_KEY_CODE 0x5BC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE11 . PRINCE_REGION1_KEY_CODE 0x5BC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY10 . PRINCE_REGION1_KEY_CODE 0x5C0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE12 . PRINCE_REGION1_KEY_CODE 0x5C0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_BODY11 . PRINCE_REGION1_KEY_CODE 0x5C4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION1_KEY_CODE13 . PRINCE_REGION1_KEY_CODE 0x5C4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_HEADER0 . PRINCE_REGION2_KEY_CODE 0x5C8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE0 . PRINCE_REGION2_KEY_CODE 0x5C8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_HEADER1 . PRINCE_REGION2_KEY_CODE 0x5CC 32 read-write 0 0xFFFFFFFF TYPE . 0 2 read-write INDEX . 8 4 read-write SIZE . 24 6 read-write PRINCE_REGION2_KEY_CODE1 . PRINCE_REGION2_KEY_CODE 0x5CC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY0 . PRINCE_REGION2_KEY_CODE 0x5D0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE2 . PRINCE_REGION2_KEY_CODE 0x5D0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY1 . PRINCE_REGION2_KEY_CODE 0x5D4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE3 . PRINCE_REGION2_KEY_CODE 0x5D4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY2 . PRINCE_REGION2_KEY_CODE 0x5D8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE4 . PRINCE_REGION2_KEY_CODE 0x5D8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY3 . PRINCE_REGION2_KEY_CODE 0x5DC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE5 . PRINCE_REGION2_KEY_CODE 0x5DC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY4 . PRINCE_REGION2_KEY_CODE 0x5E0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE6 . PRINCE_REGION2_KEY_CODE 0x5E0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY5 . PRINCE_REGION2_KEY_CODE 0x5E4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE7 . PRINCE_REGION2_KEY_CODE 0x5E4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY6 . PRINCE_REGION2_KEY_CODE 0x5E8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE8 . PRINCE_REGION2_KEY_CODE 0x5E8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY7 . PRINCE_REGION2_KEY_CODE 0x5EC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE9 . PRINCE_REGION2_KEY_CODE 0x5EC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY8 . PRINCE_REGION2_KEY_CODE 0x5F0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE10 . PRINCE_REGION2_KEY_CODE 0x5F0 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY9 . PRINCE_REGION2_KEY_CODE 0x5F4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE11 . PRINCE_REGION2_KEY_CODE 0x5F4 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY10 . PRINCE_REGION2_KEY_CODE 0x5F8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE12 . PRINCE_REGION2_KEY_CODE 0x5F8 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_BODY11 . PRINCE_REGION2_KEY_CODE 0x5FC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write PRINCE_REGION2_KEY_CODE13 . PRINCE_REGION2_KEY_CODE 0x5FC 32 read-write 0 0xFFFFFFFF FIELD . 0 32 read-write SYSCON SYSCON SYSCON 0x40000000 0 0x1000 registers MEMORYREMAP Memory Remap control register 0 32 read-write 0 0x3 MAP Select the location of the vector table :. 0 2 read-write ROM0 Vector Table in ROM. 0 RAM1 Vector Table in RAM. 0x1 FLASH0 Vector Table in Flash. 0x2 FLASH1 Vector Table in Flash. 0x3 AHBMATPRIO AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest 0x10 32 read-write 0 0x3FFFFFF PRI_CPU0_CBUS CPU0 C-AHB bus. 0 2 read-write PRI_CPU0_SBUS CPU0 S-AHB bus. 2 2 read-write PRI_CPU1_CBUS CPU1 C-AHB bus. 4 2 read-write PRI_CPU1_SBUS CPU1 S-AHB bus. 6 2 read-write PRI_USB_FS USB-FS.(USB0) 8 2 read-write PRI_SDMA0 DMA0 controller priority. 10 2 read-write PRI_SDIO SDIO. 16 2 read-write PRI_PQ PQ (HW Accelerator). 18 2 read-write PRI_HASH_AES HASH_AES. 20 2 read-write PRI_USB_HS USB-HS.(USB1) 22 2 read-write PRI_SDMA1 DMA1 controller priority. 24 2 read-write CPU0STCKCAL System tick calibration for secure part of CPU0 0x38 32 read-write 0 0x3FFFFFF TENMS Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW Initial value for the Systick timer. 24 1 read-write NOREF Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. 25 1 read-write CPU0NSTCKCAL System tick calibration for non-secure part of CPU0 0x3C 32 read-write 0 0x3FFFFFF TENMS Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. 24 1 read-write NOREF Initial value for the Systick timer. 25 1 read-write CPU1STCKCAL System tick calibration for CPU1 0x40 32 read-write 0 0x3FFFFFF TENMS Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. 24 1 read-write NOREF Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. 25 1 read-write NMISRC NMI Source Select 0x48 32 read-write 0 0xC0003F3F IRQCPU0 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. 0 6 read-write IRQCPU1 The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. 8 6 read-write NMIENCPU1 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. 30 1 read-write NMIENCPU0 Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. 31 1 read-write PRESETCTRL0 Peripheral reset control 0 PRESETCTRL 0x100 32 read-write 0 0xCFFE9FA ROM_RST ROM reset control. 1 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SRAM_CTRL1_RST SRAM Controller 1 reset control. 3 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SRAM_CTRL2_RST SRAM Controller 2 reset control. 4 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SRAM_CTRL3_RST SRAM Controller 3 reset control. 5 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SRAM_CTRL4_RST SRAM Controller 4 reset control. 6 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FLASH_RST Flash controller reset control. 7 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FMC_RST FMC controller reset control. 8 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 MUX_RST Input Mux reset control. 11 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 IOCON_RST I/O controller reset control. 13 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GPIO0_RST GPIO0 reset control. 14 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GPIO1_RST GPIO1 reset control. 15 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GPIO2_RST GPIO2 reset control. 16 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GPIO3_RST GPIO3 reset control. 17 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 PINT_RST Pin interrupt (PINT) reset control. 18 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GINT_RST Group interrupt (GINT) reset control. 19 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 DMA0_RST DMA0 reset control. 20 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 CRCGEN_RST CRCGEN reset control. 21 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 WWDT_RST Watchdog Timer reset control. 22 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 RTC_RST Real Time Clock (RTC) reset control. 23 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 MAILBOX_RST Inter CPU communication Mailbox reset control. 26 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 ADC_RST ADC reset control. 27 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 PRESETCTRL1 Peripheral reset control 1 PRESETCTRL 0x104 32 read-write 0 0xDE57FC47 MRT_RST MRT reset control. 0 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 OSTIMER_RST OS Event Timer reset control. 1 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SCT_RST SCT reset control. 2 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SCTIPU_RST SCTIPU reset control. 6 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 UTICK_RST UTICK reset control. 10 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC0_RST FC0 reset control. 11 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC1_RST FC1 reset control. 12 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC2_RST FC2 reset control. 13 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC3_RST FC3 reset control. 14 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC4_RST FC4 reset control. 15 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC5_RST FC5 reset control. 16 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC6_RST FC6 reset control. 17 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FC7_RST FC7 reset control. 18 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 TIMER2_RST Timer 2 reset control. 22 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB0_DEV_RST USB0 DEV reset control. 25 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 TIMER0_RST Timer 0 reset control. 26 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 TIMER1_RST Timer 1 reset control. 27 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 PRESETCTRL2 Peripheral reset control 2 PRESETCTRL 0x108 32 read-write 0 0x7FFF77FE DMA1_RST DMA1 reset control. 1 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 COMP_RST Comparator reset control. 2 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SDIO_RST SDIO reset control. 3 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB1_HOST_RST USB1 Host reset control. 4 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB1_DEV_RST USB1 dev reset control. 5 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB1_RAM_RST USB1 RAM reset control. 6 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB1_PHY_RST USB1 PHY reset control. 7 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 FREQME_RST Frequency meter reset control. 8 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 RNG_RST RNG reset control. 13 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 SYSCTL_RST SYSCTL Block reset. 15 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB0_HOSTM_RST USB0 Host Master reset control. 16 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 USB0_HOSTS_RST USB0 Host Slave reset control. 17 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 HASH_AES_RST HASH_AES reset control. 18 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 PQ_RST Power Quad reset control. 19 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 PLULUT_RST PLU LUT reset control. 20 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 TIMER3_RST Timer 3 reset control. 21 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 TIMER4_RST Timer 4 reset control. 22 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 PUF_RST PUF reset control reset control. 23 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 CASPER_RST Casper reset control. 24 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 ANALOG_CTRL_RST analog control reset control. 27 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 HS_LSPI_RST HS LSPI reset control. 28 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GPIO_SEC_RST GPIO secure reset control. 29 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 GPIO_SEC_INT_RST GPIO secure int reset control. 30 1 read-write RELEASED Bloc is not reset. 0 ASSERTED Bloc is reset. 0x1 3 0x4 PRESETCTRLSET[%s] Peripheral reset control set register 0x120 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write 3 0x4 PRESETCTRLCLR[%s] Peripheral reset control clear register 0x140 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write SWR_RESET generate a software_reset 0x160 32 write-only 0 0xFFFFFFFF SWR_RESET Write 0x5A00_0001 to generate a software_reset. 0 32 write-only RELEASED Bloc is not reset. 0 ASSERTED Generate a software reset. 0x5A000001 AHBCLKCTRL0 AHB Clock control 0 AHBCLKCTRL 0x200 32 read-write 0x180 0xCFFE9FA ROM Enables the clock for the ROM. 1 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SRAM_CTRL1 Enables the clock for the SRAM Controller 1. 3 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SRAM_CTRL2 Enables the clock for the SRAM Controller 2. 4 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SRAM_CTRL3 Enables the clock for the SRAM Controller 3. 5 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SRAM_CTRL4 Enables the clock for the SRAM Controller 4. 6 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FLASH Enables the clock for the Flash controller. 7 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FMC Enables the clock for the FMC controller. 8 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 MUX Enables the clock for the Input Mux. 11 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 IOCON Enables the clock for the I/O controller. 13 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GPIO0 Enables the clock for the GPIO0. 14 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GPIO1 Enables the clock for the GPIO1. 15 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GPIO2 Enables the clock for the GPIO2. 16 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GPIO3 Enables the clock for the GPIO3. 17 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 PINT Enables the clock for the Pin interrupt (PINT). 18 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GINT Enables the clock for the Group interrupt (GINT). 19 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 DMA0 Enables the clock for the DMA0. 20 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 CRCGEN Enables the clock for the CRCGEN. 21 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 WWDT Enables the clock for the Watchdog Timer. 22 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 RTC Enables the clock for the Real Time Clock (RTC). 23 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 MAILBOX Enables the clock for the Inter CPU communication Mailbox. 26 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 ADC Enables the clock for the ADC. 27 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 AHBCLKCTRL1 AHB Clock control 1 AHBCLKCTRL 0x204 32 read-write 0 0xDE57FC47 MRT Enables the clock for the MRT. 0 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 OSTIMER Enables the clock for the OS Event Timer. 1 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SCT Enables the clock for the SCT. 2 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 UTICK Enables the clock for the UTICK. 10 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC0 Enables the clock for the FC0. 11 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC1 Enables the clock for the FC1. 12 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC2 Enables the clock for the FC2. 13 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC3 Enables the clock for the FC3. 14 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC4 Enables the clock for the FC4. 15 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC5 Enables the clock for the FC5. 16 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC6 Enables the clock for the FC6. 17 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FC7 Enables the clock for the FC7. 18 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 TIMER2 Enables the clock for the Timer 2. 22 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB0_DEV Enables the clock for the USB0 DEV. 25 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 TIMER0 Enables the clock for the Timer 0. 26 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 TIMER1 Enables the clock for the Timer 1. 27 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 AHBCLKCTRL2 AHB Clock control 2 AHBCLKCTRL 0x208 32 read-write 0 0x7FFF77FE DMA1 Enables the clock for the DMA1. 1 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 COMP Enables the clock for the Comparator. 2 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SDIO Enables the clock for the SDIO. 3 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB1_HOST Enables the clock for the USB1 Host. 4 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB1_DEV Enables the clock for the USB1 dev. 5 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB1_RAM Enables the clock for the USB1 RAM. 6 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB1_PHY Enables the clock for the USB1 PHY. 7 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 FREQME Enables the clock for the Frequency meter. 8 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 RNG Enables the clock for the RNG. 13 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 SYSCTL SYSCTL block clock. 15 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB0_HOSTM Enables the clock for the USB0 Host Master. 16 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 USB0_HOSTS Enables the clock for the USB0 Host Slave. 17 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 HASH_AES Enables the clock for the HASH_AES. 18 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 PQ Enables the clock for the Power Quad. 19 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 PLULUT Enables the clock for the PLU LUT. 20 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 TIMER3 Enables the clock for the Timer 3. 21 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 TIMER4 Enables the clock for the Timer 4. 22 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 PUF Enables the clock for the PUF reset control. 23 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 CASPER Enables the clock for the Casper. 24 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 ANALOG_CTRL Enables the clock for the analog control. 27 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 HS_LSPI Enables the clock for the HS LSPI. 28 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GPIO_SEC Enables the clock for the GPIO secure. 29 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 GPIO_SEC_INT Enables the clock for the GPIO secure int. 30 1 read-write DISABLE Disable Clock. 0 ENABLE Enable Clock. 0x1 3 0x4 AHBCLKCTRLSET[%s] Peripheral reset control register 0x220 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write 3 0x4 AHBCLKCTRLCLR[%s] Peripheral reset control register 0x240 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write SYSTICKCLKSEL0 System Tick Timer for CPU0 source select SYSTICKCLKSEL 0x260 32 read-write 0x7 0x7 SEL System Tick Timer for CPU0 source select. 0 3 read-write ENUM_0x0 System Tick 0 divided clock. 0 ENUM_0x1 FRO 1MHz clock. 0x1 ENUM_0x2 Oscillator 32 kHz clock. 0x2 ENUM_0x3 No clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 SYSTICKCLKSELX0 Peripheral reset control register SYSTICKCLKSEL 0x260 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write SYSTICKCLKSEL1 System Tick Timer for CPU1 source select SYSTICKCLKSEL 0x264 32 read-write 0x7 0x7 SEL System Tick Timer for CPU1 source select. 0 3 read-write ENUM_0x0 System Tick 1 divided clock. 0 ENUM_0x1 FRO 1MHz clock. 0x1 ENUM_0x2 Oscillator 32 kHz clock. 0x2 ENUM_0x3 No clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 SYSTICKCLKSELX1 Peripheral reset control register SYSTICKCLKSEL 0x264 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write TRACECLKSEL Trace clock source select 0x268 32 read-write 0x7 0x7 SEL Trace clock source select. 0 3 read-write ENUM_0x0 Trace divided clock. 0 ENUM_0x1 FRO 1MHz clock. 0x1 ENUM_0x2 Oscillator 32 kHz clock. 0x2 ENUM_0x3 No clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 CTIMERCLKSEL0 CTimer 0 clock source select CTIMERCLKSEL 0x26C 32 read-write 0x7 0x7 SEL CTimer 0 clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32kHz clock. 0x6 ENUM_0x7 No clock. 0x7 CTIMERCLKSELX0 Peripheral reset control register CTIMERCLKSEL 0x26C 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write CTIMERCLKSEL1 CTimer 1 clock source select CTIMERCLKSEL 0x270 32 read-write 0x7 0x7 SEL CTimer 1 clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32kHz clock. 0x6 ENUM_0x7 No clock. 0x7 CTIMERCLKSELX1 Peripheral reset control register CTIMERCLKSEL 0x270 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write CTIMERCLKSEL2 CTimer 2 clock source select CTIMERCLKSEL 0x274 32 read-write 0x7 0x7 SEL CTimer 2 clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32kHz clock. 0x6 ENUM_0x7 No clock. 0x7 CTIMERCLKSELX2 Peripheral reset control register CTIMERCLKSEL 0x274 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write CTIMERCLKSEL3 CTimer 3 clock source select CTIMERCLKSEL 0x278 32 read-write 0x7 0x7 SEL CTimer 3 clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32kHz clock. 0x6 ENUM_0x7 No clock. 0x7 CTIMERCLKSELX3 Peripheral reset control register CTIMERCLKSEL 0x278 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write CTIMERCLKSEL4 CTimer 4 clock source select CTIMERCLKSEL 0x27C 32 read-write 0x7 0x7 SEL CTimer 4 clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32kHz clock. 0x6 ENUM_0x7 No clock. 0x7 CTIMERCLKSELX4 Peripheral reset control register CTIMERCLKSEL 0x27C 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write MAINCLKSELA Main clock A source select 0x280 32 read-write 0 0x7 SEL Main clock A source select. 0 3 read-write ENUM_0x0 FRO 12 MHz clock. 0 ENUM_0x1 CLKIN clock. 0x1 ENUM_0x2 FRO 1MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 MAINCLKSELB Main clock source select 0x284 32 read-write 0 0x7 SEL Main clock source select. 0 3 read-write ENUM_0x0 Main Clock A. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 PLL1 clock. 0x2 ENUM_0x3 Oscillator 32 kHz clock. 0x3 CLKOUTSEL CLKOUT clock source select 0x288 32 read-write 0x7 0x7 SEL CLKOUT clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 CLKIN clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 PLL1 clock. 0x5 ENUM_0x6 Oscillator 32kHz clock. 0x6 ENUM_0x7 No clock. 0x7 PLL0CLKSEL PLL0 clock source select 0x290 32 read-write 0x7 0x7 SEL PLL0 clock source select. 0 3 read-write ENUM_0x0 FRO 12 MHz clock. 0 ENUM_0x1 CLKIN clock. 0x1 ENUM_0x2 FRO 1MHz clock. 0x2 ENUM_0x3 Oscillator 32kHz clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 PLL1CLKSEL PLL1 clock source select 0x294 32 read-write 0x7 0x7 SEL PLL1 clock source select. 0 3 read-write ENUM_0x0 FRO 12 MHz clock. 0 ENUM_0x1 CLKIN clock. 0x1 ENUM_0x2 FRO 1MHz clock. 0x2 ENUM_0x3 Oscillator 32kHz clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 ADCCLKSEL ADC clock source select 0x2A4 32 read-write 0x7 0x7 SELADC clock source selectread-write03SELread-writemainclkMain clk.0pll0PLL0 clk.1fro96FRO 96 MHZ clk.2noneNo clk.4 USB0CLKSEL FS USB clock source select 0x2A8 32 read-write 0x7 0x7 SEL FS USB clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 PLL1 clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSEL0 Flexcomm Interface 0 clock source select for Fractional Rate Divider FCCLKSEL 0x2B0 32 read-write 0x7 0x7 SEL Flexcomm Interface 0 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX0 Peripheral reset control register FCCLKSEL 0x2B0 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL1 Flexcomm Interface 1 clock source select for Fractional Rate Divider FCCLKSEL 0x2B4 32 read-write 0x7 0x7 SEL Flexcomm Interface 1 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX1 Peripheral reset control register FCCLKSEL 0x2B4 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL2 Flexcomm Interface 2 clock source select for Fractional Rate Divider FCCLKSEL 0x2B8 32 read-write 0x7 0x7 SEL Flexcomm Interface 2 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX2 Peripheral reset control register FCCLKSEL 0x2B8 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL3 Flexcomm Interface 3 clock source select for Fractional Rate Divider FCCLKSEL 0x2BC 32 read-write 0x7 0x7 SEL Flexcomm Interface 3 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX3 Peripheral reset control register FCCLKSEL 0x2BC 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL4 Flexcomm Interface 4 clock source select for Fractional Rate Divider FCCLKSEL 0x2C0 32 read-write 0x7 0x7 SEL Flexcomm Interface 4 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX4 Peripheral reset control register FCCLKSEL 0x2C0 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL5 Flexcomm Interface 5 clock source select for Fractional Rate Divider FCCLKSEL 0x2C4 32 read-write 0x7 0x7 SEL Flexcomm Interface 5 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX5 Peripheral reset control register FCCLKSEL 0x2C4 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL6 Flexcomm Interface 6 clock source select for Fractional Rate Divider FCCLKSEL 0x2C8 32 read-write 0x7 0x7 SEL Flexcomm Interface 6 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX6 Peripheral reset control register FCCLKSEL 0x2C8 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FCCLKSEL7 Flexcomm Interface 7 clock source select for Fractional Rate Divider FCCLKSEL 0x2CC 32 read-write 0x7 0x7 SEL Flexcomm Interface 7 clock source select for Fractional Rate Divider. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 FCCLKSELX7 Peripheral reset control register FCCLKSEL 0x2CC 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write HSLSPICLKSEL HS LSPI clock source select 0x2D0 32 read-write 0x7 0x7 SEL HS LSPI clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 system PLL divided clock. 0x1 ENUM_0x2 FRO 12 MHz clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 FRO 1MHz clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 Oscillator 32 kHz clock. 0x6 ENUM_0x7 No clock. 0x7 MCLKCLKSEL MCLK clock source select 0x2E0 32 read-write 0x7 0x7 SEL MCLK clock source select. 0 3 read-write ENUM_0x0 FRO 96 MHz clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x4 No clock. 0x4 ENUM_0x5 No clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 SCTCLKSEL SCTimer/PWM clock source select 0x2F0 32 read-write 0x7 0x7 SEL SCTimer/PWM clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 CLKIN clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 MCLK clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 SDIOCLKSEL SDIO clock source select 0x2F8 32 read-write 0x7 0x7 SEL SDIO clock source select. 0 3 read-write ENUM_0x0 Main clock. 0 ENUM_0x1 PLL0 clock. 0x1 ENUM_0x2 No clock. 0x2 ENUM_0x3 FRO 96 MHz clock. 0x3 ENUM_0x4 No clock. 0x4 ENUM_0x5 PLL1 clock. 0x5 ENUM_0x6 No clock. 0x6 ENUM_0x7 No clock. 0x7 SYSTICKCLKDIV0 System Tick Timer divider for CPU0 0x300 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 SYSTICKCLKDIV1 System Tick Timer divider for CPU1 0x304 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 TRACECLKDIV TRACE clock divider 0x308 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 FLEXFRG0CTRL Fractional rate divider for flexcomm 0 FLEXFRGCTRL 0x320 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL0 Peripheral reset control register FLEXFRGCTRL 0x320 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG1CTRL Fractional rate divider for flexcomm 1 FLEXFRGCTRL 0x324 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL1 Peripheral reset control register FLEXFRGCTRL 0x324 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG2CTRL Fractional rate divider for flexcomm 2 FLEXFRGCTRL 0x328 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL2 Peripheral reset control register FLEXFRGCTRL 0x328 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG3CTRL Fractional rate divider for flexcomm 3 FLEXFRGCTRL 0x32C 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL3 Peripheral reset control register FLEXFRGCTRL 0x32C 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG4CTRL Fractional rate divider for flexcomm 4 FLEXFRGCTRL 0x330 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL4 Peripheral reset control register FLEXFRGCTRL 0x330 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG5CTRL Fractional rate divider for flexcomm 5 FLEXFRGCTRL 0x334 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL5 Peripheral reset control register FLEXFRGCTRL 0x334 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG6CTRL Fractional rate divider for flexcomm 6 FLEXFRGCTRL 0x338 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL6 Peripheral reset control register FLEXFRGCTRL 0x338 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write FLEXFRG7CTRL Fractional rate divider for flexcomm 7 FLEXFRGCTRL 0x33C 32 read-write 0xFF 0xFFFF DIV Denominator of the fractional rate divider. 0 8 read-write MULT Numerator of the fractional rate divider. 8 8 read-write FLEXFRGXCTRL7 Peripheral reset control register FLEXFRGCTRL 0x33C 32 read-write 0 0xFFFFFFFF DATA Data array value 0 32 read-write AHBCLKDIV System clock divider 0x380 32 read-write 0 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 CLKOUTDIV CLKOUT clock divider 0x384 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 FROHFDIV FRO_HF (96MHz) clock divider 0x388 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 WDTCLKDIV WDT clock divider 0x38C 32 read-write 0x40000000 0xE000003F DIV Clock divider value. 0 6 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 ADCCLKDIV ADC clock divider 0x394 32 read-write 0x40000000 0xE0000007 DIV Clock divider value. 0 3 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 USB0CLKDIV USB0 Clock divider 0x398 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 MCLKDIV I2S MCLK clock divider 0x3AC 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 SCTCLKDIV SCT/PWM clock divider 0x3B4 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 SDIOCLKDIV SDIO clock divider 0x3BC 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 PLL0CLKDIV PLL0 clock divider 0x3C4 32 read-write 0x40000000 0xE00000FF DIV Clock divider value. 0 8 read-write RESET Resets the divider counter. 29 1 write-only RELEASED Divider is not reset. 0 ASSERTED Divider is reset. 0x1 HALT Halts the divider counter. 30 1 read-write RUN Divider clock is running. 0 HALT Divider clock is stoped. 0x1 REQFLAG Divider status flag. 31 1 read-only STABLE Divider clock is stable. 0 ONGOING Clock frequency is not stable. 0x1 CLOCKGENUPDATELOCKOUT Control clock configuration registers access (like xxxDIV, xxxSEL) 0x3FC 32 read-write 0 0xFFFFFFFF CLOCKGENUPDATELOCKOUT Control clock configuration registers access (like xxxDIV, xxxSEL). 0 32 read-write FREEZE all hardware clock configruration are freeze. 0 ENABLE update all clock configuration. 0x1 FMCCR FMC configuration register 0x400 32 read-write 0x2000 0xFFFFFFFF FLASHTIM Flash memory access time. 12 4 read-write FLASHTIM0 1 system clock flash access time (for system clock rates up to 11 MHz). 0 FLASHTIM1 2 system clocks flash access time (for system clock rates up to 22 MHz). 0x1 FLASHTIM2 3 system clocks flash access time (for system clock rates up to 33 MHz). 0x2 FLASHTIM3 4 system clocks flash access time (for system clock rates up to 44 MHz). 0x3 FLASHTIM4 5 system clocks flash access time (for system clock rates up to 55 MHz). 0x4 FLASHTIM5 6 system clocks flash access time (for system clock rates up to 66 MHz). 0x5 FLASHTIM6 7 system clocks flash access time (for system clock rates up to 77 MHz). 0x6 FLASHTIM7 8 system clocks flash access time (for system clock rates up to 88 MHz). 0x7 FLASHTIM8 9 system clocks flash access time (for system clock rates up to 100 MHz). 0x8 USB0NEEDCLKCTRL USB0 need clock control 0x40C 32 read-write 0 0x1F AP_FS_DEV_NEEDCLK USB0 Device USB0_NEEDCLK signal control:. 0 1 read-write HW_CTRL Under hardware control. 0 FORCED Forced high. 0x1 POL_FS_DEV_NEEDCLK USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. 1 1 read-write FALLING Falling edge of device USB0_NEEDCLK triggers wake-up. 0 RISING Rising edge of device USB0_NEEDCLK triggers wake-up. 0x1 AP_FS_HOST_NEEDCLK USB0 Host USB0_NEEDCLK signal control:. 2 1 read-write HW_CTRL Under hardware control. 0 FORCED Forced high. 0x1 POL_FS_HOST_NEEDCLK USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. 3 1 read-write FALLING Falling edge of device USB0_NEEDCLK triggers wake-up. 0 RISING Rising edge of device USB0_NEEDCLK triggers wake-up. 0x1 USB0NEEDCLKSTAT USB0 need clock status 0x410 32 read-write 0 0x3 DEV_NEEDCLK USB0 Device USB0_NEEDCLK signal status:. 0 1 read-only LOW USB0 Device clock is low. 0 HIGH USB0 Device clock is high. 0x1 HOST_NEEDCLK USB0 Host USB0_NEEDCLK signal status:. 1 1 read-only LOW USB0 Host clock is low. 0 HIGH USB0 Host clock is high. 0x1 FMCFLUSH FMCflush control 0x41C 32 write-only 0 0xFFFFFFFF FLUSH Flush control 0 1 write-only NO_FLUSH No action is performed. 0 FLUSH Flush the FMC buffer contents. 0x1 MCLKIO MCLK control 0x420 32 read-write 0 0xFFFFFFFF MCLKIO MCLK control. 0 1 read-write INPUT input mode. 0 OUTPUT output mode. 0x1 USB1NEEDCLKCTRL USB1 need clock control 0x424 32 read-write 0x10 0x1F AP_HS_DEV_NEEDCLK USB1 Device need_clock signal control: 0 1 read-write HW_CTRL HOST_NEEDCLK is under hardware control. 0 FORCED HOST_NEEDCLK is forced high. 0x1 POL_HS_DEV_NEEDCLK USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: 1 1 read-write FALLING Falling edge of DEV_NEEDCLK triggers wake-up. 0 RISING Rising edge of DEV_NEEDCLK triggers wake-up. 0x1 AP_HS_HOST_NEEDCLK USB1 Host need clock signal control: 2 1 read-write HW_CTRL HOST_NEEDCLK is under hardware control. 0 FORCED HOST_NEEDCLK is forced high. 0x1 POL_HS_HOST_NEEDCLK USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. 3 1 read-write FALLING Falling edge of HOST_NEEDCLK triggers wake-up. 0 RISING Rising edge of HOST_NEEDCLK triggers wake-up. 0x1 HS_DEV_WAKEUP_N Software override of device controller PHY wake up logic. 4 1 read-write FORCE_WUP Forces USB1_PHY to wake-up. 0 NORMAL_WUP Normal USB1_PHY behavior. 0x1 USB1NEEDCLKSTAT USB1 need clock status 0x428 32 read-write 0 0x3 DEV_NEEDCLK USB1 Device need_clock signal status:. 0 1 read-only LOW DEV_NEEDCLK is low. 0 HIGH DEV_NEEDCLK is high. 0x1 HOST_NEEDCLK USB1 Host need_clock signal status:. 1 1 read-only LOW HOST_NEEDCLK is low. 0 HIGH HOST_NEEDCLK is high. 0x1 SDIOCLKCTRL SDIO CCLKIN phase and delay control 0x460 32 read-write 0 0x9F9F008F CCLK_DRV_PHASE Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. 0 2 read-write ENUM_0_DEG 0 degree shift. 0 ENUM_90_DEG 90 degree shift. 0x1 ENUM_180_DEG 180 degree shift. 0x2 ENUM_270_DEG 270 degree shift. 0x3 CCLK_SAMPLE_PHASE Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. 2 2 read-write ENUM_0_DEG 0 degree shift. 0 ENUM_90_DEG 90 degree shift. 0x1 ENUM_180_DEG 180 degree shift. 0x2 ENUM_270_DEG 270 degree shift. 0x3 PHASE_ACTIVE Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. 7 1 read-write BYPASSED Bypassed. 0 PH_SHIFT Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. 0x1 CCLK_DRV_DELAY Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. 16 5 read-write CCLK_DRV_DELAY_ACTIVE Enables drive delay, as controlled by the CCLK_DRV_DELAY field. 23 1 read-write DISABLE Disable drive delay. 0 ENABLE Enable drive delay. 0x1 CCLK_SAMPLE_DELAY Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. 24 5 read-write CCLK_SAMPLE_DELAY_ACTIVE Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. 31 1 read-write DISABLE Disables sample delay. 0 ENABLE Enables sample delay. 0x1 PLL1CTRL PLL1 550m control 0x560 32 read-write 0 0x1FFFFFF SELR Bandwidth select R value. 0 4 read-write SELI Bandwidth select I value. 4 6 read-write SELP Bandwidth select P value. 10 5 read-write BYPASSPLL Bypass PLL input clock is sent directly to the PLL output (default). 15 1 read-write USED use PLL. 0 BYPASSED PLL input clock is sent directly to the PLL output. 0x1 BYPASSPOSTDIV2 bypass of the divide-by-2 divider in the post-divider. 16 1 read-write USED use the divide-by-2 divider in the post-divider. 0 BYPASSED bypass of the divide-by-2 divider in the post-divider. 0x1 LIMUPOFF limup_off = 1 in spread spectrum and fractional PLL applications. 17 1 read-write BWDIRECT control of the bandwidth of the PLL. 18 1 read-write SYNC the bandwidth is changed synchronously with the feedback-divider. 0 DIRECT modify the bandwidth of the PLL directly. 0x1 BYPASSPREDIV bypass of the pre-divider. 19 1 read-write USED use the pre-divider. 0 BYPASSED bypass of the pre-divider. 0x1 BYPASSPOSTDIV bypass of the post-divider. 20 1 read-write USED use the post-divider. 0 BYPASSED bypass of the post-divider. 0x1 CLKEN enable the output clock. 21 1 read-write DISABLE Disable the output clock. 0 ENABLE Enable the output clock. 0x1 FRMEN 1: free running mode. 22 1 read-write FRMCLKSTABLE free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. 23 1 read-write SKEWEN Skew mode. 24 1 read-write DISABLE skewmode is disable. 0 ENABLE skewmode is enable. 0x1 PLL1STAT PLL1 550m status 0x564 32 read-write 0 0x1F LOCK lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. 0 1 read-only PREDIVACK pre-divider ratio change acknowledge. 1 1 read-only FEEDDIVACK feedback divider ratio change acknowledge. 2 1 read-only POSTDIVACK post-divider ratio change acknowledge. 3 1 read-only FRMDET free running detector output (active high). 4 1 read-only PLL1NDEC PLL1 550m N divider 0x568 32 read-write 0 0x1FF NDIV pre-divider divider ratio (N-divider). 0 8 read-write NREQ pre-divider ratio change request. 8 1 read-write PLL1MDEC PLL1 550m M divider 0x56C 32 read-write 0 0x1FFFF MDIV feedback divider divider ratio (M-divider). 0 16 read-write MREQ feedback ratio change request. 16 1 read-write PLL1PDEC PLL1 550m P divider 0x570 32 read-write 0 0x3F PDIV post-divider divider ratio (P-divider) 0 5 read-write PREQ feedback ratio change request. 5 1 read-write PLL0CTRL PLL0 550m control 0x580 32 read-write 0 0x1FFFFFF SELR Bandwidth select R value. 0 4 read-write SELI Bandwidth select I value. 4 6 read-write SELP Bandwidth select P value. 10 5 read-write BYPASSPLL Bypass PLL input clock is sent directly to the PLL output (default). 15 1 read-write USED use PLL. 0 BYPASSED Bypass PLL input clock is sent directly to the PLL output. 0x1 BYPASSPOSTDIV2 bypass of the divide-by-2 divider in the post-divider. 16 1 read-write USED use the divide-by-2 divider in the post-divider. 0 BYPASSED bypass of the divide-by-2 divider in the post-divider. 0x1 LIMUPOFF limup_off = 1 in spread spectrum and fractional PLL applications. 17 1 read-write BWDIRECT Control of the bandwidth of the PLL. 18 1 read-write SYNC the bandwidth is changed synchronously with the feedback-divider. 0 DIRECT modify the bandwidth of the PLL directly. 0x1 BYPASSPREDIV bypass of the pre-divider. 19 1 read-write USED use the pre-divider. 0 BYPASSED bypass of the pre-divider. 0x1 BYPASSPOSTDIV bypass of the post-divider. 20 1 read-write USED use the post-divider. 0 BYPASSED bypass of the post-divider. 0x1 CLKEN enable the output clock. 21 1 read-write DISABLE disable the output clock. 0 ENABLE enable the output clock. 0x1 FRMEN free running mode. 22 1 read-write DISABLE free running mode is disable. 0 ENABLE free running mode is enable. 0x1 FRMCLKSTABLE free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. 23 1 read-write SKEWEN skew mode. 24 1 read-write DISABLE skew mode is disable. 0 ENABLE skew mode is enable. 0x1 PLL0STAT PLL0 550m status 0x584 32 read-write 0 0x1F LOCK lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. 0 1 read-only PREDIVACK pre-divider ratio change acknowledge. 1 1 read-only FEEDDIVACK feedback divider ratio change acknowledge. 2 1 read-only POSTDIVACK post-divider ratio change acknowledge. 3 1 read-only FRMDET free running detector output (active high). 4 1 read-only PLL0NDEC PLL0 550m N divider 0x588 32 read-write 0 0x1FF NDIV pre-divider divider ratio (N-divider). 0 8 read-write NREQ pre-divider ratio change request. 8 1 read-write PLL0PDEC PLL0 550m P divider 0x58C 32 read-write 0 0x3F PDIV post-divider divider ratio (P-divider) 0 5 read-write PREQ feedback ratio change request. 5 1 read-write PLL0SSCG0 PLL0 Spread Spectrum Wrapper control register 0 0x590 32 read-write 0 0xFFFFFFFF MD_LBS input word of the wrapper bit 31 to 0. 0 32 read-write PLL0SSCG1 PLL0 Spread Spectrum Wrapper control register 1 0x594 32 read-write 0 0x1FFFFFFF MD_MBS input word of the wrapper bit 32. 0 1 read-write MD_REQ md change request. 1 1 read-write MF programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. 2 3 read-write MR programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. 5 3 read-write MC modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 8 2 read-write MDIV_EXT to select an external mdiv value. 10 16 read-write MREQ to select an external mreq value. 26 1 read-write DITHER dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen. 27 1 read-write SEL_EXT to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. 28 1 read-write CPUCTRL CPU Control for multiple processors 0x800 32 read-write 0x2C 0x3D CPU1CLKEN CPU1 clock enable. 3 1 read-write DISABLE The CPU1 clock is not enabled. 0 ENABLE The CPU1 clock is enabled. 0x1 CPU1RSTEN CPU1 reset. 5 1 read-write RELEASED The CPU1 is not being reset. 0 ASSERTED The CPU1 is being reset. 0x1 CPBOOT Coprocessor Boot Address 0x804 32 read-write 0 0xFFFFFFFF CPBOOT Coprocessor Boot Address for CPU1. 0 32 read-write CPSTAT CPU Status 0x80C 32 read-write 0 0xF CPU0SLEEPING The CPU0 sleeping state. 0 1 read-only AWAKE the CPU is not sleeping. 0 SLEEPING the CPU is sleeping. 0x1 CPU1SLEEPING The CPU1 sleeping state. 1 1 read-only AWAKE the CPU is not sleeping. 0 SLEEPING the CPU is sleeping. 0x1 CPU0LOCKUP The CPU0 lockup state. 2 1 read-only AWAKE the CPU is not in lockup. 0 SLEEPING the CPU is in lockup. 0x1 CPU1LOCKUP The CPU1 lockup state. 3 1 read-only AWAKE the CPU is not in lockup. 0 SLEEPING the CPU is in lockup. 0x1 CLOCK_CTRL Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures 0xA18 32 read-write 0x1 0x3FF XTAL32MHZ_FREQM_ENA Enable XTAL32MHz clock for Frequency Measure module. 1 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 FRO1MHZ_UTICK_ENA Enable FRO 1MHz clock for Frequency Measure module and for UTICK. 2 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 FRO12MHZ_FREQM_ENA Enable FRO 12MHz clock for Frequency Measure module. 3 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 FRO_HF_FREQM_ENA Enable FRO 96MHz clock for Frequency Measure module. 4 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 CLKIN_ENA Enable clock_in clock for clock module. 5 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 FRO1MHZ_CLK_ENA Enable FRO 1MHz clock for clock muxing in clock gen. 6 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 ANA_FRO12M_CLK_ENA Enable FRO 12MHz clock for analog control of the FRO 192MHz. 7 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 XO_CAL_CLK_ENA Enable clock for cristal oscilator calibration. 8 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 PLU_DEGLITCH_CLK_ENA Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. 9 1 read-write DISABLE The clock is not enabled. 0 ENABLE The clock is enabled. 0x1 COMP_INT_CTRL Comparator Interrupt control 0xB10 32 read-write 0 0x3F INT_ENABLE Analog Comparator interrupt enable control:. 0 1 read-write INT_DISABLE interrupt disable. 0 INT_ENABLE interrupt enable. 0x1 INT_CLEAR Analog Comparator interrupt clear. 1 1 read-write NONE No effect. 0 CLEAR Clear the interrupt. Self-cleared bit. 0x1 INT_CTRL Comparator interrupt type selector:. 2 3 read-write EDGE_DISABLE The analog comparator interrupt edge sensitive is disabled. 0 LVL_DISABLE The analog comparator interrupt level sensitive is disabled. 0x1 EDGE_RISING analog comparator interrupt is rising edge sensitive. 0x2 LVL_HIGH Analog Comparator interrupt is high level sensitive. 0x3 EDGE_FALLING analog comparator interrupt is falling edge sensitive. 0x4 LVL_LOW Analog Comparator interrupt is low level sensitive. 0x5 EDGE_BOTH analog comparator interrupt is rising and falling edge sensitive. 0x6 LVL_DIS2 The analog comparator interrupt level sensitive is disabled. 0x7 INT_SOURCE Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. 5 1 read-write FILTER_INT Select Analog Comparator filtered output as input for interrupt detection. 0 RAW_INT Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode. 0x1 COMP_INT_STATUS Comparator Interrupt status 0xB14 32 read-write 0 0x7 STATUS Interrupt status BEFORE Interrupt Enable. 0 1 read-only NO_INT no interrupt pending. 0 PENDING interrupt pending. 0x1 INT_STATUS Interrupt status AFTER Interrupt Enable. 1 1 read-only NO_INT no interrupt pending. 0 PENDING interrupt pending. 0x1 VAL comparator analog output. 2 1 read-only SMALLER P+ is smaller than P-. 0 GREATER P+ is greater than P-. 0x1 AUTOCLKGATEOVERRIDE Control automatic clock gating 0xE04 32 read-write 0xFFFF 0xFFFFFFFF ROM Control automatic clock gating of ROM controller. 0 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 RAMX_CTRL Control automatic clock gating of RAMX controller. 1 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 RAM0_CTRL Control automatic clock gating of RAM0 controller. 2 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 RAM1_CTRL Control automatic clock gating of RAM1 controller. 3 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 RAM2_CTRL Control automatic clock gating of RAM2 controller. 4 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 RAM3_CTRL Control automatic clock gating of RAM3 controller. 5 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 RAM4_CTRL Control automatic clock gating of RAM4 controller. 6 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 SYNC0_APB Control automatic clock gating of synchronous bridge controller 0. 7 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 SYNC1_APB Control automatic clock gating of synchronous bridge controller 1. 8 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 CRCGEN Control automatic clock gating of CRCGEN controller. 11 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 SDMA0 Control automatic clock gating of DMA0 controller. 12 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 SDMA1 Control automatic clock gating of DMA1 controller. 13 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 USB0 Control automatic clock gating of USB controller. 14 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 SYSCON Control automatic clock gating of synchronous system controller registers bank. 15 1 read-write DISABLE Automatic clock gating is not overridden. 0 ENABLE Automatic clock gating is overridden (Clock gating is disabled). 0x1 ENABLEUPDATE The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. 16 16 write-only DISABLE Bit Fields 0 - 15 of this register are not updated 0 ENABLE Bit Fields 0 - 15 of this register are updated 0xC0DE GPIOPSYNC Enable bypass of the first stage of synchonization inside GPIO_INT module 0xE08 32 read-write 0 0x1 PSYNC Enable bypass of the first stage of synchonization inside GPIO_INT module. 0 1 read-write USED use the first stage of synchonization inside GPIO_INT module. 0 BYPASS bypass of the first stage of synchonization inside GPIO_INT module. 0x1 DEBUG_LOCK_EN Control write access to security registers. 0xFA0 32 read-write 0x5 0xF LOCK_ALL Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. 0 4 read-write DISABLE Any other value than b1010: disable write access to all 6 registers. 0 ENABLE 1010: Enable write access to all 6 registers. 0xA DEBUG_FEATURES Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. 0xFA4 32 read-write 0 0xFFF CPU0_DBGEN CPU0 Invasive debug control:. 0 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU0_NIDEN CPU0 Non Invasive debug control:. 2 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU0_SPIDEN CPU0 Secure Invasive debug control:. 4 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU0_SPNIDEN CPU0 Secure Non Invasive debug control:. 6 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU1_DBGEN CPU1 Invasive debug control:. 8 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU1_NIDEN CPU1 Non Invasive debug control:. 10 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 DEBUG_FEATURES_DP Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. 0xFA8 32 read-write 0x555 0xFFF CPU0_DBGEN CPU0 (CPU0) Invasive debug control:. 0 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU0_NIDEN CPU0 Non Invasive debug control:. 2 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU0_SPIDEN CPU0 Secure Invasive debug control:. 4 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU0_SPNIDEN CPU0 Secure Non Invasive debug control:. 6 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU1_DBGEN CPU1 Invasive debug control:. 8 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 CPU1_NIDEN CPU1 Non Invasive debug control:. 10 2 read-write DISABLE Any other value than b10: invasive debug is disable. 0x1 ENABLE 10: Invasive debug is enabled. 0x2 KEY_BLOCK block quiddikey/PUF all index. 0xFBC 32 write-only 0x3CC35AA5 0xFFFFFFFF KEY_BLOCK Write a value to block quiddikey/PUF all index. 0 32 write-only DEBUG_AUTH_BEACON Debug authentication BEACON register 0xFC0 32 read-write 0 0xFFFFFFFF BEACON Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. 0 32 read-write CPUCFG CPUs configuration register 0xFD4 32 read-write 0x2 0x7 CPU1ENABLE Enable CPU1. 2 1 read-write DISABLE CPU1 is disable (Processor in reset). 0 ENABLE CPU1 is enable. 0x1 DEVICE_ID0 Device ID 0xFF8 32 read-only 0 0xFFFFFFFF ROM_REV_MINOR ROM revision. 20 4 read-only DIEID Chip revision ID and Number 0xFFC 32 read-only 0x426B0 0xFFFFFF REV_ID Chip Metal Revision ID. 0 4 read-only MCO_NUM_IN_DIE_ID Chip Number 0x426B. 4 20 read-only IOCON I/O pin configuration (IOCON) IOCON 0x40001000 0 0x100 registers PIO0_0 Digital I/O control for port 0 pins PIO0_0 0 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_1 Digital I/O control for port 0 pins PIO0_1 0x4 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_2 Digital I/O control for port 0 pins PIO0_2 0x8 32 read-write 0x110 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_3 Digital I/O control for port 0 pins PIO0_3 0xC 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_4 Digital I/O control for port 0 pins PIO0_4 0x10 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_5 Digital I/O control for port 0 pins PIO0_5 0x14 32 read-write 0x120 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_6 Digital I/O control for port 0 pins PIO0_6 0x18 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_7 Digital I/O control for port 0 pins PIO0_7 0x1C 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_8 Digital I/O control for port 0 pins PIO0_8 0x20 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_9 Digital I/O control for port 0 pins PIO0_9 0x24 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_10 Digital I/O control for port 0 pins PIO0_10 0x28 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_11 Digital I/O control for port 0 pins PIO0_11 0x2C 32 read-write 0x116 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_12 Digital I/O control for port 0 pins PIO0_12 0x30 32 read-write 0x126 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_13 Digital I/O control for port 0 pins PIO0_13 0x34 32 read-write 0x5000 0xFFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 SSEL Supply Selection bit. 11 1 read-write SEL3V3 3V3 Signaling in I2C Mode. 0 SEL1V8 1V8 Signaling in I2C Mode. 0x1 FILTEROFF Controls input glitch filter. 12 1 read-write ENABLED Filter enabled. 0 DISABLED Filter disabled. 0x1 ECS Pull-up current source enable in I2C mode. 13 1 read-write DISABLED Disabled. IO is in open drain cell. 0 ENABLED Enabled. Pull resistor is conencted. 0x1 EGP Switch between GPIO mode and I2C mode. 14 1 read-write I2C_MODE I2C mode. 0 GPIO_MODE GPIO mode. 0x1 I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. 15 1 read-write FAST_MODE I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. 0 STANDARD_MODE I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. 0x1 PIO0_14 Digital I/O control for port 0 pins PIO0_14 0x38 32 read-write 0x5000 0xFFFF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 SSEL Supply Selection bit. 11 1 read-write SEL3V3 3V3 Signaling in I2C Mode. 0 SEL1V8 1V8 Signaling in I2C Mode. 0x1 FILTEROFF Controls input glitch filter. 12 1 read-write ENABLED Filter enabled. 0 DISABLED Filter disabled. 0x1 ECS Pull-up current source enable in I2C mode. 13 1 read-write DISABLED Disabled. IO is in open drain cell. 0 ENABLED Enabled. Pull resistor is conencted. 0x1 EGP Switch between GPIO mode and I2C mode. 14 1 read-write I2C_MODE I2C mode. 0 GPIO_MODE GPIO mode. 0x1 I2CFILTER Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. 15 1 read-write FAST_MODE I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. 0 STANDARD_MODE I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. 0x1 PIO0_15 Digital I/O control for port 0 pins PIO0_15 0x3C 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_16 Digital I/O control for port 0 pins PIO0_16 0x40 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_17 Digital I/O control for port 0 pins PIO0_17 0x44 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_18 Digital I/O control for port 0 pins PIO0_18 0x48 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_19 Digital I/O control for port 0 pins PIO0_19 0x4C 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_20 Digital I/O control for port 0 pins PIO0_20 0x50 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_21 Digital I/O control for port 0 pins PIO0_21 0x54 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_22 Digital I/O control for port 0 pins PIO0_22 0x58 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_23 Digital I/O control for port 0 pins PIO0_23 0x5C 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO0_24 Digital I/O control for port 0 pins PIO0_24 0x60 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_25 Digital I/O control for port 0 pins PIO0_25 0x64 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_26 Digital I/O control for port 0 pins PIO0_26 0x68 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_27 Digital I/O control for port 0 pins PIO0_27 0x6C 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_28 Digital I/O control for port 0 pins PIO0_28 0x70 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_29 Digital I/O control for port 0 pins PIO0_29 0x74 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_30 Digital I/O control for port 0 pins PIO0_30 0x78 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO0_31 Digital I/O control for port 0 pins PIO0_31 0x7C 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO1_0 Digital I/O control for port 1 pins PIO1_0 0x80 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO1_1 Digital I/O control for port 1 pins PIO1_1 0x84 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_2 Digital I/O control for port 1 pins PIO1_2 0x88 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_3 Digital I/O control for port 1 pins PIO1_3 0x8C 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_4 Digital I/O control for port 1 pins PIO1_4 0x90 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_5 Digital I/O control for port 1 pins PIO1_5 0x94 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_6 Digital I/O control for port 1 pins PIO1_6 0x98 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_7 Digital I/O control for port 1 pins PIO1_7 0x9C 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_8 Digital I/O control for port 1 pins PIO1_8 0xA0 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO1_9 Digital I/O control for port 1 pins PIO1_9 0xA4 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO1_10 Digital I/O control for port 1 pins PIO1_10 0xA8 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_11 Digital I/O control for port 1 pins PIO1_11 0xAC 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_12 Digital I/O control for port 1 pins PIO1_12 0xB0 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_13 Digital I/O control for port 1 pins PIO1_13 0xB4 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_14 Digital I/O control for port 1 pins PIO1_14 0xB8 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO1_15 Digital I/O control for port 1 pins PIO1_15 0xBC 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_16 Digital I/O control for port 1 pins PIO1_16 0xC0 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_17 Digital I/O control for port 1 pins PIO1_17 0xC4 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_18 Digital I/O control for port 1 pins PIO1_18 0xC8 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_19 Digital I/O control for port 1 pins PIO1_19 0xCC 32 read-write 0 0x7FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 ASW Analog switch input control. 10 1 read-write VALUE0 For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 VALUE1 For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 PIO1_20 Digital I/O control for port 1 pins PIO1_20 0xD0 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_21 Digital I/O control for port 1 pins PIO1_21 0xD4 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_22 Digital I/O control for port 1 pins PIO1_22 0xD8 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_23 Digital I/O control for port 1 pins PIO1_23 0xDC 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_24 Digital I/O control for port 1 pins PIO1_24 0xE0 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_25 Digital I/O control for port 1 pins PIO1_25 0xE4 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_26 Digital I/O control for port 1 pins PIO1_26 0xE8 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_27 Digital I/O control for port 1 pins PIO1_27 0xEC 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_28 Digital I/O control for port 1 pins PIO1_28 0xF0 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_29 Digital I/O control for port 1 pins PIO1_29 0xF4 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_30 Digital I/O control for port 1 pins PIO1_30 0xF8 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 PIO1_31 Digital I/O control for port 1 pins PIO1_31 0xFC 32 read-write 0 0x3FF FUNC Selects pin function. 0 4 read-write ALT0 Alternative connection 0. 0 ALT1 Alternative connection 1. 0x1 ALT2 Alternative connection 2. 0x2 ALT3 Alternative connection 3. 0x3 ALT4 Alternative connection 4. 0x4 ALT5 Alternative connection 5. 0x5 ALT6 Alternative connection 6. 0x6 ALT7 Alternative connection 7. 0x7 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 4 2 read-write INACTIVE Inactive. Inactive (no pull-down/pull-up resistor enabled). 0 PULL_DOWN Pull-down. Pull-down resistor enabled. 0x1 PULL_UP Pull-up. Pull-up resistor enabled. 0x2 REPEATER Repeater. Repeater mode. 0x3 SLEW Driver slew rate. 6 1 read-write STANDARD Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 INVERT Input polarity. 7 1 read-write DISABLED Disabled. Input function is not inverted. 0 ENABLED Enabled. Input is function inverted. 0x1 DIGIMODE Select Digital mode. 8 1 read-write ANALOG Disable digital mode. Digital input set to 0. 0 DIGITAL Enable Digital mode. Digital input is enabled. 0x1 OD Controls open-drain mode. 9 1 read-write NORMAL Normal. Normal push-pull output 0 OPEN_DRAIN Open-drain. Simulated open-drain output (high drive disabled). 0x1 GINT0 Group GPIO input interrupt (GINT0/1) GINT GINT 0x40002000 0 0x48 registers GINT0 2 CTRL GPIO grouped interrupt control register 0 32 read-write 0 0x7 INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. 0 1 read-write NO_REQUEST No request. No interrupt request is pending. 0 REQUEST_ACTIVE Request active. Interrupt request is active. 0x1 COMB Combine enabled inputs for group interrupt 1 1 read-write OR Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 0x1 TRIG Group interrupt trigger 2 1 read-write EDGE_TRIGGERED Edge-triggered. 0 LEVEL_TRIGGERED Level-triggered. 0x1 2 0x4 PORT_POL[%s] GPIO grouped interrupt port 0 polarity register 0x20 32 read-write 0xFFFFFFFF 0xFFFFFFFF POL Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. 0 32 read-write 2 0x4 PORT_ENA[%s] GPIO grouped interrupt port 0 enable register 0x40 32 read-write 0 0xFFFFFFFF ENA Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt. 0 32 read-write GINT1 Group GPIO input interrupt (GINT0/1) GINT 0x40003000 0 0x48 registers GINT1 3 PINT Pin interrupt and pattern match (PINT) PINT PINT 0x40004000 0 0x34 registers PIN_INT0 4 PIN_INT1 5 PIN_INT2 6 PIN_INT3 7 PIN_INT4 32 PIN_INT5 33 PIN_INT6 34 PIN_INT7 35 ISEL Pin Interrupt Mode register 0 32 read-write 0 0xFF PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 0 8 read-write IENR Pin interrupt level or rising edge interrupt enable register 0x4 32 read-write 0 0xFF ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. 0 8 read-write SIENR Pin interrupt level or rising edge interrupt set register 0x8 32 write-only 0 0 SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 0 8 write-only CIENR Pin interrupt level (rising edge interrupt) clear register 0xC 32 write-only 0 0 CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. 0 8 write-only IENF Pin interrupt active level or falling edge interrupt enable register 0x10 32 read-write 0 0xFF ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. 0 8 read-write SIENF Pin interrupt active level or falling edge interrupt set register 0x14 32 write-only 0 0 SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. 0 8 write-only CIENF Pin interrupt active level or falling edge interrupt clear register 0x18 32 write-only 0 0 CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. 0 8 write-only RISE Pin interrupt rising edge register 0x1C 32 read-write 0 0xFF RDET Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 0 8 read-write FALL Pin interrupt falling edge register 0x20 32 read-write 0 0xFF FDET Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. 0 8 read-write IST Pin interrupt status register 0x24 32 read-write 0 0xFF PSTAT Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 0 8 read-write PMCTRL Pattern match interrupt control register 0x28 32 read-write 0 0xFF000003 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 0 1 read-write PIN_INTERRUPT Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 0 PATTERN_MATCH Pattern match. Interrupts are driven in response to pattern matches. 0x1 ENA_RXEV Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 1 1 read-write DISABLED Disabled. RXEV output to the CPU is disabled. 0 ENABLED Enabled. RXEV output to the CPU is enabled. 0x1 PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. 24 8 read-write PMSRC Pattern match interrupt bit-slice source register 0x2C 32 read-write 0 0xFFFFFF00 SRC0 Selects the input source for bit slice 0 8 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 0x7 SRC1 Selects the input source for bit slice 1 11 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 0x7 SRC2 Selects the input source for bit slice 2 14 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 0x7 SRC3 Selects the input source for bit slice 3 17 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 0x7 SRC4 Selects the input source for bit slice 4 20 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 0x7 SRC5 Selects the input source for bit slice 5 23 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 0x7 SRC6 Selects the input source for bit slice 6 26 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 0x7 SRC7 Selects the input source for bit slice 7 29 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 0x7 PMCFG Pattern match interrupt bit slice configuration register 0x30 32 read-write 0 0xFFFFFF7F PROD_ENDPTS0 Determines whether slice 0 is an endpoint. 0 1 read-write NO_EFFECT No effect. Slice 0 is not an endpoint. 0 ENDPOINT endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS1 Determines whether slice 1 is an endpoint. 1 1 read-write NO_EFFECT No effect. Slice 1 is not an endpoint. 0 ENDPOINT endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS2 Determines whether slice 2 is an endpoint. 2 1 read-write NO_EFFECT No effect. Slice 2 is not an endpoint. 0 ENDPOINT endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS3 Determines whether slice 3 is an endpoint. 3 1 read-write NO_EFFECT No effect. Slice 3 is not an endpoint. 0 ENDPOINT endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS4 Determines whether slice 4 is an endpoint. 4 1 read-write NO_EFFECT No effect. Slice 4 is not an endpoint. 0 ENDPOINT endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS5 Determines whether slice 5 is an endpoint. 5 1 read-write NO_EFFECT No effect. Slice 5 is not an endpoint. 0 ENDPOINT endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS6 Determines whether slice 6 is an endpoint. 6 1 read-write NO_EFFECT No effect. Slice 6 is not an endpoint. 0 ENDPOINT endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 0x1 CFG0 Specifies the match contribution condition for bit slice 0. 8 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG1 Specifies the match contribution condition for bit slice 1. 11 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG2 Specifies the match contribution condition for bit slice 2. 14 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG3 Specifies the match contribution condition for bit slice 3. 17 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG4 Specifies the match contribution condition for bit slice 4. 20 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG5 Specifies the match contribution condition for bit slice 5. 23 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG6 Specifies the match contribution condition for bit slice 6. 26 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG7 Specifies the match contribution condition for bit slice 7. 29 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 SECPINT Pin interrupt and pattern match (PINT) PINT 0x40005000 0 0x34 registers SEC_GPIO_INT0_IRQ0 50 SEC_GPIO_INT0_IRQ1 51 INPUTMUX Input multiplexing (INPUT MUX) INPUTMUX 0x40006000 0 0x7B4 registers 7 0x4 SCT0_INMUX[%s] Input mux register for SCT0 input 0 32 read-write 0x1F 0x1F INP_NInput number to SCT0 inputs 0 to 6.read-write05 4 0x4 TIMER0CAPTSEL[%s] Capture select registers for TIMER0 inputs 0x20 32 read-write 0x1F 0x1F CAPTSELInput number to TIMER%s capture inputs 0 to 4read-write05 4 0x4 TIMER1CAPTSEL[%s] Capture select registers for TIMER1 inputs 0x40 32 read-write 0x1F 0x1F CAPTSELInput number to TIMER%s capture inputs 0 to 4read-write05 4 0x4 TIMER2CAPTSEL[%s] Capture select registers for TIMER2 inputs 0x60 32 read-write 0x1F 0x1F CAPTSELInput number to TIMER%s capture inputs 0 to 4read-write05 8 0x4 PINTSEL[%s] Pin interrupt select register 0xC0 32 read-write 0x7F 0x7F INTPIN Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. 0 7 read-write 23 0x4 DMA0_ITRIG_INMUX[%s] Trigger select register for DMA0 channel 0xE0 32 read-write 0x1F 0x1F INPTrigger input number (decimal value) for DMA channel n (n = 0 to 22).read-write05 4 0x4 DMA0_OTRIG_INMUX[%s] DMA0 output trigger selection to become DMA0 trigger 0x160 32 read-write 0x1F 0x1F INP DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). 0 5 read-write FREQMEAS_REF Selection for frequency measurement reference clock 0x180 32 read-write 0x1F 0x1F CLKIN Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 0 5 read-write FREQMEAS_TARGET Selection for frequency measurement target clock 0x184 32 read-write 0x1F 0x1F CLKIN Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 0 5 read-write 4 0x4 TIMER3CAPTSEL[%s] Capture select registers for TIMER3 inputs 0x1A0 32 read-write 0x1F 0x1F CAPTSELInput number to TIMER%s capture inputs 0 to 4read-write05 4 0x4 TIMER4CAPTSEL[%s] Capture select registers for TIMER4 inputs 0x1C0 32 read-write 0x1F 0x1F CAPTSELInput number to TIMER%s capture inputs 0 to 4read-write05 2 0x4 PINTSECSEL[%s] Pin interrupt secure select register 0x1E0 32 read-write 0x3F 0x3F INTPIN Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. 0 6 read-write 10 0x4 DMA1_ITRIG_INMUX[%s] Trigger select register for DMA1 channel 0x200 32 read-write 0xF 0xF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 9). 0 4 read-write val0 Pin interrupt 0 0 val1 Pin interrupt 1 0x1 val2 Pin interrupt 2 0x2 val3 Pin interrupt 3 0x3 val4 Timer CTIMER0 Match 0 0x4 val5 Timer CTIMER0 Match 1 0x5 val6 Timer CTIMER2 Match 0 0x6 val7 Timer CTIMER4 Match 0 0x7 val8 DMA1 output trigger mux 0 0x8 val9 DMA1 output trigger mux 1 0x9 val10 DMA1 output trigger mux 2 0xA val11 DMA1 output trigger mux 3 0xB val12 SCT0 DMA request 0 0xC val13 SCT0 DMA request 1 0xD val14 HASH DMA RX trigger 0xE val15 None 0xF 4 0x4 DMA1_OTRIG_INMUX[%s] DMA1 output trigger selection to become DMA1 trigger 0x240 32 read-write 0xF 0xF INP DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). 0 4 read-write DMA0_REQ_ENA Enable DMA0 requests 0x740 32 read-write 0x7FFFFF 0x7FFFFF REQ_ENA Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. 0 23 read-write DMA0_REQ_ENA_SET Set one or several bits in DMA0_REQ_ENA register 0x748 32 write-only 0 0x7FFFFF SET Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register 0 23 write-only DMA0_REQ_ENA_CLR Clear one or several bits in DMA0_REQ_ENA register 0x750 32 write-only 0 0x7FFFFF CLR Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register 0 23 write-only DMA1_REQ_ENA Enable DMA1 requests 0x760 32 read-write 0x3FF 0x3FF REQ_ENA Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. 0 10 read-write DMA1_REQ_ENA_SET Set one or several bits in DMA1_REQ_ENA register 0x768 32 write-only 0 0x3FF SET Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register 0 10 write-only DMA1_REQ_ENA_CLR Clear one or several bits in DMA1_REQ_ENA register 0x770 32 write-only 0 0x3FF CLR Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register 0 10 write-only DMA0_ITRIG_ENA Enable DMA0 triggers 0x780 32 read-write 0x3FFFFF 0x3FFFFF ITRIG_ENA Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. 0 22 read-write DMA0_ITRIG_ENA_SET Set one or several bits in DMA0_ITRIG_ENA register 0x788 32 write-only 0 0x3FFFFF SET Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register 0 22 write-only DMA0_ITRIG_ENA_CLR Clear one or several bits in DMA0_ITRIG_ENA register 0x790 32 write-only 0 0x3FFFFF CLR Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register 0 22 write-only DMA1_ITRIG_ENA Enable DMA1 triggers 0x7A0 32 read-write 0x7FFF 0x7FFF ITRIG_ENA Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. 0 15 read-write DMA1_ITRIG_ENA_SET Set one or several bits in DMA1_ITRIG_ENA register 0x7A8 32 write-only 0 0x7FFF SET Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register 0 15 write-only DMA1_ITRIG_ENA_CLR Clear one or several bits in DMA1_ITRIG_ENA register 0x7B0 32 write-only 0 0x7FFF CLR Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register 0 15 write-only CTIMER0 Standard counter/timers (CTIMER0 to 4) CTIMER CTIMER 0x40008000 0 0x88 registers CTIMER0 10 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0 32 read-write 0 0xFF MR0INT Interrupt flag for match channel 0. 0 1 read-write MR1INT Interrupt flag for match channel 1. 1 1 read-write MR2INT Interrupt flag for match channel 2. 2 1 read-write MR3INT Interrupt flag for match channel 3. 3 1 read-write CR0INT Interrupt flag for capture channel 0 event. 4 1 read-write CR1INT Interrupt flag for capture channel 1 event. 5 1 read-write CR2INT Interrupt flag for capture channel 2 event. 6 1 read-write CR3INT Interrupt flag for capture channel 3 event. 7 1 read-write TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 32 read-write 0 0x3 CEN Counter enable. 0 1 read-write DISABLED Disabled.The counters are disabled. 0 ENABLED Enabled. The Timer Counter and Prescale Counter are enabled. 0x1 CRST Counter reset. 1 1 read-write DISABLED Disabled. Do nothing. 0 ENABLED Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 0x1 TC Timer Counter 0x8 32 read-write 0 0xFFFFFFFF TCVAL Timer counter value. 0 32 read-write PR Prescale Register 0xC 32 read-write 0 0xFFFFFFFF PRVAL Prescale counter value. 0 32 read-write PC Prescale Counter 0x10 32 read-write 0 0xFFFFFFFF PCVAL Prescale counter value. 0 32 read-write MCR Match Control Register 0x14 32 read-write 0 0xF000FFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 read-write MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 1 read-write MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 1 read-write MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 1 read-write MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 1 read-write MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 1 read-write MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 1 read-write MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 1 read-write MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 1 read-write MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 1 read-write MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 1 read-write MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 1 read-write MR0RL Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 24 1 read-write MR1RL Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 25 1 read-write MR2RL Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 26 1 read-write MR3RL Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR). 27 1 read-write 4 0x4 MR[%s] Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x18 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 32 read-write 0 0xFFF CAP0RE Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 0 1 read-write CAP0FE Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 1 1 read-write CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 2 1 read-write CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 3 1 read-write CAP1FE Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 4 1 read-write CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 5 1 read-write CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 6 1 read-write CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 7 1 read-write CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 8 1 read-write CAP3RE Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 9 1 read-write CAP3FE Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 10 1 read-write CAP3I Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. 11 1 read-write 4 0x4 CR[%s] Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x2C 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only EMR External Match Register. The EMR controls the match function and the external match pins. 0x3C 32 read-write 0 0xFFF EM0 External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 0 1 read-write EM1 External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1 1 read-write EM2 External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 2 1 read-write EM3 External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 3 1 read-write EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 32 read-write 0 0xFF CTMODE Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 2 read-write TIMER Timer Mode. Incremented every rising APB bus clock edge. 0 COUNTER_RISING_EDGE Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 COUNTER_FALLING_EDGE Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 COUNTER_DUAL_EDGE Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 2 2 read-write CHANNEL_0 Channel 0. CAPn.0 for CTIMERn 0 CHANNEL_1 Channel 1. CAPn.1 for CTIMERn 0x1 CHANNEL_2 Channel 2. CAPn.2 for CTIMERn 0x2 CHANNEL_3 Channel 3. CAPn.3 for CTIMERn 0x3 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. 4 1 read-write SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 5 3 read-write CHANNEL_0_RISING Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0 CHANNEL_0_FALLING Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0x1 CHANNEL_1_RISING Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x2 CHANNEL_1_FALLING Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x3 CHANNEL_2_RISING Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x4 CHANNEL_2_FALLING Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x5 PWMC PWM Control Register. This register enables PWM mode for the external match pins. 0x74 32 read-write 0 0xF PWMEN0 PWM mode enable for channel0. 0 1 read-write MATCH Match. CTIMERn_MAT0 is controlled by EM0. 0 PWM PWM. PWM mode is enabled for CTIMERn_MAT0. 0x1 PWMEN1 PWM mode enable for channel1. 1 1 read-write MATCH Match. CTIMERn_MAT01 is controlled by EM1. 0 PWM PWM. PWM mode is enabled for CTIMERn_MAT1. 0x1 PWMEN2 PWM mode enable for channel2. 2 1 read-write MATCH Match. CTIMERn_MAT2 is controlled by EM2. 0 PWM PWM. PWM mode is enabled for CTIMERn_MAT2. 0x1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 3 1 read-write MATCH Match. CTIMERn_MAT3 is controlled by EM3. 0 PWM PWM. PWM mode is enabled for CT132Bn_MAT3. 0x1 4 0x4 MSR[%s] Match Shadow Register 0x78 32 read-write 0 0xFFFFFFFF SHADOW Timer counter match shadow value. 0 32 read-write CTIMER1 Standard counter/timers (CTIMER0 to 4) CTIMER 0x40009000 0 0x88 registers CTIMER1 11 CTIMER2 Standard counter/timers (CTIMER0 to 4) CTIMER 0x40028000 0 0x88 registers CTIMER2 36 CTIMER3 Standard counter/timers (CTIMER0 to 4) CTIMER 0x40029000 0 0x88 registers CTIMER3 13 CTIMER4 Standard counter/timers (CTIMER0 to 4) CTIMER 0x4002A000 0 0x88 registers CTIMER4 37 WWDT Windowed Watchdog Timer (WWDT) WWDT 0x4000C000 0 0x1C registers WDT_BOD 0 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0 32 read-write 0 0x3F WDEN Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. 0 1 read-write STOP Stop. The watchdog timer is stopped. 0 RUN Run. The watchdog timer is running. 0x1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 1 1 read-write INTERRUPT Interrupt. A watchdog time-out will not cause a chip reset. 0 RESET Reset. A watchdog time-out will cause a chip reset. 0x1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1. 2 1 read-write WDINT Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 3 1 read-write WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 4 1 read-write FLEXIBLE Flexible. The watchdog time-out value (TC) can be changed at any time. 0 THRESHOLD Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 0x1 TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x4 32 read-write 0xFF 0xFFFFFF COUNT Watchdog time-out value. 0 24 read-write FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. 0x8 32 write-only 0 0 FEED Feed value should be 0xAA followed by 0x55. 0 8 write-only TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0xC 32 read-only 0xFF 0xFFFFFF COUNT Counter timer value. 0 24 read-only WARNINT Watchdog Warning Interrupt compare value. 0x14 32 read-write 0 0x3FF WARNINT Watchdog warning interrupt compare value. 0 10 read-write WINDOW Watchdog Window compare value. 0x18 32 read-write 0xFFFFFF 0xFFFFFF WINDOW Watchdog window value. 0 24 read-write MRT0 Multi-Rate Timer (MRT) MRT 0x4000D000 0 0xFC registers MRT0 9 4 0x10 CHANNEL[%s] no description available 0 INTVAL MRT Time interval value register. This value is loaded into the TIMER register. 0 32 read-write 0 0x80FFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 0 24 read-write LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 31 1 read-write NO_FORCE_LOAD No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. 0 FORCE_LOAD Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 0x1 TIMER MRT Timer register. This register reads the value of the down-counter. 0x4 32 read-only 0xFFFFFF 0xFFFFFF VALUE Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 24 read-only CTRL MRT Control register. This register controls the MRT modes. 0x8 32 read-write 0 0x7 INTEN Enable the TIMERn interrupt. 0 1 read-write DISABLED Disabled. TIMERn interrupt is disabled. 0 ENABLED Enabled. TIMERn interrupt is enabled. 0x1 MODE Selects timer mode. 1 2 read-write REPEAT_INTERRUPT_MODE Repeat interrupt mode. 0 ONE_SHOT_INTERRUPT_MODE One-shot interrupt mode. 0x1 ONE_SHOT_STALL_MODE One-shot stall mode. 0x2 STAT MRT Status register. 0xC 32 read-write 0 0x7 INTFLAG Monitors the interrupt flag. 0 1 read-write NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 0x1 RUN Indicates the state of TIMERn. This bit is read-only. 1 1 read-write IDLE_STATE Idle state. TIMERn is stopped. 0 RUNNING Running. TIMERn is running. 0x1 INUSE Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. 2 1 read-write NO This channel is not in use. 0 YES This channel is in use. 0x1 MODCFG Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. 0xF0 32 read-write 0x173 0x800001FF NOC Identifies the number of channels in this MRT.(4 channels on this device.) 0 4 read-write NOB Identifies the number of timer bits in this MRT. (24 bits wide on this device.) 4 5 read-write MULTITASK Selects the operating mode for the INUSE flags and the IDLE_CH register. 31 1 read-write HARDWARE_STATUS_MODE Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. 0 MULTI_TASK_MODE Multi-task mode. 0x1 IDLE_CH Idle channel register. This register returns the number of the first idle channel. 0xF4 32 read-only 0 0xF0 CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details. 4 4 read-only IRQ_FLAG Global interrupt flag register 0xF8 32 read-write 0 0xF GFLAG0 Monitors the interrupt flag of TIMER0. 0 1 read-write NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 0x1 GFLAG1 Monitors the interrupt flag of TIMER1. See description of channel 0. 1 1 read-write GFLAG2 Monitors the interrupt flag of TIMER2. See description of channel 0. 2 1 read-write GFLAG3 Monitors the interrupt flag of TIMER3. See description of channel 0. 3 1 read-write UTICK0 Micro-tick Timer (UTICK) UTICK 0x4000E000 0 0x20 registers UTICK0 8 CTRL Control register. 0 32 read-write 0 0xFFFFFFFF DELAYVAL Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. 0 31 read-write REPEAT Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. 31 1 read-write STAT Status register. 0x4 32 read-write 0 0x3 INTR Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag. 0 1 read-write ACTIVE Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. 1 1 read-write CFG Capture configuration register. 0x8 32 read-write 0 0xF0F CAPEN0 Enable Capture 0. 1 = Enabled, 0 = Disabled. 0 1 read-write CAPEN1 Enable Capture 1. 1 = Enabled, 0 = Disabled. 1 1 read-write CAPEN2 Enable Capture 2. 1 = Enabled, 0 = Disabled. 2 1 read-write CAPEN3 Enable Capture 3. 1 = Enabled, 0 = Disabled. 3 1 read-write CAPPOL0 Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. 8 1 read-write CAPPOL1 Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. 9 1 read-write CAPPOL2 Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. 10 1 read-write CAPPOL3 Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. 11 1 read-write CAPCLR Capture clear register. 0xC 32 write-only 0 0 CAPCLR0 Clear capture 0. Writing 1 to this bit clears the CAP0 register value. 0 1 write-only CAPCLR1 Clear capture 1. Writing 1 to this bit clears the CAP1 register value. 1 1 write-only CAPCLR2 Clear capture 2. Writing 1 to this bit clears the CAP2 register value. 2 1 write-only CAPCLR3 Clear capture 3. Writing 1 to this bit clears the CAP3 register value. 3 1 write-only 4 0x4 CAP[%s] Capture register . 0x10 32 read-only 0 0xFFFFFFFF CAP_VALUE Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event. 0 31 read-only VALID Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. 31 1 read-only ANACTRL ANALOGCTRL ANACTRL 0x40013000 0 0x104 registers ANALOG_CTRL_STATUS Analog Macroblock Identity registers, Flash Status registers 0x4 32 read-only 0x50000000 0xF0003FFF FLASH_PWRDWN Flash Power Down status. 12 1 read-only PWRUP Flash is not in power down mode. 0 PWRDWN Flash is in power down mode. 0x1 FLASH_INIT_ERROR Flash initialization error status. 13 1 read-only NOERROR No error. 0 ERROR At least one error occured during flash initialization.. 0x1 FREQ_ME_CTRL Frequency Measure function control register 0xC 32 read-write 0 0xFFFFFFFF CAPVAL_SCALE Frequency measure result /Frequency measur scale 0 31 read-write PROG Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0). 31 1 read-write FRO192M_CTRL 192MHz Free Running OScillator (FRO) Control register 0x10 32 read-write 0x80D01A 0xF3FFFFBF ENA_12MHZCLK 12 MHz clock control. 14 1 read-write DISABLE 12 MHz clock is disabled. 0 ENABLE 12 MHz clock is enabled. 0x1 ENA_48MHZCLK 48 MHz clock control. 15 1 read-write ENABLE 48 MHz clock is enabled. 0x1 DAC_TRIM Frequency trim. 16 8 read-write USBCLKADJ If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets. 24 1 read-write USBMODCHG If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. 25 1 read-only ENA_96MHZCLK 96 MHz clock control. 30 1 read-write DISABLE 96 MHz clock is disabled. 0 ENABLE 96 MHz clock is enabled. 0x1 FRO192M_STATUS 192MHz Free Running OScillator (FRO) Status register 0x14 32 read-write 0x3 0x3 CLK_VALID Output clock valid signal. Indicates that CCO clock has settled. 0 1 read-only NOCLKOUT No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). 0 CLKOUT Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). 0x1 ATB_VCTRL CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal. 1 1 read-only XO32M_CTRL High speed Crystal Oscillator Control register 0x20 32 read-write 0x21428A 0x1FFFFFFE ACBUF_PASS_ENABLE Bypass enable of XO AC buffer enable in pll and top level. 22 1 read-write DISABLE XO AC buffer bypass is disabled. 0 ENABLE XO AC buffer bypass is enabled. 0x1 ENABLE_PLL_USB_OUT Enable High speed Crystal oscillator output to USB HS PLL. 23 1 read-write DISABLE High speed Crystal oscillator output to USB HS PLL is disabled. 0 ENABLE High speed Crystal oscillator output to USB HS PLL is enabled. 0x1 ENABLE_SYSTEM_CLK_OUT Enable XO 32 MHz output to CPU system. 24 1 read-write DISABLE High speed Crystal oscillator output to CPU system is disabled. 0 ENABLE High speed Crystal oscillator output to CPU system is enabled. 0x1 XO32M_STATUS High speed Crystal Oscillator Status register 0x24 32 read-only 0 0x1 XO_READY Indicates XO out frequency statibilty. 0 1 read-only NOT_STABLE XO output frequency is not yet stable. 0 STABLE XO output frequency is stable. 0x1 BOD_DCDC_INT_CTRL Brown Out Detectors (BoDs) & DCDC interrupts generation control register 0x30 32 read-write 0 0x3F BODVBAT_INT_ENABLE BOD VBAT interrupt control. 0 1 read-write DISABLE BOD VBAT interrupt is disabled. 0 ENABLE BOD VBAT interrupt is enabled. 0x1 BODVBAT_INT_CLEAR BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. 1 1 read-write BODCORE_INT_ENABLE BOD CORE interrupt control. 2 1 read-write DISABLE BOD CORE interrupt is disabled. 0 ENABLE BOD CORE interrupt is enabled. 0x1 BODCORE_INT_CLEAR BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. 3 1 read-write DCDC_INT_ENABLE DCDC interrupt control. 4 1 read-write DISABLE DCDC interrupt is disabled. 0 ENABLE DCDC interrupt is enabled. 0x1 DCDC_INT_CLEAR DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. 5 1 read-write BOD_DCDC_INT_STATUS BoDs & DCDC interrupts status register 0x34 32 read-only 0x104 0x1FF BODVBAT_STATUS BOD VBAT Interrupt status before Interrupt Enable. 0 1 read-only NOT_PENDING No interrupt pending.. 0 PENDING Interrupt pending.. 0x1 BODVBAT_INT_STATUS BOD VBAT Interrupt status after Interrupt Enable. 1 1 read-only NOT_PENDING No interrupt pending.. 0 PENDING Interrupt pending.. 0x1 BODVBAT_VAL Current value of BOD VBAT power status output. 2 1 read-only NOT_OK VBAT voltage level is below the threshold. 0 OK VBAT voltage level is above the threshold. 0x1 BODCORE_STATUS BOD CORE Interrupt status before Interrupt Enable. 3 1 read-only NOT_PENDING No interrupt pending.. 0 PENDING Interrupt pending.. 0x1 BODCORE_INT_STATUS BOD CORE Interrupt status after Interrupt Enable. 4 1 read-only NOT_PENDING No interrupt pending.. 0 PENDING Interrupt pending.. 0x1 BODCORE_VAL Current value of BOD CORE power status output. 5 1 read-only NOT_OK CORE voltage level is below the threshold. 0 OK CORE voltage level is above the threshold. 0x1 DCDC_STATUS DCDC Interrupt status before Interrupt Enable. 6 1 read-only NOT_PENDING No interrupt pending.. 0 PENDING Interrupt pending.. 0x1 DCDC_INT_STATUS DCDC Interrupt status after Interrupt Enable. 7 1 read-only NOT_PENDING No interrupt pending.. 0 PENDING Interrupt pending.. 0x1 DCDC_VAL Current value of DCDC power status output. 8 1 read-only NOT_OK DCDC output Voltage is below the targeted regulation level. 0 OK DCDC output Voltage is above the targeted regulation level. 0x1 RINGO0_CTRL First Ring Oscillator module control register. 0x40 32 read-write 0x40 0x803F1FFF SL Select short or long ringo (for all ringos types). 0 1 read-write SHORT Select short ringo (few elements). 0 LONG Select long ringo (many elements). 0x1 FS Ringo frequency output divider. 1 1 read-write FAST High frequency output (frequency lower than 100 MHz). 0 SLOW Low frequency output (frequency lower than 10 MHz). 0x1 SWN_SWP PN-Ringos (P-Transistor and N-Transistor processing) control. 2 2 read-write NORMAL Normal mode. 0 P_MONITOR P-Monitor mode. Measure with weak P transistor. 0x1 N_MONITOR P-Monitor mode. Measure with weak N transistor. 0x2 FORBIDDEN Don't use. 0x3 PD Ringo module Power control. 4 1 read-write POWERED_ON The Ringo module is enabled. 0 POWERED_DOWN The Ringo module is disabled. 0x1 E_ND0 First NAND2-based ringo control. 5 1 read-write DISABLE First NAND2-based ringo is disabled. 0 ENABLE First NAND2-based ringo is enabled. 0x1 E_ND1 Second NAND2-based ringo control. 6 1 read-write DISABLE Second NAND2-based ringo is disabled. 0 ENABLE Second NAND2-based ringo is enabled. 0x1 E_NR0 First NOR2-based ringo control. 7 1 read-write DISABLE First NOR2-based ringo is disabled. 0 ENABLE First NOR2-based ringo is enabled. 0x1 E_NR1 Second NOR2-based ringo control. 8 1 read-write DISABLE Second NORD2-based ringo is disabled. 0 ENABLE Second NORD2-based ringo is enabled. 0x1 E_IV0 First Inverter-based ringo control. 9 1 read-write DISABLE First INV-based ringo is disabled. 0 ENABLE First INV-based ringo is enabled. 0x1 E_IV1 Second Inverter-based ringo control. 10 1 read-write DISABLE Second INV-based ringo is disabled. 0 ENABLE Second INV-based ringo is enabled. 0x1 E_PN0 First PN (P-Transistor and N-Transistor processing) monitor control. 11 1 read-write DISABLE First PN-based ringo is disabled. 0 ENABLE First PN-based ringo is enabled. 0x1 E_PN1 Second PN (P-Transistor and N-Transistor processing) monitor control. 12 1 read-write DISABLE Second PN-based ringo is disabled. 0 ENABLE Second PN-based ringo is enabled. 0x1 DIVISOR Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) 16 4 read-write DIV_UPDATE_REQ Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. 31 1 read-only RINGO1_CTRL Second Ring Oscillator module control register. 0x44 32 read-write 0x40 0x803F01FF S Select short or long ringo (for all ringos types). 0 1 read-write SHORT Select short ringo (few elements). 0 LONG Select long ringo (many elements). 0x1 FS Ringo frequency output divider. 1 1 read-write FAST High frequency output (frequency lower than 100 MHz). 0 SLOW Low frequency output (frequency lower than 10 MHz). 0x1 PD Ringo module Power control. 2 1 read-write POWERED_ON The Ringo module is enabled. 0 POWERED_DOWN The Ringo module is disabled. 0x1 E_R24 . 3 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_R35 . 4 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M2 Metal 2 (M2) monitor control. 5 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M3 Metal 3 (M3) monitor control. 6 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M4 Metal 4 (M4) monitor control. 7 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M5 Metal 5 (M5) monitor control. 8 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 DIVISOR Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) 16 4 read-write DIV_UPDATE_REQ Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. 31 1 read-only RINGO2_CTRL Third Ring Oscillator module control register. 0x48 32 read-write 0x40 0x803F01FF S Select short or long ringo (for all ringos types). 0 1 read-write SHORT Select short ringo (few elements). 0 LONG Select long ringo (many elements). 0x1 FS Ringo frequency output divider. 1 1 read-write FAST High frequency output (frequency lower than 100 MHz). 0 SLOW Low frequency output (frequency lower than 10 MHz). 0x1 PD Ringo module Power control. 2 1 read-write POWERED_ON The Ringo module is enabled. 0 POWERED_DOWN The Ringo module is disabled. 0x1 E_R24 . 3 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_R35 . 4 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M2 Metal 2 (M2) monitor control. 5 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M3 Metal 3 (M3) monitor control. 6 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M4 Metal 4 (M4) monitor control. 7 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 E_M5 Metal 5 (M5) monitor control. 8 1 read-write DISABLE Ringo is disabled. 0 ENABLE Ringo is enabled. 0x1 DIVISOR Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) 16 4 read-write DIV_UPDATE_REQ Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete. 31 1 read-only USBHS_PHY_CTRL USB High Speed Phy Control 0x100 32 read-write 0x8 0xF usb_vbusvalid_ext Override value for Vbus if using external detectors. 0 1 read-write usb_id_ext Override value for ID if using external detectors. 1 1 read-write PMC PMC PMC 0x40020000 0 0xCC registers RESETCTRL Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] 0x8 32 read-write 0 0xF DPDWAKEUPRESETENABLE Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). 0 1 read-write DISABLE Reset event from DEEP POWER DOWN mode is disable. 0 ENABLE Reset event from DEEP POWER DOWN mode is enable. 0x1 BODVBATRESETENABLE BOD VBAT reset enable. 1 1 read-write DISABLE BOD VBAT reset is disable. 0 ENABLE BOD VBAT reset is enable. 0x1 SWRRESETENABLE Software reset enable. 3 1 read-write DISABLE Software reset is disable. 0 ENABLE Software reset is enable. 0x1 BODVBAT VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] 0x30 32 read-write 0x47 0x7F TRIGLVL BoD trigger level. 0 5 read-write V_1P00 1.00 V. 0 V_1P10 1.10 V. 0x1 V_1P20 1.20 V. 0x2 V_1P30 1.30 V. 0x3 V_1P40 1.40 V. 0x4 V_1P50 1.50 V. 0x5 V_1P60 1.60 V. 0x6 V_1P65 1.65 V. 0x7 V_1P70 1.70 V. 0x8 V_1P75 1.75 V. 0x9 V_1P80 1.80 V. 0xA V_1P90 1.90 V. 0xB V_2P00 2.00 V. 0xC V_2P10 2.10 V. 0xD V_2P20 2.20 V. 0xE V_2P30 2.30 V. 0xF V_2P40 2.40 V. 0x10 V_2P50 2.50 V. 0x11 V_2P60 2.60 V. 0x12 V_2P70 2.70 V. 0x13 V_2P80 2.806 V. 0x14 V_2P90 2.90 V. 0x15 V_3P00 3.00 V. 0x16 V_3P10 3.10 V. 0x17 V_3P20 3.20 V. 0x18 V_3P30_2 3.30 V. 0x19 V_3P30_3 3.30 V. 0x1A V_3P30_4 3.30 V. 0x1B V_3P30_5 3.30 V. 0x1C V_3P30_6 3.30 V. 0x1D V_3P30_7 3.30 V. 0x1E V_3P30_8 3.30 V. 0x1F HYST BoD Hysteresis control. 5 2 read-write HYST_25MV 25 mV. 0 HYST_50MV 50 mV. 0x1 HYST_75MV 75 mV. 0x2 HYST_100MV 100 mV. 0x3 COMP Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] 0x50 32 read-write 0xA 0xFF7FFE HYST Hysteris when hyst = '1'. 1 1 read-write DISABLE Hysteresis is disable. 0 ENABLE Hysteresis is enable. 0x1 VREFINPUT Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). 2 1 read-write INTERNALREF Select internal VREF. 0 VDDA Select VDDA. 0x1 LOWPOWER Low power mode. 3 1 read-write HIGHSPEED High speed mode. 0 LOWSPEED Low power mode (Low speed). 0x1 PMUX Control word for P multiplexer:. 4 3 read-write VREF VREF (See fiedl VREFINPUT). 0 CMP0_A Pin P0_0. 0x1 CMP0_B Pin P0_9. 0x2 CMP0_C Pin P0_18. 0x3 CMP0_D Pin P1_14. 0x4 CMP0_E Pin P2_23. 0x5 NMUX Control word for N multiplexer:. 7 3 read-write VREF VREF (See field VREFINPUT). 0 CMP0_A Pin P0_0. 0x1 CMP0_B Pin P0_9. 0x2 CMP0_C Pin P0_18. 0x3 CMP0_D Pin P1_14. 0x4 CMP0_E Pin P2_23. 0x5 VREF Control reference voltage step, per steps of (VREFINPUT/31). 10 5 read-write FILTERCGF_SAMPLEMODE Control the filtering of the Analog Comparator output. 16 2 read-write BYPASS Bypass mode. 0 FILTER1CLK Filter 1 clock period. 0x1 FILTER2CLK Filter 2 clock period. 0x2 FILTER3CLK Filter 3 clock period. 0x3 FILTERCGF_CLKDIV Filter Clock divider. 18 3 read-write FILTER_1CLK_PERIOD Filter clock period duration equals 1 Analog Comparator clock period. 0 FILTER_2CLK_PERIOD Filter clock period duration equals 2 Analog Comparator clock period. 0x1 FILTER_4CLK_PERIOD Filter clock period duration equals 4 Analog Comparator clock period. 0x2 FILTER_8CLK_PERIOD Filter clock period duration equals 8 Analog Comparator clock period. 0x3 FILTER_16CLK_PERIOD Filter clock period duration equals 16 Analog Comparator clock period. 0x4 FILTER_32CLK_PERIOD Filter clock period duration equals 32 Analog Comparator clock period. 0x5 FILTER_64CLK_PERIOD Filter clock period duration equals 64 Analog Comparator clock period. 0x6 FILTER_128CLK_PERIOD Filter clock period duration equals 128 Analog Comparator clock period. 0x7 WAKEIOCAUSE Allows to identify the Wake-up I/O source from Deep Power Down mode 0x68 32 read-write 0 0xF WAKEUP0 Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. 0 1 read-only NOEVENT Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. 0 EVENT Last wake up from Deep Power down mode was triggred by wake up I/O 0. 0x1 WAKEUP1 Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. 1 1 read-write NOEVENT Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. 0 EVENT Last wake up from Deep Power down mode was triggred by wake up I/O 1. 0x1 WAKEUP2 Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. 2 1 read-write NOEVENT Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. 0 EVENT Last wake up from Deep Power down mode was triggred by wake up I/O 2. 0x1 WAKEUP3 Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. 3 1 read-write NOEVENT Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. 0 EVENT Last wake up from Deep Power down mode was triggred by wake up I/O 3. 0x1 STATUSCLK FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] 0x74 32 read-write 0x6 0x7 XTAL32KOK XTAL oscillator 32 K OK signal. 0 1 read-only XTAL32KOSCFAILURE XTAL32 KHZ oscillator oscillation failure detection indicator. 2 1 read-write NOFAIL No oscillation failure has been detetced since the last time this bit has been cleared.. 0 FAILURE At least one oscillation failure has been detetced since the last time this bit has been cleared.. 0x1 AOREG1 General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] 0x84 32 read-write 0 0xFFFFFFFF POR The last chip reset was caused by a Power On Reset. 4 1 read-write PADRESET The last chip reset was caused by a Pin Reset. 5 1 read-write BODRESET The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. 6 1 read-write SYSTEMRESET The last chip reset was caused by a System Reset requested by the ARM CPU. 7 1 read-write WDTRESET The last chip reset was caused by the Watchdog Timer. 8 1 read-write SWRRESET The last chip reset was caused by a Software event. 9 1 read-write DPDRESET_WAKEUPIO The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. 10 1 read-write DPDRESET_RTC The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. 11 1 read-write DPDRESET_OSTIMER The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. 12 1 read-write BOOTERRORCOUNTER ROM Boot Fatal Error Counter. 16 4 read-write RTCOSC32K RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] 0x98 32 read-write 0x3FF0008 0xC7FF800F SEL Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . 0 1 read-write FRO32K FRO 32 KHz. 0 XTAL32K XTAL 32KHz. 0x1 CLK1KHZDIV Actual division ratio is : 28 + CLK1KHZDIV. 1 3 read-write CLK1KHZDIVUPDATEREQ RTC 1KHz clock Divider status flag. 15 1 read-write CLK1HZDIV Actual division ratio is : 31744 + CLK1HZDIV. 16 11 read-write CLK1HZDIVHALT Halts the divider counter. 30 1 read-write CLK1HZDIVUPDATEREQ RTC 1Hz Divider status flag. 31 1 read-write OSTIMER OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] 0x9C 32 read-write 0x8 0xF SOFTRESET Active high reset. 0 1 read-write CLOCKENABLE Enable OSTIMER 32 KHz clock. 1 1 read-write DPDWAKEUPENABLE Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). 2 1 read-write OSC32KPD Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. 3 1 read-write PDRUNCFG0 Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] 0xB8 32 read-write 0xDEFFC4 0xFFFFEF PDEN_BODVBAT Controls power to VBAT Brown Out Detector (BOD). 3 1 read-write POWEREDON BOD VBAT is powered. 0 POWEREDOFF BOD VBAT is powered down. 0x1 PDEN_FRO32K Controls power to the Free Running Oscillator (FRO) 32 KHz. 6 1 read-write POWEREDON FRO32KHz is powered. 0 POWEREDOFF FRO32KHz is powered down. 0x1 PDEN_XTAL32K Controls power to crystal 32 KHz. 7 1 read-write POWEREDON Crystal 32KHz is powered. 0 POWEREDOFF Crystal 32KHz is powered down. 0x1 PDEN_XTAL32M Controls power to crystal 32 MHz. 8 1 read-write POWEREDON Crystal 32MHz is powered. 0 POWEREDOFF Crystal 32MHz is powered down. 0x1 PDEN_PLL0 Controls power to System PLL (also refered as PLL0). 9 1 read-write POWEREDON PLL0 is powered. 0 POWEREDOFF PLL0 is powered down. 0x1 PDEN_PLL1 Controls power to USB PLL (also refered as PLL1). 10 1 read-write POWEREDON PLL1 is powered. 0 POWEREDOFF PLL1 is powered down. 0x1 PDEN_USBFSPHY Controls power to USB Full Speed phy. 11 1 read-write POWEREDON USB Full Speed phy is powered. 0 POWEREDOFF USB Full Speed phy is powered down. 0x1 PDEN_USBHSPHY Controls power to USB High Speed Phy. 12 1 read-write POWEREDON USB HS phy is powered. 0 POWEREDOFF USB HS phy is powered down. 0x1 PDEN_COMP Controls power to Analog Comparator. 13 1 read-write POWEREDON Analog Comparator is powered. 0 POWEREDOFF Analog Comparator is powered down. 0x1 PDEN_LDOUSBHS Controls power to USB high speed LDO. 18 1 read-write POWEREDON USB high speed LDO is powered. 0 POWEREDOFF USB high speed LDO is powered down. 0x1 PDEN_AUXBIAS Controls power to auxiliary biasing (AUXBIAS) 19 1 read-write POWEREDON auxiliary biasing is powered. 0 POWEREDOFF auxiliary biasing is powered down. 0x1 PDEN_LDOXO32M Controls power to crystal 32 MHz LDO. 20 1 read-write POWEREDON crystal 32 MHz LDO is powered. 0 POWEREDOFF crystal 32 MHz LDO is powered down. 0x1 PDEN_RNG Controls power to all True Random Number Genetaor (TRNG) clock sources. 22 1 read-write POWEREDON TRNG clocks are powered. 0 POWEREDOFF TRNG clocks are powered down. 0x1 PDEN_PLL0_SSCG Controls power to System PLL (PLL0) Spread Spectrum module. 23 1 read-write POWEREDON PLL0 Sread spectrum module is powered. 0 POWEREDOFF PLL0 Sread spectrum module is powered down. 0x1 PDRUNCFGSET0 Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] 0xC0 32 write-only 0 0xFFFFFFFF PDRUNCFGSET0 Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. 0 32 write-only PDRUNCFGCLR0 Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] 0xC8 32 write-only 0 0xFFFFFFFF PDRUNCFGCLR0 Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. 0 32 write-only SYSCTL system controller SYSCTL 0x40023000 0 0x104 registers UPDATELCKOUT update lock out control 0 32 read-write 0 0x1 UPDATELCKOUT All Registers 0 1 read-write NORMAL_MODE Normal Mode. Can be written to. 0 PROTECTED_MODE Protected Mode. Cannot be written to. 0x1 8 0x4 0,1,2,3,4,5,6,7 FCCTRLSEL%s Selects the source for SCK going into Flexcomm 0 0x40 32 read-write 0 0x3030303 SCKINSEL Selects the source for SCK going into this Flexcomm. 0 2 read-writeOnce ORIG_FLEX_I2S_SIGNALS Selects the dedicated FCn_SCK function for this Flexcomm. 0 SHARED_SET0_I2S_SIGNALS SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). 0x1 SHARED_SET1_I2S_SIGNALS SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). 0x2 WSINSEL Selects the source for WS going into this Flexcomm. 8 2 read-write ORIG_FLEX_I2S_SIGNALS Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. 0 SHARED_SET0_I2S_SIGNALS WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). 0x1 SHARED_SET1_I2S_SIGNALS WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). 0x2 DATAINSEL Selects the source for DATA input to this Flexcomm. 16 2 read-write ORIG_FLEX_I2S_SIGNALS Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. 0 SHARED_SET0_I2S_SIGNALS Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). 0x1 SHARED_SET1_I2S_SIGNALS Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). 0x2 DATAOUTSEL Selects the source for DATA output from this Flexcomm. 24 2 read-write ORIG_FLEX_I2S_SIGNALS Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. 0 SHARED_SET0_I2S_SIGNALS Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). 0x1 SHARED_SET1_I2S_SIGNALS Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). 0x2 2 0x4 0,1 SHAREDCTRLSET%s Selects sources and data combinations for shared signal set 0. 0x80 32 read-write 0 0xFF0777 SHAREDSCKSEL Selects the source for SCK of this shared signal set. 0 3 read-write FLEXCOMM0 SCK for this shared signal set comes from Flexcomm 0. 0 FLEXCOMM1 SCK for this shared signal set comes from Flexcomm 1. 0x1 FLEXCOMM2 SCK for this shared signal set comes from Flexcomm 2. 0x2 FLEXCOMM3 SCK for this shared signal set comes from Flexcomm 3. 0x3 FLEXCOMM4 SCK for this shared signal set comes from Flexcomm 4. 0x4 FLEXCOMM5 SCK for this shared signal set comes from Flexcomm 5. 0x5 FLEXCOMM6 SCK for this shared signal set comes from Flexcomm 6. 0x6 FLEXCOMM7 SCK for this shared signal set comes from Flexcomm 7. 0x7 SHAREDWSSEL Selects the source for WS of this shared signal set. 4 3 read-write FLEXCOMM0 WS for this shared signal set comes from Flexcomm 0. 0 FLEXCOMM1 WS for this shared signal set comes from Flexcomm 1. 0x1 FLEXCOMM2 WS for this shared signal set comes from Flexcomm 2. 0x2 FLEXCOMM3 WS for this shared signal set comes from Flexcomm 3. 0x3 FLEXCOMM4 WS for this shared signal set comes from Flexcomm 4. 0x4 FLEXCOMM5 WS for this shared signal set comes from Flexcomm 5. 0x5 FLEXCOMM6 WS for this shared signal set comes from Flexcomm 6. 0x6 FLEXCOMM7 WS for this shared signal set comes from Flexcomm 7. 0x7 SHAREDDATASEL Selects the source for DATA input for this shared signal set. 8 3 read-write FLEXCOMM0 DATA input for this shared signal set comes from Flexcomm 0. 0 FLEXCOMM1 DATA input for this shared signal set comes from Flexcomm 1. 0x1 FLEXCOMM2 DATA input for this shared signal set comes from Flexcomm 2. 0x2 FLEXCOMM3 DATA input for this shared signal set comes from Flexcomm 3. 0x3 FLEXCOMM4 DATA input for this shared signal set comes from Flexcomm 4. 0x4 FLEXCOMM5 DATA input for this shared signal set comes from Flexcomm 5. 0x5 FLEXCOMM6 DATA input for this shared signal set comes from Flexcomm 6. 0x6 FLEXCOMM7 DATA input for this shared signal set comes from Flexcomm 7. 0x7 FC0DATAOUTEN Controls FC0 contribution to SHAREDDATAOUT for this shared set. 16 1 read-write INPUT Data output from FC0 does not contribute to this shared set. 0 OUTPUT Data output from FC0 does contribute to this shared set. 0x1 FC1DATAOUTEN Controls FC1 contribution to SHAREDDATAOUT for this shared set. 17 1 read-write INPUT Data output from FC1 does not contribute to this shared set. 0 OUTPUT Data output from FC1 does contribute to this shared set. 0x1 FC2DATAOUTEN Controls FC2 contribution to SHAREDDATAOUT for this shared set. 18 1 read-write INPUT Data output from FC2 does not contribute to this shared set. 0 OUTPUT Data output from FC2 does contribute to this shared set. 0x1 FC4DATAOUTEN Controls FC4 contribution to SHAREDDATAOUT for this shared set. 20 1 read-write INPUT Data output from FC4 does not contribute to this shared set. 0 OUTPUT Data output from FC4 does contribute to this shared set. 0x1 FC5DATAOUTEN Controls FC5 contribution to SHAREDDATAOUT for this shared set. 21 1 read-write INPUT Data output from FC5 does not contribute to this shared set. 0 OUTPUT Data output from FC5 does contribute to this shared set. 0x1 FC6DATAOUTEN Controls FC6 contribution to SHAREDDATAOUT for this shared set. 22 1 read-write INPUT Data output from FC6 does not contribute to this shared set. 0 OUTPUT Data output from FC6 does contribute to this shared set. 0x1 FC7DATAOUTEN Controls FC7 contribution to SHAREDDATAOUT for this shared set. 23 1 read-write INPUT Data output from FC7 does not contribute to this shared set. 0 OUTPUT Data output from FC7 does contribute to this shared set. 0x1 USB_HS_STATUS Status register for USB HS 0x100 32 read-write 0 0x1C0FF00 USBHS_3V_NOK USB_HS: Low voltage detection on 3.3V supply. 0 1 read-only SUPPLY_3V_OK 3v3 supply is good. 0 SUPPLY_3V_LOW 3v3 supply is too low. 0x1 RTC Real-Time Clock (RTC) RTC 0x4002C000 0 0x60 registers RTC 29 CTRL RTC control register 0 32 read-write 0x1 0x7FD SWRESET Software reset control 0 1 read-write NOT_IN_RESET Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. 0 IN_RESET In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. 0x1 ALARM1HZ RTC 1 Hz timer alarm flag status. 2 1 read-write NO_MATCH No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. 0 MATCH Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. 0x1 WAKE1KHZ RTC 1 kHz timer wake-up flag status. 3 1 read-write RUN Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. 0 TIMEOUT Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. 0x1 ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. 4 1 read-write DISABLE Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. 0x1 WAKEDPD_EN RTC 1 kHz timer wake-up enable for Deep power-down. 5 1 read-write DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. 0x1 RTC1KHZ_EN RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). 6 1 read-write DISABLE Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. 0 ENABLE Enable. The 1 kHz RTC timer is enabled. 0x1 RTC_EN RTC enable. 7 1 read-write DISABLE Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. 0 ENABLE Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. 0x1 RTC_OSC_PD RTC oscillator power-down control. 8 1 read-write POWER_UP See RTC_OSC_BYPASS 0 POWERED_DOWN RTC oscillator is powered-down. 0x1 RTC_OSC_BYPASS RTC oscillator bypass control. 9 1 read-write USED The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. 0 BYPASS The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. 0x1 RTC_SUBSEC_ENA RTC Sub-second counter control. 10 1 read-write POWER_UP The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'. 0 POWERED_DOWN The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode. 0x1 MATCH RTC match register 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF MATVAL Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. 0 32 read-write COUNT RTC counter register 0x8 32 read-write 0 0xFFFFFFFF VAL A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set. 0 32 read-write WAKE High-resolution/wake-up timer control register 0xC 32 read-write 0 0xFFFF VAL A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress. 0 16 read-write SUBSEC Sub-second counter register 0x10 32 read-write 0 0xFFFF SUBSEC A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. 0 15 read-only 8 0x4 GPREG[%s] General Purpose register 0x40 32 read-write 0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. 0 32 read-write OSTIMER Synchronous OS/Event timer with Wakeup Timer OSTIMER 0x4002D000 0 0x20 registers OS_EVENT 38 EVTIMERL EVTIMER Low Register 0 32 read-only 0 0xFFFFFFFF EVTIMER_COUNT_VALUE A read reflects the current value of the lower 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. 0 32 read-only EVTIMERH EVTIMER High Register 0x4 32 read-write 0 0xFFFFFFFF EVTIMER_COUNT_VALUE A read reflects the current value of the upper 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. 0 10 read-only CAPTUREn_L Local Capture Low Register for CPUn 0x8 32 read-only 0 0xFFFFFFFF CAPTUREn_VALUE A read reflects the value of the lower 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. 0 32 read-only CAPTUREn_H Local Capture High Register for CPUn 0xC 32 read-write 0 0xFFFFFFFF CAPTUREn_VALUE A read reflects the value of the upper 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. 0 10 read-only MATCHn_L Local Match Low Register for CPUn 0x10 32 read-write 0 0xFFFFFFFF MATCHn_VALUE The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. 0 32 read-write MATCHn_H Match High Register for CPUn 0x14 32 read-write 0 0xFFFFFFFF MATCHn_VALUE The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. 0 10 read-write OSEVENT_CTRL OS_EVENT TIMER Control Register for CPUn 0x1C 32 read-write 0 0x3 OSTIMER_INTRFLAG This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in the Match-register pair for the associated CPU This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match value is written into the MATCH_L/H registers 0 1 read-write OSTIMER_INTENA When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for each CPU. Each CPU reads its own local value at the same address. 1 1 read-write FLASH FLASH FLASH 0x40034000 0 0x1000 registers CMD command register 0 32 write-only 0 0xFFFFFFFF CMD command register. 0 32 write-only EVENT event register 0x4 32 write-only 0 0x7 RST When bit is set, the controller and flash are reset. 0 1 write-only WAKEUP When bit is set, the controller wakes up from whatever low power or powerdown mode was active. 1 1 write-only ABORT When bit is set, a running program/erase command is aborted. 2 1 write-only STARTA start (or only) address for next flash command 0x10 32 read-write 0 0x3FFFF STARTA Address / Start address for commands that take an address (range) as a parameter. 0 18 read-write STOPA end address for next flash command, if command operates on address ranges 0x14 32 read-write 0 0x3FFFF STOPA Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range). 0 18 read-write 4 0x4 DATAW[%s] data register, word 0-7; Memory data, or command parameter, or command result. 0x80 32 read-write 0 0xFFFFFFFF DATAW no description available 0 32 read-write INT_CLR_ENABLE Clear interrupt enable bits 0xFD8 32 write-only 0 0xF FAIL When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. 0 1 write-only ERR When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. 1 1 write-only DONE When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. 2 1 write-only ECC_ERR When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. 3 1 write-only INT_SET_ENABLE Set interrupt enable bits 0xFDC 32 write-only 0 0xF FAIL When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. 0 1 write-only ERR When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. 1 1 write-only DONE When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. 2 1 write-only ECC_ERR When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. 3 1 write-only INT_STATUS Interrupt status bits 0xFE0 32 read-write 0 0xF FAIL This status bit is set if execution of a (legal) command failed. 0 1 read-only ERR This status bit is set if execution of an illegal command is detected. 1 1 read-only DONE This status bit is set at the end of command execution. 2 1 read-only ECC_ERR This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic. 3 1 read-only INT_ENABLE Interrupt enable bits 0xFE4 32 read-write 0 0xF FAIL If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. 0 1 read-only ERR If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. 1 1 read-only DONE If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. 2 1 read-only ECC_ERR If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. 3 1 read-only INT_CLR_STATUS Clear interrupt status bits 0xFE8 32 write-only 0 0xF FAIL When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. 0 1 write-only ERR When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. 1 1 write-only DONE When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. 2 1 write-only ECC_ERR When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. 3 1 write-only INT_SET_STATUS Set interrupt status bits 0xFEC 32 write-only 0 0xF FAIL When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. 0 1 write-only ERR When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. 1 1 write-only DONE When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. 2 1 write-only ECC_ERR When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. 3 1 write-only MODULE_ID Controller+Memory module identification 0xFFC 32 read-only 0xC40F0800 0xFFFFFFFF APERTURE Aperture i. 0 8 read-only MINOR_REV Minor revision i. 8 4 read-only MAJOR_REV Major revision i. 12 4 read-only ID Identifier. 16 16 read-only PRINCE PRINCE PRINCE 0x40035000 0 0x40 registers ENC_ENABLE Encryption Enable register 0 32 read-write 0 0x1 EN Encryption Enable. 0 1 read-write DISABLED Encryption of writes to the flash controller DATAW* registers is disabled. 0 ENABLED Encryption of writes to the flash controller DATAW* registers is enabled. 0x1 MASK_LSB Data Mask register, 32 Least Significant Bits 0x4 32 write-only 0 0xFFFFFFFF MASKVAL Value of the 32 Least Significant Bits of the 64-bit data mask. 0 32 write-only MASK_MSB Data Mask register, 32 Most Significant Bits 0x8 32 write-only 0 0xFFFFFFFF MASKVAL Value of the 32 Most Significant Bits of the 64-bit data mask. 0 32 write-only LOCK Lock register 0xC 32 read-write 0 0x107 LOCKREG0 Lock Region 0 registers. 0 1 read-write DISABLED Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. 0 ENABLED Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. 0x1 LOCKREG1 Lock Region 1 registers. 1 1 read-write DISABLED Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. 0 ENABLED Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. 0x1 LOCKREG2 Lock Region 2 registers. 2 1 read-write DISABLED Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. 0 ENABLED Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. 0x1 LOCKMASK Lock the Mask registers. 8 1 read-write DISABLED Disabled. MASK_LSB, and MASK_MSB are writable.. 0 ENABLED Enabled. MASK_LSB, and MASK_MSB are not writable.. 0x1 IV_LSB0 Initial Vector register for region 0, Least Significant Bits 0x10 32 write-only 0 0xFFFFFFFF IVVAL Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. 0 32 write-only IV_MSB0 Initial Vector register for region 0, Most Significant Bits 0x14 32 write-only 0 0xFFFFFFFF IVVAL Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. 0 32 write-only BASE_ADDR0 Base Address for region 0 register 0x18 32 read-write 0 0xFFFFF ADDR_FIXED Fixed portion of the base address of region 0. 0 18 read-only ADDR_PRG Programmable portion of the base address of region 0. 18 2 read-write SR_ENABLE0 Sub-Region Enable register for region 0 0x1C 32 read-write 0 0xFFFFFFFF EN Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. 0 32 read-write IV_LSB1 Initial Vector register for region 1, Least Significant Bits 0x20 32 write-only 0 0xFFFFFFFF IVVAL Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. 0 32 write-only IV_MSB1 Initial Vector register for region 1, Most Significant Bits 0x24 32 write-only 0 0xFFFFFFFF IVVAL Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. 0 32 write-only BASE_ADDR1 Base Address for region 1 register 0x28 32 read-write 0x40000 0xFFFFF ADDR_FIXED Fixed portion of the base address of region 1. 0 18 read-only ADDR_PRG Programmable portion of the base address of region 1. 18 2 read-write SR_ENABLE1 Sub-Region Enable register for region 1 0x2C 32 read-write 0 0xFFFFFFFF EN Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. 0 32 read-write IV_LSB2 Initial Vector register for region 2, Least Significant Bits 0x30 32 write-only 0 0xFFFFFFFF IVVAL Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. 0 32 write-only IV_MSB2 Initial Vector register for region 2, Most Significant Bits 0x34 32 write-only 0 0xFFFFFFFF IVVAL Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. 0 32 write-only BASE_ADDR2 Base Address for region 2 register 0x38 32 read-write 0x80000 0xFFFFF ADDR_FIXED Fixed portion of the base address of region 2. 0 18 read-only ADDR_PRG Programmable portion of the base address of region 2. 18 2 read-write SR_ENABLE2 Sub-Region Enable register for region 2 0x3C 32 read-write 0 0xFFFFFFFF EN Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. 0 32 read-write USBPHY Universal System Bus Physical Layer USBPHY 0x40038000 0 0x110 registers USB1_PHY 46 PWD USB PHY Power-Down Register 0 32 read-write 0x1E1C00 0xFFFFFFFF TXPWDFS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 10 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the 0x1 TXPWDIBIAS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 11 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the 0x1 TXPWDV2I Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 12 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY transmit V-to-I converter and the current mirror 0x1 RXPWDENV Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 17 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed receiver envelope detector (squelch signal) 0x1 RXPWD1PT1 Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 18 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed differential receiver. 0x1 RXPWDDIFF Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 19 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed differential receive 0x1 RXPWDRX This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 20 1 read-write value0 Normal operation. 0 value1 Power-down the entire USB PHY receiver block except for the full-speed differential receiver 0x1 PWD_SET USB PHY Power-Down Register 0x4 32 read-write 0x1E1C00 0xFFFFFFFF TXPWDFS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 10 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the 0x1 TXPWDIBIAS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 11 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the 0x1 TXPWDV2I Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 12 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY transmit V-to-I converter and the current mirror 0x1 RXPWDENV Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 17 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed receiver envelope detector (squelch signal) 0x1 RXPWD1PT1 Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 18 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed differential receiver. 0x1 RXPWDDIFF Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 19 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed differential receive 0x1 RXPWDRX This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 20 1 read-write value0 Normal operation. 0 value1 Power-down the entire USB PHY receiver block except for the full-speed differential receiver 0x1 PWD_CLR USB PHY Power-Down Register 0x8 32 read-write 0x1E1C00 0xFFFFFFFF TXPWDFS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 10 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the 0x1 TXPWDIBIAS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 11 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the 0x1 TXPWDV2I Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 12 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY transmit V-to-I converter and the current mirror 0x1 RXPWDENV Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 17 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed receiver envelope detector (squelch signal) 0x1 RXPWD1PT1 Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 18 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed differential receiver. 0x1 RXPWDDIFF Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 19 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed differential receive 0x1 RXPWDRX This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 20 1 read-write value0 Normal operation. 0 value1 Power-down the entire USB PHY receiver block except for the full-speed differential receiver 0x1 PWD_TOG USB PHY Power-Down Register 0xC 32 read-write 0x1E1C00 0xFFFFFFFF TXPWDFS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 10 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the 0x1 TXPWDIBIAS Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 11 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the 0x1 TXPWDV2I Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 12 1 read-write value0 Normal operation. 0 value1 Power-down the USB PHY transmit V-to-I converter and the current mirror 0x1 RXPWDENV Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 17 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed receiver envelope detector (squelch signal) 0x1 RXPWD1PT1 Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 18 1 read-write value0 Normal operation. 0 value1 Power-down the USB full-speed differential receiver. 0x1 RXPWDDIFF Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 19 1 read-write value0 Normal operation. 0 value1 Power-down the USB high-speed differential receive 0x1 RXPWDRX This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled 20 1 read-write value0 Normal operation. 0 value1 Power-down the entire USB PHY receiver block except for the full-speed differential receiver 0x1 TX USB PHY Transmitter Control Register 0x10 32 read-write 0xA000402 0xFFFFFFFF D_CAL Decode to trim the nominal 17 0 4 read-write value0 Maximum current, approximately 19% above nominal. 0 value7 Nominal 0x7 value15 Minimum current, approximately 19% below nominal. 0xF TXCAL45DM Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin 8 4 read-write TXENCAL45DN Enable resistance calibration on DN. 13 1 read-write TXCAL45DP Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin 16 4 read-write TXENCAL45DP Enable resistance calibration on DP. 21 1 read-write TX_SET USB PHY Transmitter Control Register 0x14 32 read-write 0xA000402 0xFFFFFFFF D_CAL Decode to trim the nominal 17 0 4 read-write value0 Maximum current, approximately 19% above nominal. 0 value7 Nominal 0x7 value15 Minimum current, approximately 19% below nominal. 0xF TXCAL45DM Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin 8 4 read-write TXENCAL45DN Enable resistance calibration on DN. 13 1 read-write TXCAL45DP Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin 16 4 read-write TXENCAL45DP Enable resistance calibration on DP. 21 1 read-write TX_CLR USB PHY Transmitter Control Register 0x18 32 read-write 0xA000402 0xFFFFFFFF D_CAL Decode to trim the nominal 17 0 4 read-write value0 Maximum current, approximately 19% above nominal. 0 value7 Nominal 0x7 value15 Minimum current, approximately 19% below nominal. 0xF TXCAL45DM Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin 8 4 read-write TXENCAL45DN Enable resistance calibration on DN. 13 1 read-write TXCAL45DP Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin 16 4 read-write TXENCAL45DP Enable resistance calibration on DP. 21 1 read-write TX_TOG USB PHY Transmitter Control Register 0x1C 32 read-write 0xA000402 0xFFFFFFFF D_CAL Decode to trim the nominal 17 0 4 read-write value0 Maximum current, approximately 19% above nominal. 0 value7 Nominal 0x7 value15 Minimum current, approximately 19% below nominal. 0xF TXCAL45DM Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin 8 4 read-write TXENCAL45DN Enable resistance calibration on DN. 13 1 read-write TXCAL45DP Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin 16 4 read-write TXENCAL45DP Enable resistance calibration on DP. 21 1 read-write RX USB PHY Receiver Control Register 0x20 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write value0 Trip-Level Voltage is 0.1000 V 0 value1 Trip-Level Voltage is 0.1125 V 0x1 value2 Trip-Level Voltage is 0.1250 V 0x2 value3 Trip-Level Voltage is 0.0875 V 0x3 DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector. 4 3 read-write value0 Trip-Level Voltage is 0.56875 V 0 value1 Trip-Level Voltage is 0.55000 V 0x1 value2 Trip-Level Voltage is 0.58125 V 0x2 value3 Trip-Level Voltage is 0.60000 V 0x3 RXDBYPASS This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver 22 1 read-write value0 Normal operation. 0 value1 Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver 0x1 RX_SET USB PHY Receiver Control Register 0x24 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write value0 Trip-Level Voltage is 0.1000 V 0 value1 Trip-Level Voltage is 0.1125 V 0x1 value2 Trip-Level Voltage is 0.1250 V 0x2 value3 Trip-Level Voltage is 0.0875 V 0x3 DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector. 4 3 read-write value0 Trip-Level Voltage is 0.56875 V 0 value1 Trip-Level Voltage is 0.55000 V 0x1 value2 Trip-Level Voltage is 0.58125 V 0x2 value3 Trip-Level Voltage is 0.60000 V 0x3 RXDBYPASS This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver 22 1 read-write value0 Normal operation. 0 value1 Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver 0x1 RX_CLR USB PHY Receiver Control Register 0x28 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write value0 Trip-Level Voltage is 0.1000 V 0 value1 Trip-Level Voltage is 0.1125 V 0x1 value2 Trip-Level Voltage is 0.1250 V 0x2 value3 Trip-Level Voltage is 0.0875 V 0x3 DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector. 4 3 read-write value0 Trip-Level Voltage is 0.56875 V 0 value1 Trip-Level Voltage is 0.55000 V 0x1 value2 Trip-Level Voltage is 0.58125 V 0x2 value3 Trip-Level Voltage is 0.60000 V 0x3 RXDBYPASS This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver 22 1 read-write value0 Normal operation. 0 value1 Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver 0x1 RX_TOG USB PHY Receiver Control Register 0x2C 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write value0 Trip-Level Voltage is 0.1000 V 0 value1 Trip-Level Voltage is 0.1125 V 0x1 value2 Trip-Level Voltage is 0.1250 V 0x2 value3 Trip-Level Voltage is 0.0875 V 0x3 DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector. 4 3 read-write value0 Trip-Level Voltage is 0.56875 V 0 value1 Trip-Level Voltage is 0.55000 V 0x1 value2 Trip-Level Voltage is 0.58125 V 0x2 value3 Trip-Level Voltage is 0.60000 V 0x3 RXDBYPASS This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver 22 1 read-write value0 Normal operation. 0 value1 Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver 0x1 CTRL USB PHY General Control Register 0x30 32 read-write 0xC0000000 0xFFFFFFFF ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode 3 1 read-write ENDEVPLUGINDET Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode 4 1 read-write value0 Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) 0 value1 Enables 200kohm pullup resistors on USB_DP and USB_DM pins 0x1 DEVPLUGIN_POLARITY Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write RESUMEIRQSTICKY Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Resume IRQ: Indicates that the host is sending a wake-up after suspend 10 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write ENUTMILEVEL2 Enables UTMI+ Level 2 operation for the USB HS PHY 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level 3 operation for the USB HS PHY 15 1 read-write ENIRQWAKEUP Enable wake-up IRQ: Enables interrupt for the wake-up events. 16 1 read-write WAKEUP_IRQ Wake-up IRQ: Indicates that there is a wak-eup event 17 1 read-write AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enable DP DM change wake-up: Not for customer use 21 1 read-write ENVBUSCHG_WKUP Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended 23 1 read-write ENAUTOCLR_USBCLKGATE Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 25 1 read-write ENAUTOSET_USBCLKS Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 26 1 read-write HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with low-speed timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-write CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers 31 1 read-write CTRL_SET USB PHY General Control Register 0x34 32 read-write 0xC0000000 0xFFFFFFFF ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode 3 1 read-write ENDEVPLUGINDET Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode 4 1 read-write value0 Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) 0 value1 Enables 200kohm pullup resistors on USB_DP and USB_DM pins 0x1 DEVPLUGIN_POLARITY Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write RESUMEIRQSTICKY Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Resume IRQ: Indicates that the host is sending a wake-up after suspend 10 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write ENUTMILEVEL2 Enables UTMI+ Level 2 operation for the USB HS PHY 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level 3 operation for the USB HS PHY 15 1 read-write ENIRQWAKEUP Enable wake-up IRQ: Enables interrupt for the wake-up events. 16 1 read-write WAKEUP_IRQ Wake-up IRQ: Indicates that there is a wak-eup event 17 1 read-write AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enable DP DM change wake-up: Not for customer use 21 1 read-write ENVBUSCHG_WKUP Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended 23 1 read-write ENAUTOCLR_USBCLKGATE Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 25 1 read-write ENAUTOSET_USBCLKS Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 26 1 read-write HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with low-speed timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-only CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers 31 1 read-write CTRL_CLR USB PHY General Control Register 0x38 32 read-write 0xC0000000 0xFFFFFFFF ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode 3 1 read-write ENDEVPLUGINDET Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode 4 1 read-write value0 Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) 0 value1 Enables 200kohm pullup resistors on USB_DP and USB_DM pins 0x1 DEVPLUGIN_POLARITY Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write RESUMEIRQSTICKY Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Resume IRQ: Indicates that the host is sending a wake-up after suspend 10 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write ENUTMILEVEL2 Enables UTMI+ Level 2 operation for the USB HS PHY 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level 3 operation for the USB HS PHY 15 1 read-write ENIRQWAKEUP Enable wake-up IRQ: Enables interrupt for the wake-up events. 16 1 read-write WAKEUP_IRQ Wake-up IRQ: Indicates that there is a wak-eup event 17 1 read-write AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enable DP DM change wake-up: Not for customer use 21 1 read-write ENVBUSCHG_WKUP Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended 23 1 read-write ENAUTOCLR_USBCLKGATE Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 25 1 read-write ENAUTOSET_USBCLKS Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 26 1 read-write HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with low-speed timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-write CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers 31 1 read-write CTRL_TOG USB PHY General Control Register 0x3C 32 read-write 0xC0000000 0xFFFFFFFF ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode 3 1 read-write ENDEVPLUGINDET Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode 4 1 read-write value0 Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) 0 value1 Enables 200kohm pullup resistors on USB_DP and USB_DM pins 0x1 DEVPLUGIN_POLARITY Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write RESUMEIRQSTICKY Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Resume IRQ: Indicates that the host is sending a wake-up after suspend 10 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write ENUTMILEVEL2 Enables UTMI+ Level 2 operation for the USB HS PHY 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level 3 operation for the USB HS PHY 15 1 read-write ENIRQWAKEUP Enable wake-up IRQ: Enables interrupt for the wake-up events. 16 1 read-write WAKEUP_IRQ Wake-up IRQ: Indicates that there is a wak-eup event 17 1 read-write AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enable DP DM change wake-up: Not for customer use 21 1 read-write ENVBUSCHG_WKUP Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended 23 1 read-write ENAUTOCLR_USBCLKGATE Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 25 1 read-write ENAUTOSET_USBCLKS Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended 26 1 read-write HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with low-speed timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-write CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers 31 1 read-write STATUS USB PHY Status Register 0x40 32 read-write 0 0xFFFFFFFF OK_STATUS_3V Indicates the USB 3v power rails are in range. 0 1 read-only HOSTDISCONDETECT_STATUS Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode 3 1 read-only value0 USB cable disconnect has not been detected at the local host 0 value1 USB cable disconnect has been detected at the local host 0x1 DEVPLUGIN_STATUS Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] 6 1 read-only value0 No attachment to a USB host is detected 0 value1 Cable attachment to a USB host is detected 0x1 RESUME_STATUS Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. 10 1 read-only PLL_SIC USB PHY PLL Control/Status Register 0xA0 32 read-write 0xD12000 0xFFFFFFFF PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY 6 1 read-write PLL_POWER Power up the USB PLL 12 1 read-write PLL_ENABLE Enables the clock output from the USB PLL 13 1 read-write REFBIAS_PWD_SEL Reference bias power down select. 19 1 read-write value0 Selects PLL_POWER to control the reference bias 0 value1 Selects REFBIAS_PWD to control the reference bias 0x1 REFBIAS_PWD Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. 20 1 read-write PLL_REG_ENABLE This field controls the USB PLL regulator, set to enable the regulator 21 1 read-write PLL_DIV_SEL This field controls the USB PLL feedback loop divider 22 3 read-write value0 Divide by 13 0 value1 Divide by 15 0x1 value2 Divide by 16 0x2 value3 Divide by 20 0x3 value4 Divide by 22 0x4 value5 Divide by 25 0x5 value6 Divide by 30 0x6 value7 Divide by 240 0x7 PLL_PREDIV This is selection between /1 or /2 to expand the range of ref input clock. 30 1 read-write PLL_LOCK USB PLL lock status indicator 31 1 read-only value0 PLL is not currently locked 0 value1 PLL is currently locked 0x1 PLL_SIC_SET USB PHY PLL Control/Status Register 0xA4 32 read-write 0xD12000 0xFFFFFFFF PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY 6 1 read-write PLL_POWER Power up the USB PLL 12 1 read-write PLL_ENABLE Enables the clock output from the USB PLL 13 1 read-write REFBIAS_PWD_SEL Reference bias power down select. 19 1 read-write value0 Selects PLL_POWER to control the reference bias 0 value1 Selects REFBIAS_PWD to control the reference bias 0x1 REFBIAS_PWD Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. 20 1 read-write PLL_REG_ENABLE This field controls the USB PLL regulator, set to enable the regulator 21 1 read-write PLL_DIV_SEL This field controls the USB PLL feedback loop divider 22 3 read-write value0 Divide by 13 0 value1 Divide by 15 0x1 value2 Divide by 16 0x2 value3 Divide by 20 0x3 value4 Divide by 22 0x4 value5 Divide by 25 0x5 value6 Divide by 30 0x6 value7 Divide by 240 0x7 PLL_PREDIV This is selection between /1 or /2 to expand the range of ref input clock. 30 1 read-write PLL_LOCK USB PLL lock status indicator 31 1 read-only value0 PLL is not currently locked 0 value1 PLL is currently locked 0x1 PLL_SIC_CLR USB PHY PLL Control/Status Register 0xA8 32 read-write 0xD12000 0xFFFFFFFF PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY 6 1 read-write PLL_POWER Power up the USB PLL 12 1 read-write PLL_ENABLE Enables the clock output from the USB PLL 13 1 read-write REFBIAS_PWD_SEL Reference bias power down select. 19 1 read-write value0 Selects PLL_POWER to control the reference bias 0 value1 Selects REFBIAS_PWD to control the reference bias 0x1 REFBIAS_PWD Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. 20 1 read-write PLL_REG_ENABLE This field controls the USB PLL regulator, set to enable the regulator 21 1 read-write PLL_DIV_SEL This field controls the USB PLL feedback loop divider 22 3 read-write value0 Divide by 13 0 value1 Divide by 15 0x1 value2 Divide by 16 0x2 value3 Divide by 20 0x3 value4 Divide by 22 0x4 value5 Divide by 25 0x5 value6 Divide by 30 0x6 value7 Divide by 240 0x7 PLL_PREDIV This is selection between /1 or /2 to expand the range of ref input clock. 30 1 read-write PLL_LOCK USB PLL lock status indicator 31 1 read-only value0 PLL is not currently locked 0 value1 PLL is currently locked 0x1 PLL_SIC_TOG USB PHY PLL Control/Status Register 0xAC 32 read-write 0xD12000 0xFFFFFFFF PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY 6 1 read-write PLL_POWER Power up the USB PLL 12 1 read-write PLL_ENABLE Enables the clock output from the USB PLL 13 1 read-write REFBIAS_PWD_SEL Reference bias power down select. 19 1 read-write value0 Selects PLL_POWER to control the reference bias 0 value1 Selects REFBIAS_PWD to control the reference bias 0x1 REFBIAS_PWD Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1. 20 1 read-write PLL_REG_ENABLE This field controls the USB PLL regulator, set to enable the regulator 21 1 read-write PLL_DIV_SEL This field controls the USB PLL feedback loop divider 22 3 read-write value0 Divide by 13 0 value1 Divide by 15 0x1 value2 Divide by 16 0x2 value3 Divide by 20 0x3 value4 Divide by 22 0x4 value5 Divide by 25 0x5 value6 Divide by 30 0x6 value7 Divide by 240 0x7 PLL_PREDIV This is selection between /1 or /2 to expand the range of ref input clock. 30 1 read-write PLL_LOCK USB PLL lock status indicator 31 1 read-only value0 PLL is not currently locked 0 value1 PLL is currently locked 0x1 USB1_VBUS_DETECT USB PHY VBUS Detect Control Register 0xC0 32 read-write 0x700004 0xFFFFFFFF VBUSVALID_THRESH Sets the threshold for the VBUSVALID comparator 0 3 read-write value0 4.0V 0 value1 4.1V 0x1 value2 4.2V 0x2 value3 4.3V 0x3 value4 4.4V(Default) 0x4 value5 4.5V 0x5 value6 4.6V 0x6 value7 4.7V 0x7 VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write value0 Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) 0 value1 Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND 0x1 SESSEND_OVERRIDE Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 4 1 read-write BVALID_OVERRIDE Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 5 1 read-write AVALID_OVERRIDE Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 6 1 read-write VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 7 1 read-write VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the VBUS_VALID_3V detector results for signal reported to the USB controller 0x1 VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the Session Valid comparator results for signal reported to the USB controller 0x1 value2 Use the Session Valid comparator results for signal reported to the USB controller 0x2 ID_OVERRIDE_EN Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. 11 1 read-write ID_OVERRIDE ID override value. 12 1 read-write EXT_ID_OVERRIDE_EN Enable ID override using the pinmuxed value: 13 1 read-write value0 Select the Muxed value chosen using ID_OVERRIDE_EN. 0 value1 Select the external ID value. 0x1 EXT_VBUS_OVERRIDE_EN Enable VBUS override using the pinmuxed value. 14 1 read-write value0 Select the Muxed value chosen using VBUS_OVERRIDE_EN. 0 value1 Select the external VBUS VALID value. 0x1 VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator 18 1 read-write value0 Use the VBUS_VALID comparator for VBUS_VALID results 0 value1 Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. 0x1 VBUSVALID_5VDETECT no description available 19 1 read-write PWRUP_CMPS Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector 20 3 read-write value0 Powers down the VBUS_VALID comparator 0 value1 Enables the VBUS_VALID comparator (default) 0x7 DISCHARGE_VBUS Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground 26 1 read-write value0 VBUS discharge resistor is disabled (Default) 0 value1 VBUS discharge resistor is enabled 0x1 USB1_VBUS_DETECT_SET USB PHY VBUS Detect Control Register 0xC4 32 read-write 0x700004 0xFFFFFFFF VBUSVALID_THRESH Sets the threshold for the VBUSVALID comparator 0 3 read-write value0 4.0V 0 value1 4.1V 0x1 value2 4.2V 0x2 value3 4.3V 0x3 value4 4.4V(Default) 0x4 value5 4.5V 0x5 value6 4.6V 0x6 value7 4.7V 0x7 VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write value0 Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) 0 value1 Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND 0x1 SESSEND_OVERRIDE Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 4 1 read-write BVALID_OVERRIDE Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 5 1 read-write AVALID_OVERRIDE Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 6 1 read-write VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 7 1 read-write VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the VBUS_VALID_3V detector results for signal reported to the USB controller 0x1 VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the Session Valid comparator results for signal reported to the USB controller 0x1 value2 Use the Session Valid comparator results for signal reported to the USB controller 0x2 ID_OVERRIDE_EN Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. 11 1 read-write ID_OVERRIDE ID override value. 12 1 read-write EXT_ID_OVERRIDE_EN Enable ID override using the pinmuxed value: 13 1 read-write value0 Select the Muxed value chosen using ID_OVERRIDE_EN. 0 value1 Select the external ID value. 0x1 EXT_VBUS_OVERRIDE_EN Enable VBUS override using the pinmuxed value. 14 1 read-write value0 Select the Muxed value chosen using VBUS_OVERRIDE_EN. 0 value1 Select the external VBUS VALID value. 0x1 VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator 18 1 read-write value0 Use the VBUS_VALID comparator for VBUS_VALID results 0 value1 Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. 0x1 VBUSVALID_5VDETECT no description available 19 1 read-write PWRUP_CMPS Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector 20 3 read-write value0 Powers down the VBUS_VALID comparator 0 value1 Enables the VBUS_VALID comparator (default) 0x7 DISCHARGE_VBUS Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground 26 1 read-write value0 VBUS discharge resistor is disabled (Default) 0 value1 VBUS discharge resistor is enabled 0x1 USB1_VBUS_DETECT_CLR USB PHY VBUS Detect Control Register 0xC8 32 read-write 0x700004 0xFFFFFFFF VBUSVALID_THRESH Sets the threshold for the VBUSVALID comparator 0 3 read-write value0 4.0V 0 value1 4.1V 0x1 value2 4.2V 0x2 value3 4.3V 0x3 value4 4.4V(Default) 0x4 value5 4.5V 0x5 value6 4.6V 0x6 value7 4.7V 0x7 VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write value0 Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) 0 value1 Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND 0x1 SESSEND_OVERRIDE Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 4 1 read-write BVALID_OVERRIDE Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 5 1 read-write AVALID_OVERRIDE Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 6 1 read-write VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 7 1 read-write VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the VBUS_VALID_3V detector results for signal reported to the USB controller 0x1 VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the Session Valid comparator results for signal reported to the USB controller 0x1 value2 Use the Session Valid comparator results for signal reported to the USB controller 0x2 ID_OVERRIDE_EN Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. 11 1 read-write ID_OVERRIDE ID override value. 12 1 read-write EXT_ID_OVERRIDE_EN Enable ID override using the pinmuxed value: 13 1 read-write value0 Select the Muxed value chosen using ID_OVERRIDE_EN. 0 value1 Select the external ID value. 0x1 EXT_VBUS_OVERRIDE_EN Enable VBUS override using the pin muxed value. 14 1 read-write value0 Select the muxed value chosen using VBUS_OVERRIDE_EN. 0 value1 Select the external VBUS VALID value. 0x1 VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator 18 1 read-write value0 Use the VBUS_VALID comparator for VBUS_VALID results 0 value1 Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. 0x1 VBUSVALID_5VDETECT no description available 19 1 read-write PWRUP_CMPS Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector 20 3 read-write value0 Powers down the VBUS_VALID comparator 0 value1 Enables the VBUS_VALID comparator (default) 0x7 DISCHARGE_VBUS Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground 26 1 read-write value0 VBUS discharge resistor is disabled (Default) 0 value1 VBUS discharge resistor is enabled 0x1 USB1_VBUS_DETECT_TOG USB PHY VBUS Detect Control Register 0xCC 32 read-write 0x700004 0xFFFFFFFF VBUSVALID_THRESH Sets the threshold for the VBUSVALID comparator 0 3 read-write value0 4.0V 0 value1 4.1V 0x1 value2 4.2V 0x2 value3 4.3V 0x3 value4 4.4V(Default) 0x4 value5 4.5V 0x5 value6 4.6V 0x6 value7 4.7V 0x7 VBUS_OVERRIDE_EN VBUS detect signal override enable 3 1 read-write value0 Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) 0 value1 Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND 0x1 SESSEND_OVERRIDE Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1 4 1 read-write BVALID_OVERRIDE Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1 5 1 read-write AVALID_OVERRIDE Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1 6 1 read-write VBUSVALID_OVERRIDE Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1 7 1 read-write VBUSVALID_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 8 1 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the VBUS_VALID_3V detector results for signal reported to the USB controller 0x1 VBUS_SOURCE_SEL Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller 9 2 read-write value0 Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) 0 value1 Use the Session Valid comparator results for signal reported to the USB controller 0x1 value2 Use the Session Valid comparator results for signal reported to the USB controller 0x2 ID_OVERRIDE_EN Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. 11 1 read-write ID_OVERRIDE ID override value. 12 1 read-write EXT_ID_OVERRIDE_EN Enable ID override using the pin muxed value. 13 1 read-write value0 Select the muxed value chosen using ID_OVERRIDE_EN. 0 value1 Select the external ID value. 0x1 EXT_VBUS_OVERRIDE_EN Enable VBUS override using the pin muxed value. 14 1 read-write value0 Select the Muxed value chosen using VBUS_OVERRIDE_EN. 0 value1 Select the external VBUS VALID value. 0x1 VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator 18 1 read-write value0 Use the VBUS_VALID comparator for VBUS_VALID results 0 value1 Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. 0x1 VBUSVALID_5VDETECT no description available 19 1 read-write PWRUP_CMPS Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector 20 3 read-write value0 Powers down the VBUS_VALID comparator 0 value1 Enables the VBUS_VALID comparator (default) 0x7 DISCHARGE_VBUS Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground 26 1 read-write value0 VBUS discharge resistor is disabled (Default) 0 value1 VBUS discharge resistor is enabled 0x1 ANACTRL USB PHY Analog Control Register 0x100 32 read-write 0xA000402 0xFFFFFFFF LVI_EN Vow voltage detector enable bit. 1 1 read-write PFD_CLK_SEL For normal USB operation, this bit field must remain at value 2'b00. 2 2 read-write DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins 10 1 read-write value0 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. 0 value1 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. 0x1 ANACTRL_SET USB PHY Analog Control Register 0x104 32 read-write 0xA000402 0xFFFFFFFF LVI_EN Vow voltage detector enable bit. 1 1 read-write PFD_CLK_SEL For normal USB operation, this bit field must remain at value 2'b00. 2 2 read-write DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins 10 1 read-write value0 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. 0 value1 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. 0x1 ANACTRL_CLR USB PHY Analog Control Register 0x108 32 read-write 0xA000402 0xFFFFFFFF LVI_EN Vow voltage detector enable bit. 1 1 read-write PFD_CLK_SEL For normal USB operation, this bit field must remain at value 2'b00. 2 2 read-write DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins 10 1 read-write value0 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. 0 value1 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. 0x1 ANACTRL_TOG USB PHY Analog Control Register 0x10C 32 read-write 0xA000402 0xFFFFFFFF LVI_EN Vow voltage detector enable bit. 1 1 read-write PFD_CLK_SEL For normal USB operation, this bit field must remain at value 2'b00. 2 2 read-write DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins 10 1 read-write value0 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. 0 value1 The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. 0x1 RNG RNG RNG 0x4003A000 0 0x1000 registers RANDOM_NUMBER This register contains a random 32 bit number which is computed on demand, at each time it is read 0 32 read-only 0 0xFFFFFFFF RANDOM_NUMBER This register contains a random 32 bit number which is computed on demand, at each time it is read. 0 32 read-only COUNTER_VAL no description available 0x8 32 read-write 0 0x1FFF CLK_RATIO Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes. 0 8 read-only REFRESH_CNT Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. 8 5 read-only COUNTER_CFG no description available 0xC 32 read-write 0 0x3FF MODE 00: disabled 01: update once. 0 2 read-write CLOCK_SEL Selects the internal clock on which to compute statistics. 2 3 read-write SHIFT4X To be used to add precision to clock_ratio and determine 'entropy refill'. 5 3 read-write ONLINE_TEST_CFG no description available 0x10 32 read-write 0 0x7 ACTIVATE 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. 0 1 read-write DATA_SEL Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field. 1 2 read-write ONLINE_TEST_VAL no description available 0x14 32 read-write 0 0xFFF LIVE_CHI_SQUARED This value is updated as described in field 'activate'. 0 4 read-only MIN_CHI_SQUARED This field is reset when 'activate'==0. 4 4 read-only MAX_CHI_SQUARED This field is reset when 'activate'==0. 8 4 read-only MODULEID IP identifier 0xFFC 32 read-only 0xA0B83200 0xFFFFFFFF APERTURE Aperture i. 0 8 read-only MIN_REV Minor revision i. 8 4 read-only MAJ_REV Major revision i. 12 4 read-only ID Identifier. 16 16 read-only PUF PUFCTRL PUF 0x4003B000 0 0x260 registers PUF 56 CTRL PUF Control register 0 32 read-write 0 0x5F zeroize Begin Zeroize operation for PUF and go to Error state 0 1 read-write enroll Begin Enroll operation 1 1 read-write start Begin Start operation 2 1 read-write GENERATEKEY Begin Set Intrinsic Key operation 3 1 read-write SETKEY Begin Set User Key operation 4 1 read-write GETKEY Begin Get Key operation 6 1 read-write KEYINDEX PUF Key Index register 0x4 32 read-write 0 0xF KEYIDX Key index for Set Key operations 0 4 read-write KEYSIZE PUF Key Size register 0x8 32 read-write 0 0x3F KEYSIZE Key size for Set Key operations 0 6 read-write STAT PUF Status register 0x20 32 read-write 0x1 0xF7 busy Indicates that operation is in progress 0 1 read-only SUCCESS Last operation was successful 1 1 read-only error PUF is in the Error state and no operations can be performed 2 1 read-only KEYINREQ Request for next part of key 4 1 read-only KEYOUTAVAIL Next part of key is available 5 1 read-only CODEINREQ Request for next part of AC/KC 6 1 read-only CODEOUTAVAIL Next part of AC/KC is available 7 1 read-only ALLOW PUF Allow register 0x28 32 read-write 0 0x8F ALLOWENROLL Enroll operation is allowed 0 1 read-only ALLOWSTART Start operation is allowed 1 1 read-only ALLOWSETKEY Set Key operations are allowed 2 1 read-only ALLOWGETKEY Get Key operation is allowed 3 1 read-only KEYINPUT PUF Key Input register 0x40 32 write-only 0 0xFFFFFFFF KEYIN Key input data 0 32 write-only CODEINPUT PUF Code Input register 0x44 32 write-only 0 0xFFFFFFFF CODEIN AC/KC input data 0 32 write-only CODEOUTPUT PUF Code Output register 0x48 32 read-only 0 0xFFFFFFFF CODEOUT AC/KC output data 0 32 read-only KEYOUTINDEX PUF Key Output Index register 0x60 32 read-write 0 0xF KEYOUTIDX Key index for the key that is currently output via the Key Output register 0 4 read-only KEYOUTPUT PUF Key Output register 0x64 32 read-only 0 0xFFFFFFFF KEYOUT Key output data 0 32 read-only IFSTAT PUF Interface Status and clear register 0xDC 32 read-write 0 0x1 ERROR Indicates that an APB error has occurred,Writing logic1 clears the if_error bit 0 1 read-write VERSION PUF version register. 0xFC 32 read-only 0 0xFFFFFFFF VERSION Version of the PUF module. 0 32 read-only INTEN PUF Interrupt Enable 0x100 32 read-write 0 0xF7 READYEN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 0 1 read-write SUCCESEN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 1 1 read-write ERROREN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 2 1 read-write KEYINREQEN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 4 1 read-write KEYOUTAVAILEN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 5 1 read-write CODEINREQEN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 6 1 read-write CODEOUTAVAILEN Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) 7 1 read-write INTSTAT PUF interrupt status 0x104 32 read-write 0 0xF7 READY Triggers on falling edge of busy, write 1 to clear 0 1 read-write SUCCESS Level sensitive interrupt, cleared when interrupt source clears 1 1 read-write ERROR Level sensitive interrupt, cleared when interrupt source clears 2 1 read-write KEYINREQ Level sensitive interrupt, cleared when interrupt source clears 4 1 read-write KEYOUTAVAIL Level sensitive interrupt, cleared when interrupt source clears 5 1 read-write CODEINREQ Level sensitive interrupt, cleared when interrupt source clears 6 1 read-write CODEOUTAVAIL Level sensitive interrupt, cleared when interrupt source clears 7 1 read-write PWRCTRL PUF RAM Power Control 0x108 32 read-write 0xF8 0xFD RAMON Power on the PUF RAM. 0 1 read-write RAMSTAT PUF RAM status. 1 1 read-write CFG PUF config register for block bits 0x10C 32 read-write 0 0x3 BLOCKENROLL_SETKEY Block enroll operation. Write 1 to set, cleared on reset. 0 1 read-write BLOCKKEYOUTPUT Block set key operation. Write 1 to set, cleared on reset. 1 1 read-write KEYLOCK Only reset in case of full IC reset 0x200 32 read-write 0xAA 0xFF KEY0 "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." 0 2 read-write KEY1 "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." 2 2 read-write KEY2 "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." 4 2 read-write KEY3 "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." 6 2 read-write KEYENABLE no description available 0x204 32 read-write 0x55 0xFF KEY0 "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." 0 2 read-write KEY1 "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." 2 2 read-write KEY2 "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." 4 2 read-write KEY3 "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." 6 2 read-write KEYKey destination for PUF key.read-write08KEYread-writeaesSend key to AES engine.86prince0Send key to PRINCE engine for memory layout 0.89prince1Send key to PRINCE engine for memory layout 1.101prince2Send key to PRINCE engine for memory layout 2.149noneDo not send key to any hardware engine.85 KEYRESET Reinitialize Keys shift registers counters 0x208 32 write-only 0 0xFFFFFFFF KEY0 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. 0 2 write-only KEY1 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. 2 2 write-only KEY2 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. 4 2 write-only KEY3 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. 6 2 write-only IDXBLK_L no description available 0x20C 32 read-write 0x8000AAAA 0xC000FFFF IDX1 Use to block PUF index 1 2 2 read-write IDX2 Use to block PUF index 2 4 2 read-write IDX3 Use to block PUF index 3 6 2 read-write IDX4 Use to block PUF index 4 8 2 read-write IDX5 Use to block PUF index 5 10 2 read-write IDX6 Use to block PUF index 6 12 2 read-write IDX7 Use to block PUF index 7 14 2 read-write LOCK_IDX Lock 0 to 7 PUF key indexes 30 2 write-only IDXBLK_H_DP no description available 0x210 32 read-write 0xAAAA 0xFFFFFFFF IDX8 Use to block PUF index 8 0 2 read-write IDX9 Use to block PUF index 9 2 2 read-write IDX10 Use to block PUF index 10 4 2 read-write IDX11 Use to block PUF index 11 6 2 read-write IDX12 Use to block PUF index 12 8 2 read-write IDX13 Use to block PUF index 13 10 2 read-write IDX14 Use to block PUF index 14 12 2 read-write IDX15 Use to block PUF index 15 14 2 read-write 4 0x4 KEYMASK[%s] Only reset in case of full IC reset 0x214 32 write-only 0 0xFFFFFFFF KEYMASK no description available 0 32 write-only IDXBLK_H no description available 0x254 32 read-write 0x8000AAAA 0xC000FFFF IDX8 Use to block PUF index 8 0 2 read-write IDX9 Use to block PUF index 9 2 2 read-write IDX10 Use to block PUF index 10 4 2 read-write IDX11 Use to block PUF index 11 6 2 read-write IDX12 Use to block PUF index 12 8 2 read-write IDX13 Use to block PUF index 13 10 2 read-write IDX14 Use to block PUF index 14 12 2 read-write IDX15 Use to block PUF index 15 14 2 read-write LOCK_IDX Lock 8 to 15 PUF key indexes 30 2 write-only IDXBLK_L_DP no description available 0x258 32 read-write 0xAAAA 0xFFFF IDX1 Use to block PUF index 1 2 2 read-write IDX2 Use to block PUF index 2 4 2 read-write IDX3 Use to block PUF index 3 6 2 read-write IDX4 Use to block PUF index 4 8 2 read-write IDX5 Use to block PUF index 5 10 2 read-write IDX6 Use to block PUF index 6 12 2 read-write IDX7 Use to block PUF index 7 14 2 read-write SHIFT_STATUS no description available 0x25C 32 read-write 0 0xFFFF KEY0 Index counter from key 0 shift register 0 4 read-only KEY1 Index counter from key 1 shift register 4 4 read-only KEY2 Index counter from key 2 shift register 8 4 read-only KEY3 Index counter from key 3 shift register 12 4 read-only PLU LPC80X Programmable Logic Unit (PLU) PLU 0x4003D000 0 0xC20 registers PLU 52 26 0x20 LUT[%s] no description available 0 5 0x4 0,1,2,3,4 LUT_INP_MUX%s LUTn input x MUX 0 32 read-write 0 0x3F LUTn_INPx Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. 0 6 read-write plu_inputs0 The PLU primary inputs 0. 0 plu_inputs1 The PLU primary inputs 1. 0x1 plu_inputs2 The PLU primary inputs 2. 0x2 plu_inputs3 The PLU primary inputs 3. 0x3 plu_inputs4 The PLU primary inputs 4. 0x4 plu_inputs5 The PLU primary inputs 5. 0x5 lut_outputs0 The output of LUT0. 0x6 lut_outputs1 The output of LUT1. 0x7 lut_outputs2 The output of LUT2. 0x8 lut_outputs3 The output of LUT3. 0x9 lut_outputs4 The output of LUT4. 0xA lut_outputs5 The output of LUT5. 0xB lut_outputs6 The output of LUT6. 0xC lut_outputs7 The output of LUT7. 0xD lut_outputs8 The output of LUT8. 0xE lut_outputs9 The output of LUT9. 0xF lut_outputs10 The output of LUT10. 0x10 lut_outputs11 The output of LUT11. 0x11 lut_outputs12 The output of LUT12. 0x12 lut_outputs13 The output of LUT13. 0x13 lut_outputs14 The output of LUT14. 0x14 lut_outputs15 The output of LUT15. 0x15 lut_outputs16 The output of LUT16. 0x16 lut_outputs17 The output of LUT17. 0x17 lut_outputs18 The output of LUT18. 0x18 lut_outputs19 The output of LUT19. 0x19 lut_outputs20 The output of LUT20. 0x1A lut_outputs21 The output of LUT21. 0x1B lut_outputs22 The output of LUT22. 0x1C lut_outputs23 The output of LUT23. 0x1D lut_outputs24 The output of LUT24. 0x1E lut_outputs25 The output of LUT25. 0x1F state0 state(0). 0x20 state1 state(1). 0x21 state2 state(2). 0x22 state3 state(3). 0x23 26 0x4 LUT_TRUTH[%s] Specifies the Truth Table contents for LUT0 0x800 32 read-write 0 0xFFFFFFFF LUTn_TRUTH Specifies the Truth Table contents for LUT0.. 0 32 read-write OUTPUTS Provides the current state of the 8 designated PLU Outputs. 0x900 32 read-write 0 0xFFFFFFFF OUTPUT_STATE Provides the current state of the 8 designated PLU Outputs.. 0 8 read-only WAKEINT_CTRL Wakeup interrupt control for PLU 0x904 32 read-write 0 0xFFFFFFFF MASK Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) 0 8 read-write FILTER_MODE control input of the PLU, add filtering for glitch. 8 2 read-write BYPASS Bypass mode. 0 FILTER1CLK Filter 1 clock period. 0x1 FILTER2CLK Filter 2 clock period. 0x2 FILTER3CLK Filter 3 clock period. 0x3 FILTER_CLKSEL hclk is divided by 2**filter_clksel. 10 2 read-write FRO1MHZ Selects the 1 MHz low-power oscillator as the filter clock. 0 FRO12MHZ Selects the 12 Mhz FRO as the filter clock. 0x1 OTHER_CLOCK Selects a third filter clock source, if provided. 0x2 LATCH_ENABLE latch the interrupt , then can be cleared with next bit INTR_CLEAR 12 1 read-write INTR_CLEAR Write to clear wakeint_latched 13 1 read-write oneToClear 8 0x4 OUTPUT_MUX[%s] Selects the source to be connected to PLU Output 0 0xC00 32 read-write 0 0xFFFFFFFF OUTPUTn Selects the source to be connected to PLU Output 0. 0 5 read-write plu_output0 The PLU output 0. 0 plu_output1 The PLU output 1. 0x1 plu_output2 The PLU output 2. 0x2 plu_output3 The PLU output 3. 0x3 plu_output4 The PLU output 4. 0x4 plu_output5 The PLU output 5. 0x5 plu_output6 The PLU output 6. 0x6 plu_output7 The PLU output 7. 0x7 plu_output8 The PLU output 8. 0x8 plu_output9 The PLU output 9. 0x9 plu_output10 The PLU output 10. 0xA plu_output11 The PLU output 11. 0xB plu_output12 The PLU output 12. 0xC plu_output13 The PLU output 13. 0xD plu_output14 The PLU output 14. 0xE plu_output15 The PLU output 15. 0xF plu_output16 The PLU output 16. 0x10 plu_output17 The PLU output 17. 0x11 plu_output18 The PLU output 18. 0x12 plu_output19 The PLU output 19. 0x13 plu_output20 The PLU output 20. 0x14 plu_output21 The PLU output 21. 0x15 plu_output22 The PLU output 22. 0x16 plu_output23 The PLU output 23. 0x17 plu_output24 The PLU output 24. 0x18 plu_output25 The PLU output 25. 0x19 state0 state(0). 0x1A state1 state(1). 0x1B state2 state(2). 0x1C state3 state(3). 0x1D DMA0 DMA controller DMA DMA 0x40082000 0 0x56C registers DMA0 1 CTRL DMA control. 0 32 read-write 0 0x1 ENABLE DMA controller master enable. 0 1 read-write DISABLED Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 0 ENABLED Enabled. The DMA controller is enabled. 0x1 INTSTAT Interrupt status. 0x4 32 read-only 0 0x6 ACTIVEINT Summarizes whether any enabled interrupts (other than error interrupts) are pending. 1 1 read-only NOT_PENDING Not pending. No enabled interrupts are pending. 0 PENDING Pending. At least one enabled interrupt is pending. 0x1 ACTIVEERRINT Summarizes whether any error interrupts are pending. 2 1 read-only NOT_PENDING Not pending. No error interrupts are pending. 0 PENDING Pending. At least one error interrupt is pending. 0x1 SRAMBASE SRAM address of the channel configuration table. 0x8 32 read-write 0 0xFFFFFE00 OFFSET Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. 9 23 read-write ENABLESET0 Channel Enable read and Set for all DMA channels. 0x20 32 read-write 0 0xFFFFFFFF ENA Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 0 32 read-write ENABLECLR0 Channel Enable Clear for all DMA channels. 0x28 32 write-only 0 0 CLR Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 32 write-only ACTIVE0 Channel Active status for all DMA channels. 0x30 32 read-only 0 0xFFFFFFFF ACT Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 0 32 read-only BUSY0 Channel Busy status for all DMA channels. 0x38 32 read-only 0 0xFFFFFFFF BSY Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 0 32 read-only ERRINT0 Error Interrupt status for all DMA channels. 0x40 32 read-write 0 0xFFFFFFFF ERR Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. 0 32 read-write INTENSET0 Interrupt Enable read and Set for all DMA channels. 0x48 32 read-write 0 0xFFFFFFFF INTEN Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 0 32 read-write INTENCLR0 Interrupt Enable Clear for all DMA channels. 0x50 32 write-only 0 0 CLR Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 32 write-only INTA0 Interrupt A status for all DMA channels. 0x58 32 read-write 0 0xFFFFFFFF IA Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. 0 32 read-write INTB0 Interrupt B status for all DMA channels. 0x60 32 read-write 0 0xFFFFFFFF IB Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. 0 32 read-write SETVALID0 Set ValidPending control bits for all DMA channels. 0x68 32 write-only 0 0 SV SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n 0 32 write-only SETTRIG0 Set Trigger control bits for all DMA channels. 0x70 32 write-only 0 0 TRIG Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. 0 32 write-only ABORT0 Channel Abort control for all DMA channels. 0x78 32 write-only 0 0 ABORTCTRL Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. 0 32 write-only 23 0x10 CHANNEL[%s] no description available 0x400 CFG Configuration register for DMA channel . 0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write DISABLED Disabled. Peripheral DMA requests are disabled. 0 ENABLED Enabled. Peripheral DMA requests are enabled. 0x1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write DISABLED Disabled. Hardware triggering is not used. 0 ENABLED Enabled. Use hardware triggering. 0x1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write ACTIVE_LOW_FALLING Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 0 ACTIVE_HIGH_RISING Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 0x1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write EDGE Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. 0 LEVEL Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. 0x1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write SINGLE Single transfer. Hardware trigger causes a single transfer. 0 BURST Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. 0x1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write DISABLED Disabled. Source burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Source burst wrapping is enabled for this DMA channel. 0x1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write DISABLED Disabled. Destination burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Destination burst wrapping is enabled for this DMA channel. 0x1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT Control and status register for DMA channel . 0x4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only NO_EFFECT No effect. No effect on DMA operation. 0 VALID_PENDING Valid pending. 0x1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only NOT_TRIGGERED Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 0 TRIGGERED Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 0x1 XFERCFG Transfer configuration register for DMA channel . 0x8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write NOT_VALID Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 0 VALID Valid. The current channel descriptor is considered valid. 0x1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write DISABLED Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 0 ENABLED Enabled. Reload the channels' control structure when the current descriptor is exhausted. 0x1 SWTRIG Software Trigger. 2 1 read-write NOT_SET Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 0 SET Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. 0x1 CLRTRIG Clear Trigger. 3 1 read-write NOT_CLEARED Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 0 CLEARED Cleared. The trigger is cleared when this descriptor is exhausted 0x1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write NO_EFFECT No effect. 0 SET Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 0x1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write NO_EFFECT No effect. 0 SET Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 0x1 WIDTH Transfer width used for this DMA channel. 8 2 read-write BIT_8 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 0 BIT_16 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 0x1 BIT_32 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 0x2 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write NO_INCREMENT No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0 WIDTH_X_1 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. 0x1 WIDTH_X_2 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 0x2 WIDTH_X_4 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 0x3 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write NO_INCREMENT No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0 WIDTH_X_1 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. 0x1 WIDTH_X_2 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 0x2 WIDTH_X_4 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 0x3 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write DMA1 DMA controller DMA 0x400A7000 0 0x49C registers DMA1 58 USB0 USB 2.0 Device Controller USB 0x40084000 0 0x38 registers USB0_NEEDCLK 27 USB0 28 DEVCMDSTAT USB Device Command/Status register 0 32 read-write 0x800 0x171BFBFF DEV_ADDR USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. 0 7 read-write DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. 7 1 read-write SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on: 9 1 read-write NORMAL USB_NEEDCLK has normal function. 0 ALWAYS_ON USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. 0x1 LPM_SUP LPM Supported: 11 1 read-write NO LPM not supported. 0 YES LPM supported. 0x1 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP 12 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP 13 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_CO Interrupt on NAK for control OUT EP 14 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_CI Interrupt on NAK for control IN EP 15 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. 16 1 read-write DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. 17 1 read-write LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. 20 1 read-only DCON_C Device status - connect change. The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. 24 1 read-write DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. 25 1 read-write DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. 26 1 read-write VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. 28 1 read-only INFO USB Info register 0x4 32 read-write 0 0x7FFF FRAME_NR Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. 0 11 read-only ERR_CODE The error code which last occurred: 11 4 read-write NO_ERROR No error 0 PID_ENCODING_ERROR PID encoding error 0x1 PID_UNKNOWN PID unknown 0x2 PACKET_UNEXPECTED Packet unexpected 0x3 TOKEN_CRC_ERROR Token CRC error 0x4 DATA_CRC_ERROR Data CRC error 0x5 TIMEOUT Time out 0x6 BABBLE Babble 0x7 TRUNCATED_EOP Truncated EOP 0x8 SENT_RECEIVED_NAK Sent/Received NAK 0x9 SENT_STALL Sent Stall 0xA OVERRUN Overrun 0xB SENT_EMPTY_PACKET Sent empty packet 0xC BITSTUFF_ERROR Bitstuff error 0xD SYNC_ERROR Sync error 0xE WRONG_DATA_TOGGLE Wrong data toggle 0xF MINREV Minor Revision. 16 8 read-only MAJREV Major Revision. 24 8 read-only EPLISTSTART USB EP Command/Status List start address 0x8 32 read-write 0 0xFFFFFF00 EP_LIST Start address of the USB EP Command/Status List. 8 24 read-write DATABUFSTART USB Data buffer start address 0xC 32 read-write 0 0xFFC00000 DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. 22 10 read-write LPM USB Link Power Management register 0x10 32 read-write 0 0x1FF HIRD_HW Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token 0 4 read-only HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. 8 1 read-write EPSKIP USB Endpoint skip 0x14 32 read-write 0 0x3FFFFFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. 0 10 read-write EPINUSE USB Endpoint Buffer in use 0x18 32 read-write 0 0x3FC BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. 2 8 read-write EPBUFCFG USB Endpoint Buffer Configuration register 0x1C 32 read-write 0 0x3FC BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. 2 8 read-write INTSTAT USB interrupt status register 0x20 32 read-write 0 0xC00003FF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. 0 1 read-write EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. 9 1 read-write FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. 30 1 read-write DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. 31 1 read-write INTEN USB interrupt enable register 0x24 32 read-write 0 0xC00003FF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 0 10 read-write FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 31 1 read-write INTSETSTAT USB set interrupt status register 0x28 32 read-write 0 0xC00003FF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 0 10 read-write FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 31 1 read-write EPTOGGLE USB Endpoint toggle register 0x34 32 read-write 0 0x3FF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 0 10 read-write SCT0 SCTimer/PWM (SCT) SCT 0x40085000 0 0x550 registers SCT0 12 CONFIG SCT configuration register 0 32 read-write 0x1E00 0x61FFF UNIFY SCT operation 0 1 read-write DUAL_COUNTER The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 0 UNIFIED_COUNTER The SCT operates as a unified 32-bit counter. 0x1 CLKMODE SCT clock mode 1 2 read-write SYSTEM_CLOCK_MODE System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 0 SAMPLED_SYSTEM_CLOCK_MODE Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. 0x1 SCT_INPUT_CLOCK_MODE SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 0x2 ASYNCHRONOUS_MODE Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. 0x3 CKSEL SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. 3 4 read-write INPUT_0_RISING_EDGES Rising edges on input 0. 0 INPUT_0_FALLING_EDGE Falling edges on input 0. 0x1 INPUT_1_RISING_EDGES Rising edges on input 1. 0x2 INPUT_1_FALLING_EDGE Falling edges on input 1. 0x3 INPUT_2_RISING_EDGES Rising edges on input 2. 0x4 INPUT_2_FALLING_EDGE Falling edges on input 2. 0x5 INPUT_3_RISING_EDGES Rising edges on input 3. 0x6 INPUT_3_FALLING_EDGE Falling edges on input 3. 0x7 INPUT_4_RISING_EDGES Rising edges on input 4. 0x8 INPUT_4_FALLING_EDGE Falling edges on input 4. 0x9 INPUT_5_RISING_EDGES Rising edges on input 5. 0xA INPUT_5_FALLING_EDGE Falling edges on input 5. 0xB INPUT_6_RISING_EDGES Rising edges on input 6. 0xC INPUT_6_FALLING_EDGE Falling edges on input 6. 0xD INPUT_7_RISING_EDGES Rising edges on input 7. 0xE INPUT_7_FALLING_EDGE Falling edges on input 7. 0xF NORELOAD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 7 1 read-write NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 8 1 read-write INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. 9 4 read-write AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 17 1 read-write AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 18 1 read-write CTRL SCT control register 0x4 32 read-write 0x40004 0x1FFF1FFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 0 1 read-write STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. 1 1 read-write HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. 2 1 read-write CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 3 1 read-write BIDIR_L L or unified counter direction select 4 1 read-write UP Up. The counter counts up to a limit condition, then is cleared to zero. 0 UP_DOWN Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 0x1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5 8 read-write DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 16 1 read-write STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 17 1 read-write HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. 18 1 read-write CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. 19 1 read-write BIDIR_H Direction select 20 1 read-write UP The H counter counts up to its limit condition, then is cleared to zero. 0 UP_DOWN The H counter counts up to its limit, then counts down to a limit condition or to 0. 0x1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 21 8 read-write LIMIT SCT limit event select register 0x8 32 read-write 0 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write HALT SCT halt event select register 0xC 32 read-write 0 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write STOP SCT stop event select register 0x10 32 read-write 0 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write START SCT start event select register 0x14 32 read-write 0 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write COUNT SCT counter register 0x40 32 read-write 0 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. 0 16 read-write CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. 16 16 read-write STATE SCT state register 0x44 32 read-write 0 0x1F001F STATE_L State variable. 0 5 read-write STATE_H State variable. 16 5 read-write INPUT SCT input register 0x48 32 read-only 0 0xFFFFFFFF AIN0 Input 0 state. Input 0 state on the last SCT clock edge. 0 1 read-only AIN1 Input 1 state. Input 1 state on the last SCT clock edge. 1 1 read-only AIN2 Input 2 state. Input 2 state on the last SCT clock edge. 2 1 read-only AIN3 Input 3 state. Input 3 state on the last SCT clock edge. 3 1 read-only AIN4 Input 4 state. Input 4 state on the last SCT clock edge. 4 1 read-only AIN5 Input 5 state. Input 5 state on the last SCT clock edge. 5 1 read-only AIN6 Input 6 state. Input 6 state on the last SCT clock edge. 6 1 read-only AIN7 Input 7 state. Input 7 state on the last SCT clock edge. 7 1 read-only AIN8 Input 8 state. Input 8 state on the last SCT clock edge. 8 1 read-only AIN9 Input 9 state. Input 9 state on the last SCT clock edge. 9 1 read-only AIN10 Input 10 state. Input 10 state on the last SCT clock edge. 10 1 read-only AIN11 Input 11 state. Input 11 state on the last SCT clock edge. 11 1 read-only AIN12 Input 12 state. Input 12 state on the last SCT clock edge. 12 1 read-only AIN13 Input 13 state. Input 13 state on the last SCT clock edge. 13 1 read-only AIN14 Input 14 state. Input 14 state on the last SCT clock edge. 14 1 read-only AIN15 Input 15 state. Input 15 state on the last SCT clock edge. 15 1 read-only SIN0 Input 0 state. Input 0 state following the synchronization specified by INSYNC. 16 1 read-only SIN1 Input 1 state. Input 1 state following the synchronization specified by INSYNC. 17 1 read-only SIN2 Input 2 state. Input 2 state following the synchronization specified by INSYNC. 18 1 read-only SIN3 Input 3 state. Input 3 state following the synchronization specified by INSYNC. 19 1 read-only SIN4 Input 4 state. Input 4 state following the synchronization specified by INSYNC. 20 1 read-only SIN5 Input 5 state. Input 5 state following the synchronization specified by INSYNC. 21 1 read-only SIN6 Input 6 state. Input 6 state following the synchronization specified by INSYNC. 22 1 read-only SIN7 Input 7 state. Input 7 state following the synchronization specified by INSYNC. 23 1 read-only SIN8 Input 8 state. Input 8 state following the synchronization specified by INSYNC. 24 1 read-only SIN9 Input 9 state. Input 9 state following the synchronization specified by INSYNC. 25 1 read-only SIN10 Input 10 state. Input 10 state following the synchronization specified by INSYNC. 26 1 read-only SIN11 Input 11 state. Input 11 state following the synchronization specified by INSYNC. 27 1 read-only SIN12 Input 12 state. Input 12 state following the synchronization specified by INSYNC. 28 1 read-only SIN13 Input 13 state. Input 13 state following the synchronization specified by INSYNC. 29 1 read-only SIN14 Input 14 state. Input 14 state following the synchronization specified by INSYNC. 30 1 read-only SIN15 Input 15 state. Input 15 state following the synchronization specified by INSYNC. 31 1 read-only REGMODE SCT match/capture mode register 0x4C 32 read-write 0 0xFFFFFFFF REGMOD_L Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. 0 16 read-write REGMOD_H Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. 16 16 read-write OUTPUT SCT output register 0x50 32 read-write 0 0xFFFF OUT Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write OUTPUTDIRCTRL SCT output counter direction control register 0x54 32 read-write 0 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 0 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 2 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 4 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 6 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 8 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 10 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 12 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. 14 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. 16 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. 18 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR10 Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. 20 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR11 Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. 22 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. 24 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 26 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 28 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 30 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RES SCT conflict resolution register 0x58 32 read-write 0 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. 0 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. 2 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. 4 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. 6 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O4RES Effect of simultaneous set and clear on output 4. 8 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR4 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O5RES Effect of simultaneous set and clear on output 5. 10 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR5 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O6RES Effect of simultaneous set and clear on output 6. 12 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR6 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O7RES Effect of simultaneous set and clear on output 7. 14 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output n (or set based on the SETCLR7 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O8RES Effect of simultaneous set and clear on output 8. 16 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR8 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O9RES Effect of simultaneous set and clear on output 9. 18 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR9 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O10RES Effect of simultaneous set and clear on output 10. 20 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR10 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O11RES Effect of simultaneous set and clear on output 11. 22 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR11 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O12RES Effect of simultaneous set and clear on output 12. 24 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR12 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O13RES Effect of simultaneous set and clear on output 13. 26 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR13 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O14RES Effect of simultaneous set and clear on output 14. 28 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR14 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O15RES Effect of simultaneous set and clear on output 15. 30 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR15 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 DMAREQ0 SCT DMA request 0 register 0x5C 32 read-write 0 0xC000FFFF DEV_0 If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write DRL0 A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 30 1 read-write DRQ0 This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write DMAREQ1 SCT DMA request 1 register 0x60 32 read-write 0 0xC000FFFF DEV_1 If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write DRL1 A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 30 1 read-write DRQ1 This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write EVEN SCT event interrupt enable register 0xF0 32 read-write 0 0xFFFF IEN The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write EVFLAG SCT event flag register 0xF4 32 read-write 0 0xFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write CONEN SCT conflict interrupt enable register 0xF8 32 read-write 0 0xFFFF NCEN The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write CONFLAG SCT conflict flag register 0xFC 32 read-write 0 0xC000FFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. 30 1 read-write BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. 31 1 read-write CAP0 SCT capture register of capture channel CAP_MATCH 0x100 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH0 SCT match value register of match channels CAP_MATCH 0x100 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP1 SCT capture register of capture channel CAP_MATCH 0x104 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH1 SCT match value register of match channels CAP_MATCH 0x104 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP2 SCT capture register of capture channel CAP_MATCH 0x108 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH2 SCT match value register of match channels CAP_MATCH 0x108 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP3 SCT capture register of capture channel CAP_MATCH 0x10C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH3 SCT match value register of match channels CAP_MATCH 0x10C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP4 SCT capture register of capture channel CAP_MATCH 0x110 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH4 SCT match value register of match channels CAP_MATCH 0x110 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP5 SCT capture register of capture channel CAP_MATCH 0x114 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH5 SCT match value register of match channels CAP_MATCH 0x114 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP6 SCT capture register of capture channel CAP_MATCH 0x118 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH6 SCT match value register of match channels CAP_MATCH 0x118 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP7 SCT capture register of capture channel CAP_MATCH 0x11C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH7 SCT match value register of match channels CAP_MATCH 0x11C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP8 SCT capture register of capture channel CAP_MATCH 0x120 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH8 SCT match value register of match channels CAP_MATCH 0x120 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP9 SCT capture register of capture channel CAP_MATCH 0x124 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH9 SCT match value register of match channels CAP_MATCH 0x124 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP10 SCT capture register of capture channel CAP_MATCH 0x128 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH10 SCT match value register of match channels CAP_MATCH 0x128 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP11 SCT capture register of capture channel CAP_MATCH 0x12C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH11 SCT match value register of match channels CAP_MATCH 0x12C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP12 SCT capture register of capture channel CAP_MATCH 0x130 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH12 SCT match value register of match channels CAP_MATCH 0x130 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP13 SCT capture register of capture channel CAP_MATCH 0x134 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH13 SCT match value register of match channels CAP_MATCH 0x134 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP14 SCT capture register of capture channel CAP_MATCH 0x138 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH14 SCT match value register of match channels CAP_MATCH 0x138 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAP15 SCT capture register of capture channel CAP_MATCH 0x13C 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write MATCH15 SCT match value register of match channels CAP_MATCH 0x13C 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write CAPCTRL0 SCT capture control register CAPCTRL_MATCHREL 0x200 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL0 SCT match reload value register CAPCTRL_MATCHREL 0x200 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL1 SCT capture control register CAPCTRL_MATCHREL 0x204 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL1 SCT match reload value register CAPCTRL_MATCHREL 0x204 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL2 SCT capture control register CAPCTRL_MATCHREL 0x208 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL2 SCT match reload value register CAPCTRL_MATCHREL 0x208 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL3 SCT capture control register CAPCTRL_MATCHREL 0x20C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL3 SCT match reload value register CAPCTRL_MATCHREL 0x20C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL4 SCT capture control register CAPCTRL_MATCHREL 0x210 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL4 SCT match reload value register CAPCTRL_MATCHREL 0x210 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL5 SCT capture control register CAPCTRL_MATCHREL 0x214 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL5 SCT match reload value register CAPCTRL_MATCHREL 0x214 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL6 SCT capture control register CAPCTRL_MATCHREL 0x218 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL6 SCT match reload value register CAPCTRL_MATCHREL 0x218 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL7 SCT capture control register CAPCTRL_MATCHREL 0x21C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL7 SCT match reload value register CAPCTRL_MATCHREL 0x21C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL8 SCT capture control register CAPCTRL_MATCHREL 0x220 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL8 SCT match reload value register CAPCTRL_MATCHREL 0x220 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL9 SCT capture control register CAPCTRL_MATCHREL 0x224 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL9 SCT match reload value register CAPCTRL_MATCHREL 0x224 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL10 SCT capture control register CAPCTRL_MATCHREL 0x228 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL10 SCT match reload value register CAPCTRL_MATCHREL 0x228 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL11 SCT capture control register CAPCTRL_MATCHREL 0x22C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL11 SCT match reload value register CAPCTRL_MATCHREL 0x22C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL12 SCT capture control register CAPCTRL_MATCHREL 0x230 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL12 SCT match reload value register CAPCTRL_MATCHREL 0x230 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL13 SCT capture control register CAPCTRL_MATCHREL 0x234 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL13 SCT match reload value register CAPCTRL_MATCHREL 0x234 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL14 SCT capture control register CAPCTRL_MATCHREL 0x238 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL14 SCT match reload value register CAPCTRL_MATCHREL 0x238 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write CAPCTRL15 SCT capture control register CAPCTRL_MATCHREL 0x23C 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write MATCHREL15 SCT match reload value register CAPCTRL_MATCHREL 0x23C 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write 16 0x8 EV[%s] no description available 0x300 EV_STATE SCT event state register 0 0 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 16 read-write EV_CTRL SCT event control register 0 0x4 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write L_COUNTER Selects the L state and the L match register selected by MATCHSEL. 0 H_COUNTER Selects the H state and the H match register selected by MATCHSEL. 0x1 OUTSEL Input/output select 5 1 read-write INPUT Selects the inputs selected by IOSEL. 0 OUTPUT Selects the outputs selected by IOSEL. 0x1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write LOW LOW 0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write OR OR. The event occurs when either the specified match or I/O condition occurs. 0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write ADD STATEV value is added into STATE (the carry-out is ignored). 0 LOAD STATEV value is loaded into STATE. 0x1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write DIRECTION_INDEPENDENT Direction independent. This event is triggered regardless of the count direction. 0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 10 0x8 OUT[%s] no description available 0x500 OUT_SET SCT output 0 set register 0 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 16 read-write OUT_CLR SCT output 0 clear register 0x4 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 16 read-write FLEXCOMM0 Flexcomm serial communication FLEXCOMM FLEXCOMM 0x40086000 0 0x1000 registers FLEXCOMM0 14 PSELID Peripheral Select and Flexcomm ID register. 0xFF8 32 read-write 0x101000 0xFFFFF0FF PERSEL Peripheral Select. This field is writable by software. 0 3 read-write NO_PERIPH_SELECTED No peripheral selected. 0 USART USART function selected. 0x1 SPI SPI function selected. 0x2 I2C I2C function selected. 0x3 I2S_TRANSMIT I2S transmit function selected. 0x4 I2S_RECEIVE I2S receive function selected. 0x5 LOCK Lock the peripheral select. This field is writable by software. 3 1 read-write UNLOCKED Peripheral select can be changed by software. 0 LOCKED Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. 0x1 USARTPRESENT USART present indicator. This field is Read-only. 4 1 read-only NOT_PRESENT This Flexcomm does not include the USART function. 0 PRESENT This Flexcomm includes the USART function. 0x1 SPIPRESENT SPI present indicator. This field is Read-only. 5 1 read-only NOT_PRESENT This Flexcomm does not include the SPI function. 0 PRESENT This Flexcomm includes the SPI function. 0x1 I2CPRESENT I2C present indicator. This field is Read-only. 6 1 read-only NOT_PRESENT This Flexcomm does not include the I2C function. 0 PRESENT This Flexcomm includes the I2C function. 0x1 I2SPRESENT I 2S present indicator. This field is Read-only. 7 1 read-only NOT_PRESENT This Flexcomm does not include the I2S function. 0 PRESENT This Flexcomm includes the I2S function. 0x1 ID Flexcomm ID. 12 20 read-only PID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE size aperture for the register port on the bus (APB or AHB). 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only FLEXCOMM1 Flexcomm serial communication FLEXCOMM 0x40087000 0 0x1000 registers FLEXCOMM1 15 FLEXCOMM2 Flexcomm serial communication FLEXCOMM 0x40088000 0 0x1000 registers FLEXCOMM2 16 FLEXCOMM3 Flexcomm serial communication FLEXCOMM 0x40089000 0 0x1000 registers FLEXCOMM3 17 FLEXCOMM4 Flexcomm serial communication FLEXCOMM 0x4008A000 0 0x1000 registers FLEXCOMM4 18 FLEXCOMM5 Flexcomm serial communication FLEXCOMM 0x40096000 0 0x1000 registers FLEXCOMM5 19 FLEXCOMM6 Flexcomm serial communication FLEXCOMM 0x40097000 0 0x1000 registers FLEXCOMM6 20 FLEXCOMM7 Flexcomm serial communication FLEXCOMM 0x40098000 0 0x1000 registers FLEXCOMM7 21 FLEXCOMM8 Flexcomm serial communication FLEXCOMM 0x4009F000 0 0x1000 registers FLEXCOMM8 59 I2C0 I2C-bus interfaces FLEXCOMM0 I2C I2C 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG Configuration for shared functions. 0x800 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write DISABLED Disabled. The I2C Master function is disabled. 0 ENABLED Enabled. The I2C Master function is enabled. 0x1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write DISABLED Disabled. The I2C slave function is disabled. 0 ENABLED Enabled. The I2C slave function is enabled. 0x1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write DISABLED Disabled. The I2C Monitor function is disabled. 0 ENABLED Enabled. The I2C Monitor function is enabled. 0x1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write DISABLED Disabled. Time-out function is disabled. 0 ENABLED Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. 0x1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write DISABLED Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. 0 ENABLED Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. 0x1 HSCAPABLE High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. 5 1 read-write FAST_MODE_PLUS Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, 0 HIGH_SPEED High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. 0x1 STAT Status register for Master, Slave, and Monitor functions. 0x804 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only IN_PROGRESS In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 0 PENDING Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. 0x1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only IDLE Idle. The Master function is available to be used for a new transaction. 0 RECEIVE_READY Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x1 TRANSMIT_READY Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x2 NACK_ADDRESS NACK Address. Slave NACKed address. 0x3 NACK_DATA NACK Data. Slave NACKed transmitted data. 0x4 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write NO_LOSS No Arbitration Loss has occurred. 0 ARBITRATION_LOSS Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 0x1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write NO_ERROR No Start/Stop Error has occurred. 0 ERROR The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. 0x1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only IN_PROGRESS In progress. The Slave function does not currently need service. 0 PENDING Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 0x1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only SLAVE_ADDRESS Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 0 SLAVE_RECEIVE Slave receive. Received data is available (Slave Receiver mode). 0x1 SLAVE_TRANSMIT Slave transmit. Data can be transmitted (Slave Transmitter mode). 0x2 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only STRETCHING Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 0 NOT_STRETCHING Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. 0x1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only ADDRESS0 Address 0. Slave address 0 was matched. 0 ADDRESS1 Address 1. Slave address 1 was matched. 0x1 ADDRESS2 Address 2. Slave address 2 was matched. 0x2 ADDRESS3 Address 3. Slave address 3 was matched. 0x3 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only NOT_SELECTED Not selected. The Slave function is not currently selected. 0 SELECTED Selected. The Slave function is currently selected. 0x1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write NOT_DESELECTED Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. 0 DESELECTED Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 0x1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only NO_DATA No data. The Monitor function does not currently have data available. 0 DATA_WAITING Data waiting. The Monitor function has data waiting to be read. 0x1 MONOV Monitor Overflow flag. 17 1 read-write NO_OVERRUN No overrun. Monitor data has not overrun. 0 OVERRUN Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 0x1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only INACTIVE Inactive. The Monitor function considers the I2C bus to be inactive. 0 ACTIVE Active. The Monitor function considers the I2C bus to be active. 0x1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write NOT_IDLE Not idle. The I2C bus is not idle, or this flag has been cleared by software. 0 IDLE Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 0x1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write NO_TIMEOUT No time-out. I2C bus events have not caused a time-out. 0 EVEN_TIMEOUT Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 0x1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write NO_TIMEOUT No time-out. SCL low time has not caused a time-out. 0 TIMEOUT Time-out. SCL low time has caused a time-out. 0x1 INTENSET Interrupt Enable Set and read register. 0x808 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write DISABLED Disabled. The MstPending interrupt is disabled. 0 ENABLED Enabled. The MstPending interrupt is enabled. 0x1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write DISABLED Disabled. The MstArbLoss interrupt is disabled. 0 ENABLED Enabled. The MstArbLoss interrupt is enabled. 0x1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write DISABLED Disabled. The MstStStpErr interrupt is disabled. 0 ENABLED Enabled. The MstStStpErr interrupt is enabled. 0x1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write DISABLED Disabled. The SlvPending interrupt is disabled. 0 ENABLED Enabled. The SlvPending interrupt is enabled. 0x1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write DISABLED Disabled. The SlvNotStr interrupt is disabled. 0 ENABLED Enabled. The SlvNotStr interrupt is enabled. 0x1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write DISABLED Disabled. The SlvDeSel interrupt is disabled. 0 ENABLED Enabled. The SlvDeSel interrupt is enabled. 0x1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write DISABLED Disabled. The MonRdy interrupt is disabled. 0 ENABLED Enabled. The MonRdy interrupt is enabled. 0x1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write DISABLED Disabled. The MonOv interrupt is disabled. 0 ENABLED Enabled. The MonOv interrupt is enabled. 0x1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write DISABLED Disabled. The MonIdle interrupt is disabled. 0 ENABLED Enabled. The MonIdle interrupt is enabled. 0x1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write DISABLED Disabled. The Event time-out interrupt is disabled. 0 ENABLED Enabled. The Event time-out interrupt is enabled. 0x1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write DISABLED Disabled. The SCL time-out interrupt is disabled. 0 ENABLED Enabled. The SCL time-out interrupt is enabled. 0x1 INTENCLR Interrupt Enable Clear register. 0x80C 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x810 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x814 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x818 32 read-only 0x801 0x30B8951 MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x820 32 read-write 0 0xE MSTCONTINUE Master Continue. This bit is write-only. 0 1 write-only NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 0x1 MSTSTART Master Start control. This bit is write-only. 1 1 read-write NO_EFFECT No effect. 0 START Start. A Start will be generated on the I2C bus at the next allowed time. 0x1 MSTSTOP Master Stop control. This bit is write-only. 2 1 read-write NO_EFFECT No effect. 0 STOP Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). 0x1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write DISABLED Disable. No DMA requests are generated for master operation. 0 ENABLED Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 0x1 MSTTIME Master timing configuration. 0x824 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write CLOCKS_2 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 0 CLOCKS_3 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 0x1 CLOCKS_4 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 0x2 CLOCKS_5 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 0x3 CLOCKS_6 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 0x4 CLOCKS_7 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 0x5 CLOCKS_8 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 0x6 CLOCKS_9 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 0x7 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write CLOCKS_2 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 0 CLOCKS_3 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 0x1 CLOCKS_4 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 0x2 CLOCKS_5 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 0x3 CLOCKS_6 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 0x4 CLOCKS_7 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 0x5 CLOCKS_8 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 0x6 CLOCKS_9 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 0x7 MSTDAT Combined Master receiver and transmitter data register. 0x828 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x840 32 read-write 0 0x30B SLVCONTINUE Slave Continue. 0 1 read-write NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. 0x1 SLVNACK Slave NACK. 1 1 read-write NO_EFFECT No effect. 0 NACK NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 0x1 SLVDMA Slave DMA enable. 3 1 read-write DISABLED Disabled. No DMA requests are issued for Slave mode operation. 0 ENABLED Enabled. DMA requests are issued for I2C slave data transmission and reception. 0x1 AUTOACK Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. 8 1 read-write NORMAL Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). 0 AUTOMATIC_ACK A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. 0x1 AUTOMATCHREAD When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. 9 1 read-write I2C_WRITE The expected next operation in Automatic Mode is an I2C write. 0 I2C_READ The expected next operation in Automatic Mode is an I2C read. 0x1 SLVDAT Combined Slave receiver and transmitter data register. 0x844 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write SLVADR0 Slave address register. 0x848 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write ENABLED Enabled. Slave Address n is enabled. 0 DISABLED Ignored Slave Address n is ignored. 0x1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write AUTONACK Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. 15 1 read-write NORMAL Normal operation, matching I2C addresses are not ignored. 0 AUTOMATIC Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. 0x1 SLVADR1 Slave address register. 0x84C 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write ENABLED Enabled. Slave Address n is enabled. 0 DISABLED Ignored Slave Address n is ignored. 0x1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR2 Slave address register. 0x850 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write ENABLED Enabled. Slave Address n is enabled. 0 DISABLED Ignored Slave Address n is ignored. 0x1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVADR3 Slave address register. 0x854 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write ENABLED Enabled. Slave Address n is enabled. 0 DISABLED Ignored Slave Address n is ignored. 0x1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write SLVQUAL0 Slave Qualification for address 0. 0x858 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write MASK Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 0 EXTEND Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 0x1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x880 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only NO_START_DETECTED No start detected. The Monitor function has not detected a Start event on the I2C bus. 0 START_DETECTED Start detected. The Monitor function has detected a Start event on the I2C bus. 0x1 MONRESTART Monitor Received Repeated Start. 9 1 read-only NOT_DETECTED No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 0 DETECTED Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 0x1 MONNACK Monitor Received NACK. 10 1 read-only ACKNOWLEDGED Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 0 NOT_ACKNOWLEDGED Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 0x1 ID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only I2C1 I2C-bus interfaces FLEXCOMM1 I2C 0x40087000 0 0x1000 registers FLEXCOMM1 15 I2C2 I2C-bus interfaces FLEXCOMM2 I2C 0x40088000 0 0x1000 registers FLEXCOMM2 16 I2C3 I2C-bus interfaces FLEXCOMM3 I2C 0x40089000 0 0x1000 registers FLEXCOMM3 17 I2C4 I2C-bus interfaces FLEXCOMM4 I2C 0x4008A000 0 0x1000 registers FLEXCOMM4 18 I2C5 I2C-bus interfaces FLEXCOMM5 I2C 0x40096000 0 0x1000 registers FLEXCOMM5 19 I2C6 I2C-bus interfaces FLEXCOMM6 I2C 0x40097000 0 0x1000 registers FLEXCOMM6 20 I2C7 I2C-bus interfaces FLEXCOMM7 I2C 0x40098000 0 0x1000 registers FLEXCOMM7 21 I2S0 I2S interface FLEXCOMM0 I2S I2S 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG1 Configuration register 1 for the primary channel pair. 0xC00 32 read-write 0 0x1F3FFF MAINENABLE Main enable for I 2S function in this Flexcomm 0 1 read-write DISABLED All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. 0 ENABLED This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. 0x1 DATAPAUSE Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. 1 1 read-write NORMAL Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. 0 PAUSE A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. 0x1 PAIRCOUNT Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. 2 2 read-write PAIRS_1 1 I2S channel pairs in this flexcomm 0 PAIRS_2 2 I2S channel pairs in this flexcomm 0x1 PAIRS_3 3 I2S channel pairs in this flexcomm 0x2 PAIRS_4 4 I2S channel pairs in this flexcomm 0x3 MSTSLVCFG Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. 4 2 read-write NORMAL_SLAVE_MODE Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. 0 WS_SYNC_MASTER WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. 0x1 MASTER_USING_SCK Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. 0x2 NORMAL_MASTER Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. 0x3 MODE Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. 6 2 read-write CLASSIC_MODE I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. 0 DSP_MODE_WS_50_DUTYCYCLE DSP mode where WS has a 50% duty cycle. See remark for mode 0. 0x1 DSP_MODE_WS_1_CLOCK DSP mode where WS has a one clock long pulse at the beginning of each data frame. 0x2 DSP_MODE_WS_1_DATA DSP mode where WS has a one data slot long pulse at the beginning of each data frame. 0x3 RIGHTLOW Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. 8 1 read-write RIGHT_HIGH The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. 0 RIGHT_LOW The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. 0x1 LEFTJUST Left Justify data. 9 1 read-write RIGHT_JUSTIFIED Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. 0 LEFT_JUSTIFIED Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. 0x1 ONECHANNEL Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. 10 1 read-write DUAL_CHANNEL I2S data for this channel pair is treated as left and right channels. 0 SINGLE_CHANNEL I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. 0x1 SCK_POL SCK polarity. 12 1 read-write FALLING_EDGE Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). 0 RISING_EDGE Data is launched on SCK rising edges and sampled on SCK falling edges. 0x1 WS_POL WS polarity. 13 1 read-write NOT_INVERTED Data frames begin at a falling edge of WS (standard for classic I2S). 0 INVERTED WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). 0x1 DATALEN Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length 16 5 read-write CFG2 Configuration register 2 for the primary channel pair. 0xC04 32 read-write 0 0x1FF01FF FRAMELEN Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly. 0 9 read-write POSITION Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase. 16 9 read-write STAT Status register for the primary channel pair. 0xC08 32 read-write 0 0xD BUSY Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. 0 1 read-only IDLE The transmitter/receiver for channel pair is currently idle. 0 BUSY The transmitter/receiver for channel pair is currently processing data. 0x1 SLVFRMERR Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. 1 1 write-only NO_ERROR No error has been recorded. 0 ERROR An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. 0x1 LR Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. 2 1 read-only LEFT_CHANNEL Left channel. 0 RIGHT_CHANNEL Right channel. 0x1 DATAPAUSED Data Paused status flag. Applies to all I2S channels 3 1 read-only NOT_PAUSED Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. 0 PAUSED A data pause has been requested and is now in force. 0x1 DIV Clock divider, used by all channel pairs. 0xC1C 32 read-write 0 0xFFF DIV This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096. 0 12 read-write FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 TXI2SE0 Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. 2 1 read-write LAST_VALUE If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. 0 ZERO If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. 0x1 PACK48 Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. 3 1 read-write BIT_24 48-bit I2S FIFO entries are handled as all 24-bit values. 0 BIT_32_16 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 14 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. 0x1 WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 15 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 write-only 0 0 TXDATA Transmit data to the FIFO. The number of bits used depends on configuration details. 0 32 write-only FIFOWR48H FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. 0xE24 32 write-only 0 0 TXDATA Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. 0 24 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0 RXDATA Received data from the FIFO. The number of bits used depends on configuration details. 0 32 read-only FIFORD48H FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. 0xE34 32 read-only 0 0xFFFFFF RXDATA Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 0 24 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0 RXDATA Received data from the FIFO. 0 32 read-only FIFORD48HNOPOP FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. 0xE44 32 read-only 0 0xFFFFFF RXDATA Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. 0 24 read-only ID I2S Module identification 0xFFC 32 read-only 0xE0900000 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation, starting at 0. 8 4 read-only MAJOR_REV Major revision of module implementation, starting at 0. 12 4 read-only ID Unique module identifier for this IP block. 16 16 read-only I2S1 I2S interface FLEXCOMM1 I2S 0x40087000 0 0x1000 registers FLEXCOMM1 15 I2S2 I2S interface FLEXCOMM2 I2S 0x40088000 0 0x1000 registers FLEXCOMM2 16 I2S3 I2S interface FLEXCOMM3 I2S 0x40089000 0 0x1000 registers FLEXCOMM3 17 I2S4 I2S interface FLEXCOMM4 I2S 0x4008A000 0 0x1000 registers FLEXCOMM4 18 I2S5 I2S interface FLEXCOMM5 I2S 0x40096000 0 0x1000 registers FLEXCOMM5 19 I2S6 I2S interface FLEXCOMM6 I2S 0x40097000 0 0x1000 registers FLEXCOMM6 20 I2S7 I2S interface FLEXCOMM7 I2S 0x40098000 0 0x1000 registers FLEXCOMM7 21 SPI0 Serial Peripheral Interfaces (SPI) FLEXCOMM0 SPI SPI 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG SPI Configuration register 0x400 32 read-write 0 0xFBD ENABLE SPI enable. 0 1 read-write DISABLED Disabled. The SPI is disabled and the internal state machine and counters are reset. 0 ENABLED Enabled. The SPI is enabled for operation. 0x1 MASTER Master mode select. 2 1 read-write SLAVE_MODE Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 0 MASTER_MODE Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 0x1 LSBF LSB First mode enable. 3 1 read-write STANDARD Standard. Data is transmitted and received in standard MSB first order. 0 REVERSE Reverse. Data is transmitted and received in reverse order (LSB first). 0x1 CPHA Clock Phase select. 4 1 read-write CHANGE Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. 0 CAPTURE Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. 0x1 CPOL Clock Polarity select. 5 1 read-write LOW Low. The rest state of the clock (between transfers) is low. 0 HIGH High. The rest state of the clock (between transfers) is high. 0x1 LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 7 1 read-write DISABLED Disabled. 0 ENABLED Enabled. 0x1 SPOL0 SSEL0 Polarity select. 8 1 read-write LOW Low. The SSEL0 pin is active low. 0 HIGH High. The SSEL0 pin is active high. 0x1 SPOL1 SSEL1 Polarity select. 9 1 read-write LOW Low. The SSEL1 pin is active low. 0 HIGH High. The SSEL1 pin is active high. 0x1 SPOL2 SSEL2 Polarity select. 10 1 read-write LOW Low. The SSEL2 pin is active low. 0 HIGH High. The SSEL2 pin is active high. 0x1 SPOL3 SSEL3 Polarity select. 11 1 read-write LOW Low. The SSEL3 pin is active low. 0 HIGH High. The SSEL3 pin is active high. 0x1 DLY SPI Delay register 0x404 32 read-write 0 0xFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 0 4 read-write POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. 12 4 read-write STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position. 0x408 32 read-write 0x100 0x1C0 SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. 8 1 read-only INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x40C 32 read-write 0 0x130 SSAEN Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. 4 1 read-write DISABLED Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0 ENABLED Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0x1 SSDEN Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. 5 1 read-write DISABLED Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. 0 ENABLED Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. 0x1 MSTIDLEEN Master idle interrupt enable. 8 1 read-write DISABLED No interrupt will be generated when the SPI master function is idle. 0 ENABLED An interrupt will be generated when the SPI master function is fully idle. 0x1 INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x410 32 write-only 0 0 SSAEN Writing 1 clears the corresponding bit in the INTENSET register. 4 1 write-only SSDEN Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only MSTIDLE Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DIV SPI clock Divider 0x424 32 read-write 0 0xFFFF DIVVAL Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. 0 16 read-write INTSTAT SPI Interrupt Status 0x428 32 read-only 0 0x130 SSA Slave Select Assert. 4 1 read-only SSD Slave Select Deassert. 5 1 read-only MSTIDLE Master Idle status flag. 8 1 read-only FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 14 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. 0x1 WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 15 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 read-write 0 0 TXDATA Transmit data to the FIFO. 0 16 write-only TXSSEL0_N Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. 16 1 write-only ASSERTED SSEL0 asserted. 0 NOT_ASSERTED SSEL0 not asserted. 0x1 TXSSEL1_N Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. 17 1 write-only ASSERTED SSEL1 asserted. 0 NOT_ASSERTED SSEL1 not asserted. 0x1 TXSSEL2_N Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. 18 1 write-only ASSERTED SSEL2 asserted. 0 NOT_ASSERTED SSEL2 not asserted. 0x1 TXSSEL3_N Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. 19 1 write-only ASSERTED SSEL3 asserted. 0 NOT_ASSERTED SSEL3 not asserted. 0x1 EOT End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. 20 1 write-only NOT_DEASSERTED SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 0 DEASSERTED SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 0x1 EOF End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 21 1 write-only NOT_EOF Data not EOF. This piece of data transmitted is not treated as the end of a frame. 0 EOF Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. 0x1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. 22 1 write-only READ Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. 0 IGNORE Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 0x1 LEN Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length. 24 4 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. 0 16 read-only RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bits. 20 1 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. 0 16 read-only RXSSEL0_N Slave Select for receive. 16 1 read-only RXSSEL1_N Slave Select for receive. 17 1 read-only RXSSEL2_N Slave Select for receive. 18 1 read-only RXSSEL3_N Slave Select for receive. 19 1 read-only SOT Start of transfer flag. 20 1 read-only ID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only SPI1 Serial Peripheral Interfaces (SPI) FLEXCOMM1 SPI 0x40087000 0 0x1000 registers FLEXCOMM1 15 SPI2 Serial Peripheral Interfaces (SPI) FLEXCOMM2 SPI 0x40088000 0 0x1000 registers FLEXCOMM2 16 SPI3 Serial Peripheral Interfaces (SPI) FLEXCOMM3 SPI 0x40089000 0 0x1000 registers FLEXCOMM3 17 SPI4 Serial Peripheral Interfaces (SPI) FLEXCOMM4 SPI 0x4008A000 0 0x1000 registers FLEXCOMM4 18 SPI5 Serial Peripheral Interfaces (SPI) FLEXCOMM5 SPI 0x40096000 0 0x1000 registers FLEXCOMM5 19 SPI6 Serial Peripheral Interfaces (SPI) FLEXCOMM6 SPI 0x40097000 0 0x1000 registers FLEXCOMM6 20 SPI7 Serial Peripheral Interfaces (SPI) FLEXCOMM7 SPI 0x40098000 0 0x1000 registers FLEXCOMM7 21 SPI8 Serial Peripheral Interfaces (SPI) FLEXCOMM8 SPI 0x4009F000 0 0x1000 registers FLEXCOMM8 59 USART0 USARTs FLEXCOMM0 USART USART 0x40086000 0 0x1000 registers FLEXCOMM0 14 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write DISABLED Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. 0 ENABLED Enabled. The USART is enabled for operation. 0x1 DATALEN Selects the data size for the USART. 2 2 read-write BIT_7 7 bit Data length. 0 BIT_8 8 bit Data length. 0x1 BIT_9 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 0x2 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write NO_PARITY No parity. 0 EVEN_PARITY Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x2 ODD_PARITY Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. 0x3 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write BIT_1 1 stop bit. 0 BITS_2 2 stop bits. This setting should only be used for asynchronous communication. 0x1 MODE32K Selects standard or 32 kHz clocking mode. 7 1 read-write DISABLED Disabled. USART uses standard clocking. 0 ENABLED Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 0x1 LINMODE LIN break mode enable. 8 1 read-write DISABLED Disabled. Break detect and generate is configured for normal operation. 0 ENABLED Enabled. Break detect and generate is configured for LIN bus operation. 0x1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. 9 1 read-write DISABLED No flow control. The transmitter does not receive any automatic flow control signal. 0 ENABLED Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 0x1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write ASYNCHRONOUS_MODE Asynchronous mode. 0 SYNCHRONOUS_MODE Synchronous mode. 0x1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write FALLING_EDGE Falling edge. Un_RXD is sampled on the falling edge of SCLK. 0 RISING_EDGE Rising edge. Un_RXD is sampled on the rising edge of SCLK. 0x1 SYNCMST Synchronous mode Master select. 14 1 read-write SLAVE Slave. When synchronous mode is enabled, the USART is a slave. 0 MASTER Master. When synchronous mode is enabled, the USART is a master. 0x1 LOOP Selects data loopback mode. 15 1 read-write NORMAL Normal operation. 0 LOOPBACK Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 0x1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write DISABLED Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 0 ENABLED Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. 0x1 AUTOADDR Automatic Address matching enable. 19 1 read-write DISABLED Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 0 ENABLED Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. 0x1 OESEL Output Enable Select. 20 1 read-write STANDARD Standard. The RTS signal is used as the standard flow control function. 0 RS_485 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 0x1 OEPOL Output Enable Polarity. 21 1 read-write LOW Low. If selected by OESEL, the output enable is active low. 0 HIGH High. If selected by OESEL, the output enable is active high. 0x1 RXPOL Receive data polarity. 22 1 read-write STANDARD Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 0x1 TXPOL Transmit data polarity. 23 1 read-write STANDARD Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 0x1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write NORMAL Normal operation. 0 CONTINOUS Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 0x1 ADDRDET Enable address detect mode. 2 1 read-write DISABLED Disabled. The USART presents all incoming data. 0 ENABLED Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. 0x1 TXDIS Transmit Disable. 6 1 read-write ENABLED Not disabled. USART transmitter is not disabled. 0 DISABLED Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. 0x1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write CLOCK_ON_CHARACTER Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 0 CONTINOUS_CLOCK Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). 0x1 CLRCCONRX Clear Continuous Clock. 9 1 read-write NO_EFFECT No effect. No effect on the CC bit. 0 AUTO_CLEAR Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 0x1 AUTOBAUD Autobaud enable. 16 1 read-write DISABLED Disabled. USART is in normal operating mode. 0 ENABLED Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. 0x1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xA 0x45A RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 write-only TXDISSTAT Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). 6 1 read-only RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. 11 1 write-only START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 write-only FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 write-only PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 write-only RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 write-only ABERR Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. 16 1 write-only INTENSET Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F868 TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. 15 1 read-write ABERREN When 1, enables an interrupt when an auto baud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-only 0 0x1F968 TXIDLE Transmitter Idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERRINT Auto baud Error Interrupt flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 WAKETX Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 14 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. 0x1 WAKERX Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. 15 1 read-write DISABLED Only enabled interrupts will wake up the device form reduced power modes. 0 ENABLED A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 read-write 0 0 TXDATA Transmit data to the FIFO. 0 9 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 0 9 read-only FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. 15 1 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 0 9 read-only FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. 15 1 read-only ID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation. 8 4 read-only MAJOR_REV Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only USART1 USARTs FLEXCOMM1 USART 0x40087000 0 0x1000 registers FLEXCOMM1 15 USART2 USARTs FLEXCOMM2 USART 0x40088000 0 0x1000 registers FLEXCOMM2 16 USART3 USARTs FLEXCOMM3 USART 0x40089000 0 0x1000 registers FLEXCOMM3 17 USART4 USARTs FLEXCOMM4 USART 0x4008A000 0 0x1000 registers FLEXCOMM4 18 USART5 USARTs FLEXCOMM5 USART 0x40096000 0 0x1000 registers FLEXCOMM5 19 USART6 USARTs FLEXCOMM6 USART 0x40097000 0 0x1000 registers FLEXCOMM6 20 USART7 USARTs FLEXCOMM7 USART 0x40098000 0 0x1000 registers FLEXCOMM7 21 MAILBOX Mailbox MAILBOX 0x4008B000 0 0xFC registers MAILBOX 31 2 0x10 MBOXIRQ[%s] no description available 0 IRQ Interrupt request register for the Cortex-M0+ CPU. 0 32 read-write 0 0xFFFFFFFF INTREQ If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. 0 32 read-write IRQSET Set bits in IRQ0 0x4 32 write-only 0 0 INTREQSET Writing 1 sets the corresponding bit in the IRQ0 register. 0 32 write-only IRQCLR Clear bits in IRQ0 0x8 32 write-only 0 0 INTREQCLR Writing 1 clears the corresponding bit in the IRQ0 register. 0 32 write-only MUTEX Mutual exclusion register[1] 0xF8 32 read-write 0x1 0x1 EX Cleared when read, set when written. See usage description above. 0 1 read-write GPIO General Purpose I/O (GPIO) GPIO 0x4008C000 0 0x2488 registers 2 0x20 B[%s] no description available 0 32 0x1 B_[%s] Byte pin registers for all port GPIO pins 0 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write 2 0x80 W[%s] no description available 0x1000 32 0x4 W_[%s] Word pin registers for all port GPIO pins 0 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write 2 0x4 DIR[%s] Direction registers for all port GPIO pins 0x2000 32 read-write 0 0xFFFFFFFF DIRP Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. 0 32 read-write 2 0x4 MASK[%s] Mask register for all port GPIO pins 0x2080 32 read-write 0 0xFFFFFFFF MASKP Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. 0 32 read-write 2 0x4 PIN[%s] Port pin register for all port GPIO pins 0x2100 32 read-write 0 0xFFFFFFFF PORT Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. 0 32 read-write 2 0x4 MPIN[%s] Masked port register for all port GPIO pins 0x2180 32 read-write 0 0xFFFFFFFF MPORTP Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. 0 32 read-write 2 0x4 SET[%s] Write: Set register for port. Read: output bits for port 0x2200 32 read-write 0 0xFFFFFFFF SETP Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. 0 32 read-write 2 0x4 CLR[%s] Clear port for all port GPIO pins 0x2280 32 write-only 0 0 CLRP Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. 0 32 write-only 2 0x4 NOT[%s] Toggle port for all port GPIO pins 0x2300 32 write-only 0 0 NOTP Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. 0 32 write-only 2 0x4 DIRSET[%s] Set pin direction bits for port 0x2380 32 write-only 0 0 DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 32 write-only 2 0x4 DIRCLR[%s] Clear pin direction bits for port 0x2400 32 write-only 0 0 DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 32 write-only 2 0x4 DIRNOT[%s] Toggle pin direction bits for port 0x2480 32 write-only 0 0 DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 32 write-only USBHSD USB1 High-speed Device Controller USBHSD 0x40094000 0 0x38 registers USB1 47 USB1_NEEDCLK 48 DEVCMDSTAT USB Device Command/Status register 0 32 read-write 0x800 0xF7DBFFFF DEV_ADDR USB device address. 0 7 read-write DEV_EN USB device enable. 7 1 read-write SETUP SETUP token received. 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on:. 9 1 read-write LPM_SUP LPM Supported:. 11 1 read-write INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP:. 12 1 read-write INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP:. 13 1 read-write INTONNAK_CO Interrupt on NAK for control OUT EP:. 14 1 read-write INTONNAK_CI Interrupt on NAK for control IN EP:. 15 1 read-write DCON Device status - connect. 16 1 read-write DSUS Device status - suspend. 17 1 read-write LPM_SUS Device status - LPM Suspend. 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. 20 1 read-only Speed This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use). 22 2 read-only DCON_C Device status - connect change. 24 1 read-write DSUS_C Device status - suspend change. 25 1 read-write DRES_C Device status - reset change. 26 1 read-write VBUS_DEBOUNCED This bit indicates if VBUS is detected or not. 28 1 read-only PHY_TEST_MODE This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification 29 3 read-write INFO USB Info register 0x4 32 read-only 0x2000000 0xFFFF7FFF FRAME_NR Frame number. 0 11 read-only ERR_CODE The error code which last occurred:. 11 4 read-only MINREV Minor revision. 16 8 read-only MAJREV Major revision. 24 8 read-only EPLISTSTART USB EP Command/Status List start address 0x8 32 read-write 0 0xFFFFFF00 EP_LIST_PRG Programmable portion of the USB EP Command/Status List address. 8 12 read-write EP_LIST_FIXED Fixed portion of USB EP Command/Status List address. 20 12 read-only DATABUFSTART USB Data buffer start address 0xC 32 read-write 0x41000000 0xFFFFFFFF DA_BUF Start address of the memory page where all endpoint data buffers are located. 0 32 read-write LPM USB Link Power Management register 0x10 32 read-write 0 0x1FF HIRD_HW Host Initiated Resume Duration - HW. 0 4 read-only HIRD_SW Host Initiated Resume Duration - SW. 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. 8 1 read-write EPSKIP USB Endpoint skip 0x14 32 read-write 0 0xFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. 0 12 read-write EPINUSE USB Endpoint Buffer in use 0x18 32 read-write 0 0xFFC BUF Buffer in use: This register has one bit per physical endpoint. 2 10 read-write EPBUFCFG USB Endpoint Buffer Configuration register 0x1C 32 read-write 0 0xFFC BUF_SB Buffer usage: This register has one bit per physical endpoint. 2 10 read-write INTSTAT USB interrupt status register 0x20 32 read-write 0 0xC0000FFF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. 0 1 read-write EP0IN Interrupt status register bit for the Control EP0 IN direction. 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. 9 1 read-write EP5OUT Interrupt status register bit for the EP5 OUT direction. 10 1 read-write EP5IN Interrupt status register bit for the EP5 IN direction. 11 1 read-write FRAME_INT Frame interrupt. 30 1 read-write DEV_INT Device status interrupt. 31 1 read-write INTEN USB interrupt enable register 0x24 32 read-write 0 0xC0000FFF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. 0 12 read-write FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line. 31 1 read-write INTSETSTAT USB set interrupt status register 0x28 32 read-write 0 0xC0000FFF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. 0 12 read-write FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. 31 1 read-write EPTOGGLE USB Endpoint toggle register 0x34 32 read-only 0 0x3FFFFFFF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 0 30 read-only CRC_ENGINE CRC engine CRC 0x40095000 0 0xC registers MODE CRC mode register 0 32 read-write 0 0x3F CRC_POLY CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 0 2 read-write BIT_RVS_WR Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 2 1 read-write CMPL_WR Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 3 1 read-write BIT_RVS_SUM CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 4 1 read-write CMPL_SUM CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 5 1 read-write SEED CRC seed register 0x4 32 read-write 0xFFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. 0 32 read-write SUM CRC checksum register SUM_WR_DATA 0x8 32 read-only 0xFFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 0 32 read-only WR_DATA CRC data register SUM_WR_DATA 0x8 32 write-only 0 0 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. 0 32 write-only SDIF SDMMC SDIF 0x4009B000 0 0x300 registers SDIO 42 CTRL Control register 0 32 read-write 0 0x2070FD7 CONTROLLER_RESET Controller reset. 0 1 read-write FIFO_RESET Fifo reset. 1 1 read-write DMA_RESET DMA reset. 2 1 read-write INT_ENABLE Global interrupt enable/disable bit. 4 1 read-write READ_WAIT Read/wait. 6 1 read-write SEND_IRQ_RESPONSE Send irq response. 7 1 read-write ABORT_READ_DATA Abort read data. 8 1 read-write SEND_CCSD Send ccsd. 9 1 read-write SEND_AUTO_STOP_CCSD Send auto stop ccsd. 10 1 read-write CEATA_DEVICE_INTERRUPT_STATUS CEATA device interrupt status. 11 1 read-write CARD_VOLTAGE_A0 Controls the state of the SD_VOLT0 pin. 16 1 read-write CARD_VOLTAGE_A1 Controls the state of the SD_VOLT1 pin. 17 1 read-write CARD_VOLTAGE_A2 Controls the state of the SD_VOLT2 pin. 18 1 read-write USE_INTERNAL_DMAC SD/MMC DMA use. 25 1 read-write PWREN Power Enable register 0x4 32 read-write 0 0x3 POWER_ENABLE0 Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0. 0 1 read-write POWER_ENABLE1 Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1. 1 1 read-write CLKDIV Clock Divider register 0x8 32 read-write 0 0xFF CLK_DIVIDER0 Clock divider-0 value. 0 8 read-write CLKENA Clock Enable register 0x10 32 read-write 0 0x30003 CCLK0_ENABLE Clock-enable control for SD card 0 clock. 0 1 read-write CCLK1_ENABLE Clock-enable control for SD card 1 clock. 1 1 read-write CCLK0_LOW_POWER Low-power control for SD card 0 clock. 16 1 read-write CCLK1_LOW_POWER Low-power control for SD card 1 clock. 17 1 read-write TMOUT Time-out register 0x14 32 read-write 0xFFFFFF40 0xFFFFFFFF RESPONSE_TIMEOUT Response time-out value. 0 8 read-write DATA_TIMEOUT Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. 8 24 read-write CTYPE Card Type register 0x18 32 read-write 0 0x30003 CARD0_WIDTH0 Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0). 0 1 read-write CARD1_WIDTH0 Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0). 1 1 read-write CARD0_WIDTH1 Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. 16 1 read-write CARD1_WIDTH1 Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. 17 1 read-write BLKSIZ Block Size register 0x1C 32 read-write 0x200 0xFFFF BLOCK_SIZE Block size. 0 16 read-write BYTCNT Byte Count register 0x20 32 read-write 0x200 0xFFFFFFFF BYTE_COUNT Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. 0 32 read-write INTMASK Interrupt Mask register 0x24 32 read-write 0 0x1FFFF CDET Card detect. 0 1 read-write RE Response error. 1 1 read-write CDONE Command done. 2 1 read-write DTO Data transfer over. 3 1 read-write TXDR Transmit FIFO data request. 4 1 read-write RXDR Receive FIFO data request. 5 1 read-write RCRC Response CRC error. 6 1 read-write DCRC Data CRC error. 7 1 read-write RTO Response time-out. 8 1 read-write DRTO Data read time-out. 9 1 read-write HTO Data starvation-by-host time-out (HTO). 10 1 read-write FRUN FIFO underrun/overrun error. 11 1 read-write HLE Hardware locked write error. 12 1 read-write SBE Start-bit error. 13 1 read-write ACD Auto command done. 14 1 read-write EBE End-bit error (read)/Write no CRC. 15 1 read-write SDIO_INT_MASK Mask SDIO interrupt. 16 1 read-write CMDARG Command Argument register 0x28 32 read-write 0 0xFFFFFFFF CMD_ARG Value indicates command argument to be passed to card. 0 32 read-write CMD Command register 0x2C 32 read-write 0 0xBFFFFFFF CMD_INDEX Command index. 0 6 read-write RESPONSE_EXPECT Response expect. 6 1 read-write RESPONSE_LENGTH Response length. 7 1 read-write CHECK_RESPONSE_CRC Check response CRC. 8 1 read-write DATA_EXPECTED Data expected. 9 1 read-write READ_WRITE read/write. 10 1 read-write TRANSFER_MODE Transfer mode. 11 1 read-write SEND_AUTO_STOP Send auto stop. 12 1 read-write WAIT_PRVDATA_COMPLETE Wait prvdata complete. 13 1 read-write STOP_ABORT_CMD Stop abort command. 14 1 read-write SEND_INITIALIZATION Send initialization. 15 1 read-write CARD_NUMBER Specifies the card number of SDCARD for which the current Command is being executed 16 5 read-write CARD0 Command will be execute on SDCARD 0 0 CARD1 Command will be execute on SDCARD 1 0x1 UPDATE_CLOCK_REGISTERS_ONLY Update clock registers only. 21 1 read-write READ_CEATA_DEVICE Read ceata device. 22 1 read-write CCS_EXPECTED CCS expected. 23 1 read-write ENABLE_BOOT Enable Boot - this bit should be set only for mandatory boot mode. 24 1 read-write EXPECT_BOOT_ACK Expect Boot Acknowledge. 25 1 read-write DISABLE_BOOT Disable Boot. 26 1 read-write BOOT_MODE Boot Mode. 27 1 read-write VOLT_SWITCH Voltage switch bit. 28 1 read-write USE_HOLD_REG Use Hold Register. 29 1 read-write START_CMD Start command. 31 1 read-write 4 0x4 RESP[%s] Response register 0x30 32 read-write 0 0xFFFFFFFF RESPONSE Bits of response. 0 32 read-write MINTSTS Masked Interrupt Status register 0x40 32 read-write 0 0x1FFFF CDET Card detect. 0 1 read-write RE Response error. 1 1 read-write CDONE Command done. 2 1 read-write DTO Data transfer over. 3 1 read-write TXDR Transmit FIFO data request. 4 1 read-write RXDR Receive FIFO data request. 5 1 read-write RCRC Response CRC error. 6 1 read-write DCRC Data CRC error. 7 1 read-write RTO Response time-out. 8 1 read-write DRTO Data read time-out. 9 1 read-write HTO Data starvation-by-host time-out (HTO). 10 1 read-write FRUN FIFO underrun/overrun error. 11 1 read-write HLE Hardware locked write error. 12 1 read-write SBE Start-bit error. 13 1 read-write ACD Auto command done. 14 1 read-write EBE End-bit error (read)/write no CRC. 15 1 read-write SDIO_INTERRUPT Interrupt from SDIO card. 16 1 read-write RINTSTS Raw Interrupt Status register 0x44 32 read-write 0 0x1FFFF CDET Card detect. 0 1 read-write RE Response error. 1 1 read-write CDONE Command done. 2 1 read-write DTO Data transfer over. 3 1 read-write TXDR Transmit FIFO data request. 4 1 read-write RXDR Receive FIFO data request. 5 1 read-write RCRC Response CRC error. 6 1 read-write DCRC Data CRC error. 7 1 read-write RTO_BAR Response time-out (RTO)/Boot Ack Received (BAR). 8 1 read-write DRTO_BDS Data read time-out (DRTO)/Boot Data Start (BDS). 9 1 read-write HTO Data starvation-by-host time-out (HTO). 10 1 read-write FRUN FIFO underrun/overrun error. 11 1 read-write HLE Hardware locked write error. 12 1 read-write SBE Start-bit error. 13 1 read-write ACD Auto command done. 14 1 read-write EBE End-bit error (read)/write no CRC. 15 1 read-write SDIO_INTERRUPT Interrupt from SDIO card. 16 1 read-write STATUS Status register 0x48 32 read-write 0x406 0xFFFFFFFF FIFO_RX_WATERMARK FIFO reached Receive watermark level; not qualified with data transfer. 0 1 read-write FIFO_TX_WATERMARK FIFO reached Transmit watermark level; not qualified with data transfer. 1 1 read-write FIFO_EMPTY FIFO is empty status. 2 1 read-write FIFO_FULL FIFO is full status. 3 1 read-write CMDFSMSTATES Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. 4 4 read-write DATA_3_STATUS Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. 8 1 read-write DATA_BUSY Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. 9 1 read-write DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy. 10 1 read-write RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. 11 6 read-write FIFO_COUNT FIFO count - Number of filled locations in FIFO. 17 13 read-write DMA_ACK DMA acknowledge signal state. 30 1 read-write DMA_REQ DMA request signal state. 31 1 read-write FIFOTH FIFO Threshold Watermark register 0x4C 32 read-write 0x1F0000 0x7FFF0FFF TX_WMARK FIFO threshold watermark level when transmitting data to card. 0 12 read-write RX_WMARK FIFO threshold watermark level when receiving data to card. 16 12 read-write DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE. 28 3 read-write CDETECT Card Detect register 0x50 32 read-write 0 0x1 CARD0_DETECT Card 0 detect 0 1 read-write CARD1_DETECT Card 1 detect 1 1 read-write WRTPRT Write Protect register 0x54 32 read-write 0 0x1 WRITE_PROTECT Write protect. 0 1 read-write TCBCNT Transferred CIU Card Byte Count register 0x5C 32 read-write 0 0xFFFFFFFF TRANS_CARD_BYTE_COUNT Number of bytes transferred by CIU unit to card. 0 32 read-write TBBCNT Transferred Host to BIU-FIFO Byte Count register 0x60 32 read-write 0 0xFFFFFFFF TRANS_FIFO_BYTE_COUNT Number of bytes transferred between Host/DMA memory and BIU FIFO. 0 32 read-write DEBNCE Debounce Count register 0x64 32 read-write 0xFFFFFF 0xFFFFFF DEBOUNCE_COUNT Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. 0 24 read-write RST_N Hardware Reset 0x78 32 read-write 0x1 0x1 CARD_RESET Hardware reset. 0 1 read-write BMOD Bus Mode register 0x80 32 read-write 0 0x7FF SWR Software Reset. 0 1 read-write FB Fixed Burst. 1 1 read-write DSL Descriptor Skip Length. 2 5 read-write DE SD/MMC DMA Enable. 7 1 read-write PBL Programmable Burst Length. 8 3 read-write PLDMND Poll Demand register 0x84 32 read-write 0 0xFFFFFFFF PD Poll Demand. 0 32 read-write DBADDR Descriptor List Base Address register 0x88 32 read-write 0 0xFFFFFFFF SDL Start of Descriptor List. 0 32 read-write IDSTS Internal DMAC Status register 0x8C 32 read-write 0 0x1FF37 TI Transmit Interrupt. 0 1 read-write RI Receive Interrupt. 1 1 read-write FBE Fatal Bus Error Interrupt. 2 1 read-write DU Descriptor Unavailable Interrupt. 4 1 read-write CES Card Error Summary. 5 1 read-write NIS Normal Interrupt Summary. 8 1 read-write AIS Abnormal Interrupt Summary. 9 1 read-write EB Error Bits. 10 3 read-write FSM DMAC state machine present state. 13 4 read-write IDINTEN Internal DMAC Interrupt Enable register 0x90 32 read-write 0 0x337 TI Transmit Interrupt Enable. 0 1 read-write RI Receive Interrupt Enable. 1 1 read-write FBE Fatal Bus Error Enable. 2 1 read-write DU Descriptor Unavailable Interrupt. 4 1 read-write CES Card Error summary Interrupt Enable. 5 1 read-write NIS Normal Interrupt Summary Enable. 8 1 read-write AIS Abnormal Interrupt Summary Enable. 9 1 read-write DSCADDR Current Host Descriptor Address register 0x94 32 read-write 0 0xFFFFFFFF HDA Host Descriptor Address Pointer. 0 32 read-write BUFADDR Current Buffer Descriptor Address register 0x98 32 read-write 0 0xFFFFFFFF HBA Host Buffer Address Pointer. 0 32 read-write CARDTHRCTL Card Threshold Control 0x100 32 read-write 0 0xFF0003 CARDRDTHREN Card Read Threshold Enable. 0 1 read-write BSYCLRINTEN Busy Clear Interrupt Enable. 1 1 read-write CARDTHRESHOLD Card Threshold size. 16 8 read-write BACKENDPWR Power control 0x104 32 read-write 0 0x1 BACKENDPWR Back-end Power control for card application. 0 1 read-write 64 0x4 FIFO[%s] SDIF FIFO 0x200 32 read-write 0 0xFFFFFFFF DATA SDIF FIFO. 0 32 read-write DBGMAILBOX MCU Debugger Mailbox DBGMAILBOX 0x4009C000 0 0x100 registers CSW CRC mode register 0 32 read-write 0 0x3F RESYNCH_REQ Debugger will set this bit to 1 to request a resynchronrisation 0 1 read-write REQ_PENDING Request is pending from debugger (i.e unread value in REQUEST) 1 1 read-write DBG_OR_ERR Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) 2 1 read-write AHB_OR_ERR AHB overrun Error (Return value overwritten by ROM) 3 1 read-write SOFT_RESET Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM. 4 1 read-write CHIP_RESET_REQ Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) 5 1 write-only REQUEST CRC seed register 0x4 32 read-write 0xFFFF 0xFFFFFFFF REQ Request Value 0 32 read-write RETURN Return value from ROM. 0x8 32 read-write 0 0xFFFFFFFF RET The Return value from ROM. 0 32 read-write ID Identification register 0xFC 32 read-only 0x2A0000 0xFFFFFFFF ID Identification value. 0 32 read-only ADC0 ADC ADC 0x400A0000 0 0x1000 registers ADC0 22 VERID Version ID Register 0 32 read-only 0x1002C0B 0xFFFFFFFF RES Resolution 0 1 read-only RES_0 Up to 13-bit differential/12-bit single ended resolution supported. 0 RES_1 Up to 16-bit differential/16-bit single ended resolution supported. 0x1 DIFFEN Differential Supported 1 1 read-only DIFFEN_0 Differential operation not supported. 0 DIFFEN_1 Differential operation supported. CMDLa[CTYPE] controls fields implemented. 0x1 MVI Multi Vref Implemented 3 1 read-only MVI_0 Single voltage reference high (VREFH) input supported. 0 MVI_1 Multiple voltage reference high (VREFH) inputs supported. 0x1 CSW Channel Scale Width 4 3 read-only CSW_0 Channel scaling not supported. 0 CSW_1 Channel scaling supported. 1-bit CSCALE control field. 0x1 CSW_6 Channel scaling supported. 6-bit CSCALE control field. 0x6 VR1RNGI Voltage Reference 1 Range Control Bit Implemented 8 1 read-only VR1RNGI_0 Range control not required. CFG[VREF1RNG] is not implemented. 0 VR1RNGI_1 Range control required. CFG[VREF1RNG] is implemented. 0x1 IADCKI Internal ADC Clock implemented 9 1 read-only IADCKI_0 Internal clock source not implemented. 0 IADCKI_1 Internal clock source (and CFG[ADCKEN]) implemented. 0x1 CALOFSI Calibration Function Implemented 10 1 read-only CALOFSI_0 Calibration Not Implemented. 0 CALOFSI_1 Calibration Implemented. 0x1 NUM_SEC Number of Single Ended Outputs Supported 11 1 read-only NUM_SEC_0 This design supports one single ended conversion at a time. 0 NUM_SEC_1 This design supports two simultanious single ended conversions. 0x1 NUM_FIFO Number of FIFOs 12 3 read-only NUM_FIFO_0 N/A 0 NUM_FIFO_1 This design supports one result FIFO. 0x1 NUM_FIFO_2 This design supports two result FIFOs. 0x2 NUM_FIFO_3 This design supports three result FIFOs. 0x3 NUM_FIFO_4 This design supports four result FIFOs. 0x4 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0xF041010 0xFFFFFFFF TRIG_NUM Trigger Number 0 8 read-only FIFOSIZE Result FIFO Depth 8 8 read-only FIFOSIZE_1 Result FIFO depth = 1 dataword. 0x1 FIFOSIZE_4 Result FIFO depth = 4 datawords. 0x4 FIFOSIZE_8 Result FIFO depth = 8 datawords. 0x8 FIFOSIZE_16 Result FIFO depth = 16 datawords. 0x10 FIFOSIZE_32 Result FIFO depth = 32 datawords. 0x20 FIFOSIZE_64 Result FIFO depth = 64 datawords. 0x40 CV_NUM Compare Value Number 16 8 read-only CMD_NUM Command Buffer Number 24 8 read-only CTRL ADC Control Register 0x10 32 read-write 0 0xFFFFFFFF ADCEN ADC Enable 0 1 read-write ADCEN_0 ADC is disabled. 0 ADCEN_1 ADC is enabled. 0x1 RST Software Reset 1 1 read-write RST_0 ADC logic is not reset. 0 RST_1 ADC logic is reset. 0x1 DOZEN Doze Enable 2 1 read-write DOZEN_0 ADC is enabled in Doze mode. 0 DOZEN_1 ADC is disabled in Doze mode. 0x1 CAL_REQ Auto-Calibration Request 3 1 read-write CAL_REQ_0 No request for auto-calibration has been made. 0 CAL_REQ_1 A request for auto-calibration has been made 0x1 CALOFS Configure for offset calibration function 4 1 read-write CALOFS_0 Calibration function disabled 0 CALOFS_1 Request for offset calibration function 0x1 RSTFIFO0 Reset FIFO 0 8 1 read-write RSTFIFO0_0 No effect. 0 RSTFIFO0_1 FIFO 0 is reset. 0x1 RSTFIFO1 Reset FIFO 1 9 1 read-write RSTFIFO1_0 No effect. 0 RSTFIFO1_1 FIFO 1 is reset. 0x1 CAL_AVGS Auto-Calibration Averages 16 3 read-write CAL_AVGS_0 Single conversion. 0 CAL_AVGS_1 2 conversions averaged. 0x1 CAL_AVGS_2 4 conversions averaged. 0x2 CAL_AVGS_3 8 conversions averaged. 0x3 CAL_AVGS_4 16 conversions averaged. 0x4 CAL_AVGS_5 32 conversions averaged. 0x5 CAL_AVGS_6 64 conversions averaged. 0x6 CAL_AVGS_7 128 conversions averaged. 0x7 STAT ADC Status Register 0x14 32 read-write 0 0xFFFFFFFF RDY0 Result FIFO 0 Ready Flag 0 1 read-only RDY0_0 Result FIFO 0 data level not above watermark level. 0 RDY0_1 Result FIFO 0 holding data above watermark level. 0x1 FOF0 Result FIFO 0 Overflow Flag 1 1 read-write oneToClear FOF0_0 No result FIFO 0 overflow has occurred since the last time the flag was cleared. 0 FOF0_1 At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. 0x1 RDY1 Result FIFO1 Ready Flag 2 1 read-only RDY1_0 Result FIFO1 data level not above watermark level. 0 RDY1_1 Result FIFO1 holding data above watermark level. 0x1 FOF1 Result FIFO1 Overflow Flag 3 1 read-write oneToClear FOF1_0 No result FIFO1 overflow has occurred since the last time the flag was cleared. 0 FOF1_1 At least one result FIFO1 overflow has occurred since the last time the flag was cleared. 0x1 TEXC_INT Interrupt Flag For High Priority Trigger Exception 8 1 read-write oneToClear TEXC_INT_0 No trigger exceptions have occurred. 0 TEXC_INT_1 A trigger exception has occurred and is pending acknowledgement. 0x1 TCOMP_INT Interrupt Flag For Trigger Completion 9 1 read-write oneToClear TCOMP_INT_0 Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. 0 TCOMP_INT_1 Trigger sequence has been completed and all data is stored in the associated FIFO. 0x1 CAL_RDY Calibration Ready 10 1 read-only CAL_RDY_0 Calibration is incomplete or hasn't been ran. 0 CAL_RDY_1 The ADC is calibrated. 0x1 ADC_ACTIVE ADC Active 11 1 read-only ADC_ACTIVE_0 The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. 0 ADC_ACTIVE_1 The ADC is processing a conversion, running through the power up delay, or servicing a trigger. 0x1 TRGACT Trigger Active 16 4 read-only TRGACT_0 Command (sequence) associated with Trigger 0 currently being executed. 0 TRGACT_1 Command (sequence) associated with Trigger 1 currently being executed. 0x1 TRGACT_2 Command (sequence) associated with Trigger 2 currently being executed. 0x2 TRGACT_3 Command (sequence) from the associated Trigger number is currently being executed. 0x3 TRGACT_4 Command (sequence) from the associated Trigger number is currently being executed. 0x4 TRGACT_5 Command (sequence) from the associated Trigger number is currently being executed. 0x5 TRGACT_6 Command (sequence) from the associated Trigger number is currently being executed. 0x6 TRGACT_7 Command (sequence) from the associated Trigger number is currently being executed. 0x7 TRGACT_8 Command (sequence) from the associated Trigger number is currently being executed. 0x8 TRGACT_9 Command (sequence) from the associated Trigger number is currently being executed. 0x9 CMDACT Command Active 24 4 read-only CMDACT_0 No command is currently in progress. 0 CMDACT_1 Command 1 currently being executed. 0x1 CMDACT_2 Command 2 currently being executed. 0x2 CMDACT_3 Associated command number is currently being executed. 0x3 CMDACT_4 Associated command number is currently being executed. 0x4 CMDACT_5 Associated command number is currently being executed. 0x5 CMDACT_6 Associated command number is currently being executed. 0x6 CMDACT_7 Associated command number is currently being executed. 0x7 CMDACT_8 Associated command number is currently being executed. 0x8 CMDACT_9 Associated command number is currently being executed. 0x9 IE Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF FWMIE0 FIFO 0 Watermark Interrupt Enable 0 1 read-write FWMIE0_0 FIFO 0 watermark interrupts are not enabled. 0 FWMIE0_1 FIFO 0 watermark interrupts are enabled. 0x1 FOFIE0 Result FIFO 0 Overflow Interrupt Enable 1 1 read-write FOFIE0_0 FIFO 0 overflow interrupts are not enabled. 0 FOFIE0_1 FIFO 0 overflow interrupts are enabled. 0x1 FWMIE1 FIFO1 Watermark Interrupt Enable 2 1 read-write FWMIE1_0 FIFO1 watermark interrupts are not enabled. 0 FWMIE1_1 FIFO1 watermark interrupts are enabled. 0x1 FOFIE1 Result FIFO1 Overflow Interrupt Enable 3 1 read-write FOFIE1_0 No result FIFO1 overflow has occurred since the last time the flag was cleared. 0 FOFIE1_1 At least one result FIFO1 overflow has occurred since the last time the flag was cleared. 0x1 TEXC_IE Trigger Exception Interrupt Enable 8 1 read-write TEXC_IE_0 Trigger exception interrupts are disabled. 0 TEXC_IE_1 Trigger exception interrupts are enabled. 0x1 TCOMP_IE Trigger Completion Interrupt Enable 16 16 read-write TCOMP_IE_0 Trigger completion interrupts are disabled. 0 TCOMP_IE_1 Trigger completion interrupts are enabled for trigger source 0 only. 0x1 TCOMP_IE_2 Trigger completion interrupts are enabled for trigger source 1 only. 0x2 TCOMP_IE_3 Associated trigger completion interrupts are enabled. 0x3 TCOMP_IE_4 Associated trigger completion interrupts are enabled. 0x4 TCOMP_IE_5 Associated trigger completion interrupts are enabled. 0x5 TCOMP_IE_6 Associated trigger completion interrupts are enabled. 0x6 TCOMP_IE_7 Associated trigger completion interrupts are enabled. 0x7 TCOMP_IE_8 Associated trigger completion interrupts are enabled. 0x8 TCOMP_IE_9 Associated trigger completion interrupts are enabled. 0x9 TCOMP_IE_65535 Trigger completion interrupts are enabled for every trigger source. 0xFFFF DE DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF FWMDE0 FIFO 0 Watermark DMA Enable 0 1 read-write FWMDE0_0 DMA request disabled. 0 FWMDE0_1 DMA request enabled. 0x1 FWMDE1 FIFO1 Watermark DMA Enable 1 1 read-write FWMDE1_0 DMA request disabled. 0 FWMDE1_1 DMA request enabled. 0x1 CFG ADC Configuration Register 0x20 32 read-write 0x800000 0xFFFFFFFF TPRICTRL ADC trigger priority control 0 2 read-write TPRICTRL_0 If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. 0 TPRICTRL_1 If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. 0x1 TPRICTRL_2 If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. 0x2 PWRSEL Power Configuration Select 4 2 read-write PWRSEL_0 Lowest power setting. 0 PWRSEL_1 Higher power setting than 0b0. 0x1 PWRSEL_2 Higher power setting than 0b1. 0x2 PWRSEL_3 Highest power setting. 0x3 REFSEL Voltage Reference Selection 6 2 read-write REFSEL_0 (Default) Option 1 setting. 0 REFSEL_1 Option 2 setting. 0x1 REFSEL_2 Option 3 setting. 0x2 TRES Trigger Resume Enable 8 1 read-write TRES_0 Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. 0 TRES_1 Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. 0x1 TCMDRES Trigger Command Resume 9 1 read-write TCMDRES_0 Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. 0 TCMDRES_1 Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. 0x1 HPT_EXDI High Priority Trigger Exception Disable 10 1 read-write HPT_EXDI_0 High priority trigger exceptions are enabled. 0 HPT_EXDI_1 High priority trigger exceptions are disabled. 0x1 PUDLY Power Up Delay 16 8 read-write PWREN ADC Analog Pre-Enable 28 1 read-write PWREN_0 ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. 0 PWREN_1 ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed. 0x1 PAUSE ADC Pause Register 0x24 32 read-write 0 0xFFFFFFFF PAUSEDLY Pause Delay 0 9 read-write PAUSEEN PAUSE Option Enable 31 1 read-write PAUSEEN_0 Pause operation disabled 0 PAUSEEN_1 Pause operation enabled 0x1 SWTRIG Software Trigger Register 0x34 32 read-write 0 0xFFFFFFFF SWT0 Software trigger 0 event 0 1 read-write SWT0_0 No trigger 0 event generated. 0 SWT0_1 Trigger 0 event generated. 0x1 SWT1 Software trigger 1 event 1 1 read-write SWT1_0 No trigger 1 event generated. 0 SWT1_1 Trigger 1 event generated. 0x1 SWT2 Software trigger 2 event 2 1 read-write SWT2_0 No trigger 2 event generated. 0 SWT2_1 Trigger 2 event generated. 0x1 SWT3 Software trigger 3 event 3 1 read-write SWT3_0 No trigger 3 event generated. 0 SWT3_1 Trigger 3 event generated. 0x1 SWT4 Software trigger 4 event 4 1 read-write SWT4_0 No trigger 4 event generated. 0 SWT4_1 Trigger 4 event generated. 0x1 SWT5 Software trigger 5 event 5 1 read-write SWT5_0 No trigger 5 event generated. 0 SWT5_1 Trigger 5 event generated. 0x1 SWT6 Software trigger 6 event 6 1 read-write SWT6_0 No trigger 6 event generated. 0 SWT6_1 Trigger 6 event generated. 0x1 SWT7 Software trigger 7 event 7 1 read-write SWT7_0 No trigger 7 event generated. 0 SWT7_1 Trigger 7 event generated. 0x1 SWT8 Software trigger 8 event 8 1 read-write SWT8_0 No trigger 8 event generated. 0 SWT8_1 Trigger 8 event generated. 0x1 SWT9 Software trigger 9 event 9 1 read-write SWT9_0 No trigger 9 event generated. 0 SWT9_1 Trigger 9 event generated. 0x1 SWT10 Software trigger 10 event 10 1 read-write SWT10_0 No trigger 10 event generated. 0 SWT10_1 Trigger 10 event generated. 0x1 SWT11 Software trigger 11 event 11 1 read-write SWT11_0 No trigger 11 event generated. 0 SWT11_1 Trigger 11 event generated. 0x1 SWT12 Software trigger 12 event 12 1 read-write SWT12_0 No trigger 12 event generated. 0 SWT12_1 Trigger 12 event generated. 0x1 SWT13 Software trigger 13 event 13 1 read-write SWT13_0 No trigger 13 event generated. 0 SWT13_1 Trigger 13 event generated. 0x1 SWT14 Software trigger 14 event 14 1 read-write SWT14_0 No trigger 14 event generated. 0 SWT14_1 Trigger 14 event generated. 0x1 SWT15 Software trigger 15 event 15 1 read-write SWT15_0 No trigger 15 event generated. 0 SWT15_1 Trigger 15 event generated. 0x1 TSTAT Trigger Status Register 0x38 32 read-write 0 0xFFFFFFFF TEXC_NUM Trigger Exception Number 0 16 read-write oneToClear TEXC_NUM_0 No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. 0 TEXC_NUM_1 Trigger 0 has been interrupted by a high priority exception. 0x1 TEXC_NUM_2 Trigger 1 has been interrupted by a high priority exception. 0x2 TEXC_NUM_3 Associated trigger sequence has interrupted by a high priority exception. 0x3 TEXC_NUM_4 Associated trigger sequence has interrupted by a high priority exception. 0x4 TEXC_NUM_5 Associated trigger sequence has interrupted by a high priority exception. 0x5 TEXC_NUM_6 Associated trigger sequence has interrupted by a high priority exception. 0x6 TEXC_NUM_7 Associated trigger sequence has interrupted by a high priority exception. 0x7 TEXC_NUM_8 Associated trigger sequence has interrupted by a high priority exception. 0x8 TEXC_NUM_9 Associated trigger sequence has interrupted by a high priority exception. 0x9 TEXC_NUM_65535 Every trigger sequence has been interrupted by a high priority exception. 0xFFFF TCOMP_FLAG Trigger Completion Flag 16 16 read-write oneToClear TCOMP_FLAG_0 No triggers have been completed. Trigger completion interrupts are disabled. 0 TCOMP_FLAG_1 Trigger 0 has been completed and triger 0 has enabled completion interrupts. 0x1 TCOMP_FLAG_2 Trigger 1 has been completed and triger 1 has enabled completion interrupts. 0x2 TCOMP_FLAG_3 Associated trigger sequence has completed and has enabled completion interrupts. 0x3 TCOMP_FLAG_4 Associated trigger sequence has completed and has enabled completion interrupts. 0x4 TCOMP_FLAG_5 Associated trigger sequence has completed and has enabled completion interrupts. 0x5 TCOMP_FLAG_6 Associated trigger sequence has completed and has enabled completion interrupts. 0x6 TCOMP_FLAG_7 Associated trigger sequence has completed and has enabled completion interrupts. 0x7 TCOMP_FLAG_8 Associated trigger sequence has completed and has enabled completion interrupts. 0x8 TCOMP_FLAG_9 Associated trigger sequence has completed and has enabled completion interrupts. 0x9 TCOMP_FLAG_65535 Every trigger sequence has been completed and every trigger has enabled completion interrupts. 0xFFFF OFSTRIM ADC Offset Trim Register 0x40 32 read-write 0 0xFFFFFFFF OFSTRIM_A Trim for offset 0 5 read-write OFSTRIM_B Trim for offset 16 5 read-write 16 0x4 TCTRL[%s] Trigger Control Register 0xA0 32 read-write 0 0xFFFFFFFF HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 FIFO_SEL_A SAR Result Destination For Channel A 1 1 read-write FIFO_SEL_A_0 Result written to FIFO 0 0 FIFO_SEL_A_1 Result written to FIFO 1 0x1 FIFO_SEL_B SAR Result Destination For Channel B 2 1 read-write FIFO_SEL_B_0 Result written to FIFO 0 0 FIFO_SEL_B_1 Result written to FIFO 1 0x1 TPRI Trigger priority setting 8 4 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to corresponding priority level 0x3 TPRI_4 Set to corresponding priority level 0x4 TPRI_5 Set to corresponding priority level 0x5 TPRI_6 Set to corresponding priority level 0x6 TPRI_7 Set to corresponding priority level 0x7 TPRI_8 Set to corresponding priority level 0x8 TPRI_9 Set to corresponding priority level 0x9 TPRI_15 Set to lowest priority, Level 16 0xF RSYNC Trigger Resync 15 1 read-write TDLY Trigger delay select 16 4 read-write TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF 2 0x4 FCTRL[%s] FIFO Control Register 0xE0 32 read-write 0 0xFFFFFFFF FCOUNT Result FIFO counter 0 5 read-only FWMARK Watermark level selection 16 4 read-write 2 0x4 GCC[%s] Gain Calibration Control 0xF0 32 read-only 0 0xFFFFFFFF GAIN_CAL Gain Calibration Value 0 16 read-only RDY Gain Calibration Value Valid 24 1 read-only RDY_0 The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. 0 RDY_1 The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. 0x1 2 0x4 GCR[%s] Gain Calculation Result 0xF8 32 read-write 0 0xFFFFFFFF GCALR Gain Calculation Result 0 16 read-write RDY Gain Calculation Ready 24 1 read-write RDY_0 The gain offset calculation value is invalid. 0 RDY_1 The gain calibration value is valid. 0x1 CMDL1 ADC Command Low Buffer Register 0x100 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH1 ADC Command High Buffer Register 0x104 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL2 ADC Command Low Buffer Register 0x108 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH2 ADC Command High Buffer Register 0x10C 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL3 ADC Command Low Buffer Register 0x110 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH3 ADC Command High Buffer Register 0x114 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL4 ADC Command Low Buffer Register 0x118 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH4 ADC Command High Buffer Register 0x11C 32 read-write 0 0xFFFFFFFF CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL5 ADC Command Low Buffer Register 0x120 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH5 ADC Command High Buffer Register 0x124 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL6 ADC Command Low Buffer Register 0x128 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH6 ADC Command High Buffer Register 0x12C 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL7 ADC Command Low Buffer Register 0x130 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH7 ADC Command High Buffer Register 0x134 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL8 ADC Command Low Buffer Register 0x138 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH8 ADC Command High Buffer Register 0x13C 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL9 ADC Command Low Buffer Register 0x140 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH9 ADC Command High Buffer Register 0x144 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL10 ADC Command Low Buffer Register 0x148 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH10 ADC Command High Buffer Register 0x14C 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL11 ADC Command Low Buffer Register 0x150 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH11 ADC Command High Buffer Register 0x154 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL12 ADC Command Low Buffer Register 0x158 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH12 ADC Command High Buffer Register 0x15C 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL13 ADC Command Low Buffer Register 0x160 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH13 ADC Command High Buffer Register 0x164 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL14 ADC Command Low Buffer Register 0x168 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH14 ADC Command High Buffer Register 0x16C 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF CMDL15 ADC Command Low Buffer Register 0x170 32 read-write 0 0xFFFFFFFF ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B or CH0A/CH0B pair. 0 ADCH_1 Select CH1A or CH1B or CH1A/CH1B pair. 0x1 ADCH_2 Select CH2A or CH2B or CH2A/CH2B pair. 0x2 ADCH_3 Select CH3A or CH3B or CH3A/CH3B pair. 0x3 ADCH_4 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x4 ADCH_5 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x5 ADCH_6 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x6 ADCH_7 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x7 ADCH_8 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x8 ADCH_9 Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0x9 ADCH_30 Select CH30A or CH30B or CH30A/CH30B pair. 0x1E ADCH_31 Select CH31A or CH31B or CH31A/CH31B pair. 0x1F CTYPE Conversion Type 5 2 read-write CTYPE_0 Single-Ended Mode. Only A side channel is converted. 0 CTYPE_1 Single-Ended Mode. Only B side channel is converted. 0x1 CTYPE_2 Differential Mode. A-B. 0x2 CTYPE_3 Dual-Single-Ended Mode. Both A side and B side channels are converted independently. 0x3 MODE Select resolution of conversions 7 1 read-write MODE_0 Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. 0 MODE_1 High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. 0x1 CMDH15 ADC Command High Buffer Register 0x174 32 read-write 0 0xFFFFFFFF WAIT_TRIG Wait for trigger assertion before execution. 2 1 read-write WAIT_TRIG_0 This command will be automatically executed. 0 WAIT_TRIG_1 The active trigger must be asserted again before executing this command. 0x1 LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 STS Sample Time Select 8 3 read-write STS_0 Minimum sample time of 3 ADCK cycles. 0 STS_1 3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0x1 STS_2 3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0x2 STS_3 3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0x3 STS_4 3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0x4 STS_5 3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0x5 STS_6 3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0x6 STS_7 3 + 27 ADCK cycles; 131 ADCK cycles total sample time. 0x7 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF 4 0x4 1,2,3,4 CV%s Compare Value Register 0x200 32 read-write 0 0xFFFFFFFF CVL Compare Value Low. 0 16 read-write CVH Compare Value High. 16 16 read-write 2 0x4 RESFIFO[%s] ADC Data Result FIFO Register 0x300 32 read-only 0 0xFFFFFFFF D Data result 0 16 read-only TSRC Trigger Source 16 4 read-only TSRC_0 Trigger source 0 initiated this conversion. 0 TSRC_1 Trigger source 1 initiated this conversion. 0x1 TSRC_2 Corresponding trigger source initiated this conversion. 0x2 TSRC_3 Corresponding trigger source initiated this conversion. 0x3 TSRC_4 Corresponding trigger source initiated this conversion. 0x4 TSRC_5 Corresponding trigger source initiated this conversion. 0x5 TSRC_6 Corresponding trigger source initiated this conversion. 0x6 TSRC_7 Corresponding trigger source initiated this conversion. 0x7 TSRC_8 Corresponding trigger source initiated this conversion. 0x8 TSRC_9 Corresponding trigger source initiated this conversion. 0x9 TSRC_15 Trigger source 15 initiated this conversion. 0xF LOOPCNT Loop count value 20 4 read-only LOOPCNT_0 Result is from initial conversion in command. 0 LOOPCNT_1 Result is from second conversion in command. 0x1 LOOPCNT_2 Result is from LOOPCNT+1 conversion in command. 0x2 LOOPCNT_3 Result is from LOOPCNT+1 conversion in command. 0x3 LOOPCNT_4 Result is from LOOPCNT+1 conversion in command. 0x4 LOOPCNT_5 Result is from LOOPCNT+1 conversion in command. 0x5 LOOPCNT_6 Result is from LOOPCNT+1 conversion in command. 0x6 LOOPCNT_7 Result is from LOOPCNT+1 conversion in command. 0x7 LOOPCNT_8 Result is from LOOPCNT+1 conversion in command. 0x8 LOOPCNT_9 Result is from LOOPCNT+1 conversion in command. 0x9 LOOPCNT_15 Result is from 16th conversion in command. 0xF CMDSRC Command Buffer Source 24 4 read-only CMDSRC_0 Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. 0 CMDSRC_1 CMD1 buffer used as control settings for this conversion. 0x1 CMDSRC_2 Corresponding command buffer used as control settings for this conversion. 0x2 CMDSRC_3 Corresponding command buffer used as control settings for this conversion. 0x3 CMDSRC_4 Corresponding command buffer used as control settings for this conversion. 0x4 CMDSRC_5 Corresponding command buffer used as control settings for this conversion. 0x5 CMDSRC_6 Corresponding command buffer used as control settings for this conversion. 0x6 CMDSRC_7 Corresponding command buffer used as control settings for this conversion. 0x7 CMDSRC_8 Corresponding command buffer used as control settings for this conversion. 0x8 CMDSRC_9 Corresponding command buffer used as control settings for this conversion. 0x9 CMDSRC_15 CMD15 buffer used as control settings for this conversion. 0xF VALID FIFO entry is valid 31 1 read-only VALID_0 FIFO is empty. Discard any read from RESFIFO. 0 VALID_1 FIFO record read from RESFIFO is valid. 0x1 33 0x4 CAL_GAR[%s] Calibration General A-Side Registers 0x400 32 read-write 0 0xFFFFFFFF CAL_GAR_VAL Calibration General A Side Register Element 0 16 read-write 33 0x4 CAL_GBR[%s] Calibration General B-Side Registers 0x500 32 read-write 0 0xFFFFFFFF CAL_GBR_VAL Calibration General B Side Register Element 0 16 read-write TST ADC Test Register 0xFFC 32 read-write 0 0xFFFFFFFF CST_LONG Calibration Sample Time Long 0 1 read-write CST_LONG_0 Normal sample time. Minimum sample time of 3 ADCK cycles. 0 CST_LONG_1 Increased sample time. 67 ADCK cycles total sample time. 0x1 FOFFM Force M-side positive offset 8 1 read-write FOFFM_0 Normal operation. No forced offset. 0 FOFFM_1 Test configuration. Forced positive offset on MDAC. 0x1 FOFFP Force P-side positive offset 9 1 read-write FOFFP_0 Normal operation. No forced offset. 0 FOFFP_1 Test configuration. Forced positive offset on PDAC. 0x1 FOFFM2 Force M-side negative offset 10 1 read-write FOFFM2_0 Normal operation. No forced offset. 0 FOFFM2_1 Test configuration. Forced negative offset on MDAC. 0x1 FOFFP2 Force P-side negative offset 11 1 read-write FOFFP2_0 Normal operation. No forced offset. 0 FOFFP2_1 Test configuration. Forced negative offset on PDAC. 0x1 TESTEN Enable test configuration 23 1 read-write TESTEN_0 Normal operation. Test configuration not enabled. 0 TESTEN_1 Hardware BIST Test in progress. 0x1 USBFSH USB0 Full-speed Host controller USBFSH 0x400A2000 0 0x60 registers USB0_NEEDCLK 27 USB0 28 HCREVISION BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) 0 32 read-only 0x10 0xFF REV Revision. 0 8 read-only HCCONTROL Defines the operating modes of the HC 0x4 32 read-write 0 0x7FF CBSR ControlBulkServiceRatio. 0 2 read-write PLE PeriodicListEnable. 2 1 read-write IE IsochronousEnable. 3 1 read-write CLE ControlListEnable. 4 1 read-write BLE BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. 5 1 read-write HCFS HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later. 6 2 read-write IR InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. 8 1 read-write RWC RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. 9 1 read-write RWE RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. 10 1 read-write HCCOMMANDSTATUS This register is used to receive the commands from the Host Controller Driver (HCD) 0x8 32 read-write 0 0xCF HCR HostControllerReset This bit is set by HCD to initiate a software reset of HC. 0 1 read-write CLF ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. 1 1 read-write BLF BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. 2 1 read-write OCR OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. 3 1 read-write SOC SchedulingOverrunCount These bits are incremented on each scheduling overrun error. 6 2 read-write HCINTERRUPTSTATUS Indicates the status on various events that cause hardware interrupts by setting the appropriate bits 0xC 32 read-write 0 0xFFFFFC7F SO SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. 0 1 read-write WDH WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. 1 1 read-write SF StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. 2 1 read-write RD ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. 3 1 read-write UE UnrecoverableError This bit is set when HC detects a system error not related to USB. 4 1 read-write FNO FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. 5 1 read-write RHSC RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. 6 1 read-write OC OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. 10 22 read-write HCINTERRUPTENABLE Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt 0x10 32 read-write 0 0xC000007F SO Scheduling Overrun interrupt. 0 1 read-write WDH HcDoneHead Writeback interrupt. 1 1 read-write SF Start of Frame interrupt. 2 1 read-write RD Resume Detect interrupt. 3 1 read-write UE Unrecoverable Error interrupt. 4 1 read-write FNO Frame Number Overflow interrupt. 5 1 read-write RHSC Root Hub Status Change interrupt. 6 1 read-write OC Ownership Change interrupt. 30 1 read-write MIE Master Interrupt Enable. 31 1 read-write HCINTERRUPTDISABLE The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt 0x14 32 read-write 0 0xC000007F SO Scheduling Overrun interrupt. 0 1 read-write WDH HcDoneHead Writeback interrupt. 1 1 read-write SF Start of Frame interrupt. 2 1 read-write RD Resume Detect interrupt. 3 1 read-write UE Unrecoverable Error interrupt. 4 1 read-write FNO Frame Number Overflow interrupt. 5 1 read-write RHSC Root Hub Status Change interrupt. 6 1 read-write OC Ownership Change interrupt. 30 1 read-write MIE A 0 written to this field is ignored by HC. 31 1 read-write HCHCCA Contains the physical address of the host controller communication area 0x18 32 read-write 0 0xFFFFFF00 HCCA Base address of the Host Controller Communication Area. 8 24 read-write HCPERIODCURRENTED Contains the physical address of the current isochronous or interrupt endpoint descriptor 0x1C 32 read-write 0 0xFFFFFFF0 PCED The content of this register is updated by HC after a periodic ED is processed. 4 28 read-only HCCONTROLHEADED Contains the physical address of the first endpoint descriptor of the control list 0x20 32 read-write 0 0xFFFFFFF0 CHED HC traverses the Control list starting with the HcControlHeadED pointer. 4 28 read-write HCCONTROLCURRENTED Contains the physical address of the current endpoint descriptor of the control list 0x24 32 read-write 0 0xFFFFFFF0 CCED ControlCurrentED. 4 28 read-write HCBULKHEADED Contains the physical address of the first endpoint descriptor of the bulk list 0x28 32 read-write 0 0xFFFFFFF0 BHED BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. 4 28 read-write HCBULKCURRENTED Contains the physical address of the current endpoint descriptor of the bulk list 0x2C 32 read-write 0 0xFFFFFFF0 BCED BulkCurrentED This is advanced to the next ED after the HC has served the current one. 4 28 read-write HCDONEHEAD Contains the physical address of the last transfer descriptor added to the 'Done' queue 0x30 32 read-write 0 0xFFFFFFF0 DH DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. 4 28 read-only HCFMINTERVAL Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun 0x34 32 read-write 0x2EDF 0xFFFF3FFF FI FrameInterval This specifies the interval between two consecutive SOFs in bit times. 0 14 read-write FSMPS FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. 16 15 read-write FIT FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. 31 1 read-write HCFMREMAINING A 14-bit counter showing the bit time remaining in the current frame 0x38 32 read-write 0 0x80003FFF FR FrameRemaining This counter is decremented at each bit time. 0 14 read-only FRT FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. 31 1 read-only HCFMNUMBER Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD 0x3C 32 read-write 0 0xFFFF FN FrameNumber This is incremented when HcFmRemaining is re-loaded. 0 16 read-only HCPERIODICSTART Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list 0x40 32 read-write 0 0x3FFF PS PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. 0 14 read-write HCLSTHRESHOLD Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF 0x44 32 read-write 0x628 0xFFF LST LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. 0 12 read-write HCRHDESCRIPTORA First of the two registers which describes the characteristics of the root hub 0x48 32 read-write 0xFF000902 0xFF001FFF NDP NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. 0 8 read-write PSM PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. 8 1 read-write NPS NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. 9 1 read-write DT DeviceType This bit specifies that the root hub is not a compound device. 10 1 read-write OCPM OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. 11 1 read-write NOCP NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. 12 1 read-write POTPGT PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub. 24 8 read-write HCRHDESCRIPTORB Second of the two registers which describes the characteristics of the Root Hub 0x4C 32 read-write 0 0x3FFFFFFF DR DeviceRemovable Each bit is dedicated to a port of the Root Hub. 0 16 read-write PPCM PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. 16 16 read-write HCRHSTATUS This register is divided into two parts 0x50 32 read-write 0 0x80038003 LPS (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0. 0 1 read-write OCI OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. 1 1 read-write DRWE (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. 15 1 read-write LPSC (read) LocalPowerStatusChange The root hub does not support the local power status feature. 16 1 read-write OCIC OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. 17 1 read-write CRWE (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. 31 1 read-write HCRHPORTSTATUS Controls and reports the port events on a per-port basis 0x54 32 read-write 0 0x1F031F CCS (read) CurrentConnectStatus This bit reflects the current state of the downstream port. 0 1 read-write PES (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. 1 1 read-write PSS (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. 2 1 read-write POCI (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. 3 1 read-write PRS (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. 4 1 read-write PPS (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented. 8 1 read-write LSDA (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. 9 1 read-write CSC ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. 16 1 read-write PESC PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. 17 1 read-write PSSC PortSuspendStatusChange This bit is set when the full resume sequence is completed. 18 1 read-write OCIC PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. 19 1 read-write PRSC PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. 20 1 read-write PORTMODE Controls the port if it is attached to the host block or the device block 0x5C 32 read-write 0 0x10101 ID Port ID pin value. 0 1 read-write ID_EN Port ID pin pull-up enable. 8 1 read-write DEV_ENABLE 1: device 0: host. 16 1 read-write USBHSH USB1 High-speed Host Controller USBHSH 0x400A3000 0 0x54 registers USB1 47 USB1_NEEDCLK 48 CAPLENGTH_CHIPID This register contains the offset value towards the start of the operational register space and the version number of the IP block 0 32 read-only 0x1010010 0xFFFF00FF CAPLENGTH Capability Length: This is used as an offset. 0 8 read-only CHIPID Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2. 16 16 read-only HCSPARAMS Host Controller Structural Parameters 0x4 32 read-only 0x10011 0x1001F N_PORTS This register specifies the number of physical downstream ports implemented on this host controller. 0 4 read-only PPC This field indicates whether the host controller implementation includes port power control. 4 1 read-only P_INDICATOR This bit indicates whether the ports support port indicator control. 16 1 read-only FLADJ_FRINDEX Frame Length Adjustment 0xC 32 read-write 0x20 0x3FFF003F FLADJ Frame Length Timing Value. 0 6 read-write FRINDEX Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. 16 14 read-write ATLPTD Memory base address where ATL PTD0 is stored 0x10 32 read-write 0 0xFFFFFFF0 ATL_CUR This indicates the current PTD that is used by the hardware when it is processing the ATL list. 4 5 read-write ATL_BASE Base address to be used by the hardware to find the start of the ATL list. 9 23 read-write ISOPTD Memory base address where ISO PTD0 is stored 0x14 32 read-write 0 0xFFFFFFE0 ISO_FIRST This indicates the first PTD that is used by the hardware when it is processing the ISO list. 5 5 read-write ISO_BASE Base address to be used by the hardware to find the start of the ISO list. 10 22 read-write INTPTD Memory base address where INT PTD0 is stored 0x18 32 read-write 0 0xFFFFFFE0 INT_FIRST This indicates the first PTD that is used by the hardware when it is processing the INT list. 5 5 read-write INT_BASE Base address to be used by the hardware to find the start of the INT list. 10 22 read-write DATAPAYLOAD Memory base address that indicates the start of the data payload buffers 0x1C 32 read-write 0 0xFFFF0000 DAT_BASE Base address to be used by the hardware to find the start of the data payload section. 16 16 read-write USBCMD USB Command register 0x20 32 read-write 0 0x1F00078F RS Run/Stop: 1b = Run. 0 1 read-write HCRESET Host Controller Reset: This control bit is used by the software to reset the host controller. 1 1 read-write FLS Frame List Size: This field specifies the size of the frame list. 2 2 read-write LHCR Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports. 7 1 read-write ATL_EN ATL List enabled. 8 1 read-write ISO_EN ISO List enabled. 9 1 read-write INT_EN INT List enabled. 10 1 read-write USBSTS USB Interrupt Status register 0x24 32 read-write 0 0xF000C PCD Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port. 2 1 read-write FLR Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0. 3 1 read-write ATL_IRQ ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. 16 1 read-write ISO_IRQ ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. 17 1 read-write INT_IRQ INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. 18 1 read-write SOF_IRQ SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. 19 1 read-write USBINTR USB Interrupt Enable register 0x28 32 read-write 0 0xF000C PCDE Port Change Detect Interrupt Enable: 1: enable 0: disable. 2 1 read-write FLRE Frame List Rollover Interrupt Enable: 1: enable 0: disable. 3 1 read-write ATL_IRQ_E ATL IRQ Enable bit: 1: enable 0: disable. 16 1 read-write ISO_IRQ_E ISO IRQ Enable bit: 1: enable 0: disable. 17 1 read-write INT_IRQ_E INT IRQ Enable bit: 1: enable 0: disable. 18 1 read-write SOF_E SOF Interrupt Enable bit: 1: enable 0: disable. 19 1 read-write PORTSC1 Port Status and Control register 0x2C 32 read-write 0 0xFFFFDFFF CCS Current Connect Status: Logic 1 indicates a device is present on the port. 0 1 read-write CSC Connect Status Change: Logic 1 means that the value of CCS has changed. 1 1 read-write PED Port Enabled/Disabled. 2 1 read-write PEDC Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. 3 1 read-write OCA Over-current active: Logic 1 means that this port has an over-current condition. 4 1 read-write OCC Over-current change: Logic 1 means that the value of OCA has changed. 5 1 read-write FPR Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. 6 1 read-write SUSP Suspend: Logic 1 means port is in the suspend state. 7 1 read-write PR Port Reset: Logic 1 means the port is in the reset state. 8 1 read-write LS Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. 10 2 read-only PP Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. 12 1 read-write PIC Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. 14 2 read-write PTC Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. 16 4 read-write PSPD Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. 20 2 read-write WOO Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events. 22 1 read-write ATLPTDD Done map for each ATL PTD 0x30 32 read-write 0 0xFFFFFFFF ATL_DONE The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write ATLPTDS Skip map for each ATL PTD 0x34 32 read-write 0 0xFFFFFFFF ATL_SKIP When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. 0 32 read-write ISOPTDD Done map for each ISO PTD 0x38 32 read-write 0 0xFFFFFFFF ISO_DONE The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write ISOPTDS Skip map for each ISO PTD 0x3C 32 read-write 0 0xFFFFFFFF ISO_SKIP The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write INTPTDD Done map for each INT PTD 0x40 32 read-write 0 0xFFFFFFFF INT_DONE The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. 0 32 read-write INTPTDS Skip map for each INT PTD 0x44 32 read-write 0 0xFFFFFFFF INT_SKIP When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting. 0 32 read-write LASTPTD Marks the last PTD in the list for ISO, INT and ATL 0x48 32 read-write 0 0x1F1F1F ATL_LAST If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. 0 5 read-write ISO_LAST This indicates the last PTD in the ISO list. 8 5 read-write INT_LAST This indicates the last PTD in the INT list. 16 5 read-write PORTMODE Controls the port if it is attached to the host block or the device block 0x50 32 read-write 0x40000 0xD0101 DEV_ENABLE If this bit is set to one, one of the ports will behave as a USB device. 16 1 read-write SW_CTRL_PDCOM This bit indicates if the PHY power-down input is controlled by software or by hardware. 18 1 read-write SW_PDCOM This bit is only used when SW_CTRL_PDCOM is set to 1b. 19 1 read-write HASHCRYPT Hash-Crypt peripheral HASHCRYPT 0x400A4000 0 0xA0 registers HASHCRYPT 54 CTRL Control register to enable and operate Hash and Crypto 0 32 read-write 0 0x3317 Mode The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available. 0 3 read-write DISABLED Disabled 0 SHA1 SHA1 is enabled 0x1 SHA2_256 SHA2-256 is enabled 0x2 AES AES if available (see also CRYPTCFG register for more controls) 0x4 ICB_AES ICB-AES if available (see also CRYPTCFG register for more controls) 0x5 New_Hash Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. 4 1 write-only START Starts a new Hash/Crypto and initializes the Digest/Result. 0x1 DMA_I Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed). 8 1 read-write NOT_USED DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. 0 PUSH DMA will push in the data. 0x1 DMA_O Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses. 9 1 read-write NOTUSED DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. 0 HASHSWPB If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register. 12 1 read-write STATUS Indicates status of Hash peripheral. 0x4 32 read-write 0 0x3F0037 WAITING If 1, the block is waiting for more data to process. 0 1 read-only NOT_WAITING Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output. 0 WAITING Waiting for data to be written in (16 words) 0x1 DIGEST For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. 1 1 read-only NOT_READY No Digest is ready 0 READY Digest is ready. Application may read it or may write more data 0x1 ERROR If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on. 2 1 read-write oneToClear NO_ERROR No error. 0 ERROR An error occurred since last cleared (written 1 to clear). 0x1 NEEDKEY Indicates the block wants the key to be written in (set along with WAITING) 4 1 read-only NOT_NEED No Key is needed and writes will not be treated as Key 0 NEED Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. 0x1 NEEDIV Indicates the block wants an IV/NONE to be written in (set along with WAITING) 5 1 read-only NOT_NEED No IV/Nonce is needed, either because written already or because not needed. 0 NEED IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. 0x1 ICBIDX If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, it has to compute the full ICB, quicker when not 0. 16 6 read-only INTENSET Write 1 to enable interrupts; reads back with which are set. 0x8 32 read-write 0 0x7 WAITING Indicates if should interrupt when waiting for data input. 0 1 read-write NO_INTERRUPT Will not interrupt when waiting. 0 INTERRUPT Will interrupt when waiting 0x1 DIGEST Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). 1 1 read-write NO_INTERRUPT Will not interrupt when Digest is ready 0 INTERRUPT Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). 0x1 ERROR Indicates if should interrupt on an ERROR (as defined in Status) 2 1 read-write NOT_INTERRUPT Will not interrupt on Error. 0 INTERRUPT Will interrupt on Error (until cleared). 0x1 INTENCLR Write 1 to clear interrupts. 0xC 32 read-write 0 0 WAITING Write 1 to clear mask. 0 1 read-write oneToClear DIGEST Write 1 to clear mask. 1 1 read-write oneToClear ERROR Write 1 to clear mask. 2 1 read-write oneToClear MEMCTRL Setup Master to access memory (if available) 0x10 32 read-write 0 0x7FF0001 MASTER Enables mastering. 0 1 read-write NOT_USED Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. 0 ENABLED Mastering is enabled and DMA and INDATA should not be used. 0x1 COUNT Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash. 16 11 read-write MEMADDR Address to start memory access from (if available). 0x14 32 read-write 0 0xFFFFFFFF BASE Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI. 0 32 read-write INDATA Input of 16 words at a time to load up buffer. 0x20 32 write-only 0 0 DATA Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. 0 32 write-only 7 0x4 ALIAS[%s] no description available 0x24 32 write-only 0 0 DATA Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian. 0 32 write-only 8 0x4 DIGEST0[%s] no description available 0x40 32 read-only 0 0xFFFFFFFF DIGEST One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. 0 32 read-only CRYPTCFG Crypto settings for AES and Salsa and ChaCha 0x80 32 read-write 0 0xF31FFF MSW1ST_OUT If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration. 0 1 read-write SWAPKEY If 1, will Swap the key input (bytes in each word). 1 1 read-write SWAPDAT If 1, will SWAP the data and IV inputs (bytes in each word). 2 1 read-write MSW1ST If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration. 3 1 read-write AESMODE AES Cipher mode to use if plain AES 4 2 read-write ECB ECB - used as is 0 CBC CBC mode (see details on IV/nonce) 0x1 CTR CTR mode (see details on IV/nonce). See also AESCTRPOS. 0x2 AESDECRYPT AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB 6 1 read-write ENCRYPT Encrypt 0 DECRYPT Decrypt 0x1 AESSECRET Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this. 7 1 read-write NORMAL_WAY User key provided in normal way 0 HIDDEN_WAY Secret key provided in hidden way by HW 0x1 AESKEYSZ Sets the AES key size 8 2 read-write BITS_128 128 bit key 0 BITS_192 192 bit key 0x1 BITS_256 256 bit key 0x2 AESCTRPOS Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on. 10 3 read-write STREAMLAST Is 1 if last stream block. If not 1, then the engine will compute the next "hash". 16 1 read-write ICBSZ This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. 20 2 read-write BITS_32 32 bits of the IV/ctr are used (from 127:96) 0 BITS_64 64 bits of the IV/ctr are used (from 127:64) 0x1 BITS_96 96 bits of the IV/ctr are used (from 127:32) 0x2 BIT_128 All 128 bits of the IV/ctr are used 0x3 ICBSTRM The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. 22 2 read-write BLOCKS_8 8 blocks 0 BLOCKS_16 16 blocks 0x1 BLOCKS_32 32 blocks 0x2 BLOCKS_64 64 blocks 0x3 CONFIG Returns the configuration of this block in this chip - indicates what services are available. 0x84 32 read-write 0 0 DUAL 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit 0 1 read-only DMA 1 if DMA is connected 1 1 read-only AHB 1 if AHB Master is enabled 3 1 read-only AES 1 if AES 128 included 6 1 read-only AESKEY 1 if AES 192 and 256 also included 7 1 read-only SECRET 1 if AES Secret key available 8 1 read-only ICB 1 if ICB over AES included 11 1 read-only LOCK Lock register allows locking to the current security level or unlocking by the lock holding level. 0x8C 32 read-write 0 0xFFF3 SECLOCK Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level. 0 2 read-write UNLOCK Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. 0 LOCK Locks to the current security level. AHB Master will issue requests at this level. 0x1 PATTERN Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 4 12 read-write 4 0x4 MASK[%s] no description available 0x90 32 write-only 0 0 MASK A random word. 0 32 write-only CASPER CASPER CASPER 0x400A5000 0 0x84 registers CTRL0 Contains the offsets of AB and CD in the RAM. 0 32 read-write 0 0x1FFD0005 ABBPAIR Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up 0 1 read-write PAIR0 Bank-pair 0 (1st) 0 PAIR1 Bank-pair 1 (2nd) 0x1 ABOFF Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up 2 1 read-write CDBPAIR Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up 16 1 read-write PAIR0 Bank-pair 0 (1st) 0 PAIR1 Bank-pair 1 (2nd) 0x1 CDOFF Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values 18 11 read-write CTRL1 Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. 0x4 32 read-write 0 0xDFFDFFFF ITER Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. 0 8 read-write MODE Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. 8 8 read-write RESBPAIR Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported) 16 1 read-write PAIR0 Bank-pair 0 (1st) 0 PAIR1 Bank-pair 1 (2nd) 0x1 RESOFF Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values 18 11 read-write CSKIP Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: 30 2 read-write NO_SKIP No Skip 0 SKIP_IF_1 Skip if Carry is 1 0x1 SKIP_IF_0 Skip if Carry is 0 0x2 SET_AND_SKIP Set CTRLOFF to CDOFF and Skip 0x3 LOADER Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. 0x8 32 read-write 0 0x1FFD00FF COUNT Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load 0 8 read-write CTRLBPAIR Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation. 16 1 read-write PAIR0 Bank-pair 0 (1st) 0 PAIR1 Bank-pair 1 (2nd) 0x1 CTRLOFF DWord Offset of CTRL pair to load next. 18 11 read-write STATUS Indicates operational status and would contain the carry bit if used. 0xC 32 read-write 0 0x31 DONE Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. 0 1 read-write BUSY Busy or just cleared 0 COMPLETED Completed last operation 0x1 CARRY Last carry value if operation produced a carry bit 4 1 read-only NO_CARRY Carry was 0 or no carry 0 CARRY Carry was 1 0x1 BUSY Indicates if the accelerator is busy performing an operation 5 1 read-only IDLE Not busy - is idle 0 BUSY Is busy 0x1 INTENSET Sets interrupts 0x10 32 read-write 0 0x1 DONE Set if the accelerator should interrupt when done. 0 1 read-write NO_INTERRUPT Do not interrupt when done 0 INTERRUPT Interrupt when done 0x1 INTENCLR Clears interrupts 0x14 32 read-write 0 0x1 DONE Written to clear an interrupt set with INTENSET. 0 1 read-write oneToClear IGNORED If written 0, ignored 0 NO_INTERRUPT If written 1, do not Interrupt when done 0x1 INTSTAT Interrupt status bits (mask of INTENSET and STATUS) 0x18 32 read-write 0 0x1 DONE If set, interrupt is caused by accelerator being done. 0 1 read-only NOT_CAUSED Not caused by accelerator being done 0 CAUSED Caused by accelerator being done 0x1 AREG A register 0x20 32 read-write 0 0xFFFFFFFF REG_VALUE Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write BREG B register 0x24 32 read-write 0 0xFFFFFFFF REG_VALUE Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write CREG C register 0x28 32 read-write 0 0xFFFFFFFF REG_VALUE Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write DREG D register 0x2C 32 read-write 0 0xFFFFFFFF REG_VALUE Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write RES0 Result register 0 0x30 32 read-write 0 0xFFFFFFFF REG_VALUE Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write RES1 Result register 1 0x34 32 read-write 0 0xFFFFFFFF REG_VALUE Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write RES2 Result register 2 0x38 32 read-write 0 0xFFFFFFFF REG_VALUE Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write RES3 Result register 3 0x3C 32 read-write 0 0xFFFFFFFF REG_VALUE Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy. 0 32 read-write MASK Optional mask register 0x60 32 read-write 0 0xFFFFFFFF MASK Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values 0 32 read-write REMASK Optional re-mask register 0x64 32 read-write 0 0xFFFFFFFF MASK Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values 0 32 read-write LOCK Security lock register 0x80 32 read-write 0 0x1FFFF LOCK Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. 0 1 read-write UNLOCK unlock 0 LOCK Lock to current security level 0x1 KEY Must be written as 0x73D to change the register. 4 13 read-write KWY_VALUE If set during write, will allow lock or unlock 0x73D POWERQUAD Digital Signal Co-Processing companion to a Cortex-M v8M CPU core POWERQUAD 0x400A6000 0 0x260 registers OUTBASE Base address register for output region 0 32 read-write 0 0xFFFFFFFF outbase Base address register for the output region 0 32 read-write OUTFORMAT Output format 0x4 32 read-write 0 0xFF33 out_formatint Output Internal format (00: q15; 01:q31; 10:float) 0 2 read-write out_formatext Output External format (00: q15; 01:q31; 10:float) 4 2 read-write out_scaler Output Scaler value (for scaled 'q31' formats) 8 8 read-write TMPBASE Base address register for temp region 0x8 32 read-write 0 0xFFFFFFFF tmpbase Base address register for the temporary region 0 32 read-write TMPFORMAT Temp format 0xC 32 read-write 0 0xFF33 tmp_formatint Temp Internal format (00: q15; 01:q31; 10:float) 0 2 read-write tmp_formatext Temp External format (00: q15; 01:q31; 10:float) 4 2 read-write tmp_scaler Temp Scaler value (for scaled 'q31' formats) 8 8 read-write INABASE Base address register for input A region 0x10 32 read-write 0 0xFFFFFFFF inabase Base address register for the input A region 0 32 read-write INAFORMAT Input A format 0x14 32 read-write 0 0xFF33 ina_formatint Input A Internal format (00: q15; 01:q31; 10:float) 0 2 read-write ina_formatext Input A External format (00: q15; 01:q31; 10:float) 4 2 read-write ina_scaler Input A Scaler value (for scaled 'q31' formats) 8 8 read-write INBBASE Base address register for input B region 0x18 32 read-write 0 0xFFFFFFFF inbbase Base address register for the input B region 0 32 read-write INBFORMAT Input B format 0x1C 32 read-write 0 0xFF33 inb_formatint Input B Internal format (00: q15; 01:q31; 10:float) 0 2 read-write inb_formatext Input B External format (00: q15; 01:q31; 10:float) 4 2 read-write inb_scaler Input B Scaler value (for scaled 'q31' formats) 8 8 read-write CONTROL PowerQuad Control register 0x100 32 read-write 0 0x8000FFFF decode_opcode opcode specific to decode_machine 0 4 read-write decode_machine 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA 4 4 read-write inst_busy Instruction busy signal when high indicates processing is on 31 1 read-only LENGTH Length register 0x104 32 read-write 0 0xFFFFFFFF inst_length Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16] 0 32 read-write CPPRE Pre-scale register 0x108 32 read-write 0 0x3FFFF cppre_in co-processor scaling of input 0 8 read-write cppre_out co-processor fixed point output 8 8 read-write cppre_sat 1 : forces sub-32 bit saturation 16 1 read-write cppre_sat8 0 = 8bits, 1 = 16bits 17 1 read-write MISC Misc register 0x10C 32 read-write 0 0xFFFFFFFF inst_misc Misc register. For Matrix : Used for scale factor 0 32 read-write CURSORY Cursory register 0x110 32 read-write 0 0x1 cursory 1 : Enable cursory mode 0 1 read-write CORDIC_X Cordic input X register 0x180 32 read-write 0 0xFFFFFFFF cordic_x Cordic input x 0 32 read-write CORDIC_Y Cordic input Y register 0x184 32 read-write 0 0xFFFFFFFF cordic_y Cordic input y 0 32 read-write CORDIC_Z Cordic input Z register 0x188 32 read-write 0 0xFFFFFFFF cordic_z Cordic input z 0 32 read-write ERRSTAT Read/Write register where error statuses are captured (sticky) 0x18C 32 read-write 0 0x1F OVERFLOW overflow 0 1 read-write NAN nan 1 1 read-write FIXEDOVERFLOW fixed_pt_overflow 2 1 read-write UNDERFLOW underflow 3 1 read-write BUSERROR bus_error 4 1 read-write INTREN INTERRUPT enable register 0x190 32 read-write 0 0x7F intr_oflow 1 : Enable interrupt on Floating point overflow 0 1 read-write intr_nan 1 : Enable interrupt on Floating point NaN 1 1 read-write intr_fixed 1: Enable interrupt on Fixed point Overflow 2 1 read-write intr_uflow 1 : Enable interrupt on Subnormal truncation 3 1 read-write intr_berr 1: Enable interrupt on AHBM Buss Error 4 1 read-write intr_comp 1: Enable interrupt on instruction completion 7 1 read-write EVENTEN Event Enable register 0x194 32 read-write 0 0xFFFFFFFF event_oflow 1 : Enable event trigger on Floating point overflow 0 1 read-write event_nan 1 : Enable event trigger on Floating point NaN 1 1 read-write event_fixed 1: Enable event trigger on Fixed point Overflow 2 1 read-write event_uflow 1 : Enable event trigger on Subnormal truncation 3 1 read-write event_berr 1: Enable event trigger on AHBM Buss Error 4 1 read-write event_comp 1: Enable event trigger on instruction completion 7 1 read-write INTRSTAT INTERRUPT STATUS register 0x198 32 read-write 0 0x1 intr_stat Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit 0 1 read-write 16 0x4 gpreg[%s] General purpose register bank N. 0x200 32 read-write 0 0x7CF73 gpreg General purpose register bank 0 32 read-write 8 0x4 compreg[%s] Compute register bank 0x240 32 read-write 0 0xFFFFFFFF compreg Compute register bank 0 32 read-write SECGPIO General Purpose I/O (GPIO) GPIO 0x400A8000 0 0x2484 registers B0_0 Byte pin registers for all port GPIO pins 0 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_1 Byte pin registers for all port GPIO pins 0x1 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_2 Byte pin registers for all port GPIO pins 0x2 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_3 Byte pin registers for all port GPIO pins 0x3 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_4 Byte pin registers for all port GPIO pins 0x4 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_5 Byte pin registers for all port GPIO pins 0x5 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_6 Byte pin registers for all port GPIO pins 0x6 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_7 Byte pin registers for all port GPIO pins 0x7 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_8 Byte pin registers for all port GPIO pins 0x8 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_9 Byte pin registers for all port GPIO pins 0x9 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_10 Byte pin registers for all port GPIO pins 0xA 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_11 Byte pin registers for all port GPIO pins 0xB 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_12 Byte pin registers for all port GPIO pins 0xC 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_13 Byte pin registers for all port GPIO pins 0xD 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_14 Byte pin registers for all port GPIO pins 0xE 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_15 Byte pin registers for all port GPIO pins 0xF 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_16 Byte pin registers for all port GPIO pins 0x10 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_17 Byte pin registers for all port GPIO pins 0x11 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_18 Byte pin registers for all port GPIO pins 0x12 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_19 Byte pin registers for all port GPIO pins 0x13 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_20 Byte pin registers for all port GPIO pins 0x14 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_21 Byte pin registers for all port GPIO pins 0x15 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_22 Byte pin registers for all port GPIO pins 0x16 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_23 Byte pin registers for all port GPIO pins 0x17 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_24 Byte pin registers for all port GPIO pins 0x18 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_25 Byte pin registers for all port GPIO pins 0x19 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_26 Byte pin registers for all port GPIO pins 0x1A 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_27 Byte pin registers for all port GPIO pins 0x1B 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_28 Byte pin registers for all port GPIO pins 0x1C 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_29 Byte pin registers for all port GPIO pins 0x1D 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_30 Byte pin registers for all port GPIO pins 0x1E 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write B0_31 Byte pin registers for all port GPIO pins 0x1F 8 read-write 0 0x1 PBYTE Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 1 read-write W0_0 Word pin registers for all port GPIO pins 0x1000 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_1 Word pin registers for all port GPIO pins 0x1004 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_2 Word pin registers for all port GPIO pins 0x1008 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_3 Word pin registers for all port GPIO pins 0x100C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_4 Word pin registers for all port GPIO pins 0x1010 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_5 Word pin registers for all port GPIO pins 0x1014 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_6 Word pin registers for all port GPIO pins 0x1018 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_7 Word pin registers for all port GPIO pins 0x101C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_8 Word pin registers for all port GPIO pins 0x1020 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_9 Word pin registers for all port GPIO pins 0x1024 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_10 Word pin registers for all port GPIO pins 0x1028 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_11 Word pin registers for all port GPIO pins 0x102C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_12 Word pin registers for all port GPIO pins 0x1030 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_13 Word pin registers for all port GPIO pins 0x1034 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_14 Word pin registers for all port GPIO pins 0x1038 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_15 Word pin registers for all port GPIO pins 0x103C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_16 Word pin registers for all port GPIO pins 0x1040 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_17 Word pin registers for all port GPIO pins 0x1044 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_18 Word pin registers for all port GPIO pins 0x1048 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_19 Word pin registers for all port GPIO pins 0x104C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_20 Word pin registers for all port GPIO pins 0x1050 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_21 Word pin registers for all port GPIO pins 0x1054 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_22 Word pin registers for all port GPIO pins 0x1058 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_23 Word pin registers for all port GPIO pins 0x105C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_24 Word pin registers for all port GPIO pins 0x1060 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_25 Word pin registers for all port GPIO pins 0x1064 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_26 Word pin registers for all port GPIO pins 0x1068 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_27 Word pin registers for all port GPIO pins 0x106C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_28 Word pin registers for all port GPIO pins 0x1070 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_29 Word pin registers for all port GPIO pins 0x1074 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_30 Word pin registers for all port GPIO pins 0x1078 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write W0_31 Word pin registers for all port GPIO pins 0x107C 32 read-write 0 0xFFFFFFFF PWORD Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. 0 32 read-write DIR0 Direction registers for all port GPIO pins 0x2000 32 read-write 0 0xFFFFFFFF DIRP Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. 0 32 read-write MASK0 Mask register for all port GPIO pins 0x2080 32 read-write 0 0xFFFFFFFF MASKP Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. 0 32 read-write PIN0 Port pin register for all port GPIO pins 0x2100 32 read-write 0 0xFFFFFFFF PORT Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. 0 32 read-write MPIN0 Masked port register for all port GPIO pins 0x2180 32 read-write 0 0xFFFFFFFF MPORTP Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. 0 32 read-write SET0 Write: Set register for port. Read: output bits for port 0x2200 32 read-write 0 0xFFFFFFFF SETP Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. 0 32 read-write CLR0 Clear port for all port GPIO pins 0x2280 32 write-only 0 0 CLRP Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. 0 32 write-only NOT0 Toggle port for all port GPIO pins 0x2300 32 write-only 0 0 NOTP Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. 0 32 write-only DIRSET0 Set pin direction bits for port 0x2380 32 write-only 0 0 DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 32 write-only DIRCLR0 Clear pin direction bits for port 0x2400 32 write-only 0 0 DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 32 write-only DIRNOT0 Toggle pin direction bits for port 0x2480 32 write-only 0 0 DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 32 write-only AHB_SECURE_CTRL AHB secure controller AHB_SECURE_CTRL 0x400AC000 0 0x1000 registers SEC_CTRL_FLASH_ROM_SLAVE_RULE Security access rules for Flash and ROM slaves. 0 32 read-write 0 0xFFFFFFFF FLASH_RULE Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 ROM_RULE Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_FLASH_MEM_RULE0 Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. 0x10 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_FLASH_MEM_RULE1 Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. 0x14 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_FLASH_MEM_RULE2 Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. 0x18 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_ROM_MEM_RULE0 Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. 0x20 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_ROM_MEM_RULE1 Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. 0x24 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_ROM_MEM_RULE2 Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. 0x28 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_ROM_MEM_RULE3 Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. 0x2C 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAMX_SLAVE_RULE Security access rules for RAMX slaves. 0x30 32 read-write 0 0xFFFFFFFF RAMX_RULE Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAMX_MEM_RULE0 Security access rules for RAMX slaves. 0x40 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM0_SLAVE_RULE Security access rules for RAM0 slaves. 0x50 32 read-write 0 0xFFFFFFFF RAM0_RULE Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM0_MEM_RULE0 Security access rules for RAM0 slaves. 0x60 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM0_MEM_RULE1 Security access rules for RAM0 slaves. 0x64 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM1_SLAVE_RULE Security access rules for RAM1 slaves. 0x70 32 read-write 0 0xFFFFFFFF RAM1_RULE Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM1_MEM_RULE0 Security access rules for RAM1 slaves. 0x80 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM1_MEM_RULE1 Security access rules for RAM1 slaves. 0x84 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM2_SLAVE_RULE Security access rules for RAM2 slaves. 0x90 32 read-write 0 0xFFFFFFFF RAM2_RULE Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM2_MEM_RULE0 Security access rules for RAM2 slaves. 0xA0 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM2_MEM_RULE1 Security access rules for RAM2 slaves. 0xA4 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM3_SLAVE_RULE Security access rules for RAM3 slaves. 0xB0 32 read-write 0 0xFFFFFFFF RAM3_RULE Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM3_MEM_RULE0 Security access rules for RAM3 slaves. 0xC0 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM3_MEM_RULE1 Security access rules for RAM3 slaves. 0xC4 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE4 secure control rule4. it can be set when check_reg's write_lock is '0' 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE5 secure control rule5. it can be set when check_reg's write_lock is '0' 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE6 secure control rule6. it can be set when check_reg's write_lock is '0' 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE7 secure control rule7. it can be set when check_reg's write_lock is '0' 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM4_SLAVE_RULE Security access rules for RAM4 slaves. 0xD0 32 read-write 0 0xFFFFFFFF RAM4_RULE Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_RAM4_MEM_RULE0 Security access rules for RAM4 slaves. 0xE0 32 read-write 0 0xFFFFFFFF RULE0 secure control rule0. it can be set when check_reg's write_lock is '0' 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE1 secure control rule1. it can be set when check_reg's write_lock is '0' 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE2 secure control rule2. it can be set when check_reg's write_lock is '0' 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RULE3 secure control rule3. it can be set when check_reg's write_lock is '0' 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE_SLAVE_RULE Security access rules for both APB Bridges slaves. 0xF0 32 read-write 0 0xFFFFFFFF APBBRIDGE0_RULE Security access rules for the whole APB Bridge 0 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 APBBRIDGE1_RULE Security access rules for the whole APB Bridge 1 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. 0x100 32 read-write 0 0xFFFFFFFF SYSCON_RULE System Configuration 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 IOCON_RULE I/O Configuration 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 GINT0_RULE GPIO input Interrupt 0 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 GINT1_RULE GPIO input Interrupt 1 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 PINT_RULE Pin Interrupt and Pattern match 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_PINT_RULE Secure Pin Interrupt and Pattern match 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 INPUTMUX_RULE Peripheral input multiplexing 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. 0x104 32 read-write 0 0xFFFFFFFF CTIMER0_RULE Standard counter/Timer 0 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 CTIMER1_RULE Standard counter/Timer 1 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 WWDT_RULE Windiwed wtachdog Timer 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 MRT_RULE Multi-rate Timer 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 UTICK_RULE Micro-Timer 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. 0x108 32 read-write 0 0xFFFFFFFF ANACTRL_RULE Analog Modules controller 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. 0x110 32 read-write 0 0xFFFFFFFF PMC_RULE Power Management Controller 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SYSCTRL_RULE System Controller 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. 0x114 32 read-write 0 0xFFFFFFFF CTIMER2_RULE Standard counter/Timer 2 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 CTIMER3_RULE Standard counter/Timer 3 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 CTIMER4_RULE Standard counter/Timer 4 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RTC_RULE Real Time Counter 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 OSEVENT_RULE OS Event Timer 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. 0x118 32 read-write 0 0xFFFFFFFF FLASH_CTRL_RULE Flash Controller 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 PRINCE_RULE Prince 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. 0x11C 32 read-write 0 0xFFFFFFFF USBHPHY_RULE USB High Speed Phy controller 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 RNG_RULE True Random Number Generator 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 PUF_RULE PUF 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 PLU_RULE Programmable Look-Up logic 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_PORT8_SLAVE0_RULE Security access rules for AHB peripherals. 0x120 32 read-write 0 0xFFFFFFFF DMA0_RULE DMA Controller 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FS_USB_DEV_RULE USB Full-speed device 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SCT_RULE SCTimer 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FLEXCOMM0_RULE Flexcomm interface 0 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FLEXCOMM1_RULE Flexcomm interface 1 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_PORT8_SLAVE1_RULE Security access rules for AHB peripherals. 0x124 32 read-write 0 0xFFFFFFFF FLEXCOMM2_RULE Flexcomm interface 2 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FLEXCOMM3_RULE Flexcomm interface 3 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FLEXCOMM4_RULE Flexcomm interface 4 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 MAILBOX_RULE Inter CPU communication Mailbox 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 GPIO0_RULE High Speed GPIO 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_PORT9_SLAVE0_RULE Security access rules for AHB peripherals. 0x130 32 read-write 0 0xFFFFFFFF USB_HS_DEV_RULE USB high Speed device registers 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 CRC_RULE CRC engine 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FLEXCOMM5_RULE Flexcomm interface 5 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 FLEXCOMM6_RULE Flexcomm interface 6 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_PORT9_SLAVE1_RULE Security access rules for AHB peripherals. 0x134 32 read-write 0 0xFFFFFFFF FLEXCOMM7_RULE Flexcomm interface 7 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SDIO_RULE SDMMC card interface 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 DBG_MAILBOX_RULE Debug mailbox (aka ISP-AP) 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 HS_LSPI_RULE High Speed SPI 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_PORT10_SLAVE0_RULE Security access rules for AHB peripherals. 0x140 32 read-write 0 0xFFFFFFFF ADC_RULE ADC 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 USB_FS_HOST_RULE USB Full Speed Host registers. 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 USB_HS_HOST_RULE USB High speed host registers 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 HASH_RULE SHA-2 crypto registers 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 CASPER_RULE RSA/ECC crypto accelerator 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 PQ_RULE Power Quad (CPU0 processor hardware accelerator) 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 DMA1_RULE DMA Controller (Secure) 28 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_PORT10_SLAVE1_RULE Security access rules for AHB peripherals. 0x144 32 read-write 0 0xFFFFFFFF GPIO1_RULE Secure High Speed GPIO 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 AHB_SEC_CTRL_RULE AHB Secure Controller 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_AHB_SEC_CTRL_MEM_RULE Security access rules for AHB_SEC_CTRL_AHB. 0x150 32 read-write 0 0xFFFFFFFF AHB_SEC_CTRL_SECT_0_RULE Address space: 0x400A_0000 - 0x400A_CFFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 AHB_SEC_CTRL_SECT_1_RULE Address space: 0x400A_D000 - 0x400A_DFFF 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 AHB_SEC_CTRL_SECT_2_RULE Address space: 0x400A_E000 - 0x400A_EFFF 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 AHB_SEC_CTRL_SECT_3_RULE Address space: 0x400A_F000 - 0x400A_FFFF 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_USB_HS_SLAVE_RULE Security access rules for USB High speed RAM slaves. 0x160 32 read-write 0 0xFFFFFFFF RAM_USB_HS_RULE Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SEC_CTRL_USB_HS_MEM_RULE Security access rules for RAM_USB_HS. 0x170 32 read-write 0 0xFFFFFFFF SRAM_SECT_0_RULE Address space: 0x4010_0000 - 0x4010_0FFF 0 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SRAM_SECT_1_RULE Address space: 0x4010_1000 - 0x4010_1FFF 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SRAM_SECT_2_RULE Address space: 0x4010_2000 - 0x4010_2FFF 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SRAM_SECT_3_RULE Address space: 0x4010_3000 - 0x4010_3FFF 12 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 12 0x4 sec_vio_addr[%s] most recent security violation address for AHB port n 0xE00 32 read-only 0 0xFFFFFFFF SEC_VIO_ADDR security violation address for AHB port 0 32 read-only 12 0x4 sec_vio_misc_info[%s] most recent security violation miscellaneous information for AHB port n 0xE80 32 read-only 0 0xFF3 SEC_VIO_INFO_WRITE security violation access read/write indicator. 0 1 read-only READ Read access. 0 WRITE Write access. 0x1 SEC_VIO_INFO_DATA_ACCESS security violation access data/code indicator. 1 1 read-only CODE Code access. 0 DATA Data access. 0x1 SEC_VIO_INFO_MASTER_SEC_LEVEL bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level 4 4 read-only SEC_VIO_INFO_MASTER security violation master number 8 4 read-only VALUE_0 CPU0 Code. 0 VALUE_1 CPU0 System. 0x1 VALUE_2 CPU1 Data. 0x2 VALUE_3 CPU1 System. 0x3 VALUE_4 USB-HS Device. 0x4 VALUE_5 SDMA0. 0x5 VALUE_8 SDIO. 0x8 VALUE_9 PowerQuad. 0x9 VALUE_10 HASH. 0xA VALUE_11 USB-FS Host. 0xB VALUE_12 SDMA1. 0xC SEC_VIO_INFO_VALID security violation address/information registers valid flags 0xF00 32 read-write 0 0x3FFFF VIO_INFO_VALID0 violation information valid flag for AHB port 0. Write 1 to clear. 0 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID1 violation information valid flag for AHB port 1. Write 1 to clear. 1 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID2 violation information valid flag for AHB port 2. Write 1 to clear. 2 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID3 violation information valid flag for AHB port 3. Write 1 to clear. 3 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID4 violation information valid flag for AHB port 4. Write 1 to clear. 4 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID5 violation information valid flag for AHB port 5. Write 1 to clear. 5 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID6 violation information valid flag for AHB port 6. Write 1 to clear. 6 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID7 violation information valid flag for AHB port 7. Write 1 to clear. 7 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID8 violation information valid flag for AHB port 8. Write 1 to clear. 8 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID9 violation information valid flag for AHB port 9. Write 1 to clear. 9 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID10 violation information valid flag for AHB port 10. Write 1 to clear. 10 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 VIO_INFO_VALID11 violation information valid flag for AHB port 11. Write 1 to clear. 11 1 read-write NOT_VALID Not valid. 0 VALID Valid (violation occurred). 0x1 SEC_GPIO_MASK0 Secure GPIO mask for port 0 pins. 0xF80 32 read-write 0xFFFFFFFF 0xFFFFFFFF PIO0_PIN0_SEC_MASK Secure mask for pin P0_0 0 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN1_SEC_MASK Secure mask for pin P0_1 1 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN2_SEC_MASK Secure mask for pin P0_2 2 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN3_SEC_MASK Secure mask for pin P0_3 3 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN4_SEC_MASK Secure mask for pin P0_4 4 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN5_SEC_MASK Secure mask for pin P0_5 5 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN6_SEC_MASK Secure mask for pin P0_6 6 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN7_SEC_MASK Secure mask for pin P0_7 7 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN8_SEC_MASK Secure mask for pin P0_8 8 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN9_SEC_MASK Secure mask for pin P0_9 9 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN10_SEC_MASK Secure mask for pin P0_10 10 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN11_SEC_MASK Secure mask for pin P0_11 11 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN12_SEC_MASK Secure mask for pin P0_12 12 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN13_SEC_MASK Secure mask for pin P0_13 13 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN14_SEC_MASK Secure mask for pin P0_14 14 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN15_SEC_MASK Secure mask for pin P0_15 15 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN16_SEC_MASK Secure mask for pin P0_16 16 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN17_SEC_MASK Secure mask for pin P0_17 17 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN18_SEC_MASK Secure mask for pin P0_18 18 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN19_SEC_MASK Secure mask for pin P0_19 19 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN20_SEC_MASK Secure mask for pin P0_20 20 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN21_SEC_MASK Secure mask for pin P0_21 21 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN22_SEC_MASK Secure mask for pin P0_22 22 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN23_SEC_MASK Secure mask for pin P0_23 23 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN24_SEC_MASK Secure mask for pin P0_24 24 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN25_SEC_MASK Secure mask for pin P0_25 25 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN26_SEC_MASK Secure mask for pin P0_26 26 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN27_SEC_MASK Secure mask for pin P0_27 27 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN28_SEC_MASK Secure mask for pin P0_28 28 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN29_SEC_MASK Secure mask for pin P0_29 29 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN30_SEC_MASK Secure mask for pin P0_30 30 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO0_PIN31_SEC_MASK Secure mask for pin P0_31 31 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 SEC_GPIO_MASK1 Secure GPIO mask for port 1 pins. 0xF84 32 read-write 0xFFFFFFFF 0xFFFFFFFF PIO1_PIN0_SEC_MASK Secure mask for pin P1_0 0 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN1_SEC_MASK Secure mask for pin P1_1 1 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN2_SEC_MASK Secure mask for pin P1_2 2 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN3_SEC_MASK Secure mask for pin P1_3 3 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN4_SEC_MASK Secure mask for pin P1_4 4 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN5_SEC_MASK Secure mask for pin P1_5 5 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN6_SEC_MASK Secure mask for pin P1_6 6 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN7_SEC_MASK Secure mask for pin P1_7 7 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN8_SEC_MASK Secure mask for pin P1_8 8 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN9_SEC_MASK Secure mask for pin P1_9 9 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN10_SEC_MASK Secure mask for pin P1_10 10 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN11_SEC_MASK Secure mask for pin P1_11 11 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN12_SEC_MASK Secure mask for pin P1_12 12 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN13_SEC_MASK Secure mask for pin P1_13 13 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN14_SEC_MASK Secure mask for pin P1_14 14 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN15_SEC_MASK Secure mask for pin P1_15 15 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN16_SEC_MASK Secure mask for pin P1_16 16 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN17_SEC_MASK Secure mask for pin P1_17 17 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN18_SEC_MASK Secure mask for pin P1_18 18 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN19_SEC_MASK Secure mask for pin P1_19 19 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN20_SEC_MASK Secure mask for pin P1_20 20 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN21_SEC_MASK Secure mask for pin P1_21 21 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN22_SEC_MASK Secure mask for pin P1_22 22 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN23_SEC_MASK Secure mask for pin P1_23 23 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN24_SEC_MASK Secure mask for pin P1_24 24 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN25_SEC_MASK Secure mask for pin P1_25 25 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN26_SEC_MASK Secure mask for pin P1_26 26 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN27_SEC_MASK Secure mask for pin P1_27 27 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN28_SEC_MASK Secure mask for pin P1_28 28 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN29_SEC_MASK Secure mask for pin P1_29 29 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN30_SEC_MASK Secure mask for pin P1_30 30 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 PIO1_PIN31_SEC_MASK Secure mask for pin P1_31 31 1 read-write BLOCKED Pin state is blocked to non-secure world. 0 READABLE Pin state is readable by non-secure world. 0x1 SEC_CPU_INT_MASK0 Secure Interrupt mask for CPU1 0xF90 32 read-write 0xFFFFFFFF 0xFFFFFFFF SYS_IRQ Watchdog Timer, Brown Out Detectors and Flash Controller interrupts 0 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SDMA0_IRQ System DMA 0 (non-secure) interrupt. 1 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_GLOBALINT0_IRQ GPIO Group 0 interrupt. 2 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_GLOBALINT1_IRQ GPIO Group 1 interrupt. 3 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ0 Pin interrupt 0 or pattern match engine slice 0 interrupt. 4 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ1 Pin interrupt 1 or pattern match engine slice 1 interrupt. 5 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ2 Pin interrupt 2 or pattern match engine slice 2 interrupt. 6 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ3 Pin interrupt 3 or pattern match engine slice 3 interrupt. 7 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 UTICK_IRQ Micro Tick Timer interrupt. 8 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 MRT_IRQ Multi-Rate Timer interrupt. 9 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 CTIMER0_IRQ Standard counter/timer 0 interrupt. 10 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 CTIMER1_IRQ Standard counter/timer 1 interrupt. 11 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SCT_IRQ SCTimer/PWM interrupt. 12 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 CTIMER3_IRQ Standard counter/timer 3 interrupt. 13 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM0_IRQ Flexcomm 0 interrupt (USART, SPI, I2C, I2S). 14 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM1_IRQ Flexcomm 1 interrupt (USART, SPI, I2C, I2S). 15 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM2_IRQ Flexcomm 2 interrupt (USART, SPI, I2C, I2S). 16 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM3_IRQ Flexcomm 3 interrupt (USART, SPI, I2C, I2S). 17 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM4_IRQ Flexcomm 4 interrupt (USART, SPI, I2C, I2S). 18 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM5_IRQ Flexcomm 5 interrupt (USART, SPI, I2C, I2S). 19 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM6_IRQ Flexcomm 6 interrupt (USART, SPI, I2C, I2S). 20 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 FLEXCOMM7_IRQ Flexcomm 7 interrupt (USART, SPI, I2C, I2S). 21 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 ADC_IRQ General Purpose ADC interrupt. 22 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED0 Reserved. Read value is undefined, only zero should be written. 23 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 ACMP_IRQ Analog Comparator interrupt. 24 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED1 Reserved. Read value is undefined, only zero should be written. 25 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED2 Reserved. Read value is undefined, only zero should be written. 26 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 USB0_NEEDCLK USB Full Speed Controller Clock request interrupt. 27 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 USB0_IRQ USB Full Speed Controller interrupt. 28 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RTC_IRQ RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ 29 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED3 Reserved. Read value is undefined, only zero should be written. 30 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 MAILBOX_IRQ Mailbox interrupt. 31 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SEC_CPU_INT_MASK1 Secure Interrupt mask for CPU1 0xF94 32 read-write 0xFFFFFFFF 0xFFFFFFFF GPIO_INT0_IRQ4 Pin interrupt 4 or pattern match engine slice 4 interrupt. 0 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ5 Pin interrupt 5 or pattern match engine slice 5 interrupt. 1 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ6 Pin interrupt 6 or pattern match engine slice 6 interrupt. 2 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 GPIO_INT0_IRQ7 Pin interrupt 7 or pattern match engine slice 7 interrupt. 3 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 CTIMER2_IRQ Standard counter/timer 2 interrupt. 4 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 CTIMER4_IRQ Standard counter/timer 4 interrupt. 5 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 OS_EVENT_TIMER_IRQ OS Event Timer and OS Event Timer Wakeup interrupts 6 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED0 Reserved. Read value is undefined, only zero should be written. 7 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED1 Reserved. Read value is undefined, only zero should be written. 8 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED2 Reserved. Read value is undefined, only zero should be written. 9 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SDIO_IRQ SDIO Controller interrupt. 10 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED3 Reserved. Read value is undefined, only zero should be written. 11 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED4 Reserved. Read value is undefined, only zero should be written. 12 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 RESERVED5 Reserved. Read value is undefined, only zero should be written. 13 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 USB1_PHY_IRQ USB High Speed PHY Controller interrupt. 14 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 USB1_IRQ USB High Speed Controller interrupt. 15 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 USB1_NEEDCLK USB High Speed Controller Clock request interrupt. 16 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SEC_HYPERVISOR_CALL_IRQ Secure fault Hyper Visor call interrupt. 17 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SEC_GPIO_INT0_IRQ0 Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. 18 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SEC_GPIO_INT0_IRQ1 Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. 19 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 PLU_IRQ Programmable Look-Up Controller interrupt. 20 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SEC_VIO_IRQ Security Violation interrupt. 21 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SHA_IRQ HASH-AES interrupt. 22 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 CASPER_IRQ CASPER interrupt. 23 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 PUFKEY_IRQ PUF interrupt. 24 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 PQ_IRQ Power Quad interrupt. 25 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SDMA1_IRQ System DMA 1 (Secure) interrupt 26 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 LSPI_HS_IRQ High Speed SPI interrupt 27 1 read-write INVISIBLE no description available 0 VISIBLE no description available 0x1 SEC_MASK_LOCK Security General Purpose register access control. 0xFBC 32 read-write 0xAAA 0xFFF SEC_GPIO_MASK0_LOCK SEC_GPIO_MASK0 register write-lock. 0 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 SEC_GPIO_MASK1_LOCK SEC_GPIO_MASK1 register write-lock. 2 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 SEC_CPU1_INT_MASK0_LOCK SEC_CPU_INT_MASK0 register write-lock. 8 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 SEC_CPU1_INT_MASK1_LOCK SEC_CPU_INT_MASK1 register write-lock. 10 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 MASTER_SEC_LEVEL master secure level register 0xFD0 32 read-write 0x80000000 0xFFFFFFFF CPU1C Micro-Cortex M33 (CPU1) Code bus. 4 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 CPU1S Micro-Cortex M33 (CPU1) System bus. 6 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 USBFSD USB Full Speed Device. 8 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SDMA0 System DMA 0. 10 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SDIO SDIO. 16 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 PQ Power Quad. 18 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 HASH Hash. 20 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 USBFSH USB Full speed Host. 22 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 SDMA1 System DMA 1 security level. 24 2 read-write ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0 ENUM_NS_P Non-secure and Privilege access allowed. 0x1 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x2 ENUM_S_P Secure and Priviledge user access allowed. 0x3 MASTER_SEC_LEVEL_LOCK MASTER_SEC_LEVEL write-lock. 30 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 MASTER_SEC_ANTI_POL_REG master secure level anti-pole register 0xFD4 32 read-write 0xBFFFFFFF 0xFFFFFFFF CPU1C Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) 4 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 CPU1S Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) 6 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 USBFSD USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) 8 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 SDMA0 System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) 10 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 SDIO SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) 16 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 PQ Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) 18 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 HASH Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) 20 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 USBFSH USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) 22 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 SDMA1 System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) 24 2 read-write ENUM_S_P Secure and Priviledge user access allowed. 0 ENUM_S_NP Secure and Non-priviledge user access allowed. 0x1 ENUM_NS_P Non-secure and Privilege access allowed. 0x2 ENUM_NS_NP Non-secure and Non-priviledge user access allowed. 0x3 MASTER_SEC_LEVEL_ANTIPOL_LOCK MASTER_SEC_ANTI_POL_REG register write-lock. 30 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 CPU0_LOCK_REG Miscalleneous control signals for in Cortex M33 (CPU0) 0xFEC 32 read-write 0x800002AA 0xC00003FF LOCK_NS_VTOR Cortex M33 (CPU0) VTOR_NS register write-lock. 0 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 LOCK_NS_MPU Cortex M33 (CPU0) non-secure MPU register write-lock. 2 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 LOCK_S_VTAIRCR Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. 4 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 LOCK_S_MPU Cortex M33 (CPU0) Secure MPU registers write-lock. 6 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 LOCK_SAU Cortex M33 (CPU0) SAU registers write-lock. 8 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 CPU0_LOCK_REG_LOCK CPU0_LOCK_REG write-lock. 30 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 CPU1_LOCK_REG Miscalleneous control signals for in micro-Cortex M33 (CPU1) 0xFF0 32 read-write 0x8000000A 0xC000000F LOCK_NS_VTOR micro-Cortex M33 (CPU1) VTOR_NS register write-lock. 0 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 LOCK_NS_MPU micro-Cortex M33 (CPU1) non-secure MPU register write-lock. 2 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 CPU1_LOCK_REG_LOCK CPU1_LOCK_REG write-lock. 30 2 read-write BLOCKED Restricted mode. 0x1 WRITABLE Writable. 0x2 MISC_CTRL_DP_REG secure control duplicate register 0xFF8 32 read-write 0xAAAA 0xFFFF WRITE_LOCK Write lock. 0 2 read-write RESTRICTED Restricted mode. 0x1 ACCESSIBLE Secure control registers can be written. 0x2 ENABLE_SECURE_CHECKING Enable secure check for AHB matrix. 2 2 read-write ENABLE Restricted mode. 0x1 DISABLE Disable check. 0x2 ENABLE_S_PRIV_CHECK Enable secure privilege check for AHB matrix. 4 2 read-write ENABLE Restricted mode. 0x1 DISABLE Disable check. 0x2 ENABLE_NS_PRIV_CHECK Enable non-secure privilege check for AHB matrix. 6 2 read-write ENABLE Restricted mode. 0x1 DISABLE Disable check. 0x2 DISABLE_VIOLATION_ABORT Disable secure violation abort. 8 2 read-write DISABLE Disable abort fort secure checker. 0x1 ENABLE Enable abort fort secure checker. 0x2 DISABLE_SIMPLE_MASTER_STRICT_MODE Disable simple master strict mode. 10 2 read-write TIER_MODE Simple master in tier mode. 0x1 STRICT_MODE Simple master in strict mode. 0x2 DISABLE_SMART_MASTER_STRICT_MODE Disable smart master strict mode. 12 2 read-write TIER_MODE Smart master in tier mode. 0x1 STRICT_MODE Smart master in strict mode. 0x2 IDAU_ALL_NS Disable IDAU. 14 2 read-write DISABLE IDAU is disable. 0x1 ENABLE IDAU is enabled. 0x2 MISC_CTRL_REG secure control register 0xFFC 32 read-write 0xAAAA 0xFFFF WRITE_LOCK Write lock. 0 2 read-write RESTRICTED Restricted mode. 0x1 ACCESSIBLE Secure control registers can be written. 0x2 ENABLE_SECURE_CHECKING Enable secure check for AHB matrix. 2 2 read-write ENABLE Restricted mode. 0x1 DISABLE Disable check. 0x2 ENABLE_S_PRIV_CHECK Enable secure privilege check for AHB matrix. 4 2 read-write ENABLE Restricted mode. 0x1 DISABLE Disable check. 0x2 ENABLE_NS_PRIV_CHECK Enable non-secure privilege check for AHB matrix. 6 2 read-write ENABLE Restricted mode. 0x1 DISABLE Disable check. 0x2 DISABLE_VIOLATION_ABORT Disable secure violation abort. 8 2 read-write DISABLE Disable abort fort secure checker. 0x1 ENABLE Enable abort fort secure checker. 0x2 DISABLE_SIMPLE_MASTER_STRICT_MODE Disable simple master strict mode. 10 2 read-write TIER_MODE Simple master in tier mode. 0x1 STRICT_MODE Simple master in strict mode. 0x2 DISABLE_SMART_MASTER_STRICT_MODE Disable smart master strict mode. 12 2 read-write TIER_MODE Smart master in tier mode. 0x1 STRICT_MODE Smart master in strict mode. 0x2 IDAU_ALL_NS Disable IDAU. 14 2 read-write DISABLE IDAU is disable. 0x1 ENABLE IDAU is enabled. 0x2 SCnSCB no description available SCNSCB 0xE000E000 0 0x10 registers CPPWR Coprocessor Power Control Register 0xC 32 read-write 0 0 SU0 State UNKNOWN 0. 0 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS0 State UNKNOWN Secure only 0. 1 1 read-write SECURE_AND_NON_SECURE The SU0 field is accessible from both Security states. 0 SECURE_ONLY The SU0 field is only accessible from the Secure state. 0x1 SU1 State UNKNOWN 1. 2 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS1 State UNKNOWN Secure only 1. 3 1 read-write SECURE_AND_NON_SECURE The SU7 field is accessible from both Security states. 0 SECURE_ONLY The SU7 field is only accessible from the Secure state. 0x1 SU2 State UNKNOWN 2. 4 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS2 State UNKNOWN Secure only 2. 5 1 read-write SECURE_AND_NON_SECURE The SU2 field is accessible from both Security states. 0 SECURE_ONLY The SU2 field is only accessible from the Secure state. 0x1 SU3 State UNKNOWN 3. 6 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS3 State UNKNOWN Secure only 3. 7 1 read-write SECURE_AND_NON_SECURE The SU3 field is accessible from both Security states. 0 SECURE_ONLY The SU3 field is only accessible from the Secure state. 0x1 SU4 State UNKNOWN 4. 8 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS4 State UNKNOWN Secure only 4. 9 1 read-write SECURE_AND_NON_SECURE The SU4 field is accessible from both Security states. 0 SECURE_ONLY The SU4 field is only accessible from the Secure state. 0x1 SU5 State UNKNOWN 5. 10 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS5 State UNKNOWN Secure only 5. 11 1 read-write SECURE_AND_NON_SECURE The SU5 field is accessible from both Security states. 0 SECURE_ONLY The SU5 field is only accessible from the Secure state. 0x1 SU6 State UNKNOWN 6. 12 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS6 State UNKNOWN Secure only 6. 13 1 read-write SECURE_AND_NON_SECURE The SU6 field is accessible from both Security states. 0 SECURE_ONLY The SU6 field is only accessible from the Secure state. 0x1 SU7 State UNKNOWN 7. 14 1 read-write UNKNOWN_NOT_PERMITTED The coprocessor state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The coprocessor state is permitted to become UNKNOWN. 0x1 SUS7 State UNKNOWN Secure only 7. 15 1 read-write SECURE_AND_NON_SECURE The SU7 field is accessible from both Security states. 0 SECURE_ONLY The SU7 field is only accessible from the Secure state. 0x1 SU10 State UNKNOWN 10. 20 1 read-write UNKNOWN_NOT_PERMITTED The floating-point state is not permitted to become UNKNOWN. 0 UNKNOWN_PERMITTED The floating-point state is permitted to become UNKNOWN 0x1 SUS10 State UNKNOWN Secure only 10. 21 1 read-write SECURE_AND_NON_SECURE The SU10 field is accessible from both Security states. 0 SECURE_ONLY The SU10 field is only accessible from the Secure state. 0x1 SU11 State UNKNOWN 11. 22 1 read-write SUS11 State UNKNOWN Secure only 11. 23 1 read-write NVIC no description available NVIC 0xE000E100 0 0xE04 registers 16 0x4 ISER[%s] Interrupt Set Enable Register 0 32 read-write 0 0xFFFFFFFF SETENA0 Interrupt set-enable bits. 0 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA1 Interrupt set-enable bits. 1 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA2 Interrupt set-enable bits. 2 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA3 Interrupt set-enable bits. 3 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA4 Interrupt set-enable bits. 4 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA5 Interrupt set-enable bits. 5 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA6 Interrupt set-enable bits. 6 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA7 Interrupt set-enable bits. 7 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA8 Interrupt set-enable bits. 8 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA9 Interrupt set-enable bits. 9 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA10 Interrupt set-enable bits. 10 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA11 Interrupt set-enable bits. 11 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA12 Interrupt set-enable bits. 12 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA13 Interrupt set-enable bits. 13 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA14 Interrupt set-enable bits. 14 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA15 Interrupt set-enable bits. 15 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA16 Interrupt set-enable bits. 16 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA17 Interrupt set-enable bits. 17 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA18 Interrupt set-enable bits. 18 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA19 Interrupt set-enable bits. 19 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA20 Interrupt set-enable bits. 20 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA21 Interrupt set-enable bits. 21 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA22 Interrupt set-enable bits. 22 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA23 Interrupt set-enable bits. 23 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA24 Interrupt set-enable bits. 24 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA25 Interrupt set-enable bits. 25 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA26 Interrupt set-enable bits. 26 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA27 Interrupt set-enable bits. 27 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA28 Interrupt set-enable bits. 28 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA29 Interrupt set-enable bits. 29 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA30 Interrupt set-enable bits. 30 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 SETENA31 Interrupt set-enable bits. 31 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 16 0x4 ICER[%s] Interrupt Clear Enable Register 0x80 32 read-write 0 0xFFFFFFFF CLRENA0 Interrupt clear-enable bits. 0 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA1 Interrupt clear-enable bits. 1 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA2 Interrupt clear-enable bits. 2 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA3 Interrupt clear-enable bits. 3 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA4 Interrupt clear-enable bits. 4 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA5 Interrupt clear-enable bits. 5 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA6 Interrupt clear-enable bits. 6 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA7 Interrupt clear-enable bits. 7 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA8 Interrupt clear-enable bits. 8 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA9 Interrupt clear-enable bits. 9 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA10 Interrupt clear-enable bits. 10 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA11 Interrupt clear-enable bits. 11 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA12 Interrupt clear-enable bits. 12 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA13 Interrupt clear-enable bits. 13 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA14 Interrupt clear-enable bits. 14 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA15 Interrupt clear-enable bits. 15 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA16 Interrupt clear-enable bits. 16 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA17 Interrupt clear-enable bits. 17 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA18 Interrupt clear-enable bits. 18 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA19 Interrupt clear-enable bits. 19 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA20 Interrupt clear-enable bits. 20 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA21 Interrupt clear-enable bits. 21 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA22 Interrupt clear-enable bits. 22 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA23 Interrupt clear-enable bits. 23 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA24 Interrupt clear-enable bits. 24 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA25 Interrupt clear-enable bits. 25 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA26 Interrupt clear-enable bits. 26 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA27 Interrupt clear-enable bits. 27 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA28 Interrupt clear-enable bits. 28 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA29 Interrupt clear-enable bits. 29 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA30 Interrupt clear-enable bits. 30 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 CLRENA31 Interrupt clear-enable bits. 31 1 read-write DISABLED Write: No effect; Read: Interrupt 32n+m disabled 0 ENABLED Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled 0x1 16 0x4 ISPR[%s] Interrupt Set Pending Register 0x100 32 read-write 0 0xFFFFFFFF SETPEND0 Interrupt set-pending bits. 0 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND1 Interrupt set-pending bits. 1 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND2 Interrupt set-pending bits. 2 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND3 Interrupt set-pending bits. 3 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND4 Interrupt set-pending bits. 4 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND5 Interrupt set-pending bits. 5 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND6 Interrupt set-pending bits. 6 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND7 Interrupt set-pending bits. 7 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND8 Interrupt set-pending bits. 8 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND9 Interrupt set-pending bits. 9 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND10 Interrupt set-pending bits. 10 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND11 Interrupt set-pending bits. 11 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND12 Interrupt set-pending bits. 12 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND13 Interrupt set-pending bits. 13 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND14 Interrupt set-pending bits. 14 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND15 Interrupt set-pending bits. 15 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND16 Interrupt set-pending bits. 16 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND17 Interrupt set-pending bits. 17 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND18 Interrupt set-pending bits. 18 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND19 Interrupt set-pending bits. 19 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND20 Interrupt set-pending bits. 20 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND21 Interrupt set-pending bits. 21 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND22 Interrupt set-pending bits. 22 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND23 Interrupt set-pending bits. 23 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND24 Interrupt set-pending bits. 24 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND25 Interrupt set-pending bits. 25 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND26 Interrupt set-pending bits. 26 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND27 Interrupt set-pending bits. 27 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND28 Interrupt set-pending bits. 28 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND29 Interrupt set-pending bits. 29 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND30 Interrupt set-pending bits. 30 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 SETPEND31 Interrupt set-pending bits. 31 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending 0x1 16 0x4 ICPR[%s] Interrupt Clear Pending Register 0x180 32 read-write 0 0xFFFFFFFF CLRPEND0 Interrupt clear-pending bits. 0 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND1 Interrupt clear-pending bits. 1 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND2 Interrupt clear-pending bits. 2 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND3 Interrupt clear-pending bits. 3 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND4 Interrupt clear-pending bits. 4 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND5 Interrupt clear-pending bits. 5 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND6 Interrupt clear-pending bits. 6 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND7 Interrupt clear-pending bits. 7 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND8 Interrupt clear-pending bits. 8 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND9 Interrupt clear-pending bits. 9 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND10 Interrupt clear-pending bits. 10 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND11 Interrupt clear-pending bits. 11 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND12 Interrupt clear-pending bits. 12 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND13 Interrupt clear-pending bits. 13 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND14 Interrupt clear-pending bits. 14 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND15 Interrupt clear-pending bits. 15 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND16 Interrupt clear-pending bits. 16 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND17 Interrupt clear-pending bits. 17 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND18 Interrupt clear-pending bits. 18 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND19 Interrupt clear-pending bits. 19 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND20 Interrupt clear-pending bits. 20 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND21 Interrupt clear-pending bits. 21 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND22 Interrupt clear-pending bits. 22 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND23 Interrupt clear-pending bits. 23 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND24 Interrupt clear-pending bits. 24 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND25 Interrupt clear-pending bits. 25 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND26 Interrupt clear-pending bits. 26 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND27 Interrupt clear-pending bits. 27 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND28 Interrupt clear-pending bits. 28 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND29 Interrupt clear-pending bits. 29 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND30 Interrupt clear-pending bits. 30 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 CLRPEND31 Interrupt clear-pending bits. 31 1 read-write NOT_PENDING Write: No effect; Read: Interrupt 32n+m is not pending 0 PENDING Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending 0x1 16 0x4 IABR[%s] Interrupt Active Bit Register 0x200 32 read-write 0 0 ACTIVE0 Active state bits. 0 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE1 Active state bits. 1 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE2 Active state bits. 2 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE3 Active state bits. 3 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE4 Active state bits. 4 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE5 Active state bits. 5 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE6 Active state bits. 6 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE7 Active state bits. 7 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE8 Active state bits. 8 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE9 Active state bits. 9 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE10 Active state bits. 10 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE11 Active state bits. 11 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE12 Active state bits. 12 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE13 Active state bits. 13 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE14 Active state bits. 14 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE15 Active state bits. 15 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE16 Active state bits. 16 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE17 Active state bits. 17 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE18 Active state bits. 18 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE19 Active state bits. 19 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE20 Active state bits. 20 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE21 Active state bits. 21 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE22 Active state bits. 22 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE23 Active state bits. 23 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE24 Active state bits. 24 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE25 Active state bits. 25 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE26 Active state bits. 26 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE27 Active state bits. 27 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE28 Active state bits. 28 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE29 Active state bits. 29 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE30 Active state bits. 30 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 ACTIVE31 Active state bits. 31 1 read-write NOT_ACTIVE The interrupt is not active. 0 ACTIVE The interrupt is active. 0x1 16 0x4 ITNS[%s] Interrupt Target Non-secure Register 0x280 32 read-write 0 0 INTS0 Interrupt Targets Non-secure bits. 0 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS1 Interrupt Targets Non-secure bits. 1 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS2 Interrupt Targets Non-secure bits. 2 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS3 Interrupt Targets Non-secure bits. 3 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS4 Interrupt Targets Non-secure bits. 4 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS5 Interrupt Targets Non-secure bits. 5 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS6 Interrupt Targets Non-secure bits. 6 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS7 Interrupt Targets Non-secure bits. 7 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS8 Interrupt Targets Non-secure bits. 8 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS9 Interrupt Targets Non-secure bits. 9 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS10 Interrupt Targets Non-secure bits. 10 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS11 Interrupt Targets Non-secure bits. 11 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS12 Interrupt Targets Non-secure bits. 12 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS13 Interrupt Targets Non-secure bits. 13 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS14 Interrupt Targets Non-secure bits. 14 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS15 Interrupt Targets Non-secure bits. 15 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS16 Interrupt Targets Non-secure bits. 16 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS17 Interrupt Targets Non-secure bits. 17 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS18 Interrupt Targets Non-secure bits. 18 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS19 Interrupt Targets Non-secure bits. 19 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS20 Interrupt Targets Non-secure bits. 20 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS21 Interrupt Targets Non-secure bits. 21 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS22 Interrupt Targets Non-secure bits. 22 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS23 Interrupt Targets Non-secure bits. 23 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS24 Interrupt Targets Non-secure bits. 24 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS25 Interrupt Targets Non-secure bits. 25 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS26 Interrupt Targets Non-secure bits. 26 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS27 Interrupt Targets Non-secure bits. 27 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS28 Interrupt Targets Non-secure bits. 28 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS29 Interrupt Targets Non-secure bits. 29 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS30 Interrupt Targets Non-secure bits. 30 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 INTS31 Interrupt Targets Non-secure bits. 31 1 read-write SECURE_STATE The interrupt targets Secure state. 0 NON_SECURE_STATE The interrupt targets Non-secure state. 0x1 120 0x4 IPR[%s] Interrupt Priority Register 0x300 32 read-write 0 0 PRI_0 no description available 0 8 read-write PRI_1 no description available 8 8 read-write PRI_2 no description available 16 8 read-write PRI_3 no description available 24 8 read-write STIR Software Trigger Interrupt Register 0xE00 32 read-write 0 0xFFFFFFFF INTID Interrupt ID of the interrupt to trigger, in the range 0-479. 0 9 write-only SCB no description available SCB 0xE000ED00 0 0x90 registers AIRCR Application Interrupt and Reset Control Register 0xC 32 read-write 0xFA050000 0xFFFFFFFF VECTCLRACTIVE Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states. 1 1 write-only SYSRESETREQ System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI. 2 1 read-write NO_REQUEST Do not request a system reset. 0 REQUEST_RESET Request a system reset. 0x1 SYSRESETREQS System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state. 3 1 read-write SECURE_AND_NON_SECURE SYSRESETREQ functionality is available to both Security states. 0 SECURE_ONLY SYSRESETREQ functionality is only available to Secure state. 0x1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states 8 3 read-write BFHFNMINS BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state. 13 1 read-write SECURE BusFault, HardFault, and NMI are Secure. 0 NON_SECURE BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. 0x1 PRIS Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state. 14 1 read-write SAME_PRIORITY Priority ranges of Secure and Non-secure exceptions are identical 0 SECURE_PRIORITIZED Non-secure exceptions are de-prioritized 0x1 ENDIANNESS Data endianness bit. This bit is not banked between Security states. 15 1 read-only LITTLE_ENDIAN Little-endian. 0 BIG_ENDIAN Big-endian 0x1 VECTKEY Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states. 16 16 read-only SCR The SCR controls features of entry to and exit from low-power state. 0x10 32 read-write 0 0xFFFFFFFF SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states. 1 1 read-write NOT_SLEEP Do not sleep when returning to Thread mode. 0 SLEEP Enter sleep, or deep sleep, on return from an ISR 0x1 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states. 2 1 read-write SLEEP Sleep. 0 DEEP_SLEEP Deep sleep. 0x1 SLEEPDEEPS Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states. 3 1 read-write SECURE_AND_NON_SECURE The SLEEPDEEP bit is accessible from both Security states. 0 SECURE_ONLY The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state. 0x1 SEVONPEND Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states. 4 1 read-write EXCLUDE_DISABLED_INTERRUPTS Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 0 INCLUDE_DISABLED_INTERRUPTS Enabled events and all interrupts, including disabled interrupts, can wakeup the processor 0x1 SHCSR System Handler Control and State Register 0x24 32 read-write 0 0xFFFFFFFF MEMFAULTACT MemManage exception active. 0 1 read-write NOT_ACTIVE MemManage exception is not active. 0 ACTIVE MemManage exception is active. 0x1 BUSFAULTACT BusFault exception active. 1 1 read-write NOT_ACTIVE BusFault exception is not active. 0 ACTIVE BusFault exception is active. 0x1 HARDFAULTACT HardFault exception active. 2 1 read-write NOT_ACTIVE HardFault exception is not active. 0 ACTIVE HardFault exception is active. 0x1 USGFAULTACT UsageFault exception active. 3 1 read-write NOT_ACTIVE UsageFault exception is not active. 0 ACTIVE UsageFault exception is active. 0x1 SECUREFAULTACT SecureFault exception active 4 1 read-write NOT_ACTIVE SecureFault exception is not active. 0 ACTIVE SecureFault exception is active. 0x1 NMIACT NMI exception active. 5 1 read-write NOT_ACTIVE NMI exception is not active. 0 ACTIVE NMI exception is active. 0x1 SVCALLACT SVCall active. 7 1 read-write NOT_ACTIVE SVCall exception is not active. 0 ACTIVE SVCall exception is active. 0x1 MONITORACT Debug monitor active. 8 1 read-write NOT_ACTIVE Debug monitor exception is not active. 0 ACTIVE Debug monitor exception is active. 0x1 PENDSVACT PendSV exception active. 10 1 read-write NOT_ACTIVE PendSV exception is not active. 0 ACTIVE PendSV exception is active. 0x1 SYSTICKACT SysTick exception active. 11 1 read-write NOT_ACTIVE SysTick exception is not active. 0 ACTIVE SysTick exception is active. 0x1 USGFAULTPENDED UsageFault exception pending. 12 1 read-write NOT_PENDING UsageFault exception is not pending. 0 PENDING UsageFault exception is pending. 0x1 MEMFAULTPENDED MemManage exception pending. 13 1 read-write NOT_PENDING MemManage exception is not pending. 0 PENDING MemManage exception is pending. 0x1 BUSFAULTPENDED BusFault exception pending. 14 1 read-write NOT_PENDING BusFault exception is pending. 0 PENDING BusFault exception is not pending. 0x1 SVCALLPENDED SVCall pending. 15 1 read-write NOT_PENDING SVCall exception is not pending. 0 PENDING SVCall exception is pending. 0x1 MEMFAULTENA MemManage enable. 16 1 read-write DISABLED MemManage exception is disabled. 0 ENABLED MemManage exception is enabled. 0x1 BUSFAULTENA BusFault enable. 17 1 read-write DISABLED BusFault is disabled. 0 ENABLED BusFault is enabled. 0x1 USGFAULTENA UsageFault enable. 18 1 read-write DISABLED UsageFault is disabled. 0 ENABLED UsageFault is enabled. 0x1 SECUREFAULTENA SecureFault exception enable. 19 1 read-write DISABLED SecureFault exception is disabled. 0 ENABLED SecureFault exception is enabled. 0x1 SECUREFAULTPENDED SecureFault exception pended state bit. 20 1 read-write DISABLED SecureFault exception modification is disabled. 0 ENABLED SecureFault exception modification is enabled. 0x1 HARDFAULTPENDED HardFault exception pended state 21 1 read-write DISABLED HardFault exception modification is disabled. 0 ENABLED HardFault exception modification is enabled. 0x1 NSACR Non-secure Access Control Register 0x8C 32 read-write 0 0 CP0 CP0 access. 0 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP1 CP1 access. 1 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP2 CP2 access. 2 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP3 CP3 access. 3 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP4 CP4 access. 4 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP5 CP5 access. 5 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP6 CP6 access. 6 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP7 CP7 access. 7 1 read-write NOT_PERMITTED Non-secure accesses to this coprocessor generate a NOCP UsageFault. 0 PERMITTED Non-secure access to this coprocessor permitted. 0x1 CP10 CP10 access. 10 1 read-write NOT_PERMITTED Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault. 0 PERMITTED Non-secure access to the Floatingpoint Extension permitted. 0x1 CP11 CP11 access. 11 1 read-write SAU no description available SAU 0xE000EDD0 0 0xEC registers CTRL Security Attribution Unit Control Register 0xD0 32 read-write 0 0xFFFFFFFF ENABLE Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region. 0 1 read-write DISABLED The SAU is disabled. 0 ENABLED The SAU is enabled. 0x1 ALLNS All Non-secure. 1 1 read-write SECURED_MEMORY Memory is marked as Secure and is not Non-secure callable. 0 NON_SECURED_MEMORY Memory is marked as Non-secure. 0x1 TYPE Security Attribution Unit Type Register 0xD4 32 read-write 0 0xFFFFFFFF SREGION SAU regions. The number of implemented SAU regions. 0 8 read-write RNR Security Attribution Unit Region Number Register 0xD8 32 read-write 0 0 REGION Region number. 0 8 read-write RBAR Security Attribution Unit Region Base Address Register 0xDC 32 read-write 0 0 BADDR Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00. 5 27 read-write RLAR Security Attribution Unit Region Limit Address Register 0xE0 32 read-write 0 0 ENABLE Enable. SAU region enable. 0 1 read-write ENABLED SAU region is enabled. 0 DISABLED SAU region is disabled. 0x1 NSC Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region. 1 1 read-write NOT_NON_SECURE_CALLABLE Region is not Non-secure callable. 0 NON_SECURE_CALLABLE Region is Non-secure callable. 0x1 LADDR Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F. 5 27 read-write SFSR Secure Fault Status Register 0xE4 32 read-write 0 0xFFFFFFFF INVEP Invalid entry point. 0 1 read-write NO_ERROR Error has not occurred. 0 ERROR Error has occurred. 0x1 INVIS Invalid integrity signature flag. 1 1 read-write NO_ERROR Error has not occurred. 0 ERROR Error has occurred. 0x1 INVER Invalid exception return flag. 2 1 read-write NO_ERROR Error has not occurred. 0 ERROR Error has occurred. 0x1 AUVIOL Attribution unit violation flag. 3 1 read-write NO_ERROR Error has not occurred. 0 ERROR Error has occurred. 0x1 INVTRAN Invalid transition flag. 4 1 read-write NO_ERROR Error has not occurred. 0 ERROR Error has occurred. 0x1 LSPERR Lazy state preservation error flag. 5 1 read-write NO_ERROR Error has not occurred. 0 ERROR Error has occurred. 0x1 SFARVALID Secure fault address valid. 6 1 read-write NOT_VALID SFAR content not valid. 0 VALID SFAR content valid. 0x1 LSERR Lazy state error flag. 7 1 read-write NO_ERROR Error has not occurred 0 ERROR Error has occurred. 0x1 SFAR Secure Fault Address Register 0xE8 32 read-write 0 0 ADDRESS When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation. 0 32 read-write