LPC800 0.2 LPC800 CM0 r0p0 little 0 0 2 0 LPC_ 8 32 32 WWDT Windowed Watchdog Timer (WWDT) WWDT 0x40000000 0x0 0xFFF registers WDT 12 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. Once this bit has been written with a 1, it cannot be rewritten with a 0. [0:0] ENUM STOPPED The watchdog timer is stopped. 0 RUNNING The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. [1:1] ENUM NORESET A watchdog timeout will not cause a chip reset. 0 RESET A watchdog timeout will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. [2:2] WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. [3:3] WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. [4:4] ENUM PROTECTED The watchdog time-out value (TC) can be changed at any time. 0 UNPROTECTED The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 1 LOCK A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset. [5:5] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TC Watchdog timer constant register. This 24-bit register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF COUNT Watchdog time-out value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 FEED Feed value should be 0xAA followed by 0x55. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TV Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF COUNT Counter timer value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] WARNINT Watchdog Warning Interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] WINDOW Watchdog Window compare value. 0x018 read-write 0xFFFFFF 0xFFFFFFFF WINDOW Watchdog window value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] MRT Multi-Rate Timer (MRT) MRT 0x40004000 0x0 0xFFF registers MRT 10 4 0x10 0-3 INTVAL%s MRT0 Time interval value register. This value is loaded into the TIMER0 register. 0x0 read-write 0 0xFFFFFFFF IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRTn starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [30:24] LOAD Determines how the timer interval value IVALUE is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. [31:31] ENUM NO_FORCE_LOAD_THE_L No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. 0 FORCE_LOAD_THE_INTV Force load. The INTVALn interval value IVALUE is immediately loaded into the TIMERn register while TIMERn is running. 1 4 0x10 0-3 TIMER%s MRT0 Timer register. This register reads the value of the down-counter. 0x4 read-only 0x00FFFFFF 0xFFFFFFFF VALUE Holds the current timer value of the down-counter. The initial value is loaded as IVALUE - 1 from the TIME_INTVALn register either at the end of the time interval if the LOAD bit in TIME_INTVALn is 0 and the timer is in repeat mode or immediately if LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x7FFF FFFF). [23:0] RESERVED Reserved. [31:24] 4 0x10 0-3 CTRL%s MRT0 Control register. This register controls the MRT0 modes. 0x8 read-write 0 0xFFFFFFFF INTEN Enable the TIMERn interrupt. [0:0] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 MODE Selects timer mode. [2:1] ENUM REPEAT_INTERRUPT_MOD Repeat interrupt mode. 0x0 ONE_SHOT_INTERRUPT_M One-shot interrupt mode. 0x1 ONE_SHOT_BUS_STALL_M One-shot bus stall mode. 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. [31:3] 4 0x10 0-3 STAT%s MRT0 Status register. 0xC read-write 0 0xFFFFFFFF INTFLAG Monitors the interrupt flag. [0:0] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT_T Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 RUN Indicates the state of TIMERn. This bit is read-only. [1:1] ENUM IDLE_STATE_TIMERN_I Idle state. TIMERn is stopped. 0 RUNNING_TIMERN_IS_R Running. TIMERn is running. 1 RESERVED Reserved. [31:2] IDLE_CH Idle channel register. This register returns the number of the first idle channel. 0xF4 read-only 0 0xFFFFFFFF RESERVED Reserved. [3:0] CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. If all timer channels are running, CHAN = . [7:4] RESERVED Reserved. [31:8] IRQ_FLAG Global interrupt flag register 0xF8 read-write 0 0xFFFFFFFF GFLAG0 Monitors the interrupt flag of TIMER0. [0:0] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT_T Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG1 Monitors the interrupt flag of TIMER1. [1:1] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT_T Pending interrupt. The interrupt is pending because TIMER1 has reached the end of the time interval. If the INTEN bit in the CONTROL1 register is also set to 1, the interrupt for timer channel 1 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG2 Monitors the interrupt flag of TIMER2. [2:2] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT_T Pending interrupt. The interrupt is pending because TIMER2 has reached the end of the time interval. If the INTEN bit in the CONTROL2 register is also set to 1, the interrupt for timer channel 2 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG3 Monitors the interrupt flag of TIMER3. [3:3] ENUM NO_PENDING_INTERRUPT No pending interrupt. Writing a zero is equivalent to no operation. 0 PENDING_INTERRUPT_T Pending interrupt. The interrupt is pending because TIMER3 has reached the end of the time interval. If the INTEN bit in the CONTROL3 register is also set to 1, the interrupt for timer channel 3 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 RESERVED Reserved. [31:4] WKT Self wake-up timer (WKT) WKT 0x40008000 0x0 0xFFF registers WKT 15 CTRL Self wake-up timer control register. 0x0 read-write 0 0xFFFFFFFF CLKSEL Select the self wake-up timer clock source. [0:0] ENUM DIVIDED_IRC_CLOCK_T Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. This clock is not available in most low-power modes and must not be selected if the timer is to be used to wake up from one of these modes. 0 LOW_POWER_CLOCK_THI Low power clock. This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 CTS can be from the input pin, or fs increments. The accuracy of this clock is limited to +/- 45 % over temperature and processing. This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed. 1 ALARMFLAG Wake-up or alarm timer flag. [1:1] ENUM NO_TIME_OUT_THE_SEL No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect. 0 TIME_OUT_THE_SELF_W Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any low power mode not deep power-down. Writing a 1 clears this status bit and the interrupt too? 1 CLEARCTR Clears the self wake-up timer. [2:2] ENUM NO_EFFECT_READING_T No effect. Reading this bit always returns 0. 0 CLEAR_THE_COUNTER_C Clear the counter. Counting is halted until a new count value is loaded. 1 RESERVED Reserved. [31:3] COUNT Counter register. 0xC read-write 0 0x00000000 VALUE A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer. [31:0] SWM Switch matrix (SWM) SWM 0x4000C000 0x0 0xFFF registers PINASSIGN0 Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS 0x000 read-write 0xFFFFFFFF 0xFFFFFFFF U0_TXD_O U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] U0_RXD_I U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] U0_RTS_O U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] U0_CTS_I U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN1 Pin assign register 1. Assign movable functions U0_SCLC, U1_TXD, U1_RXD 0x004 read-write 0xFFFFFFFF 0xFFFFFFFF U0_SCLK_IO U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] U1_TXD_O U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] U1_RXD_I U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] U1_RTS_O U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN2 Pin assign register 2. Assign movable functions U2_TXD, U2_RXD 0x008 read-write 0xFFFFFFFF 0xFFFFFFFF U1_CTS_I U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] U1_SCLK_IO U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] U2_TXD_O U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] U2_RXD_I U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN3 Pin assignregister 3. Assign movable function SPI0_SCK 0x00C read-write 0xFFFFFFFF 0xFFFFFFFF U2_RTS_O U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] U2_CTS_I U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] U2_SCLK_IO U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] SPI0_SCK_IO SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN4 Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL, SPI1_SCK 0x010 read-write 0xFFFFFFFF 0xFFFFFFFF SPI0_MOSI_IO SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] SPI0_MISO_IO SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] SPI0_SSEL_IO SPI0_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] SPI1_SCK_IO SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN5 Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO, SPI1_SSEL, CTIN_0 0x014 read-write 0xFFFFFFFF 0xFFFFFFFF SPI1_MOSI_IO SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] SPI1_MISO_IO SPI1_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] SPI1_SSEL_IO SPI1_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] CTIN_0_I CTIN_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN6 Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3, CTOUT_0 0x018 read-write 0xFFFFFFFF 0xFFFFFFFF CTIN_1_I CTIN_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] CTIN_2_I CTIN_2function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] CTIN_3_I CTIN_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] CTOUT_0_O CTOUT_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN7 Pin assign egister 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3, I2C_SDA 0x01C read-write 0xFFFFFFFF 0xFFFFFFFF CTOUT_1_O CTOUT_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] CTOUT_2_O CTOUT_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] CTOUT_3_O CTOUT_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] I2C_SDA_IO I2C_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINASSIGN8 Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT, GPIO_INT_BMAT 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF I2C_SCL_IO I2C_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [7:0] ACMP_O_O ACMP_O_O function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [15:8] CLKOUT_O CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [23:16] GPIO_INT_BMAT_O GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). [31:24] PINENABLE0 Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP 0x1C0 read-write 0x1B3 0xFFFFFFFF ACMP_I1_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. [0:0] ENUM ENABLE_ACMP_I1_THIS Enable ACMP_I1. This function is enabled on pin PIO0_0. 0 DISABLE_ACMP_I1_GPI Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function can be assigned to pin PIO0_0. 1 ACMP_I2_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2. [1:1] ENUM ENABLE_ACMP_I2_THIS Enable ACMP_I2. This function is enabled on pin PIO0_1. 0 DISABLE_ACMP_I2_GPI Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin PIO0_1. 1 SWCLK_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default. [2:2] ENUM ENABLE_SWCLK_THIS_F Enable SWCLK. This function is enabled on pin PIO0_3. 0 DISABLE_SWCLK_GPIO_ Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable function can be assigned to pin PIO0_3. 1 SWDIO_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default. [3:3] ENUM ENABLE_SWDIO_THIS_F Enable SWDIO. This function is enabled on pin PIO0_2. 0 DISABLE_SWDIO_GPIO_ Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable function can be assigned to pin PIO0_2. 1 XTALIN_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. [4:4] ENUM ENABLE_XTALIN_THIS_ Enable XTALIN. This function is enabled on pin PIO0_8. 0 DISABLE_XTALIN_GPIO Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function can be assigned to pin PIO0_8. 1 XTALOUT_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. [5:5] ENUM ENABLE_XTALOUT_THIS Enable XTALOUT. This function is enabled on pin PIO0_9. 0 DISABLE_XTALOUT_GPI Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function can be assigned to pin PIO0_9. 1 RESET_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default. [6:6] ENUM ENABLE_RESET_THIS_F Enable RESET. This function is enabled on pin PIO0_5. 0 DISABLE_RESET_GPIO_ Disable RESET. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5. 1 CLKIN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN. [7:7] ENUM ENABLE_CLKIN_THIS_F Enable CLKIN. This function is enabled on pin PIO0_1. 0 DISABLE_CLKIN_GPIO_ Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin CLKIN. 1 VDDCMP Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. [8:8] ENUM ENABLE_VDDCMP_THIS_ Enable VDDCMP. This function is enabled on pin PIO0_6. 0 DISABLE_VDDCMP_GPIO Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function can be assigned to pin PIO0_6. 1 RESERVED Reserved. [31:9] PMU Power Management Unit (PMU) PMU 0x40020000 0x0 0xFFF registers PCON Power control register 0x000 read-write 0x0 0xFFFFFFFF PM Power mode [2:0] ENUM DEFAULT_THE_PART_IS Default. The part is in active or sleep mode. 0x0 ARM_WFI_WILL_ENTER_DEEP_SLEEP ARM WFI will enter Deep-sleep mode. 0x1 ARM_WFI_WILL_ENTER_P ARM WFI will enter Power-down mode. 0x2 ARM_WFI_WILL_ENTER_DEEP_POWER_DOWN ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down). 0x3 NODPD A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. [3:3] RESERVED Reserved. Do not write ones to this bit. [7:4] SLEEPFLAG Sleep mode flag [8:8] ENUM READ_NO_POWER_DOWN_ Read: No power-down mode entered. LPC11Uxx is in Active mode. Write: No effect. 0 READ_SLEEPDEEP_SLE Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 1 RESERVED Reserved. Do not write ones to this bit. [10:9] DPDFLAG Deep power-down flag [11:11] ENUM READ_DEEP_POWER_DOWN_NOT_ENTERED Read: Deep power-down mode not entered. Write: No effect. 0 READ_DEEP_POWER_DOWN_ENTERED Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 1 RESERVED Reserved. Do not write ones to this bit. [31:12] 4 0x4 0-3 GPREG%s General purpose register 0 0x004 read-write 0x0 0xFFFFFFFF GPDATA Data retained during Deep power-down mode. [31:0] DPDCTRL Deep power-down control register 0x014 read-write 0x0 0xFFFFFFFF WAKEUPHYS WAKEUP pin hysteresis enable [0:0] ENUM DISABLED_HYSTERESIS Disabled. Hysteresis for WAKUP pin disabled. 0 ENABLED_HYSTERESIS_ Enabled. Hysteresis for WAKEUP pin enabled. 1 WAKEPAD_DISABLE WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Setting this bit is not necessary if Deep power-down mode is not used. [1:1] ENUM ENABLED_THE_WAKE_UP Enabled. The wake-up function is enabled on pin PIO0_4. 0 DISABLED_SETTING_TH Disabled. Setting this bit disables the wake-up function on pin PIO0_4. 1 LPOSCEN Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC. [2:2] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 LPOSCDPDEN Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 12 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Do not set this bit unless you must use the self wake-up timer to wake up from Deep power-down mode. [3:3] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 RESERVED Data retained during Deep power-down mode. or reserved? [31:4] CMP Analog comparator CMP 0x40024000 0x0 0xFFF registers CMP 11 CTRL Comparator control register 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved. Write as 0. [2:0] EDGESEL This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 00 = Falling edges 01 = Rising edges 1x = Both edges [4:3] ENUM FALLING_EDGES Falling edges 0x0 RISING_EDGES Rising edges 0x1 BOTH_EDGES_2 Both edges 0x2 BOTH_EDGES_3 Both edges 0x3 RESERVED Reserved. Write as 0. [5:5] COMPSA Comparator output control [6:6] ENUM DIRECT Comparator output is used directly. 0 SYNCH Comparator output is synchronized to the bus clock for output to other modules. 1 RESERVED Reserved. Write as 0. [7:7] COMP_VP_SEL Selects positive voltage input [10:8] ENUM VOLTAGE_LADDER_OUTPU Voltage ladder output 0x0 ACMP_I1 ACMP_I1 0x1 ACMP_I2 ACMP_I2 0x2 RESERVED Reserved 0x3 RESERVED Reserved 0x4 RESERVED Reserved 0x5 INTERNAL_REFERENCE_V Internal reference voltage 0x6 RESERVED Reserved 0x7 COMP_VM_SEL Selects negative voltage input [13:11] ENUM VOLTAGE_LADDER_OUTPU voltage ladder output 0x0 ACMP_I1 ACMP_I1 0x1 ACMP_I2 ACMP_I2 0x2 RESERVED Reserved 0x3 RESERVED Reserved 0x4 RESERVED Reserved 0x5 INTERNAL_REFERENCE_V Internal reference voltage 0x6 RESERVED Reserved 0x7 RESERVED Reserved. Write as 0. [19:14] EDGECLR Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0. [20:20] COMPSTAT Comparator status. This bit reflects the state of the comparator output. [21:21] RESERVED Reserved. Write as 0. [22:22] COMPEDGE Comparator edge-detect status. [23:23] RESERVED Reserved. Write as 0. [24:24] HYS Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output. [26:25] ENUM NONE_THE_OUTPUT_WIL None (the output will switch as the voltages cross) 0x0 5_MV 5 mV 0x1 10_MV 10 mV 0x2 20_MV 20 mV 0x3 RESERVED Reserved [31:27] LAD Voltage ladder register 0x004 read-write 0 0xFFFFFFFF LADEN Voltage ladder enable [0:0] LADSEL Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref [5:1] LADREF Selects the reference voltage Vref for the voltage ladder: [6:6] ENUM SUPPLY_PIN_VDD Supply pin VDD 0 VDDCMP_PIN VDDCMP pin 1 RESERVED Unused [31:7] FLASHCTRL Flash controller FLASHCTRL 0x40040000 0x0 0xFFF registers FLASH_IRQ 14 FLASHCFG Flash configuration register 0x010 read-write 0 0x00000000 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. [1:0] ENUM 1_SYSTEM_CLOCK_FLASH 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 0x0 2_SYSTEM_CLOCKS_FLAS 2 system clocks flash access time (for system clock frequencies of up to 30 MHz). 0x1 FLASHTIM_RESERVED_ Reserved. 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. [31:2] FMSSTART Signature start address register 0x020 read-write 0 0xFFFFFFFF START Signature generation start address (corresponds to AHB byte address bits[20:4]). [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] FMSSTOP Signature stop-address register 0x024 read-write 0 0xFFFFFFFF STOPA Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. If the option bistprotection=1, bits 2:0 cannot be written and are forced to 111. [16:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [30:17] STRTBIST When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared. [31:31] FMSW0 Signature Word 0x02C read-only 0 0x00000000 SIG 32-bit signature. [31:0] IOCON I/O configuration (IOCON) IOCON 0x40044000 0x0 0xFFF registers PIO0_17 I/O configuration for pin PIO0_17 0x000 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_13 I/O configuration for pin PIO0_13 0x004 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_12 I/O configuration for pin PIO0_12 0x008 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_5 I/O configuration for pin PIO0_5/RESET 0x00C read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_4 I/O configuration for pin PIO0_4 0x010 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_3 I/O configuration for pin PIO0_3/SWCLK 0x014 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input. [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_2 I/O configuration for pin PIO0_2/SWDIO 0x018 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input. [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_11 I/O configuration for pin PIO0_11. This is the pin configuration for the true open-drain pin. 0x01C read-write 0x00000080 0xFFFFFFFF RESERVED Reserved. [5:0] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] I2CMODE Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. [10:10] S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_10 I/O configuration for pin PIO0_10. This is the pin configuration for the true open-drain pin. 0x020 read-write 0x00000080 0xFFFFFFFF RESERVED Reserved. [5:0] INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [7:7] I2CMODE Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). [9:8] ENUM STANDARD_MODE Standard mode/ Fast-mode I2C. 0x0 STANDARD_IO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. [10:10] S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_16 I/O configuration for pin PIO0_16 0x024 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_15 I/O configuration for pin PIO0_15 0x028 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_1 I/O configuration for pin PIO0_1/ACMP_I1/CLKIN 0x02C read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_9 I/O configuration for pin PIO0_9/XTALOUT 0x034 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_8 I/O configuration for pin PIO0_8/XTALIN 0x038 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_7 I/O configuration for pin PIO0_7 0x03C read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_6 I/O configuration for pin PIO0_6/VDDCMP 0x040 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_0 I/O configuration for pin PIO0_0/ACMP_I0 0x044 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] PIO0_14 I/O configuration for pin PIO0_14 0x048 read-write 0x00000090 0xFFFFFFFF RESERVED Reserved. [2:0] MODE Selects function mode (on-chip pull-up/pull-down resistor control). [4:3] ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled). 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled. 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled. 0x2 REPEATER_MODE_ Repeater mode. 0x3 HYS Hysteresis. [5:5] ENUM DISABLE_ Disable. 0 ENABLE_ Enable. 1 INV Invert input [6:6] ENUM INPUT_NOT_INVERTED_ Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 0 INPUT_INVERTED_HIGH Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 1 RESERVED Reserved. [9:7] OD Open-drain mode. [10:10] ENUM DISABLE_ Disable. 0 OPEN_DRAIN_MODE_ENAB Open-drain mode enabled. This is not a true open-drain mode. 1 S_MODE Digital filter sample mode. [12:11] ENUM BYPASS_INPUT_FILTER_ Bypass input filter. 0x0 1_CLOCK_CYCLE_INPUT 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x1 2_CLOCK_CYCLES_INPU 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x2 3_CLOCK_CYCLES_INPU 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 0x3 CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. [15:13] ENUM IOCONFILTRCLKDIV0_ IOCONFILTRCLKDIV0. 0x0 IOCONFILTRCLKDIV1_ IOCONFILTRCLKDIV1. 0x1 IOCONFILTRCLKDIV2_ IOCONFILTRCLKDIV2. 0x2 IOCONFILTRCLKDIV3_ IOCONFILTRCLKDIV3. 0x3 IOCONFILTRCLKDIV4_ IOCONFILTRCLKDIV4. 0x4 IOCONFILTRCLKDIV5_ IOCONFILTRCLKDIV5. 0x5 IOCONFILTRCLKDIV6_ IOCONFILTRCLKDIV6. 0x6 RESERVED Reserved. [31:16] SYSCON System configuration (SYSCON) SYSCON 0x40048000 0x0 0xFFF registers BOD 13 SYSMEMREMAP System memory remap 0x000 read-write 0x2 0xFFFFFFFF MAP System memory remap. Value 0x3 is reserved. [1:0] ENUM BOOT_LOADER_MODE_IN Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x0 USER_RAM_MODE_INTER User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x1 USER_FLASH_MODE_INT User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x2 RESERVED Reserved [31:2] PRESETCTRL Peripheral reset control 0x004 read-write 0x00001FFF 0xFFFFFFFF SPI0_RST_N SPI0 reset control [0:0] ENUM ASSERT_THE_SPI0_RESE Assert the SPI0 reset. 0 CLEAR_THE_SPI0_RESET Clear the SPI0 reset. 1 SPI1_RST_N SPI1 reset control [1:1] ENUM ASSERT_THE_SPI1_RESE Assert the SPI1 reset. 0 CLEAR_THE_SPI1_RESET Clear the SPI1 reset. 1 UARTFRG_RST_N UART fractional baud rate generator (UARTFRG) reset control [2:2] ENUM ASSERT_THE_UARTFRG_R Assert the UARTFRG reset. 0 CLEAR_THE_UARTFRG_RE Clear the UARTFRG reset. 1 USART0_RST_N USART0 reset control [3:3] ENUM ASSERT_THE_USART0_RE Assert the USART0 reset. 0 CLEAR_THE_USART0_RES Clear the USART0 reset. 1 UART1_RST_N U1ART1 reset control [4:4] ENUM ASSERT_THE_UART_RESE Assert the UART reset. 0 CLEAR_THE_UART1_RESE Clear the UART1 reset. 1 UART2_RST_N UART2 reset control [5:5] ENUM ASSERT_THE_UART2_RES Assert the UART2 reset. 0 CLEAR_THE_UART2_RESE Clear the UART2 reset. 1 I2C_RST_N I2C reset control [6:6] ENUM ASSERT_THE_I2C_RESET Assert the I2C reset. 0 CLEAR_THE_I2C_RESET_ Clear the I2C reset. 1 MRT_RST_N Multi-rate timer (MRT) reset control [7:7] ENUM ASSERT_THE_MRT_RESET Assert the MRT reset. 0 CLEAR_THE_MRT_RESET_ Clear the MRT reset. 1 SCT_RST_N SCT reset control [8:8] ENUM ASSERT_THE_SCT_RESET Assert the SCT reset. 0 CLEAR_THE_SCT_RESET_ Clear the SCT reset. 1 WKT_RST_N Self wake-up timer (WKT) reset control [9:9] ENUM ASSERT_THE_WKT_RESET Assert the WKT reset. 0 CLEAR_THE_WKT_RESET_ Clear the WKT reset. 1 GPIO_RST_N GPIO and GPIO pin interrupt reset control [10:10] ENUM ASSERT_THE_GPIO_RESE Assert the GPIO reset. 0 CLEAR_THE_GPIO_RESET Clear the GPIO reset. 1 FLASH_RST_N Flash controller reset control [11:11] ENUM ASSERT_THE_FLASH_CON Assert the flash controller reset. 0 CLEAR_THE_FLASH_CONT Clear the flash controller reset. 1 ACMP_RST_N Analog comparator reset control [12:12] ENUM ASSERT_THE_ANALOG_CO Assert the analog comparator reset. 0 CLEAR_THE_ANALOG_COM Clear the analog comparator controller reset. 1 RESERVED Reserved [31:12] SYSPLLCTRL System PLL control 0x008 read-write 0 0xFFFFFFFF MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 [4:0] PSEL Post divider ratio P. The division ratio is 2 x P. [6:5] ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. [31:7] SYSPLLSTAT System PLL status 0x00C read-only 0 0xFFFFFFFF LOCK PLL lock status [0:0] ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved [31:1] SYSOSCCTRL System oscillator control 0x020 read-write 0x000 0xFFFFFFFF BYPASS Bypass system oscillator [0:0] ENUM DISABLED_OSCILLATOR Disabled. Oscillator is not bypassed. 0 ENABLED_PLL_INPUT_ Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. 1 FREQRANGE Determines frequency range for Low-power oscillator. [1:1] ENUM 1_20_MHZ_FREQUENCY 1 - 20 MHz frequency range. 0 15_25_MHZ_FREQUENC 15 - 25 MHz frequency range 1 RESERVED Reserved [31:2] WDTOSCCTRL Watchdog oscillator control 0x024 read-write 0x0A0 0xFFFFFFFF DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 [4:0] FREQSEL Select watchdog oscillator analog output frequency (Fclkana). [8:5] ENUM 0_6_MHZ 0.6 MHz 0x1 1_05_MHZ 1.05 MHz 0x2 1_4_MHZ 1.4 MHz 0x3 1_75_MHZ 1.75 MHz 0x4 2_1_MHZ 2.1 MHz 0x5 2_4_MHZ 2.4 MHz 0x6 2_7_MHZ 2.7 MHz 0x7 3_0_MHZ 3.0 MHz 0x8 3_25_MHZ 3.25 MHz 0x9 3_5_MHZ 3.5 MHz 0xA 3_75_MHZ 3.75 MHz 0xB 4_0_MHZ 4.0 MHz 0xC 4_2_MHZ 4.2 MHz 0xD 4_4_MHZ 4.4 MHz 0xE 4_6_MHZ 4.6 MHz 0xF RESERVED Reserved [31:9] SYSRSTSTAT System reset status register 0x030 read-write 0 0xFFFFFFFF POR POR reset status [0:0] ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED_WRITIN POR detected. Writing a one clears this reset. 1 EXTRST Status of the external RESET pin. External reset status. [1:1] ENUM NO_RESET_EVENT_DETEC No reset event detected. 0 RESET_DETECTED_WRIT Reset detected. Writing a one clears this reset. 1 WDT Status of the Watchdog reset [2:2] ENUM NO_WDT_RESET_DETECTE No WDT reset detected 0 WDT_RESET_DETECTED_ WDT reset detected. Writing a one clears this reset. 1 BOD Status of the Brown-out detect reset [3:3] ENUM NO_BOD_RESET_DETECTE No BOD reset detected 0 BOD_RESET_DETECTED_ BOD reset detected. Writing a one clears this reset. 1 SYSRST Status of the software system reset [4:4] ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected. Writing a one clears this reset. 1 RESERVED Reserved [31:5] SYSPLLCLKSEL System PLL clock source select 0x040 read-write 0 0xFFFFFFFF SEL System PLL clock source [1:0] ENUM IRC IRC 0x0 CRYSTAL_OSCILLATOR_ Crystal Oscillator (SYSOSC) 0x1 RESERVED_ Reserved. 0x2 CLKIN_EXTERNAL_CLOC CLKIN. External clock input. 0x3 RESERVED Reserved [31:2] SYSPLLCLKUEN System PLL clock source update enable 0x044 read-write 0 0xFFFFFFFF ENA Enable system PLL clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] MAINCLKSEL Main clock source select 0x070 read-write 0 0xFFFFFFFF SEL Clock source for main clock [1:0] ENUM IRC_OSCILLATOR IRC Oscillator 0x0 PLL_INPUT PLL input 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 PLL_OUTPUT PLL output 0x3 RESERVED Reserved [31:2] MAINCLKUEN Main clock source update enable 0x074 read-write 0 0xFFFFFFFF ENA Enable main clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] SYSAHBCLKDIV System clock divider 0x078 read-write 0 0x00000000 DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] SYSAHBCLKCTRL System clock control 0x080 read-write 0x1F 0xFFFFFFFF SYS Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1. [0:0] ENUM RESERVED Reserved 0 ENABLE Enable 1 ROM Enables clock for ROM. [1:1] ENUM DISABLE Disable 0 ENABLE Enable 1 RAM Enables clock for SRAM. [2:2] ENUM DISABLE Disable 0 ENABLE Enable 1 FLASHREG Enables clock for flash register interface. [3:3] ENUM DISABLE Disable 0 ENABLE Enable 1 FLASH Enables clock for flash. [4:4] ENUM DISABLE Disable 0 ENABLE Enable 1 I2C Enables clock for I2C. [5:5] ENUM DISABLE Disable 0 ENABLE Enable 1 GPIO Enables clock for GPIO port registers and GPIO pin interrupt registers. [6:6] ENUM DISABLE Disable 0 ENABLE Enable 1 SWM Enables clock for switch matrix. [7:7] ENUM DISABLE Disable 0 ENABLE Enable 1 SCT Enables clock for state configurable timer. [8:8] ENUM DISABLE Disable 0 ENABLE Enable 1 WKT Enables clock for self wake-up timer. [9:9] ENUM DISABLE Disable 0 ENABLE Enable 1 MRT Enables clock for multi-rate timer. [10:10] ENUM DISABLE Disable 0 ENABLE Enable 1 SPI0 Enables clock for SPI0. [11:11] ENUM DISABLE Disable 0 ENABLE Enable 1 SPI1 Enables clock for SPI1. [12:12] ENUM DISABLE Disable 0 ENABLE Enable 1 CRC Enables clock for CRC. [13:13] ENUM DISABLE Disable 0 ENABLE Enable 1 UART0 Enables clock for UART0. [14:14] ENUM DISABLE Disable 0 ENABLE Enable 1 UART1 Enables clock for UART1. [15:15] ENUM DISABLE Disable 0 ENABLE Enable 1 UART2 Enables clock for UART2. [16:16] ENUM DISABLE Disable 0 ENABLE Enable 1 WWDT Enables clock for WWDT. [17:17] ENUM DISABLE Disable 0 ENABLE Enable 1 IOCON Enables clock for IOCON block. [18:18] ENUM DISABLE Disable 0 ENABLE Enable 1 ACMP Enables clock to analog comparator. [19:19] ENUM DISABLE Disable 0 ENABLE Enable 1 RESERVED Reserved [31:20] UARTCLKDIV UART clock divider 0x094 read-write 0 0xFFFFFFFF DIV UART clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] CLKOUTSEL CLKOUT clock source select 0x0E0 read-write 0 0xFFFFFFFF SEL CLKOUT clock source [1:0] ENUM IRC_OSCILLATOR IRC oscillator 0x0 CRYSTAL_OSCILLATOR_ Crystal oscillator (SYSOSC) 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 MAIN_CLOCK Main clock 0x3 RESERVED Reserved [31:2] CLKOUTUEN CLKOUT clock source update enable 0x0E4 read-write 0 0xFFFFFFFF ENA Enable CLKOUT clock source update [0:0] ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved [31:1] CLKOUTDIV CLKOUT clock divider 0x0E8 read-write 0 0xFFFFFFFF DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] UARTFRGDIV UART fractional generator divider value 0x0F0 read-write 0 0xFFFFFFFF DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. [7:0] RESERVED Reserved [31:8] UARTFRGMULT UART fractional generator multiplier value 0x0F4 read-write 0 0xFFFFFFFF MULT Numerator of the fractional divider. MULT is equal to the programmed value. [7:0] RESERVED Reserved [31:8] EXTTRACECMD External trace buffer command register 0x0FC read-write 0 0xFFFFFFFF START Trace start command [0:0] STOP Trace stop command [1:1] RESERVED Reserved [31:2] PIOPORCAP0 POR captured PIO status 0 0x100 read-only 0 0x00000000 PIOSTAT State of PIO0_17 through PIO0_0 at power-on reset [17:0] RESERVED Reserved. [31:18] IOCONCLKDIV6 Peripheral clock 6 to the IOCON block for programmable glitch filter 0x134 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV5 Peripheral clock 5 to the IOCON block for programmable glitch filter 0x138 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV4 Peripheral clock 4 to the IOCON block for programmable glitch filter 0x13C read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV3 Peripheral clock 3 to the IOCON block for programmable glitch filter 0x140 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV2 Peripheral clock 2 to the IOCON block for programmable glitch filter 0x144 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV1 Peripheral clock 1 to the IOCON block for programmable glitch filter 0x148 read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] IOCONCLKDIV0 Peripheral clock 0 to the IOCON block for programmable glitch filter 0x14C read-write 0x00000000 0xFFFFFFFF DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. [7:0] RESERVED Reserved [31:8] BODCTRL Brown-Out Detect 0x150 read-write 0 0xFFFFFFFF BODRSTLEV BOD reset level [1:0] ENUM LEVEL_0_THE_RESET_A Level 0: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is . 0x0 LEVEL_1_THE_RESET_A Level 1: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is . 0x1 LEVEL_2_THE_RESET_A Level 2: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is . 0x2 LEVEL_3_THE_RESET_A Level 3: The reset assertion threshold voltage is ; the reset de-assertion threshold voltage is. 0x3 BODINTVAL BOD interrupt level [3:2] ENUM LEVEL_0_THE_INTERRU Level 0: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is 0x0 LEVEL_1THE_INTERRUP Level 1:The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is . 0x1 LEVEL_2_THE_INTERRU Level 2: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is . 0x2 LEVEL_3_THE_INTERRU Level 3: The interrupt assertion threshold voltage is ; the interrupt de-assertion threshold voltage is . 0x3 BODRSTENA BOD reset enable [4:4] ENUM DISABLE_RESET_FUNCTI Disable reset function. 0 ENABLE_RESET_FUNCTIO Enable reset function. 1 RESERVED Reserved [31:5] SYSTCKCAL System tick counter calibration 0x154 read-write 0x0 0xFFFFFFFF CAL System tick timer calibration value [25:0] RESERVED Reserved [31:26] IRQLATENCY IQR delay. Allows trade-off between interrupt latency and determinism. 0x170 read-write 0x00000010 0xFFFFFFFF LATENCY 8-bit latency value [7:0] RESERVED Reserved [31:8] NMISRC NMI Source Control 0x174 read-write 0 0xFFFFFFFF IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 58 for the list of interrupt sources and their IRQ numbers. [4:0] RESERVED Reserved [30:5] NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. [31:31] 8 0x4 0-7 PINTSEL%s GPIO Pin Interrupt Select register 0 0x178 read-write 0 0xFFFFFFFF INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17). [5:0] RESERVED Reserved [31:6] STARTERP0 Start logic 0 pin wake-up enable register 0x204 read-write 0 0xFFFFFFFF PINT0 GPIO pin interrupt 0 wake-up [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT1 GPIO pin interrupt 1 wake-up [1:1] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT2 GPIO pin interrupt 2 wake-up [2:2] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT3 GPIO pin interrupt 3 wake-up [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT4 GPIO pin interrupt 4 wake-up [4:4] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT5 GPIO pin interrupt 5 wake-up [5:5] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT6 GPIO pin interrupt 6 wake-up [6:6] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PINT7 GPIO pin interrupt 7 wake-up [7:7] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [31:8] STARTERP1 Start logic 1 interrupt wake-up enable register 0x214 read-write 0 0xFFFFFFFF RESERVED Reserved [11:0] WWDT WWDT interrupt wake-up [12:12] ENUM DISABLED Disabled 0 ENABLED Enabled 1 BOD BOD interrupt wake-up [13:13] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [14:14] WKT Self wake-up timer interrupt wake-up [15:15] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PDSLEEPCFG Power-down states in deep-sleep mode 0x230 read-write 0xFFFF 0xFFFFFFFF BOD_PD BOD power-down control for Deep-sleep and Power-down mode [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [15:7] RESERVED Reserved [31:7] PDAWAKECFG Power-down states for wake-up from deep-sleep 0x234 read-write 0xEDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output wake-up configuration [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down wake-up configuration [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash wake-up configuration [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD wake-up configuration [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. [4:4] SYSOSC_PD Crystal oscillator wake-up configuration [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL wake-up configuration [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write these bits as 0b1101 [11:8] RESERVED Reserved. Always write these bits as 0b110 [14:12] ACMP Analog comparator wake-up configuration [15:15] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [31:16] PDRUNCFG Power configuration register 0x238 read-write 0xEDF0 0xFFFFFFFF IRCOUT_PD IRC oscillator output power [0:0] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power down [1:1] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FLASH_PD Flash power down [2:2] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD power down [3:3] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. [4:4] SYSOSC_PD Crystal oscillator power down [5:5] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power down. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. [6:6] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL power down [7:7] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved. Always write these bits as 0b1101 [11:8] RESERVED Reserved. Always write these bits as 0b110 [14:12] ACMP Analog comparator power down [15:15] ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved [31:16] DEVICE_ID Device ID 0x3F4 read-only 0 0x00000000 DEVICEID TBD [31:0] I2C I2C-bus interface I2C 0x40050000 0x0 0xFFF registers I2C 8 CFG Configuration for shared functions. 0x00 read-write 0 0xFFFFFFFF MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. [0:0] ENUM DISABLED_THE_I2C_MA Disabled. The I2C Master function is disabled. 0 ENABLED_THE_I2C_MAS Enabled. The I2C Master function is enabled. 1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. [1:1] ENUM DISABLED_THE_I2C_SL Disabled. The I2C slave function is disabled. 0 ENABLED_THE_I2C_SLA Enabled. The I2C slave function is enabled. 1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. [2:2] ENUM DISABLED_THE_I2C_MO Disabled. The I2C monitor function is disabled. 0 ENABLED_THE_I2C_MON Enabled. The I2C monitor function is enabled. 1 TIMEOUTEN I2C bus Time-out Enable. When disabled, timeout flags will be automatically cleared. [3:3] ENUM DISABLED_TIME_OUT_F Disabled. Time-out function is disabled. 0 ENABLED_TIME_OUT_FU Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one timeout will be used in a system. 1 MONCLKSTR Monitor function Clock Stretching. [4:4] ENUM DISABLED_THE_MONITO Disabled. The monitor function will not perform clock stretching. Software may not always be able to read data provided by the monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. 0 ENABLED_THE_MONITOR Enabled. The monitor function will perform clock stretching in order to ensure that software can read all incoming data supplied by the monitor function. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:5] STAT Status register for Master, Slave, and Monitor functions. 0x04 read-write 0x000801 0xFFFFFFFF MSTPENDING Master Pending. Indicates whether the Master function needs software service. This flag will cause an interrupt when set if enabled via the INTENSET register. The MSTPENDING flag is automatically cleared when a 1 is written to the MSTCONTINUE bit in the MSTCTL register. [0:0] ENUM NO_SERVICE_NEEDED_T No service needed. The Master function does not currently need service. 0 SERVICE_NEEDED_THE_ Service needed. The Master function needs service. Information on what is needed can be found in the adjacent MSTSTATE field. 1 MSTSTATE Master State code. Each value of this field indicates a specific required service for the Master function. All other values are reserved. [3:1] ENUM IDLE_THE_MASTER_FUN Idle. The Master function is available to be used for a new transaction. 0x0 RECEIVE_READY_RECEI Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x1 TRANSMIT_READY_DATA Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x2 ADDRESS_SLAVE_NACKE Address. Slave Nacked address. 0x3 DATA_SLAVE_NACKED_T Data. Slave Nacked transmitted data. 0x4 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. [4:4] ENUM NO_LOSS_NO_ARBITRAT No loss. No Arbitration Loss has occurred. 0 ARBITRATION_LOSS_TH Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MstContinue. [6:6] ENUM NO_STARTSTOP_ERROR_ No Start/Stop Error has occurred. 0 STARTSTOP_ERROR_HAS Start/stop error has occurred. The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDING Slave Pending. Indicates whether the Slave function needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. [8:8] ENUM NO_SERVICE_NEEDED_T No service needed. The Slave function does not currently need service. 0 SERVICE_NEEDED_THE_ Service needed. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. [10:9] ENUM RECEIVED_ADDRESS_PL Received. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 0x0 DATA_AVAILABLE_RECE Data available. Received data is available (Slave Receiver mode). 0x1 DATA_READY_FOR_TRANS Data ready for transmit. Data can be transmitted (Slave Transmitter mode). 0x2 RESERVED_ Reserved. 0x3 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. [11:11] ENUM STRETCHING_THE_SLAV Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 0 NOT_STRETCHING_THE_ Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. 1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. [13:12] ENUM SLAVE_ADDRESS_0_WAS_ Slave address 0 was matched. 0x0 SLAVE_ADDRESS_1_WAS_ Slave address 1 was matched. 0x1 SLAVE_ADDRESS_2_WAS_ Slave address 2 was matched. 0x2 SLAVE_ADDRESS_3_WAS_ Slave address 3 was matched. 0x3 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to Nack a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software Nacks data. [14:14] ENUM NOT_SELECTED_THE_SL Not selected. The Slave function is not currently selected. 0 SELECTED_THE_SLAVE_ Selected. The Slave function is currently selected. 1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. [15:15] ENUM NOT_DESELECTED_THE_ Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. 0 DESELECTED_THE_SLAV Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. [16:16] ENUM NO_DATA_THE_MONITOR No data. The Monitor function does not currently have data available. 0 DATA_WAITING_THE_MO Data waiting. The Monitor function has data waiting to be read. 1 MONOV Monitor Overflow flag. [17:17] ENUM NO_OVERRUN_MONITOR_ No overrun. Monitor data has not overrun. 0 OVERRUN_A_MONITOR_D Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 1 MONACTIVE Monitor Active flag. This flag indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. [18:18] ENUM INACTIVE_THE_MONITO Inactive. The Monitor function considers the I2C bus to be inactive. 0 ACTIVE_THE_MONITOR_ Active. The Monitor function considers the I2C bus to be active. 1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register . The flag can be cleared by writing a 1 to this bit. [19:19] ENUM NOT_IDLE_THE_I2C_BU Not idle. The I2C bus is not idle, or this flag has been cleared by software. 0 IDLE_THE_I2C_BUS_HA Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The case of SCL remaining low longer than TIMEOUT is not reported by this flag, it is reported in by the SCL Time-out flag. The flag is cleared by writing a 1 to this bit. [24:24] ENUM NO_TIME_OUT_I2C_BUS No time-out. I2C bus events have not caused a timeout. 0 EVENT_TIME_OUT_THE_ Event time-out. The time between I2C bus events has been longer than the time specified by the I2C Timeout register. 1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. [25:25] ENUM NO_TIME_OUT_SCL_LOW No time-out. SCL low time has not caused a timeout. 0 TIME_OUT_SCL_LOW_TI Time-out. SCL low time has caused a timeout. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] INTENSET Interrupt Enable Set and read register. 0x08 read-write 0 0xFFFFFFFF MSTPENDINGEN Master Pending interrupt Enable. [0:0] ENUM DISABLED The MstPending interrupt is disabled. 0 ENABLED The MstPending interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [3:1] MSTARBLOSSEN Master Arbitration Loss interrupt Enable. [4:4] ENUM DISABLED The MstArbLoss interrupt is disabled. 0 THE_MSTARBLOSS_INTER The MstArbLoss interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERREN Master Start/Stop Error interrupt Enable. [6:6] ENUM DISABLED The MstStStpErr interrupt is disabled. 0 THE_MSTSTSTPERR_INTE The MstStStpErr interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDINGEN Slave Pending interrupt Enable. [8:8] ENUM DISABLED The SlvPending interrupt is disabled. 0 THE_SLVPENDING_INTER The SlvPending interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] SLVNOTSTREN Slave Not Stretching interrupt Enable. [11:11] ENUM DISABLED The SlvNotStr interrupt is disabled. 0 THE_SLVNOTSTR_INTERR The SlvNotStr interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [14:12] SLVDESELEN Slave Deselect interrupt Enable. [15:15] ENUM DISABLED The SlvDeSel interrupt is disabled. 0 THE_SLVDESEL_INTERRU The SlvDeSel interrupt is enabled. 1 MONRDYEN Monitor data Ready interrupt Enable. [16:16] ENUM DISABLED The MonRdy interrupt is disabled. 0 THE_MONRDY_INTERRUPT The MonRdy interrupt is enabled. 1 MONOVEN Monitor Overrun interrupt Enable. [17:17] ENUM DISABLED The MonOv interrupt is disabled. 0 THE_MONOV_INTERRUPT_ The MonOv interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [18:18] MONIDLEEN Monitor Idle interrupt Enable. [19:19] ENUM DISABLED The MonIdle interrupt is disabled. 0 THE_MONIDLE_INTERRUP The MonIdle interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUTEN Event Timeout interrupt Enable. [24:24] ENUM DISABLED The Event Timeout interrupt is disabled. 0 THE_EVENT_TIMEOUT_IN The Event Timeout interrupt is enabled. 1 SCLTIMEOUTEN SCL Timeout interrupt Enable. [25:25] ENUM DISABLED The SCL Timeout interrupt is disabled. 0 THE_SCL_TIMEOUT_INTE The SCL Timeout interrupt is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] INTENCLR Interrupt Enable Clear register. 0x0C write-only 0 0x00000000 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [3:1] MSTARBLOSSCLR Master Arbitration Loss interrupt clear. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDINGCLR Slave Pending interrupt clear. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] SLVNOTSTRCLR Slave Not Stretching interrupt clear. [11:11] RESERVED Reserved. Read value is undefined, only zero should be written. [14:12] SLVDESELCLR Slave Deselect interrupt clear. [15:15] MONRDYCLR Monitor data Ready interrupt clear. [16:16] MONOVCLR Monitor Overrun interrupt clear. [17:17] RESERVED Reserved. Read value is undefined, only zero should be written. [18:18] MONIDLECLR Monitor Idle interrupt clear. [19:19] RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUTCLR Event Timeout interrupt clear. [24:24] SCLTIMEOUTCLR SCL Timeout interrupt clear. [25:25] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] TIMEOUT Time-out value register. 0x10 read-write 0xFFFF 0xFFFFFFFF TOMIN Timeout time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum timeout of 16 I2C function clocks and also a timeout resolution of 16 I2C function clocks. [3:0] TO Timeout time value. Specifies the timeout interval value in increments of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A timeout will occur after 65,536 counts of the I2C function clock. [15:4] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] DIV Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME and SLVTIME registers. 0x14 read-write 0 0xFFFFFFFF DIVVAL This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C function. 0x0001 = PCLK is divided by 2 before use by the I 2C function. 0x0002 = PCLK is divided by 3 before use by the I 2C function. ... 0xFFFF = PCLK is divided by 65,536 before use by the I2C function. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x18 read-only 0 0xFFFFFFFF MSTPENDING Master Pending. [0:0] RESERVED Reserved. [3:1] MSTARBLOSS Master Arbitration Loss flag. [4:4] RESERVED Reserved. Read value is undefined, only zero should be written. [5:5] MSTSTSTPERR Master Start/Stop Error flag. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] SLVPENDING Slave Pending. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] SLVNOTSTR Slave Not Stretching status. [11:11] RESERVED Reserved. Read value is undefined, only zero should be written. [14:12] SLVDESEL Slave Deselected flag. [15:15] MONRDY Monitor Ready. [16:16] MONOV Monitor Overflow flag. [17:17] RESERVED Reserved. Read value is undefined, only zero should be written. [18:18] MONIDLE Monitor Idle flag. [19:19] RESERVED Reserved. Read value is undefined, only zero should be written. [23:20] EVENTTIMEOUT Event Timeout Interrupt flag. [24:24] SCLTIMEOUT SCL Timeout Interrupt flag. [25:25] RESERVED Reserved. Read value is undefined, only zero should be written. [31:26] MSTCTL Master control register. 0x20 read-write 0 0xFFFFFFFF MSTCONTINUE Master Continue. This bit is write-only. [0:0] ENUM NO_EFFECT_ No effect. 0 CONTINUE_INFORMS_TH Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 1 MSTSTART Master Start control. This bit is write-only. [1:1] ENUM NO_EFFECT_ No effect. 0 START_A_START_WILL_ Start. A Start will be generated on the I2C bus at the next allowed time. 1 MSTSTOP Master Stop control. This bit is write-only. [2:2] ENUM NO_EFFECT_ No effect. 0 STOP_A_STOP_WILL_BE Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a Nack to the slave if the master is receiving data from the slave (Master Receiver mode). 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] MSTTIME Master timing configuration. 0x24 read-write 0x77 0xFFFFFFFF MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. [2:0] ENUM 2_CLOCKS_MINIMUM_SC 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 0x0 3_CLOCKS_MINIMUM_SC 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 0x1 4_CLOCKS_MINIMUM_SC 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 0x2 5_CLOCKS_MINIMUM_SC 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 0x3 6_CLOCKS_MINIMUM_SC 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 0x4 7_CLOCKS_MINIMUM_SC 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 0x5 8_CLOCKS_MINIMUM_SC 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 0x6 9_CLOCKS_MINIMUM_SC 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 0x7 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. [6:4] ENUM 2_CLOCKS_MINIMUM_SC 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 0x0 3_CLOCKS_MINIMUM_SC 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 0x1 4_CLOCKS_MINIMUM_SC 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 0x2 5_CLOCKS_MINIMUM_SC 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 0x3 6_CLOCKS_MINIMUM_SC 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 0x4 7_CLOCKS_MINIMUM_SC 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 0x5 8_CLOCKS_MINIMUM_SC 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 0x6 9_CLOCKS_MINIMUM_SC 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 0x7 RESERVED Reserved. Read value is undefined, only zero should be written. [31:7] MSTDAT Combined Master receiver and transmitter data register. 0x28 read-write 0 0x00000000 modify DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] SLVCTL Slave control register. 0x40 read-write 0 0xFFFFFFFF SlvContinue Slave Continue. [0:0] ENUM NO_EFFECT_ No effect. 0 CONTINUE_INFORMS_TH Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 1 SlvNack Slave Nack. [1:1] ENUM NO_EFFECT_ No effect. 0 NACK_CAUSES_THE_SLA Nack. Causes the Slave function to Nack the master when the slave is receiving data from the master (Slave Receiver mode). 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] SLVDAT Combined Slave receiver and transmitter data register. 0x44 read-write 0 0x00000000 modify DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. [7:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] 4 0x4 0-3 SLVADR%s Slave address 0. 0x48 read-write 0x01 0xFFFFFFFF SADISABLE Slave Address n Disable. [0:0] ENUM ENABLED_SLAVE_ADDRE Enabled. Slave Address n is enabled and will be recognized with any changes specified by the SLVQUAL0 register. 0 IGNORED_SLAVE_ADDRES Ignored Slave Address n is ignored. 1 SLVADR Seven bit slave address that is compared to received addresses if enabled. [7:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] SLVQUAL0 Slave Qualification for address 0. 0x58 read-write 0 0xFFFFFFFF QUALMODE0 Reserved. Read value is undefined, only zero should be written. [0:0] ENUM MASK The SLVQUAL0 field is used as a logical mask for matching address 0. 0 THE_SLVQUAL0_FIELD_I The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] less or equal than received address less or equal than SLVQUAL0[7:1]). [7:1] RESERVED Reserved. Read value is undefined, only zero should be written. [31:8] MONRXDAT Monitor receiver data register. 0x80 read-only 0 0xFFFFFFFF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins, and adds indication of Start, Repeated Start, and data Nack. [7:0] MONSTART Monitor Received Start. [8:8] ENUM NO_DETECT_THE_MONIT No detect. The monitor function has not detected a Start event on the I2C bus. 0 START_DETECT_THE_MO Start detect. The monitor function has detected a Start event on the I2C bus. 1 MONRESTART Monitor Received Repeated Start. [9:9] ENUM NO_START_DETECT_THE No start detect. The monitor function has not detected a Repeated Start event on the I2C bus. 0 REPEATED_START_DETEC Repeated start detect. The monitor function has detected a Repeated Start event on the I 2C bus. 1 MONNACK Monitor Received Nack. [10:10] ENUM ACKNOWLEDGED_THE_DA Acknowledged. The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver. 0 NOT_ACKNOWLEDGED_TH Not acknowledged. The data currently being provided by the monitor function was not acknowledged by any receiver. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:11] SPI0 SPI SPI 0x40058000 0x0 0xFFF registers SPI0 0 CFG SPI Configuration register 0x000 read-write 0 0xFFFFFFFF Enable SPI enable. [0:0] ENUM DISABLED_THE_SPI_IS Disabled. The SPI is disabled and the internal state machine and counters are reset. 0 ENABLED_THE_SPI_IS_ Enabled. The SPI is enabled for operation. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] Master Master mode select. [2:2] ENUM SLAVE_MODE_THE_SPI_ Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 0 MASTER_MODE_THE_SPI Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 1 LSBF LSB First mode enable. [3:3] ENUM STANDARD_DATA_IS_TR Standard. Data is transmitted and received in standard MSB first order. 0 REVERSE_DATA_IS_TRA Reverse. Data is transmitted and received in reverse order (LSB first). 1 CPHA Clock Phase select. . [4:4] ENUM CHANGE_THE_SPI_CAPT Change. The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge. 0 CAPTURE_THE_SPI_CHA Capture. The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge. 1 CPOL Clock Polarity select. [5:5] ENUM LOW_THE_REST_STATE_ Low. The rest state of the clock (between frames) is low. 0 HIGH_THE_REST_STATE High. The rest state of the clock (between frames) is high. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [6:6] Loop Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. [7:7] ENUM DISABLED_ Disabled. 0 ENABLED_ Enabled. 1 SPOL SSEL Polarity select. [8:8] ENUM LOW_THE_SSEL_PIN_IS Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is not inverted relative to the pins. 0 HIGH_THE_SSEL_PIN_I High. The SSEL pin is active high. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] DLY SPI Delay register 0x004 read-write 0 0xFFFFFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data frame. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. [3:0] POST_DELAY Controls the amount of time between the end of a data frame and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. [7:4] FRAME_DELAY Controls the minimum amount of time between adjacent data frames. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. [11:8] TRANSFER_DELAY Controls the minimum amount of time that the SSELs are deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. [15:12] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position 0x008 read-write 0x0102 0xFFFFFFFF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register. [0:0] TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. [1:1] RXOV Receiver Overrun interrupt flag. This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set. [2:2] TXUR Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TxUr flag is set. Data transmitted by the SPI should be considered undefined if TxUr is set. [3:3] SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. [4:4] SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. [5:5] STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. [6:6] ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes Idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted. [7:7] IDLE Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:9] INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x00C read-write 0 0xFFFFFFFF RXRDYEN Determines whether an interrupt occurs when receiver data is available. [0:0] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when receiver data is available. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when receiver data is available in the RXDAT register. 1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is available. [1:1] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when the transmitter holding register is available. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when data may be written to TXDAT. 1 RXOVEN Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur. [2:2] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when a receiver overrun occurs. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated if a receiver overrun occurs. 1 TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. [3:3] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when the transmitter underruns. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated if the transmitter underruns. 1 SSAEN Determines whether an interrupt occurs when one or more Slave Select is asserted. [4:4] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 1 SSDEN Determines whether an interrupt occurs when all Slave Selects are deasserted. [5:5] ENUM NO_INTERRUPT_WILL_BE No interrupt will be generated when all asserted Slave Selects transition to deasserted. 0 AN_INTERRUPT_WILL_BE An interrupt will be generated when all asserted Slave Selects transition to deasserted. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x010 write-only 0 0x00000000 RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. [0:0] TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. [1:1] RXOVEN Writing 1 clears the corresponding bits in the INTENSET register. [2:2] TXUREN Writing 1 clears the corresponding bits in the INTENSET register. [3:3] SSAEN Writing 1 clears the corresponding bits in the INTENSET register. [4:4] SSDEN Writing 1 clears the corresponding bits in the INTENSET register. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] RXDAT SPI Receive Data 0x014 read-only 0 0x00000000 modify RXDAT Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the FLen setting in TXCTL / TXDATCTL. [15:0] RXSSELN Slave Select for receive. This field allows the state of the SSEL pin to be saved along with received data. The value will reflect the SSEL pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. [16:16] RESERVED Reserved. [19:17] SOT Start of Transfer flag. This flag will be 1 if this is the first frame after SSEL went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the frame length is greater than 16 bit. [20:20] RESERVED Reserved, the value read from a reserved bit is not defined. [31:21] TXDATCTL SPI Transmit Data with Control 0x018 read-write 0 0xFFFFFFFF TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. [15:0] TXSSELN Transmit Slave Select . This field controls what is output for SSEL in master mode. The active state of the SSEL function is configured by bits in the CFG register. [16:16] ENUM SSEL_ASSERTED_ SSEL asserted. 0 SSEL_NOT_ASSERTED_ SSEL not asserted. 1 RESERVED Reserved. [19:17] EOT End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. [20:20] ENUM SSEL_NOT_DEASSERTED_ SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 0 SSEL_DEASSERTED_THI SSEL deasserted. This piece of data is treated as the end of a transfer. SSELs will be deasserted at the end of this piece of data. 1 EOF End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. [21:21] ENUM DATA_NOT_EOF_THIS_P Data not EOF. This piece of data transmitted is not treated as the end of a frame. 0 DATA_EOF_THIS_PIECE Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. 1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process. [22:22] ENUM READ_RECEIVED_DATA_ Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. 0 IGNORE_RECEIVED_DATA Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [23:23] FLEN Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by multiple sequential frames Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 1 bit in length. 0x2 = Data frame is 3 bits in length. ... 0xF = Data frame is 16 bits in length. [27:24] RESERVED Reserved. Read value is undefined, only zero should be written. [31:28] TXDAT SPI Transmit Data 0x01C read-write 0 0xFFFFFFFF DATA Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. [15:0] RESERVED Reserved. Only zero should be written. [31:16] TXCTL SPI Transmit Control 0x020 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [15:0] TX_SSEL Transmit Slave Select. [16:16] RESERVED Reserved. [19:17] EOT End of Transfer. [20:20] EOF End of Frame. [21:21] RXIGNORE Receive Ignore. [22:22] RESERVED Reserved. Read value is undefined, only zero should be written. [23:23] FLEN Frame Length. [27:24] RESERVED Reserved. Read value is undefined, only zero should be written. [31:28] DIV SPI clock Divider 0x024 read-write 0 0xFFFFFFFF DIVVAL Rate divider value -1. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, etc. the maximum possible divide is for the value 0xFFFF, which results in PCLK/65536. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT SPI Interrupt Status 0x028 read-only 0x02 0xFFFFFFFF RXRDY Receiver Ready flag. [0:0] TXRDY Transmitter Ready flag. [1:1] RXOV Receiver Overrun interrupt flag. [2:2] TXUR Transmitter Underrun interrupt flag. [3:3] SSA Slave Select Assert. [4:4] SSD Slave Select Deassert. [5:5] RESERVED Reserved. Read value is undefined, only zero should be written. [31:6] SPI1 0x4005C000 0 0xFFF registers SPI1 1 USART0 USART USART 0x40064000 0x0 0xFFF registers UART0 3 CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0x000 read-write 0 0xFFFFFFFF ENABLE USART Enable. [0:0] ENUM DISABLED_THE_USART_ Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt if enabled because the transmitter has been reset and is therefore available. 0 ENABLED_THE_USART_I Enabled. The USART is enabled for operation. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] DATALEN Selects the data size for the USART. [3:2] ENUM 7_BIT_DATA_LENGTH_ 7 bit Data length. 0x0 8_BIT_DATA_LENGTH_ 8 bit Data length. 0x1 9_BIT_DATA_LENGTH_T 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTRL register. 0x2 RESERVED_ Reserved. 0x3 PARITYSEL Selects what type of parity is used by the USART. [5:4] ENUM NO_PARITY_ No parity. 0x0 RESERVED_ Reserved. 0x1 EVEN_PARITY_ADDS_A_ Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x2 ODD_PARITY_ADDS_A_B Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. 0x3 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. [6:6] ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_THIS_SE 2 stop bits. This setting should only be used for asynchronous communication. 1 RESERVED Reserved. Only write 0 to this bit. [7:7] RESERVED Reserved. Read value is undefined, only zero should be written. [8:8] CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. See Section 16.7.3 for more information. [9:9] ENUM NO_FLOW_CONTROL_THE No flow control. The transmitter does not receive any automatic flow control signal. 0 FLOW_CONTROL_ENABLED Flow control enabled. The transmitter uses external or internal CTS for flow control purposes. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [10:10] SYNCEN Selects synchronous or asynchronous operation. [11:11] ENUM ASYNCHRONOUS_MODE_IS Asynchronous mode is selected. 0 SYNCHRONOUS_MODE_IS_ Synchronous mode is selected. 1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. [12:12] ENUM FALLING_EDGE_UN_RXD Falling edge. Un_RXD is sampled on the falling edge of SCLK. 0 RISING_EDGE_UN_RXD_ Rising edge. Un_RXD is sampled on the rising edge of SCLK. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [13:13] SYNCMST Synchronous mode Master select. [14:14] ENUM SLAVE_WHEN_SYNCHRON Slave. When synchronous mode is enabled, the USART is a slave. 0 MASTER_WHEN_SYNCHRO Master. When synchronous mode is enabled, the USART is a master. In asynchronous mode, the baud rate clock will be output on SCLK if it is connected to a pin. 1 LOOP Selects data loopback mode. [15:15] ENUM NORMAL_OPERATION_ Normal operation. 0 LOOPBACK_MODE_THIS_ Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] CTRL USART Control register. USART control settings that are more likely to change during operation. 0x004 read-write 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [0:0] TXBRKEN Break Enable. [1:1] ENUM NORMAL_OPERATION_ Normal operation. 0 CONTINUOUS_BREAK_IS_ Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTRL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 1 ADDRDET Enable address detect mode. [2:2] ENUM ENABLED_THE_USART_R Enabled. The USART receiver is enabled for all incoming data. 0 DISABLED_THE_USART_ Disabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [5:3] TXDIS Transmit Disable. [6:6] ENUM NOT_DISABLED_USART_ Not disabled. USART transmitter is not disabled. 0 DISABLED_USART_TRAN Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. [8:8] ENUM CLOCK_ON_CHARACTER_ Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 0 CONTINUOUS_CLOCK_SC Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). 1 CLRCC Clear Continuous Clock. [9:9] ENUM NO_AFFECT_ON_THE_CC_ No affect on the CC bit. 0 AUTO_CLEAR_THE_CC_B Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [31:10] STAT USART Status register. The complete status value can be read here. Writing 1s clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x008 read-write 0x000E 0xFFFFFFFF RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDATA or RXDATASTAT registers. [0:0] RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. [1:1] TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDATA until the data is moved to the transmit shift register. [2:2] TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. [3:3] CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. [4:4] DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. [5:5] TXDISINT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1). [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNINT Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [9:9] RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. [10:10] DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. [11:11] START This bit is set when a start is detected on the receiver input and subsequently confirmed by a mid-bit sample. Its purpose is primarily to allow wakeup from Power-down mode immediately when a start is detected. Cleared by software. [12:12] FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. [13:13] PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character, if parity is enabled via the Parity field in the CFG register. [14:14] RXNOISEINT Received Noise interrupt flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. The Noise bit is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. RXNOISEINT is not updated during a received break. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTENSET Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x00C read-write 0 0xFFFFFFFF RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDATA register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDYEN When 1, enables an interrupt when the TXDATA register is available to take another character to transmit. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [4:3] DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. [5:5] TXDISINTEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNEN When 1, enables an interrupt when an overrun error occurred. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). [11:11] STARTEN When 1, enables an interrupt when a received start bit has been detected. [12:12] FRAMERREN When 1, enables an interrupt when a framing error has been detected. [13:13] PARITYERREN When 1, enables an interrupt when a parity error has been detected. [14:14] RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 164. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x010 write-only 0 0x00000000 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [4:3] DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. [5:5] TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. [11:11] STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. [12:12] FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [13:13] PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. [14:14] RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] RXDATA Receiver Data register. Contains the last character received. 0x014 read-only 0 0x00000000 modify RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. [8:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:9] RXDATASTAT Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows software to recover incoming data and status together. 0x018 read-only 0 0x00000000 modify RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. [8:0] RESERVED Reserved, the value read from a reserved bit is not defined. [12:9] FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. [13:13] PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. [14:14] RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 164. [15:15] RESERVED Reserved, the value read from a reserved bit is not defined. [31:16] TXDATA Transmit Data register. Data to be transmitted is written here. 0x01C read-write 0 0xFFFFFFFF TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available. [8:0] RESERVED Reserved. Only zero should be written. [31:9] BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x020 read-write 0 0xFFFFFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function. [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x024 read-only 0x0005 0xFFFFFFFF RXRDY Receiver Ready flag. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [1:1] TXRDY Transmitter Ready flag. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [4:3] DELTACTS This bit is set when a change in the state of the CTS input is detected. [5:5] TXDISINT Transmitter Disabled Interrupt flag. [6:6] RESERVED Reserved. Read value is undefined, only zero should be written. [7:7] OVERRUNINT Overrun Error interrupt flag. [8:8] RESERVED Reserved. Read value is undefined, only zero should be written. [10:9] DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. [11:11] START This bit is set when a start is detected on the receiver input. [12:12] FRAMERRINT Framing Error interrupt flag. [13:13] PARITYERRINT Parity Error interrupt flag. [14:14] RXNOISEINT Received Noise interrupt flag. [15:15] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] USART1 0x40068000 0 0xFFF registers UART1 4 USART2 0x4006C000 0 0xFFF registers UART2 5 CRC Cyclic Redundancy Check (CRC) engine CRC 0x50000000 0x0 0xFFF registers MODE CRC mode register 0x00 read-write 0x00000000 0xFFFFFFFF CRC_POLY CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial [1:0] BIT_RVS_WR Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte) [2:2] CMPL_WR Data complement: 1= 1's complement for CRC_WR_DATA 0= No 1's complement for CRC_WR_DATA [3:3] BIT_RVS_SUM CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM [4:4] CMPL_SUM CRC sum complement: 1= 1's complement for CRC_SUM 0=No 1's complement for CRC_SUM [5:5] Reserved Always 0 when read [31:6] SEED CRC seed register 0x04 read-write 0x0000FFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. [31:0] SUM CRC checksum register 0x08 read-only 0x0000FFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. [31:0] WR_DATA CRC data register SUM 0x08 write-only 0 0x00000000 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. [31:0] SCT State Configurable Timer (SCT) SCT 0x50004000 0x0 0xFFF registers SCT 9 CONFIG SCT configuration register 0x000 read-write 0x00007E00 0xFFFFFFFF UNIFY SCT operation [0:0] ENUM THE_SCT_OPERATES_AS_ The SCT operates as two 16-bit counters named L and H. 0 UNIFIED The SCT operates as a unified 32-bit counter. 1 CLKMODE SCT clock mode [2:1] ENUM THE_BUS_CLOCK_CLOCKS The bus clock clocks the SCT and prescalers. 0x0 THE_SCT_CLOCK_IS_THE The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 0x1 THE_INPUT_SELECTED_B The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 0x2 RESERVED_ Reserved. 0x3 CLKSEL SCT clock select [6:3] ENUM RISING_EDGES_ON_INPUT_0 Rising edges on input 0. 0x0 FALLING_EDGES_ON_INPUT_0 Falling edges on input 0. 0x1 RISING_EDGES_ON_INPUT_1 Rising edges on input 1. 0x2 FALLING_EDGES_ON_INPUT_1 Falling edges on input 1. 0x3 RISING_EDGES_ON_INPUT_2 Rising edges on input 2. 0x4 FALLING_EDGES_ON_INPUT_2 Falling edges on input 2. 0x5 RISING_EDGES_ON_INPUT_3 Rising edges on input 3. 0x6 FALLING_EDGES_ON_INPUT_3 Falling edges on input 3. 0x7 NORELAOD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [7:7] NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [8:8] INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. [16:9] AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [17:17] AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [18:18] RESERVED Reserved [31:19] CTRL SCT control register 0x004 read-write 0x00040004 0xFFFFFFFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. [0:0] STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [1:1] HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation. [2:2] CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. [3:3] BIDIR_L L or unified counter direction select [4:4] ENUM CLEAR_TO_ZERO The counter counts up to its limit condition, then is cleared to zero. 0 THE_COUNTER_COUNTS_U The counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [12:5] RESERVED Reserved [15:13] DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. [16:16] STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [17:17] HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation. [18:18] CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. [19:19] BIDIR_H Direction select [20:20] ENUM CLEAR_TO_ZERO The H counter counts up to its limit condition, then is cleared to zero. 0 THE_H_COUNTER_COUNTS The H counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [28:21] RESERVED Reserved [31:29] LIMIT SCT limit register 0x008 read-write 0x00000000 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). [20:16] RESERVED Reserved. [31:21] HALT SCT halt condition register 0x00C read-write 0x00000000 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). [20:16] RESERVED Reserved. [31:21] STOP SCT stop condition register 0x010 read-write 0x00000000 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). [20:16] RESERVED Reserved. [31:21] START SCT start condition register 0x014 read-write 0x00000000 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). [20:16] RESERVED Reserved. [31:21] COUNT SCT counter register 0x040 read-write 0x00000000 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. [15:0] CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. [31:16] STATE SCT state register 0x044 read-write 0x00000000 0xFFFFFFFF STATE_L State variable. [4:0] RESERVED Reserved. [15:5] STATE_H State variable. [20:16] RESERVED Reserved. [31:21] INPUT SCT input register 0x048 read-only 0x00000000 0xFFFFFFFF AIN0 Real-time status of input 0. [0:0] AIN1 Real-time status of input 1. [1:1] AIN2 Real-time status of input 2. [2:2] AIN3 Real-time status of input 3. [3:3] RESERVED Reserved. [15:4] SIN0 Input 0 state synchronized to the SCT clock. [16:16] SIN1 Input 1 state synchronized to the SCT clock. [17:17] SIN2 Input 2 state synchronized to the SCT clock. [18:18] SIN3 Input 3 state synchronized to the SCT clock. [19:19] RESERVED Reserved [31:20] REGMODE SCT match/capture registers mode register 0x04C read-write 0x00000000 0xFFFFFFFF REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). 0 = registers operate as match registers. 1 = registers operate as capture registers. [4:0] RESERVED Reserved. [15:5] REGMOD_H Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 19). 0 = registers operate as match registers. 1 = registers operate as capture registers. [19:16] RESERVED Reserved. [31:20] OUTPUT SCT output register 0x050 read-write 0x00000000 0xFFFFFFFF OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). [3:0] RESERVED Reserved [31:4] OUTPUTDIRCTRL SCT output counter direction control register 0x054 read-write 0x00000000 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. [1:0] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 REVERSED_ON_H Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. [3:2] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 REVERSED_ON_H Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. [5:4] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 REVERSED_ON_H Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. [7:6] ENUM SET_AND_CLEAR_DO_NOT Set and clear do not depend on any counter. 0x0 SET_AND_CLEAR_ARE_RE Set and clear are reversed when counter L or the unified counter is counting down. 0x1 REVERSED_ON_H Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RESERVED Reserved [31:8] RES SCT conflict resolution register 0x058 read-write 0x00000000 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. [1:0] ENUM NO_CHANGE_ No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR0 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT_ Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. [3:2] ENUM NO_CHANGE_ No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR1 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT_ Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. [5:4] ENUM NO_CHANGE_ No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR2 field). 0x1 CLEAR_OUTPUT_N_OR_S Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT_ Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. [7:6] ENUM NO_CHANGE_ No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR3 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT_ Toggle output. 0x3 RESERVED Reserved [31:8] EVEN SCT event enable register 0x0F0 read-write 0x00000000 0xFFFFFFFF IEN The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved [31:6] EVFLAG SCT event flag register 0x0F4 read-write 0x00000000 0xFFFFFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved [31:6] CONEN SCT conflict enable register 0x0F8 read-write 0x00000000 0xFFFFFFFF NCEN The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). [3:0] RESERVED Reserved [31:4] CONFLAG SCT conflict flag register 0x0FC read-write 0x00000000 0xFFFFFFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). [3:0] RESERVED Reserved. [29:4] BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. [30:30] BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. [31:31] 5 0x4 0-4 MATCH%s SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0 0x100 read-write 0x00000000 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. [15:0] MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. [31:16] 5 0x4 0-4 CAP%s SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1 MATCH%s 0x100 read-write 0x00000000 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. [15:0] CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. [31:16] 5 0x4 0-4 MATCHREL%s SCT match reload value register 0 to 4 REGMOD0 = 0 to REGMODE4 = 0 0x200 read-write 0x00000000 0xFFFFFFFF RELOADn_L When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. [15:0] RELOADn_H When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. [31:16] 5 0x4 0-4 CAPCTRL%s SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1 MATCHREL%s 0x200 read-write 0x00000000 0xFFFFFFFF CAPCONm_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). [5:0] RESERVED Reserved. [15:6] CAPCONm_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 20). [20:16] RESERVED Reserved. [31:17] EV0_STATE SCT event state register 0 0x300 read-write 0x00000000 0xFFFFFFFF STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). [1:0] RESERVED Reserved. [31:2] EV0_CTRL SCT event control register 0 0x304 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE_ Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE_ Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS_ Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR_THE_EVENT_OCCURS OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH_USES_THE_SPEC MATCH. Uses the specified match only. 0x1 IO_USES_THE_SPECIFI IO. Uses the specified I/O condition only. 0x2 AND_THE_EVENT_OCCUR AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP_THIS_EV Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN_THIS_ Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] EV1_STATE SCT event state register 1 0x308 read-write 0x00000000 0xFFFFFFFF STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). [1:0] RESERVED Reserved. [31:2] EV1_CTRL SCT event control register 1 0x30C read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE_ Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE_ Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS_ Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR_THE_EVENT_OCCURS OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH_USES_THE_SPEC MATCH. Uses the specified match only. 0x1 IO_USES_THE_SPECIFI IO. Uses the specified I/O condition only. 0x2 AND_THE_EVENT_OCCUR AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP_THIS_EV Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN_THIS_ Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] EV2_STATE SCT event state register 2 0x310 read-write 0x00000000 0xFFFFFFFF STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). [1:0] RESERVED Reserved. [31:2] EV2_CTRL SCT event control register 2 0x314 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE_ Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE_ Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS_ Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR_THE_EVENT_OCCURS OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH_USES_THE_SPEC MATCH. Uses the specified match only. 0x1 IO_USES_THE_SPECIFI IO. Uses the specified I/O condition only. 0x2 AND_THE_EVENT_OCCUR AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP_THIS_EV Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN_THIS_ Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] EV3_STATE SCT event state register 3 0x318 read-write 0x00000000 0xFFFFFFFF STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). [1:0] RESERVED Reserved. [31:2] EV3_CTRL SCT event control register 3 0x31C read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE_ Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE_ Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS_ Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR_THE_EVENT_OCCURS OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH_USES_THE_SPEC MATCH. Uses the specified match only. 0x1 IO_USES_THE_SPECIFI IO. Uses the specified I/O condition only. 0x2 AND_THE_EVENT_OCCUR AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP_THIS_EV Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN_THIS_ Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] EV4_STATE SCT event state register 4 0x320 read-write 0x00000000 0xFFFFFFFF STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). [1:0] RESERVED Reserved. [31:2] EV4_CTRL SCT event control register 4 0x324 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE_ Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE_ Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS_ Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR_THE_EVENT_OCCURS OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH_USES_THE_SPEC MATCH. Uses the specified match only. 0x1 IO_USES_THE_SPECIFI IO. Uses the specified I/O condition only. 0x2 AND_THE_EVENT_OCCUR AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP_THIS_EV Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN_THIS_ Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] EV5_STATE SCT event state register 5 0x328 read-write 0x00000000 0xFFFFFFFF STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). [1:0] RESERVED Reserved. [31:2] EV5_CTRL SCT event control register 5 0x32C read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM SELECTS_THE_L_STATE_ Selects the L state and the L match register selected by MATCHSEL. 0 SELECTS_THE_H_STATE_ Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM SELECTS_THE_INPUTS_E Selects the inputs elected by IOSEL. 0 SELECTS_THE_OUTPUTS_ Selects the outputs selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR_THE_EVENT_OCCURS OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH_USES_THE_SPEC MATCH. Uses the specified match only. 0x1 IO_USES_THE_SPECIFI IO. Uses the specified I/O condition only. 0x2 AND_THE_EVENT_OCCUR AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP_THIS_EV Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN_THIS_ Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] OUT0_SET SCT output 0 set register 0x500 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT0_CLR SCT output 0 clear register 0x504 read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT1_SET SCT output 1 set register 0x508 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT1_CLR SCT output 1 clear register 0x50C read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT2_SET SCT output 2 set register 0x510 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT2_CLR SCT output 2 clear register 0x514 read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT3_SET SCT output 3 set register 0x518 read-write 0x00000000 0xFFFFFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] OUT3_CLR SCT output 3 clear register 0x51C read-write 0x00000000 0xFFFFFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. [5:0] RESERVED Reserved [31:6] GPIO_PORT General Purpose I/O port (GPIO) GPIO_PORT 0xA0000000 0x0 0xFFFFF registers 18 0x1 0-17 B%s Byte pin registers port 0; pins PIO0_0 to PIO0_17 0x0000 8 read-write 0 0x00000000 PBYTE Read: state of the pin P0_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit. [0:0] 18 0x4 0-17 W%s Word pin registers port 0 0x1000 read-write 0 0x00000000 PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. [31:0] DIR0 Direction registers port 0 0x2000 read-write 0 0xFFFFFFFF DIRP0 Selects pin direction for pin P0_n (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = input. 1 = output. [17:0] RESERVED Reserved. [31:18] MASK0 Mask register port 0 0x2080 read-write 0 0xFFFFFFFF MASKP0 Controls which bits corresponding to P0_n are active in the P0MPORT register (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [17:0] RESERVED Reserved. [31:18] PIN0 Port pin register port 0 0x2100 read-write 0 0x00000000 PORT0 Reads pin states or loads output bits (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [17:0] RESERVED Reserved. [31:18] MPIN0 Masked port register port 0 0x2180 read-write 0 0x00000000 MPORTP0 Masked port register (bit 0 = P0_0, bit 1 = P0_1, ..., bit 17 = P0_17). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [17:0] RESERVED Reserved. [31:18] SET0 Write: Set register for port 0 Read: output bits for port 0 0x2200 read-write 0 0xFFFFFFFF SETP0 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [17:0] RESERVED Reserved. [31:18] CLR0 Clear port 0 0x2280 write-only 0 0x00000000 CLRP0 Clear output bits: 0 = No operation. 1 = Clear output bit. [17:0] RESERVED Reserved. [31:18] NOT0 Toggle port 0 0x2300 write-only 0 0x00000000 NOTP0 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [17:0] RESERVED Reserved. [31:18] PIN_INT Pin interrupt and pattern match engine GPIO_PIN_INT 0xA0004000 0x0 0xFFF registers PININT0 24 PININT1 25 PININT2 26 PININT3 27 PININT4 28 PININT5 29 PININT6 30 PININT7 31 ISEL Pin Interrupt Mode register 0x000 read-write 0 0xFFFFFFFF PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [7:0] RESERVED Reserved. [31:8] IENR Pin interrupt level or rising edge interrupt enable register 0x004 read-write 0 0xFFFFFFFF ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [7:0] RESERVED Reserved. [31:8] SIENR Pin interrupt level (rising edge) interrupt set register 0x008 write-only 0 0x00000000 SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. [7:0] RESERVED Reserved. [31:8] CIENR Pin interrupt level or rising edge interrupt clear register 0x00C write-only 0 0x00000000 CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [7:0] RESERVED Reserved. [31:8] IENF Pin interrupt active level or falling edge interrupt enable register 0x010 read-write 0 0xFFFFFFFF ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [7:0] RESERVED Reserved. [31:8] SIENF Pin interrupt active level or falling edge interrupt set register 0x014 write-only 0 0x00000000 SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [7:0] RESERVED Reserved. [31:8] CIENF Pin interrupt active level (falling edge) interrupt clear register 0x018 write-only 0 0x00000000 CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [7:0] RESERVED Reserved. [31:8] RISE Pin interrupt rising edge register 0x01C read-write 0 0xFFFFFFFF RDET Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [7:0] RESERVED Reserved. [31:8] FALL Pin interrupt falling edge register 0x020 read-write 0 0xFFFFFFFF FDET Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [7:0] RESERVED Reserved. [31:8] IST Pin interrupt status register 0x024 read-write 0 0xFFFFFFFF PSTAT Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). [7:0] RESERVED Reserved. [31:8] PMCTRL GPIO pattern match interrupt control register 0x028 read-write 0 0xFFFFFFFF SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. [0:0] ENUM PIN_INTERRUPT_INTER Pin interrupt. Interrupts are driven in response to the standard pin interrupt function 0 PATTERN_MATCH_INTER Pattern match. Interrupts are driven in response to pattern matches. 1 ENA_RXEV Enables the RxEv output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true. [1:1] ENUM DISABLED_RXEV_OUTPU Disabled. RxEv output to the cpu is disabled. 0 ENABLED_RXEV_OUTPUT Enabled. RxEv output to the cpu is enabled. 1 RESERVED Reserved. Do not write 1s to unused bits. [23:2] PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. [31:24] PMSRC GPIO pattern match interrupt bit-slice source register 0x02C read-write 0 0xFFFFFFFF Reserved Software should not write 1s to unused bits. [7:0] SRC0 Selects the input source for bit slice 0 [10:8] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 0. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 0. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 0. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 0. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 0. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 0. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 0. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 0. 0x7 SRC1 Selects the input source for bit slice 1 [13:11] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 1. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 1. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 1. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 1. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 1. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 1. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 1. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 1. 0x7 SRC2 Selects the input source for bit slice 2 [16:14] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 2. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 2. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 2. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 2. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 2. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 2. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 2. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 2. 0x7 SRC3 Selects the input source for bit slice 3 [19:17] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 3. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 3. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 3. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 3. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 3. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 3. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 3. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 3. 0x7 SRC4 Selects the input source for bit slice 4 [22:20] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 4. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 4. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 4. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 4. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 4. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 4. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 4. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 4. 0x7 SRC5 Selects the input source for bit slice 5 [25:23] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 5. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 5. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 5. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 5. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 5. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 5. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 5. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 5. 0x7 SRC6 Selects the input source for bit slice 6 [28:26] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 6. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 6. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 6. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 6. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 6. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 6. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 6. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 6. 0x7 SRC7 Selects the input source for bit slice 7 [31:29] ENUM INPUT_0_SELECTS_PIN Input 0. Selects pin interrupt input 0 as the source to bit slice 7. 0x0 INPUT_1_SELECTS_PIN Input 1. Selects pin interrupt input 1 as the source to bit slice 7. 0x1 INPUT_2_SELECTS_PIN Input 2. Selects pin interrupt input 2 as the source to bit slice 7. 0x2 INPUT_3_SELECTS_PIN Input 3. Selects pin interrupt input 3 as the source to bit slice 7. 0x3 INPUT_4_SELECTS_PIN Input 4. Selects pin interrupt input 4 as the source to bit slice 7. 0x4 INPUT_5_SELECTS_PIN Input 5. Selects pin interrupt input 5 as the source to bit slice 7. 0x5 INPUT_6_SELECTS_PIN Input 6. Selects pin interrupt input 6 as the source to bit slice 7. 0x6 INPUT_7_SELECTS_PIN Input 7. Selects pin interrupt input 7 as the source to bit slice 7. 0x7 PMCFG GPIO pattern match interrupt bit slice configuration register 0x030 read-write 0 0xFFFFFFFF PROD_ENDPTS A 1 in any bit of this field causes the corresponding bit slice to be the final component of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice). [6:0] Reserved (Bit slice 7 is automatically considered a product end point) Software should not write 1s to unused bits [7:7] CFG0 Specifies the match-contribution condition for bit slice 0. [10:8] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG1 Specifies the match-contribution condition for bit slice 1. [13:11] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG2 Specifies the match-contribution condition for bit slice 2. [16:14] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG3 Specifies the match-contribution condition for bit slice 3. [19:17] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG4 Specifies the match-contribution condition for bit slice 4. [22:20] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG5 Specifies the match-contribution condition for bit slice 5. [25:23] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG6 Specifies the match-contribution condition for bit slice 6. [28:26] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7 CFG7 Specifies the match-contribution condition for bit slice 7. [31:29] ENUM CONSTANT_1_THIS_BIT Constant 1. This bit slice always contributes to a product term match. 0x0 RISING_EDGE_MATCH_O Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x1 FALLING_EDGE_MATCH_ Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x2 RISING_OR_FALLING_ED Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. 0x3 HIGH_LEVEL_MATCH_F High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL_MATCH_OCC Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_0_THIS_BIT Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x6 EVENT_MATCH_OCCURS_ Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 0x7