$version Generated by VerilatedVcd $end $date Fri Dec 30 09:26:12 2022 $end $timescale 1ps $end $scope module TOP $end $var wire 1 M, clk $end $var wire 1 V, error_flag $end $var wire 8 W, exit_code [7:0] $end $var wire 1 U, exit_flag $end $var wire 1 N, rst $end $var wire 8 Q, tty_in_data [7:0] $end $var wire 1 P, tty_in_ready $end $var wire 1 O, tty_in_valid $end $var wire 8 T, tty_out_data [7:0] $end $var wire 1 S, tty_out_ready $end $var wire 1 R, tty_out_valid $end $scope module gecko_nano_wrapper $end $var wire 8 L/ STARTUP_PROGRAM [7:0] $end $var wire 1 M, clk $end $var wire 1 a$ error_flag $end $var wire 8 b$ exit_code [7:0] $end $var wire 1 M exit_flag $end $var wire 1 N, rst $end $var wire 8 Q, tty_in_data [7:0] $end $var wire 1 ^$ tty_in_ready $end $var wire 1 O, tty_in_valid $end $var wire 8 `$ tty_out_data [7:0] $end $var wire 1 S, tty_out_ready $end $var wire 1 _$ tty_out_valid $end $scope module inst $end $var wire 1 Q/ DATA_MEMORY_OUTPUT_REG $end $var wire 1 Q/ INST_MEMORY_OUTPUT_REG $end $var wire 32 ]/ MEMORY_ADDR_WIDTH [31:0] $end $var wire 8 L/ STARTUP_PROGRAM [7:0] $end $var wire 32 P/ TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 1 a$ error_flag $end $var wire 8 b$ exit_code [7:0] $end $var wire 1 M exit_flag $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct CONFIG $end $var wire 32 V/ data_memory_latency [31:0] $end $var wire 2 T/ decode_pipeline_mode [1:0] $end $var wire 1 Q/ enable_floating_point $end $var wire 1 Q/ enable_integer_math $end $var wire 1 \/ enable_performance_counters $end $var wire 1 \/ enable_tty_io $end $var wire 2 T/ execute_pipeline_mode [1:0] $end $var wire 2 S/ fetch_pipeline_mode [1:0] $end $var wire 32 W/ float_memory_latency [31:0] $end $var wire 2 S/ imem_pipeline_mode [1:0] $end $var wire 32 U/ instruction_memory_latency [31:0] $end $var wire 2 T/ print_pipeline_mode [1:0] $end $var wire 32 R/ start_addr [31:0] $end $var wire 2 T/ system_pipeline_mode [1:0] $end $var wire 2 T/ writeback_pipeline_mode [1:0] $end $scope struct predictor_config $end $var wire 32 Z/ history_width [31:0] $end $var wire 32 [/ local_addr_width [31:0] $end $var wire 2 X/ mode [1:0] $end $var wire 32 Y/ target_addr_width [31:0] $end $upscope $end $upscope $end $scope module core $end $var wire 32 k/ TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 1 a$ error_flag $end $var wire 8 b$ exit_code [7:0] $end $var wire 1 M exit_flag $end $var wire 1 &% instruction_decoded $end $var wire 1 '% instruction_executed $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct CONFIG $end $var wire 32 V/ data_memory_latency [31:0] $end $var wire 2 T/ decode_pipeline_mode [1:0] $end $var wire 1 Q/ enable_floating_point $end $var wire 1 Q/ enable_integer_math $end $var wire 1 \/ enable_performance_counters $end $var wire 1 \/ enable_tty_io $end $var wire 2 T/ execute_pipeline_mode [1:0] $end $var wire 2 S/ fetch_pipeline_mode [1:0] $end $var wire 32 W/ float_memory_latency [31:0] $end $var wire 2 S/ imem_pipeline_mode [1:0] $end $var wire 32 U/ instruction_memory_latency [31:0] $end $var wire 2 T/ print_pipeline_mode [1:0] $end $var wire 32 R/ start_addr [31:0] $end $var wire 2 T/ system_pipeline_mode [1:0] $end $var wire 2 T/ writeback_pipeline_mode [1:0] $end $scope struct predictor_config $end $var wire 32 Z/ history_width [31:0] $end $var wire 32 [/ local_addr_width [31:0] $end $var wire 2 X/ mode [1:0] $end $var wire 32 Y/ target_addr_width [31:0] $end $upscope $end $upscope $end $scope interface data_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 ^* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 6) data [31:0] $end $var wire 1 h$ id [0:0] $end $var wire 1 j$ last $end $var wire 1 ]* read_enable $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $var wire 4 4) write_enable [3:0] $end $upscope $end $scope interface data_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 A1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 7) data [31:0] $end $var wire 1 i$ id [0:0] $end $var wire 1 k$ last $end $var wire 1 ?1 read_enable $end $var wire 1 3# ready $end $var wire 1 N, rst $end $var wire 1 l$ valid $end $var wire 4 @1 write_enable [3:0] $end $upscope $end $scope interface execute_command $end $var wire 250 o1 T_LOGIC [249:0] $end $var wire 1 M, clk $end $var wire 1 k ready $end $var wire 1 N, rst $end $var wire 1 X% valid $end $scope struct payload $end $var wire 1 <+ alu_alternate $end $var wire 32 F+ current_pc [31:0] $end $var wire 1 9+ halt $end $var wire 32 E+ immediate_value [31:0] $end $var wire 2 7+ jump_flag [1:0] $end $var wire 32 D+ jump_value [31:0] $end $var wire 32 C+ mem_value [31:0] $end $var wire 32 G+ next_pc [31:0] $end $var wire 3 :+ op_type [2:0] $end $var wire 1 8+ pc_updated $end $var wire 5 5+ reg_addr [4:0] $end $var wire 3 6+ reg_status [2:0] $end $var wire 1 @+ reuse_jump $end $var wire 1 ?+ reuse_mem $end $var wire 1 =+ reuse_rs1 $end $var wire 1 >+ reuse_rs2 $end $var wire 32 A+ rs1_value [31:0] $end $var wire 32 B+ rs2_value [31:0] $end $scope union op $end $var wire 3 ;+ b [2:0] $end $var wire 3 ;+ ir [2:0] $end $var wire 3 ;+ ls [2:0] $end $var wire 3 ;+ sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 I+ history [1:0] $end $var wire 1 H+ miss $end $upscope $end $upscope $end $upscope $end $scope struct execute_forwarded $end $var wire 5 s$ addr [4:0] $end $var wire 2 t$ jump_flag [1:0] $end $var wire 1 w$ mispredicted $end $var wire 3 u$ reg_status [2:0] $end $var wire 1 r$ valid $end $var wire 32 v$ value [31:0] $end $upscope $end $scope interface execute_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope interface float_command $end $var wire 215 z1 T_LOGIC [214:0] $end $var wire 1 M, clk $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 /* valid $end $scope struct payload $end $var wire 5 Q+ dest_reg_addr [4:0] $end $var wire 3 R+ dest_reg_status [2:0] $end $var wire 1 b+ enable_status_op $end $var wire 2 S+ jump_flag [1:0] $end $var wire 32 a+ rs1_value [31:0] $end $var wire 12 e+ sys_csr [11:0] $end $var wire 32 d+ sys_imm [31:0] $end $var wire 3 c+ sys_op [2:0] $end $scope struct instruction_fields $end $var wire 1 `+ decode_error $end $var wire 12 ^+ funct12 [11:0] $end $var wire 3 Z+ funct3 [2:0] $end $var wire 5 [+ funct5 [4:0] $end $var wire 6 \+ funct6 [5:0] $end $var wire 7 ]+ funct7 [6:0] $end $var wire 32 _+ imm [31:0] $end $var wire 32 T+ inst [31:0] $end $var wire 7 U+ opcode [6:0] $end $var wire 5 V+ rd [4:0] $end $var wire 5 W+ rs1 [4:0] $end $var wire 5 X+ rs2 [4:0] $end $var wire 5 Y+ rs3 [4:0] $end $upscope $end $upscope $end $upscope $end $scope interface float_mem_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 D1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 E1 data [31:0] $end $var wire 1 F1 id [0:0] $end $var wire 1 G1 last $end $var wire 1 B1 read_enable $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $var wire 4 C1 write_enable [3:0] $end $upscope $end $scope interface float_mem_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 J1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 K1 data [31:0] $end $var wire 1 L1 id [0:0] $end $var wire 1 M1 last $end $var wire 1 H1 read_enable $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $var wire 4 I1 write_enable [3:0] $end $upscope $end $scope interface float_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $scope module gecko_data_stage_inst $end $var wire 2 l/ PIPELINE_MODE [1:0] $end $var wire 32 _/ STAGES [31:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $scope module stream_stage_inst $end $var wire 32 ]/ PAYLOAD_WIDTH [31:0] $end $var wire 2 m/ PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 X payload_enable $end $var wire 1 Y valid_enable $end $scope module payload_register_inst $end $var wire 16 n/ RESET_VECTOR [15:0] $end $var wire 1 M, clk $end $var wire 1 X enable $end $var wire 16 (% next [15:0] $end $var wire 1 # rst $end $var wire 1 $ rst_actual $end $var wire 16 )% value [15:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 Y enable $end $var wire 1 X next $end $var wire 1 N, rst $end $var wire 1 Z rst_actual $end $var wire 1 *% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 N$ ready $end $var wire 1 N, rst $end $var wire 1 O% valid $end $scope struct payload $end $var wire 5 #, addr [4:0] $end $var wire 2 %, jump_flag [1:0] $end $var wire 1 (, mispredicted $end $var wire 2 ', offset [1:0] $end $var wire 3 &, op [2:0] $end $var wire 3 $, reg_status [2:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 *% valid $end $scope struct payload $end $var wire 5 ), addr [4:0] $end $var wire 2 +, jump_flag [1:0] $end $var wire 1 ., mispredicted $end $var wire 2 -, offset [1:0] $end $var wire 3 ,, op [2:0] $end $var wire 3 *, reg_status [2:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 N$ ready $end $var wire 1 N, rst $end $var wire 1 O% valid $end $scope struct payload $end $var wire 5 #, addr [4:0] $end $var wire 2 %, jump_flag [1:0] $end $var wire 1 (, mispredicted $end $var wire 2 ', offset [1:0] $end $var wire 3 &, op [2:0] $end $var wire 3 $, reg_status [2:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 *% valid $end $scope struct payload $end $var wire 5 ), addr [4:0] $end $var wire 2 +, jump_flag [1:0] $end $var wire 1 ., mispredicted $end $var wire 2 -, offset [1:0] $end $var wire 3 ,, op [2:0] $end $var wire 3 *, reg_status [2:0] $end $upscope $end $upscope $end $upscope $end $scope module gecko_decode_inst $end $var wire 1 \/ ENABLE_EXECUTE_SAVED $end $var wire 1 Q/ ENABLE_FLOAT $end $var wire 1 Q/ ENABLE_INTEGER_MATH $end $var wire 32 m0 NUM_FORWARDED [31:0] $end $var wire 32 m0 NUM_FORWARDED_SAFE [31:0] $end $var wire 2 l0 PIPELINE_MODE [1:0] $end $var wire 32 k0 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 1 p! consume_instruction $end $var wire 32 [, debug_jump_address [31:0] $end $var wire 1 X, debug_jump_valid $end $var wire 5 Z, debug_register_addr [4:0] $end $var wire 32 \, debug_register_data [31:0] $end $var wire 1 Y, debug_register_write $end $var wire 1 t! enable $end $var wire 1 a$ error_flag $end $var wire 2 z) execute_flag [1:0] $end $var wire 5 S) execute_saved [4:0] $end $var wire 1 M exit_flag $end $var wire 1 -" instruction_branch_jump $end $var wire 1 &% instruction_decoded $end $var wire 1 |! instruction_decoded_next $end $var wire 1 ," instruction_enable $end $var wire 1 {) mispredicted $end $var wire 1 R) next_error_flag $end $var wire 5 v! next_execute_saved [4:0] $end $var wire 2 u! next_state [1:0] $end $var wire 1 r! produce_execute $end $var wire 1 s! produce_float $end $var wire 1 q! produce_system $end $var wire 5 n0 rd_read_addr [4:0] $end $var wire 1 #" rd_read_enable $end $var wire 3 (" rd_read_status [2:0] $end $var wire 3 +" rd_read_status_front [2:0] $end $var wire 5 &" rd_write_addr [4:0] $end $var wire 1 $" rd_write_enable $end $var wire 32 '" rd_write_value [31:0] $end $var wire 1 %" rd_write_value_enable $end $var wire 1 y) reset_done $end $var wire 3 !" rs1_status [2:0] $end $var wire 3 )" rs1_status_front_last [2:0] $end $var wire 32 }! rs1_value [31:0] $end $var wire 3 "" rs2_status [2:0] $end $var wire 3 *" rs2_status_front_last [2:0] $end $var wire 32 ~! rs2_value [31:0] $end $var wire 1 N, rst $end $var wire 1 |) speculating $end $var wire 1 }) speculation_full $end $var wire 2 Q) state [1:0] $end $var wire 2 Q) state_temp [1:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module decode_state_register_inst $end $var wire 2 o0 RESET_VECTOR [1:0] $end $var wire 1 M, clk $end $var wire 1 t! enable $end $var wire 2 u! next [1:0] $end $var wire 1 N, rst $end $var wire 1 :" rst_actual $end $var wire 2 Q) value [1:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module error_flag_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 t! enable $end $var wire 1 R) next $end $var wire 1 N, rst $end $var wire 1 ;" rst_actual $end $var wire 1 a$ value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope interface execute_command $end $var wire 250 o1 T_LOGIC [249:0] $end $var wire 1 M, clk $end $var wire 1 k ready $end $var wire 1 N, rst $end $var wire 1 X% valid $end $scope struct payload $end $var wire 1 <+ alu_alternate $end $var wire 32 F+ current_pc [31:0] $end $var wire 1 9+ halt $end $var wire 32 E+ immediate_value [31:0] $end $var wire 2 7+ jump_flag [1:0] $end $var wire 32 D+ jump_value [31:0] $end $var wire 32 C+ mem_value [31:0] $end $var wire 32 G+ next_pc [31:0] $end $var wire 3 :+ op_type [2:0] $end $var wire 1 8+ pc_updated $end $var wire 5 5+ reg_addr [4:0] $end $var wire 3 6+ reg_status [2:0] $end $var wire 1 @+ reuse_jump $end $var wire 1 ?+ reuse_mem $end $var wire 1 =+ reuse_rs1 $end $var wire 1 >+ reuse_rs2 $end $var wire 32 A+ rs1_value [31:0] $end $var wire 32 B+ rs2_value [31:0] $end $scope union op $end $var wire 3 ;+ b [2:0] $end $var wire 3 ;+ ir [2:0] $end $var wire 3 ;+ ls [2:0] $end $var wire 3 ;+ sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 I+ history [1:0] $end $var wire 1 H+ miss $end $upscope $end $upscope $end $upscope $end $scope module execute_operation_stream_stage_inst $end $var wire 32 q0 PAYLOAD_WIDTH [31:0] $end $var wire 2 p0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 <" payload_enable $end $var wire 1 =" valid_enable $end $scope module payload_register_inst $end $var wire 250 r0 RESET_VECTOR [249:0] $end $var wire 1 M, clk $end $var wire 1 <" enable $end $var wire 250 >" next [249:0] $end $var wire 1 > rst $end $var wire 1 ? rst_actual $end $var wire 250 ~) value [249:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 =" enable $end $var wire 1 <" next $end $var wire 1 N, rst $end $var wire 1 F" rst_actual $end $var wire 1 X% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 250 o1 T_LOGIC [249:0] $end $var wire 1 M, clk $end $var wire 1 a# ready $end $var wire 1 N, rst $end $var wire 1 `# valid $end $scope struct payload $end $var wire 1 i# alu_alternate $end $var wire 32 s# current_pc [31:0] $end $var wire 1 f# halt $end $var wire 32 r# immediate_value [31:0] $end $var wire 2 d# jump_flag [1:0] $end $var wire 32 q# jump_value [31:0] $end $var wire 32 p# mem_value [31:0] $end $var wire 32 t# next_pc [31:0] $end $var wire 3 g# op_type [2:0] $end $var wire 1 e# pc_updated $end $var wire 5 b# reg_addr [4:0] $end $var wire 3 c# reg_status [2:0] $end $var wire 1 m# reuse_jump $end $var wire 1 l# reuse_mem $end $var wire 1 j# reuse_rs1 $end $var wire 1 k# reuse_rs2 $end $var wire 32 n# rs1_value [31:0] $end $var wire 32 o# rs2_value [31:0] $end $scope union op $end $var wire 3 h# b [2:0] $end $var wire 3 h# ir [2:0] $end $var wire 3 h# ls [2:0] $end $var wire 3 h# sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 v# history [1:0] $end $var wire 1 u# miss $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 250 o1 T_LOGIC [249:0] $end $var wire 1 M, clk $end $var wire 1 k ready $end $var wire 1 N, rst $end $var wire 1 X% valid $end $scope struct payload $end $var wire 1 <+ alu_alternate $end $var wire 32 F+ current_pc [31:0] $end $var wire 1 9+ halt $end $var wire 32 E+ immediate_value [31:0] $end $var wire 2 7+ jump_flag [1:0] $end $var wire 32 D+ jump_value [31:0] $end $var wire 32 C+ mem_value [31:0] $end $var wire 32 G+ next_pc [31:0] $end $var wire 3 :+ op_type [2:0] $end $var wire 1 8+ pc_updated $end $var wire 5 5+ reg_addr [4:0] $end $var wire 3 6+ reg_status [2:0] $end $var wire 1 @+ reuse_jump $end $var wire 1 ?+ reuse_mem $end $var wire 1 =+ reuse_rs1 $end $var wire 1 >+ reuse_rs2 $end $var wire 32 A+ rs1_value [31:0] $end $var wire 32 B+ rs2_value [31:0] $end $scope union op $end $var wire 3 ;+ b [2:0] $end $var wire 3 ;+ ir [2:0] $end $var wire 3 ;+ ls [2:0] $end $var wire 3 ;+ sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 I+ history [1:0] $end $var wire 1 H+ miss $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module execute_saved_register_inst $end $var wire 5 z0 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 t! enable $end $var wire 5 v! next [4:0] $end $var wire 1 N, rst $end $var wire 1 G" rst_actual $end $var wire 5 S) value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope interface float_command $end $var wire 215 z1 T_LOGIC [214:0] $end $var wire 1 M, clk $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 /* valid $end $scope struct payload $end $var wire 5 Q+ dest_reg_addr [4:0] $end $var wire 3 R+ dest_reg_status [2:0] $end $var wire 1 b+ enable_status_op $end $var wire 2 S+ jump_flag [1:0] $end $var wire 32 a+ rs1_value [31:0] $end $var wire 12 e+ sys_csr [11:0] $end $var wire 32 d+ sys_imm [31:0] $end $var wire 3 c+ sys_op [2:0] $end $scope struct instruction_fields $end $var wire 1 `+ decode_error $end $var wire 12 ^+ funct12 [11:0] $end $var wire 3 Z+ funct3 [2:0] $end $var wire 5 [+ funct5 [4:0] $end $var wire 6 \+ funct6 [5:0] $end $var wire 7 ]+ funct7 [6:0] $end $var wire 32 _+ imm [31:0] $end $var wire 32 T+ inst [31:0] $end $var wire 7 U+ opcode [6:0] $end $var wire 5 V+ rd [4:0] $end $var wire 5 W+ rs1 [4:0] $end $var wire 5 X+ rs2 [4:0] $end $var wire 5 Y+ rs3 [4:0] $end $upscope $end $upscope $end $upscope $end $scope module float_operation_stream_stage_inst $end $var wire 32 |0 PAYLOAD_WIDTH [31:0] $end $var wire 2 {0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 H" payload_enable $end $var wire 1 I" valid_enable $end $scope module payload_register_inst $end $var wire 215 }0 RESET_VECTOR [214:0] $end $var wire 1 M, clk $end $var wire 1 H" enable $end $var wire 215 J" next [214:0] $end $var wire 1 @ rst $end $var wire 1 A rst_actual $end $var wire 215 (* value [214:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 I" enable $end $var wire 1 H" next $end $var wire 1 N, rst $end $var wire 1 Q" rst_actual $end $var wire 1 /* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 215 z1 T_LOGIC [214:0] $end $var wire 1 M, clk $end $var wire 1 f+ ready $end $var wire 1 N, rst $end $var wire 1 #$ valid $end $scope struct payload $end $var wire 5 $$ dest_reg_addr [4:0] $end $var wire 3 %$ dest_reg_status [2:0] $end $var wire 1 5$ enable_status_op $end $var wire 2 &$ jump_flag [1:0] $end $var wire 32 4$ rs1_value [31:0] $end $var wire 12 8$ sys_csr [11:0] $end $var wire 32 7$ sys_imm [31:0] $end $var wire 3 6$ sys_op [2:0] $end $scope struct instruction_fields $end $var wire 1 3$ decode_error $end $var wire 12 1$ funct12 [11:0] $end $var wire 3 -$ funct3 [2:0] $end $var wire 5 .$ funct5 [4:0] $end $var wire 6 /$ funct6 [5:0] $end $var wire 7 0$ funct7 [6:0] $end $var wire 32 2$ imm [31:0] $end $var wire 32 '$ inst [31:0] $end $var wire 7 ($ opcode [6:0] $end $var wire 5 )$ rd [4:0] $end $var wire 5 *$ rs1 [4:0] $end $var wire 5 +$ rs2 [4:0] $end $var wire 5 ,$ rs3 [4:0] $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 215 z1 T_LOGIC [214:0] $end $var wire 1 M, clk $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 /* valid $end $scope struct payload $end $var wire 5 Q+ dest_reg_addr [4:0] $end $var wire 3 R+ dest_reg_status [2:0] $end $var wire 1 b+ enable_status_op $end $var wire 2 S+ jump_flag [1:0] $end $var wire 32 a+ rs1_value [31:0] $end $var wire 12 e+ sys_csr [11:0] $end $var wire 32 d+ sys_imm [31:0] $end $var wire 3 c+ sys_op [2:0] $end $scope struct instruction_fields $end $var wire 1 `+ decode_error $end $var wire 12 ^+ funct12 [11:0] $end $var wire 3 Z+ funct3 [2:0] $end $var wire 5 [+ funct5 [4:0] $end $var wire 6 \+ funct6 [5:0] $end $var wire 7 ]+ funct7 [6:0] $end $var wire 32 _+ imm [31:0] $end $var wire 32 T+ inst [31:0] $end $var wire 7 U+ opcode [6:0] $end $var wire 5 V+ rd [4:0] $end $var wire 5 W+ rs1 [4:0] $end $var wire 5 X+ rs2 [4:0] $end $var wire 5 Y+ rs3 [4:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct forwarded_results[0] $end $var wire 5 @) addr [4:0] $end $var wire 2 A) jump_flag [1:0] $end $var wire 1 D) mispredicted $end $var wire 3 B) reg_status [2:0] $end $var wire 1 ?) valid $end $var wire 32 C) value [31:0] $end $upscope $end $scope struct forwarded_results[1] $end $var wire 5 F) addr [4:0] $end $var wire 2 G) jump_flag [1:0] $end $var wire 1 J) mispredicted $end $var wire 3 H) reg_status [2:0] $end $var wire 1 E) valid $end $var wire 32 I) value [31:0] $end $upscope $end $scope struct forwarded_results[2] $end $var wire 5 L) addr [4:0] $end $var wire 2 M) jump_flag [1:0] $end $var wire 1 P) mispredicted $end $var wire 3 N) reg_status [2:0] $end $var wire 1 K) valid $end $var wire 32 O) value [31:0] $end $upscope $end $scope interface instruction_command $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $scope module instruction_decoded_register $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 |! next $end $var wire 1 N, rst $end $var wire 1 R" rst_actual $end $var wire 1 &% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope struct instruction_fields $end $var wire 1 s) decode_error $end $var wire 12 q) funct12 [11:0] $end $var wire 3 m) funct3 [2:0] $end $var wire 5 n) funct5 [4:0] $end $var wire 6 o) funct6 [5:0] $end $var wire 7 p) funct7 [6:0] $end $var wire 32 r) imm [31:0] $end $var wire 32 g) inst [31:0] $end $var wire 7 h) opcode [6:0] $end $var wire 5 i) rd [4:0] $end $var wire 5 j) rs1 [4:0] $end $var wire 5 k) rs2 [4:0] $end $var wire 5 l) rs3 [4:0] $end $upscope $end $scope struct instruction_op $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $scope interface instruction_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 a* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 b* data [31:0] $end $var wire 1 c* id [0:0] $end $var wire 1 d* last $end $var wire 1 _* read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 `* write_enable [3:0] $end $upscope $end $scope struct instruction_status $end $var wire 1 7" flush_instruction $end $var wire 1 8" stall_control $end $var wire 1 9" stall_data $end $upscope $end $scope struct jump_cmd_in $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $scope interface jump_command $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 M% valid $end $scope struct payload $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $upscope $end $scope interface next_execute_command $end $var wire 250 o1 T_LOGIC [249:0] $end $var wire 1 M, clk $end $var wire 1 a# ready $end $var wire 1 N, rst $end $var wire 1 `# valid $end $scope struct payload $end $var wire 1 i# alu_alternate $end $var wire 32 s# current_pc [31:0] $end $var wire 1 f# halt $end $var wire 32 r# immediate_value [31:0] $end $var wire 2 d# jump_flag [1:0] $end $var wire 32 q# jump_value [31:0] $end $var wire 32 p# mem_value [31:0] $end $var wire 32 t# next_pc [31:0] $end $var wire 3 g# op_type [2:0] $end $var wire 1 e# pc_updated $end $var wire 5 b# reg_addr [4:0] $end $var wire 3 c# reg_status [2:0] $end $var wire 1 m# reuse_jump $end $var wire 1 l# reuse_mem $end $var wire 1 j# reuse_rs1 $end $var wire 1 k# reuse_rs2 $end $var wire 32 n# rs1_value [31:0] $end $var wire 32 o# rs2_value [31:0] $end $scope union op $end $var wire 3 h# b [2:0] $end $var wire 3 h# ir [2:0] $end $var wire 3 h# ls [2:0] $end $var wire 3 h# sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 v# history [1:0] $end $var wire 1 u# miss $end $upscope $end $upscope $end $upscope $end $scope interface next_float_command $end $var wire 215 z1 T_LOGIC [214:0] $end $var wire 1 M, clk $end $var wire 1 f+ ready $end $var wire 1 N, rst $end $var wire 1 #$ valid $end $scope struct payload $end $var wire 5 $$ dest_reg_addr [4:0] $end $var wire 3 %$ dest_reg_status [2:0] $end $var wire 1 5$ enable_status_op $end $var wire 2 &$ jump_flag [1:0] $end $var wire 32 4$ rs1_value [31:0] $end $var wire 12 8$ sys_csr [11:0] $end $var wire 32 7$ sys_imm [31:0] $end $var wire 3 6$ sys_op [2:0] $end $scope struct instruction_fields $end $var wire 1 3$ decode_error $end $var wire 12 1$ funct12 [11:0] $end $var wire 3 -$ funct3 [2:0] $end $var wire 5 .$ funct5 [4:0] $end $var wire 6 /$ funct6 [5:0] $end $var wire 7 0$ funct7 [6:0] $end $var wire 32 2$ imm [31:0] $end $var wire 32 '$ inst [31:0] $end $var wire 7 ($ opcode [6:0] $end $var wire 5 )$ rd [4:0] $end $var wire 5 *$ rs1 [4:0] $end $var wire 5 +$ rs2 [4:0] $end $var wire 5 ,$ rs3 [4:0] $end $upscope $end $upscope $end $upscope $end $scope interface next_system_command $end $var wire 89 w1 T_LOGIC [88:0] $end $var wire 1 M, clk $end $var wire 1 y# ready $end $var wire 1 N, rst $end $var wire 1 x# valid $end $scope struct payload $end $var wire 12 "$ csr [11:0] $end $var wire 32 }# imm_value [31:0] $end $var wire 2 |# jump_flag [1:0] $end $var wire 5 z# reg_addr [4:0] $end $var wire 3 {# reg_status [2:0] $end $var wire 32 ~# rs1_value [31:0] $end $var wire 3 !$ sys_op [2:0] $end $upscope $end $upscope $end $scope struct opcode_status $end $var wire 1 x) error_flag $end $var wire 1 t) execute_flag $end $var wire 1 w) exit_flag $end $var wire 1 v) float_flag $end $var wire 1 u) system_flag $end $upscope $end $scope struct operands_status $end $var wire 1 0" rd_valid $end $var wire 1 ." rs1_valid $end $var wire 1 /" rs2_valid $end $upscope $end $scope struct performance_stats_next $end $var wire 1 {! backend_stalled $end $var wire 1 z! frontend_stalled $end $var wire 1 y! instruction_control_stalled $end $var wire 1 x! instruction_data_stalled $end $var wire 1 w! instruction_mispredicted $end $upscope $end $scope module performance_stats_register_inst $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 N, rst $end $var wire 1 S" rst_actual $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct RESET_VECTOR $end $var wire 1 }/ backend_stalled $end $var wire 1 }/ frontend_stalled $end $var wire 1 }/ instruction_control_stalled $end $var wire 1 }/ instruction_data_stalled $end $var wire 1 }/ instruction_mispredicted $end $upscope $end $scope struct next $end $var wire 1 {! backend_stalled $end $var wire 1 z! frontend_stalled $end $var wire 1 y! instruction_control_stalled $end $var wire 1 x! instruction_data_stalled $end $var wire 1 w! instruction_mispredicted $end $upscope $end $scope struct value $end $var wire 1 q$ backend_stalled $end $var wire 1 p$ frontend_stalled $end $var wire 1 o$ instruction_control_stalled $end $var wire 1 n$ instruction_data_stalled $end $var wire 1 m$ instruction_mispredicted $end $upscope $end $upscope $end $scope struct performance_stats $end $var wire 1 q$ backend_stalled $end $var wire 1 p$ frontend_stalled $end $var wire 1 o$ instruction_control_stalled $end $var wire 1 n$ instruction_data_stalled $end $var wire 1 m$ instruction_mispredicted $end $upscope $end $scope module regfile $end $var wire 32 61 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 Z* rd_read_addr [4:0] $end $var wire 1 )# rd_read_enable $end $var wire 3 (" rd_read_status [2:0] $end $var wire 3 +" rd_read_status_front [2:0] $end $var wire 3 +" rd_status_front [2:0] $end $var wire 3 ,# rd_status_rear [2:0] $end $var wire 5 &" rd_write_addr [4:0] $end $var wire 1 $" rd_write_enable $end $var wire 3 _, rd_write_status [2:0] $end $var wire 32 '" rd_write_value [31:0] $end $var wire 1 %" rd_write_value_enable $end $var wire 1 y) reset_done $end $var wire 5 X* rs1_addr [4:0] $end $var wire 3 !" rs1_status [2:0] $end $var wire 3 *# rs1_status_front [2:0] $end $var wire 3 )" rs1_status_front_last [2:0] $end $var wire 3 -# rs1_status_rear [2:0] $end $var wire 32 }! rs1_value [31:0] $end $var wire 5 Y* rs2_addr [4:0] $end $var wire 3 "" rs2_status [2:0] $end $var wire 3 +# rs2_status_front [2:0] $end $var wire 3 *" rs2_status_front_last [2:0] $end $var wire 3 .# rs2_status_rear [2:0] $end $var wire 32 ~! rs2_value [31:0] $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module register_file_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 \/ AUTO_RESET $end $var wire 32 a1 AUTO_RESET_VALUE [31:0] $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 b/ READ_PORTS [31:0] $end $var wire 32 `1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 u* read_addr[0] [4:0] $end $var wire 5 v* read_addr[1] [4:0] $end $var wire 32 G# read_data_out[0] [31:0] $end $var wire 32 H# read_data_out[1] [31:0] $end $var wire 1 y) reset_done $end $var wire 1 N, rst $end $var wire 5 &" write_addr [4:0] $end $var wire 5 J# write_addr_internal [4:0] $end $var wire 32 '" write_data_in [31:0] $end $var wire 32 K# write_data_in_internal [31:0] $end $var wire 32 d, write_data_out [31:0] $end $var wire 1 %" write_enable $end $var wire 1 I# write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 x* clear_reset_state $end $var wire 5 y* current_reset_counter [4:0] $end $var wire 1 w* current_reset_state $end $var wire 5 z* next_reset_counter [4:0] $end $scope module reset_counter_reg_inst $end $var wire 5 V1 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 w* enable $end $var wire 5 z* next [4:0] $end $var wire 1 N, rst $end $var wire 1 L# rst_actual $end $var wire 5 y* value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module reset_state_reg_inst $end $var wire 1 W1 RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 x* enable $end $var wire 1 }/ next $end $var wire 1 N, rst $end $var wire 1 M# rst_actual $end $var wire 1 w* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 b/ READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 32 J. data[0] [31:0] $end $var wire 32 T. data[10] [31:0] $end $var wire 32 U. data[11] [31:0] $end $var wire 32 V. data[12] [31:0] $end $var wire 32 W. data[13] [31:0] $end $var wire 32 X. data[14] [31:0] $end $var wire 32 Y. data[15] [31:0] $end $var wire 32 Z. data[16] [31:0] $end $var wire 32 [. data[17] [31:0] $end $var wire 32 \. data[18] [31:0] $end $var wire 32 ]. data[19] [31:0] $end $var wire 32 K. data[1] [31:0] $end $var wire 32 ^. data[20] [31:0] $end $var wire 32 _. data[21] [31:0] $end $var wire 32 `. data[22] [31:0] $end $var wire 32 a. data[23] [31:0] $end $var wire 32 b. data[24] [31:0] $end $var wire 32 c. data[25] [31:0] $end $var wire 32 d. data[26] [31:0] $end $var wire 32 e. data[27] [31:0] $end $var wire 32 f. data[28] [31:0] $end $var wire 32 g. data[29] [31:0] $end $var wire 32 L. data[2] [31:0] $end $var wire 32 h. data[30] [31:0] $end $var wire 32 i. data[31] [31:0] $end $var wire 32 M. data[3] [31:0] $end $var wire 32 N. data[4] [31:0] $end $var wire 32 O. data[5] [31:0] $end $var wire 32 P. data[6] [31:0] $end $var wire 32 Q. data[7] [31:0] $end $var wire 32 R. data[8] [31:0] $end $var wire 32 S. data[9] [31:0] $end $var wire 5 u* read_addr[0] [4:0] $end $var wire 5 v* read_addr[1] [4:0] $end $var wire 32 G# read_data_out[0] [31:0] $end $var wire 32 H# read_data_out[1] [31:0] $end $var wire 1 N, rst $end $var wire 5 J# write_addr [4:0] $end $var wire 32 K# write_data_in [31:0] $end $var wire 32 d, write_data_out [31:0] $end $var wire 32 V$ write_enable [31:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 J i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 Z0 i [31:0] $end $upscope $end $upscope $end $upscope $end $scope module register_status_front_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 \/ AUTO_RESET $end $var wire 3 U1 AUTO_RESET_VALUE [2:0] $end $var wire 32 m0 DATA_WIDTH [31:0] $end $var wire 32 b/ READ_PORTS [31:0] $end $var wire 32 b1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 u* read_addr[0] [4:0] $end $var wire 5 v* read_addr[1] [4:0] $end $var wire 3 O# read_data_out[0] [2:0] $end $var wire 3 P# read_data_out[1] [2:0] $end $var wire 1 {* reset_done $end $var wire 1 N, rst $end $var wire 5 Z* write_addr [4:0] $end $var wire 5 |* write_addr_internal [4:0] $end $var wire 3 N# write_data_in [2:0] $end $var wire 3 R# write_data_in_internal [2:0] $end $var wire 3 +" write_data_out [2:0] $end $var wire 1 )# write_enable $end $var wire 1 Q# write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 ~* clear_reset_state $end $var wire 5 !+ current_reset_counter [4:0] $end $var wire 1 }* current_reset_state $end $var wire 5 "+ next_reset_counter [4:0] $end $scope module reset_counter_reg_inst $end $var wire 5 V1 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 }* enable $end $var wire 5 "+ next [4:0] $end $var wire 1 N, rst $end $var wire 1 S# rst_actual $end $var wire 5 !+ value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module reset_state_reg_inst $end $var wire 1 W1 RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 ~* enable $end $var wire 1 }/ next $end $var wire 1 N, rst $end $var wire 1 T# rst_actual $end $var wire 1 }* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 m0 DATA_WIDTH [31:0] $end $var wire 32 b/ READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 3 j. data[0] [2:0] $end $var wire 3 t. data[10] [2:0] $end $var wire 3 u. data[11] [2:0] $end $var wire 3 v. data[12] [2:0] $end $var wire 3 w. data[13] [2:0] $end $var wire 3 x. data[14] [2:0] $end $var wire 3 y. data[15] [2:0] $end $var wire 3 z. data[16] [2:0] $end $var wire 3 {. data[17] [2:0] $end $var wire 3 |. data[18] [2:0] $end $var wire 3 }. data[19] [2:0] $end $var wire 3 k. data[1] [2:0] $end $var wire 3 ~. data[20] [2:0] $end $var wire 3 !/ data[21] [2:0] $end $var wire 3 "/ data[22] [2:0] $end $var wire 3 #/ data[23] [2:0] $end $var wire 3 $/ data[24] [2:0] $end $var wire 3 %/ data[25] [2:0] $end $var wire 3 &/ data[26] [2:0] $end $var wire 3 '/ data[27] [2:0] $end $var wire 3 (/ data[28] [2:0] $end $var wire 3 )/ data[29] [2:0] $end $var wire 3 l. data[2] [2:0] $end $var wire 3 */ data[30] [2:0] $end $var wire 3 +/ data[31] [2:0] $end $var wire 3 m. data[3] [2:0] $end $var wire 3 n. data[4] [2:0] $end $var wire 3 o. data[5] [2:0] $end $var wire 3 p. data[6] [2:0] $end $var wire 3 q. data[7] [2:0] $end $var wire 3 r. data[8] [2:0] $end $var wire 3 s. data[9] [2:0] $end $var wire 5 u* read_addr[0] [4:0] $end $var wire 5 v* read_addr[1] [4:0] $end $var wire 3 O# read_data_out[0] [2:0] $end $var wire 3 P# read_data_out[1] [2:0] $end $var wire 1 N, rst $end $var wire 5 |* write_addr [4:0] $end $var wire 3 R# write_data_in [2:0] $end $var wire 3 +" write_data_out [2:0] $end $var wire 3 W$ write_enable [2:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 K i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 Z0 i [31:0] $end $upscope $end $upscope $end $upscope $end $scope module register_status_rear_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 \/ AUTO_RESET $end $var wire 3 U1 AUTO_RESET_VALUE [2:0] $end $var wire 32 m0 DATA_WIDTH [31:0] $end $var wire 32 m0 READ_PORTS [31:0] $end $var wire 32 c1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 u* read_addr[0] [4:0] $end $var wire 5 v* read_addr[1] [4:0] $end $var wire 5 #+ read_addr[2] [4:0] $end $var wire 3 U# read_data_out[0] [2:0] $end $var wire 3 V# read_data_out[1] [2:0] $end $var wire 3 W# read_data_out[2] [2:0] $end $var wire 1 $+ reset_done $end $var wire 1 N, rst $end $var wire 5 &" write_addr [4:0] $end $var wire 5 Y# write_addr_internal [4:0] $end $var wire 3 e, write_data_in [2:0] $end $var wire 3 Z# write_data_in_internal [2:0] $end $var wire 3 _, write_data_out [2:0] $end $var wire 1 $" write_enable $end $var wire 1 X# write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 &+ clear_reset_state $end $var wire 5 '+ current_reset_counter [4:0] $end $var wire 1 %+ current_reset_state $end $var wire 5 (+ next_reset_counter [4:0] $end $scope module reset_counter_reg_inst $end $var wire 5 V1 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 %+ enable $end $var wire 5 (+ next [4:0] $end $var wire 1 N, rst $end $var wire 1 [# rst_actual $end $var wire 5 '+ value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module reset_state_reg_inst $end $var wire 1 W1 RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 &+ enable $end $var wire 1 }/ next $end $var wire 1 N, rst $end $var wire 1 \# rst_actual $end $var wire 1 %+ value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 m0 DATA_WIDTH [31:0] $end $var wire 32 m0 READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 3 ,/ data[0] [2:0] $end $var wire 3 6/ data[10] [2:0] $end $var wire 3 7/ data[11] [2:0] $end $var wire 3 8/ data[12] [2:0] $end $var wire 3 9/ data[13] [2:0] $end $var wire 3 :/ data[14] [2:0] $end $var wire 3 ;/ data[15] [2:0] $end $var wire 3 / data[18] [2:0] $end $var wire 3 ?/ data[19] [2:0] $end $var wire 3 -/ data[1] [2:0] $end $var wire 3 @/ data[20] [2:0] $end $var wire 3 A/ data[21] [2:0] $end $var wire 3 B/ data[22] [2:0] $end $var wire 3 C/ data[23] [2:0] $end $var wire 3 D/ data[24] [2:0] $end $var wire 3 E/ data[25] [2:0] $end $var wire 3 F/ data[26] [2:0] $end $var wire 3 G/ data[27] [2:0] $end $var wire 3 H/ data[28] [2:0] $end $var wire 3 I/ data[29] [2:0] $end $var wire 3 ./ data[2] [2:0] $end $var wire 3 J/ data[30] [2:0] $end $var wire 3 K/ data[31] [2:0] $end $var wire 3 // data[3] [2:0] $end $var wire 3 0/ data[4] [2:0] $end $var wire 3 1/ data[5] [2:0] $end $var wire 3 2/ data[6] [2:0] $end $var wire 3 3/ data[7] [2:0] $end $var wire 3 4/ data[8] [2:0] $end $var wire 3 5/ data[9] [2:0] $end $var wire 5 u* read_addr[0] [4:0] $end $var wire 5 v* read_addr[1] [4:0] $end $var wire 5 #+ read_addr[2] [4:0] $end $var wire 3 U# read_data_out[0] [2:0] $end $var wire 3 V# read_data_out[1] [2:0] $end $var wire 3 W# read_data_out[2] [2:0] $end $var wire 1 N, rst $end $var wire 5 Y# write_addr [4:0] $end $var wire 3 Z# write_data_in [2:0] $end $var wire 3 _, write_data_out [2:0] $end $var wire 3 X$ write_enable [2:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 L i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 /2 i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct rs1_rs2_status $end $var wire 5 3" rs1_addr [4:0] $end $var wire 1 1" rs1_valid $end $var wire 32 5" rs1_value [31:0] $end $var wire 5 4" rs2_addr [4:0] $end $var wire 1 2" rs2_valid $end $var wire 32 6" rs2_value [31:0] $end $upscope $end $scope module speculator $end $var wire 32 b/ COUNTER_WIDTH [31:0] $end $var wire 32 a/ HISTORY_DEPTH [31:0] $end $var wire 32 &1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 2 z) execute_flag [1:0] $end $var wire 2 2* front_flag [1:0] $end $var wire 2 U" front_flag_next [1:0] $end $var wire 1 -" instruction_branch_jump $end $var wire 1 T" instruction_enable $end $var wire 1 0* instruction_updated $end $var wire 1 {) mispredicted $end $var wire 1 ]$ mispredicted_next $end $var wire 2 3* rear_flag [1:0] $end $var wire 2 V" rear_flag_next [1:0] $end $var wire 1 '1 reset_done $end $var wire 1 N, rst $end $var wire 1 |) speculating $end $var wire 1 }) speculation_full $end $var wire 1 1* speculation_mispredicted $end $var wire 1 M% speculation_resolved $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module front_flag_register_inst $end $var wire 2 (1 RESET_VECTOR [1:0] $end $var wire 1 M, clk $end $var wire 1 T" enable $end $var wire 2 U" next [1:0] $end $var wire 1 N, rst $end $var wire 1 W" rst_actual $end $var wire 2 2* value [1:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module mispredicted_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 ]$ next $end $var wire 1 N, rst $end $var wire 1 X" rst_actual $end $var wire 1 {) value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module rear_flag_register_inst $end $var wire 2 (1 RESET_VECTOR [1:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 2 V" next [1:0] $end $var wire 1 N, rst $end $var wire 1 Y" rst_actual $end $var wire 2 3* value [1:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope struct stream_controller_result $end $var wire 1 o! enable $end $var wire 8 m! ready_input [7:0] $end $var wire 8 n! valid_output [7:0] $end $upscope $end $scope interface system_command $end $var wire 89 w1 T_LOGIC [88:0] $end $var wire 1 M, clk $end $var wire 1 w# ready $end $var wire 1 N, rst $end $var wire 1 7* valid $end $scope struct payload $end $var wire 12 P+ csr [11:0] $end $var wire 32 M+ imm_value [31:0] $end $var wire 2 L+ jump_flag [1:0] $end $var wire 5 J+ reg_addr [4:0] $end $var wire 3 K+ reg_status [2:0] $end $var wire 32 N+ rs1_value [31:0] $end $var wire 3 O+ sys_op [2:0] $end $upscope $end $upscope $end $scope module system_operation_stream_stage_inst $end $var wire 32 *1 PAYLOAD_WIDTH [31:0] $end $var wire 2 )1 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 Z" payload_enable $end $var wire 1 [" valid_enable $end $scope module payload_register_inst $end $var wire 89 +1 RESET_VECTOR [88:0] $end $var wire 1 M, clk $end $var wire 1 Z" enable $end $var wire 89 \" next [88:0] $end $var wire 1 B rst $end $var wire 1 C rst_actual $end $var wire 89 4* value [88:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 [" enable $end $var wire 1 Z" next $end $var wire 1 N, rst $end $var wire 1 _" rst_actual $end $var wire 1 7* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 89 w1 T_LOGIC [88:0] $end $var wire 1 M, clk $end $var wire 1 y# ready $end $var wire 1 N, rst $end $var wire 1 x# valid $end $scope struct payload $end $var wire 12 "$ csr [11:0] $end $var wire 32 }# imm_value [31:0] $end $var wire 2 |# jump_flag [1:0] $end $var wire 5 z# reg_addr [4:0] $end $var wire 3 {# reg_status [2:0] $end $var wire 32 ~# rs1_value [31:0] $end $var wire 3 !$ sys_op [2:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 89 w1 T_LOGIC [88:0] $end $var wire 1 M, clk $end $var wire 1 w# ready $end $var wire 1 N, rst $end $var wire 1 7* valid $end $scope struct payload $end $var wire 12 P+ csr [11:0] $end $var wire 32 M+ imm_value [31:0] $end $var wire 2 L+ jump_flag [1:0] $end $var wire 5 J+ reg_addr [4:0] $end $var wire 3 K+ reg_status [2:0] $end $var wire 32 N+ rs1_value [31:0] $end $var wire 3 O+ sys_op [2:0] $end $upscope $end $upscope $end $upscope $end $scope struct writeback_in $end $var wire 5 b) addr [4:0] $end $var wire 2 d) jump_flag [1:0] $end $var wire 1 f) mispredicted $end $var wire 3 c) reg_status [2:0] $end $var wire 32 e) value [31:0] $end $upscope $end $scope interface writeback_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 U* valid $end $scope struct payload $end $var wire 5 b) addr [4:0] $end $var wire 2 d) jump_flag [1:0] $end $var wire 1 f) mispredicted $end $var wire 3 c) reg_status [2:0] $end $var wire 32 e) value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module gecko_execute_inst $end $var wire 1 Q/ ENABLE_INTEGER_MATH $end $var wire 2 p/ PIPELINE_MODE [1:0] $end $var wire 32 o/ TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 1 +% consume $end $var wire 32 0% current_execute_value [31:0] $end $var wire 6 1% current_iteration [5:0] $end $var wire 1 [ enable $end $var wire 1 '% instruction_executed $end $var wire 1 [$ instruction_executed_next $end $var wire 1 ?% mispredicted $end $var wire 1 @% mispredicted_next $end $var wire 6 2% next_iteration [5:0] $end $var wire 1 .% produce_execute $end $var wire 1 /% produce_jump $end $var wire 1 ,% produce_mem_command $end $var wire 1 -% produce_mem_request $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct current_math_op $end $var wire 1 8% done $end $var wire 1 7% flag $end $var wire 3 3% math_op [2:0] $end $var wire 32 4% operand_value [31:0] $end $var wire 32 5% operator_value [31:0] $end $var wire 32 6% result [31:0] $end $upscope $end $scope interface execute_command $end $var wire 250 o1 T_LOGIC [249:0] $end $var wire 1 M, clk $end $var wire 1 k ready $end $var wire 1 N, rst $end $var wire 1 X% valid $end $scope struct payload $end $var wire 1 <+ alu_alternate $end $var wire 32 F+ current_pc [31:0] $end $var wire 1 9+ halt $end $var wire 32 E+ immediate_value [31:0] $end $var wire 2 7+ jump_flag [1:0] $end $var wire 32 D+ jump_value [31:0] $end $var wire 32 C+ mem_value [31:0] $end $var wire 32 G+ next_pc [31:0] $end $var wire 3 :+ op_type [2:0] $end $var wire 1 8+ pc_updated $end $var wire 5 5+ reg_addr [4:0] $end $var wire 3 6+ reg_status [2:0] $end $var wire 1 @+ reuse_jump $end $var wire 1 ?+ reuse_mem $end $var wire 1 =+ reuse_rs1 $end $var wire 1 >+ reuse_rs2 $end $var wire 32 A+ rs1_value [31:0] $end $var wire 32 B+ rs2_value [31:0] $end $scope union op $end $var wire 3 ;+ b [2:0] $end $var wire 3 ;+ ir [2:0] $end $var wire 3 ;+ ls [2:0] $end $var wire 3 ;+ sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 I+ history [1:0] $end $var wire 1 H+ miss $end $upscope $end $upscope $end $upscope $end $scope module execute_result_output_stage $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 q/ PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 \ payload_enable $end $var wire 1 ] valid_enable $end $scope module payload_register_inst $end $var wire 43 s/ RESET_VECTOR [42:0] $end $var wire 1 M, clk $end $var wire 1 \ enable $end $var wire 43 A% next [42:0] $end $var wire 1 % rst $end $var wire 1 & rst_actual $end $var wire 43 C% value [42:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 ] enable $end $var wire 1 \ next $end $var wire 1 N, rst $end $var wire 1 ^ rst_actual $end $var wire 1 E% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 C$ ready $end $var wire 1 N, rst $end $var wire 1 B$ valid $end $scope struct payload $end $var wire 5 w+ addr [4:0] $end $var wire 2 y+ jump_flag [1:0] $end $var wire 1 {+ mispredicted $end $var wire 3 x+ reg_status [2:0] $end $var wire 32 z+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface execute_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope module execute_value_register $end $var wire 32 u/ RESET_VECTOR [31:0] $end $var wire 1 M, clk $end $var wire 1 \$ enable $end $var wire 32 F% next [31:0] $end $var wire 1 ' rst $end $var wire 1 ( rst_actual $end $var wire 32 0% value [31:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module instruction_executed_register $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 [$ next $end $var wire 1 N, rst $end $var wire 1 _ rst_actual $end $var wire 1 '% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module iteration_register $end $var wire 6 v/ RESET_VECTOR [5:0] $end $var wire 1 M, clk $end $var wire 1 [ enable $end $var wire 6 2% next [5:0] $end $var wire 1 N, rst $end $var wire 1 ` rst_actual $end $var wire 6 1% value [5:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module jump_command_output_stage $end $var wire 32 x/ PAYLOAD_WIDTH [31:0] $end $var wire 2 w/ PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 a payload_enable $end $var wire 1 b valid_enable $end $scope module payload_register_inst $end $var wire 72 y/ RESET_VECTOR [71:0] $end $var wire 1 M, clk $end $var wire 1 a enable $end $var wire 72 G% next [71:0] $end $var wire 1 ) rst $end $var wire 1 * rst_actual $end $var wire 72 J% value [71:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 b enable $end $var wire 1 a next $end $var wire 1 N, rst $end $var wire 1 c rst_actual $end $var wire 1 M% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 _# valid $end $scope struct payload $end $var wire 32 0+ actual_next_pc [31:0] $end $var wire 1 -+ branched $end $var wire 32 /+ current_pc [31:0] $end $var wire 1 3+ halt $end $var wire 1 .+ jumped $end $var wire 1 4+ mispredicted $end $var wire 1 ,+ update_pc $end $scope struct prediction $end $var wire 2 2+ history [1:0] $end $var wire 1 1+ miss $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 M% valid $end $scope struct payload $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface jump_command $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 M% valid $end $scope struct payload $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $upscope $end $scope module math_op_register $end $var wire 1 M, clk $end $var wire 1 [ enable $end $var wire 1 + rst $end $var wire 1 , rst_actual $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct RESET_VECTOR $end $var wire 1 }/ done $end $var wire 1 }/ flag $end $var wire 3 |/ math_op [2:0] $end $var wire 32 R/ operand_value [31:0] $end $var wire 32 R/ operator_value [31:0] $end $var wire 32 R/ result [31:0] $end $upscope $end $scope struct next $end $var wire 1 >% done $end $var wire 1 =% flag $end $var wire 3 9% math_op [2:0] $end $var wire 32 :% operand_value [31:0] $end $var wire 32 ;% operator_value [31:0] $end $var wire 32 <% result [31:0] $end $upscope $end $scope struct value $end $var wire 1 8% done $end $var wire 1 7% flag $end $var wire 3 3% math_op [2:0] $end $var wire 32 4% operand_value [31:0] $end $var wire 32 5% operator_value [31:0] $end $var wire 32 6% result [31:0] $end $upscope $end $upscope $end $scope module mem_command_output_stage $end $var wire 32 ]/ PAYLOAD_WIDTH [31:0] $end $var wire 2 ~/ PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 d payload_enable $end $var wire 1 e valid_enable $end $scope module payload_register_inst $end $var wire 16 n/ RESET_VECTOR [15:0] $end $var wire 1 M, clk $end $var wire 1 d enable $end $var wire 16 N% next [15:0] $end $var wire 1 - rst $end $var wire 1 . rst_actual $end $var wire 16 (% value [15:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e enable $end $var wire 1 d next $end $var wire 1 N, rst $end $var wire 1 f rst_actual $end $var wire 1 O% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 P$ ready $end $var wire 1 N, rst $end $var wire 1 O$ valid $end $scope struct payload $end $var wire 5 /, addr [4:0] $end $var wire 2 1, jump_flag [1:0] $end $var wire 1 4, mispredicted $end $var wire 2 3, offset [1:0] $end $var wire 3 2, op [2:0] $end $var wire 3 0, reg_status [2:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 N$ ready $end $var wire 1 N, rst $end $var wire 1 O% valid $end $scope struct payload $end $var wire 5 #, addr [4:0] $end $var wire 2 %, jump_flag [1:0] $end $var wire 1 (, mispredicted $end $var wire 2 ', offset [1:0] $end $var wire 3 &, op [2:0] $end $var wire 3 $, reg_status [2:0] $end $upscope $end $upscope $end $upscope $end $scope interface mem_command $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 N$ ready $end $var wire 1 N, rst $end $var wire 1 O% valid $end $scope struct payload $end $var wire 5 #, addr [4:0] $end $var wire 2 %, jump_flag [1:0] $end $var wire 1 (, mispredicted $end $var wire 2 ', offset [1:0] $end $var wire 3 &, op [2:0] $end $var wire 3 $, reg_status [2:0] $end $upscope $end $upscope $end $scope module mem_request_output_stage $end $var wire 32 $0 ADDR_WIDTH [31:0] $end $var wire 32 `/ ADDR_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 ADDR_WIDTH_OVERRIDE [31:0] $end $var wire 32 $0 DATA_WIDTH [31:0] $end $var wire 32 `/ DATA_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 DATA_WIDTH_OVERRIDE [31:0] $end $var wire 32 &0 ID_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 ID_WIDTH_OVERRIDE [31:0] $end $var wire 32 %0 MASK_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH_INTERNAL [31:0] $end $var wire 32 _/ META_WIDTH [31:0] $end $var wire 2 !0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 #0 mem_in_meta [0:0] $end $var wire 1 P% mem_out_meta [0:0] $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface mem_in $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 g* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 h* data [31:0] $end $var wire 1 Q1 id [0:0] $end $var wire 1 R1 last $end $var wire 1 e* read_enable $end $var wire 1 5# ready $end $var wire 1 N, rst $end $var wire 1 4# valid $end $var wire 4 f* write_enable [3:0] $end $upscope $end $scope interface mem_out $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 ^* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 6) data [31:0] $end $var wire 1 h$ id [0:0] $end $var wire 1 j$ last $end $var wire 1 ]* read_enable $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $var wire 4 4) write_enable [3:0] $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 5# ready $end $var wire 1 N, rst $end $var wire 1 4# valid $end $scope struct payload $end $var wire 32 D, addr [31:0] $end $var wire 32 E, data [31:0] $end $var wire 1 .2 id [0:0] $end $var wire 1 R1 last $end $var wire 1 }/ meta [0:0] $end $var wire 1 e* read_enable $end $var wire 4 C, write_enable [3:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $scope struct payload $end $var wire 32 H, addr [31:0] $end $var wire 32 I, data [31:0] $end $var wire 1 J, id [0:0] $end $var wire 1 K, last $end $var wire 1 L, meta [0:0] $end $var wire 1 F, read_enable $end $var wire 4 G, write_enable [3:0] $end $upscope $end $upscope $end $scope module stream_stage_inst $end $var wire 32 x/ PAYLOAD_WIDTH [31:0] $end $var wire 2 '0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 g payload_enable $end $var wire 1 h valid_enable $end $scope module payload_register_inst $end $var wire 72 y/ RESET_VECTOR [71:0] $end $var wire 1 M, clk $end $var wire 1 g enable $end $var wire 72 Q% next [71:0] $end $var wire 1 / rst $end $var wire 1 0 rst_actual $end $var wire 72 T% value [71:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 h enable $end $var wire 1 g next $end $var wire 1 N, rst $end $var wire 1 i rst_actual $end $var wire 1 W% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 5# ready $end $var wire 1 N, rst $end $var wire 1 4# valid $end $scope struct payload $end $var wire 32 D, addr [31:0] $end $var wire 32 E, data [31:0] $end $var wire 1 .2 id [0:0] $end $var wire 1 R1 last $end $var wire 1 }/ meta [0:0] $end $var wire 1 e* read_enable $end $var wire 4 C, write_enable [3:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $scope struct payload $end $var wire 32 H, addr [31:0] $end $var wire 32 I, data [31:0] $end $var wire 1 J, id [0:0] $end $var wire 1 K, last $end $var wire 1 L, meta [0:0] $end $var wire 1 F, read_enable $end $var wire 4 G, write_enable [3:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface mem_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 ^* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 6) data [31:0] $end $var wire 1 h$ id [0:0] $end $var wire 1 j$ last $end $var wire 1 ]* read_enable $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $var wire 4 4) write_enable [3:0] $end $upscope $end $scope module mispredicted_register $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 [ enable $end $var wire 1 @% next $end $var wire 1 N, rst $end $var wire 1 j rst_actual $end $var wire 1 ?% value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope interface next_execute_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 C$ ready $end $var wire 1 N, rst $end $var wire 1 B$ valid $end $scope struct payload $end $var wire 5 w+ addr [4:0] $end $var wire 2 y+ jump_flag [1:0] $end $var wire 1 {+ mispredicted $end $var wire 3 x+ reg_status [2:0] $end $var wire 32 z+ value [31:0] $end $upscope $end $upscope $end $scope interface next_jump_command $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 _# valid $end $scope struct payload $end $var wire 32 0+ actual_next_pc [31:0] $end $var wire 1 -+ branched $end $var wire 32 /+ current_pc [31:0] $end $var wire 1 3+ halt $end $var wire 1 .+ jumped $end $var wire 1 4+ mispredicted $end $var wire 1 ,+ update_pc $end $scope struct prediction $end $var wire 2 2+ history [1:0] $end $var wire 1 1+ miss $end $upscope $end $upscope $end $upscope $end $scope struct next_math_op $end $var wire 1 >% done $end $var wire 1 =% flag $end $var wire 3 9% math_op [2:0] $end $var wire 32 :% operand_value [31:0] $end $var wire 32 ;% operator_value [31:0] $end $var wire 32 <% result [31:0] $end $upscope $end $scope interface next_mem_command $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 P$ ready $end $var wire 1 N, rst $end $var wire 1 O$ valid $end $scope struct payload $end $var wire 5 /, addr [4:0] $end $var wire 2 1, jump_flag [1:0] $end $var wire 1 4, mispredicted $end $var wire 2 3, offset [1:0] $end $var wire 3 2, op [2:0] $end $var wire 3 0, reg_status [2:0] $end $upscope $end $upscope $end $scope interface next_mem_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 g* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 h* data [31:0] $end $var wire 1 Q1 id [0:0] $end $var wire 1 R1 last $end $var wire 1 e* read_enable $end $var wire 1 5# ready $end $var wire 1 N, rst $end $var wire 1 4# valid $end $var wire 4 f* write_enable [3:0] $end $upscope $end $scope module stream_controller_inst $end $var wire 32 _/ NUM_INPUTS [31:0] $end $var wire 32 a/ NUM_OUTPUTS [31:0] $end $var wire 1 M, clk $end $var wire 1 +% consume [0:0] $end $var wire 1 [ enable $end $var wire 1 Z% input_enable $end $var wire 1 e/ input_enables [0:0] $end $var wire 1 n output_enable $end $var wire 4 o output_enables [3:0] $end $var wire 4 Y% produce [3:0] $end $var wire 1 k ready_input [0:0] $end $var wire 4 m ready_output [3:0] $end $var wire 1 N, rst $end $var wire 1 X% valid_input [0:0] $end $var wire 4 l valid_output [3:0] $end $scope module unnamedblk1 $end $var wire 32 (0 i [31:0] $end $scope module unnamedblk2 $end $var wire 32 (0 j [31:0] $end $upscope $end $upscope $end $scope module unnamedblk3 $end $var wire 32 )0 i [31:0] $end $scope module unnamedblk4 $end $var wire 32 )0 j [31:0] $end $upscope $end $upscope $end $scope module unnamedblk5 $end $var wire 32 (0 i [31:0] $end $upscope $end $scope module unnamedblk6 $end $var wire 32 )0 i [31:0] $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 [% a [31:0] $end $var wire 1 t% alt $end $var wire 32 \% b [31:0] $end $var wire 32 ]% c [31:0] $end $var wire 32 ^% d [31:0] $end $scope struct alu_result $end $var wire 32 u% add_sub_result [31:0] $end $var wire 32 w% and_result [31:0] $end $var wire 1 {% eq $end $var wire 32 y% lshift_result [31:0] $end $var wire 1 |% lt $end $var wire 1 }% ltu $end $var wire 32 v% or_result [31:0] $end $var wire 32 z% rshift_result [31:0] $end $var wire 32 x% xor_result [31:0] $end $upscope $end $scope struct cmd_in $end $var wire 1 f% alu_alternate $end $var wire 32 p% current_pc [31:0] $end $var wire 1 c% halt $end $var wire 32 o% immediate_value [31:0] $end $var wire 2 a% jump_flag [1:0] $end $var wire 32 n% jump_value [31:0] $end $var wire 32 m% mem_value [31:0] $end $var wire 32 q% next_pc [31:0] $end $var wire 3 d% op_type [2:0] $end $var wire 1 b% pc_updated $end $var wire 5 _% reg_addr [4:0] $end $var wire 3 `% reg_status [2:0] $end $var wire 1 j% reuse_jump $end $var wire 1 i% reuse_mem $end $var wire 1 g% reuse_rs1 $end $var wire 1 h% reuse_rs2 $end $var wire 32 k% rs1_value [31:0] $end $var wire 32 l% rs2_value [31:0] $end $scope union op $end $var wire 3 e% b [2:0] $end $var wire 3 e% ir [2:0] $end $var wire 3 e% ls [2:0] $end $var wire 3 e% sys [2:0] $end $upscope $end $scope struct prediction $end $var wire 2 s% history [1:0] $end $var wire 1 r% miss $end $upscope $end $upscope $end $scope struct math_op $end $var wire 1 /0 done $end $var wire 1 .0 flag $end $var wire 3 *0 math_op [2:0] $end $var wire 32 +0 operand_value [31:0] $end $var wire 32 ,0 operator_value [31:0] $end $var wire 32 -0 result [31:0] $end $upscope $end $scope struct store_result $end $var wire 4 !& mask [3:0] $end $var wire 32 ~% value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module gecko_fetch_inst $end $var wire 2 f0 PIPELINE_MODE [1:0] $end $var wire 32 g0 START_ADDR [31:0] $end $var wire 32 e0 TECHNOLOGY [31:0] $end $var wire 1 8) branch_table_reset_done $end $var wire 1 M, clk $end $var wire 1 b! enable $end $var wire 1 ;) halt_flag $end $var wire 32 9) pc [31:0] $end $var wire 32 d! pc_next [31:0] $end $var wire 1 :) pc_updated $end $var wire 1 e! pc_updated_next $end $var wire 2 i! predictor_history [1:0] $end $var wire 32 h! predictor_prediction [31:0] $end $var wire 1 g! predictor_taken $end $var wire 1 f! predictor_valid $end $var wire 1 c! produce $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct PREDICTOR_CONFIG $end $var wire 32 Z/ history_width [31:0] $end $var wire 32 [/ local_addr_width [31:0] $end $var wire 2 X/ mode [1:0] $end $var wire 32 Y/ target_addr_width [31:0] $end $upscope $end $scope module halt_flag_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 <) enable $end $var wire 1 =) next $end $var wire 1 N, rst $end $var wire 1 j! rst_actual $end $var wire 1 ;) value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module instruction_command_stage_inst $end $var wire 32 20 PAYLOAD_WIDTH [31:0] $end $var wire 2 h0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface instruction_command $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $scope module instruction_request_stage_inst $end $var wire 32 $0 ADDR_WIDTH [31:0] $end $var wire 32 `/ ADDR_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 ADDR_WIDTH_OVERRIDE [31:0] $end $var wire 32 $0 DATA_WIDTH [31:0] $end $var wire 32 `/ DATA_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 DATA_WIDTH_OVERRIDE [31:0] $end $var wire 32 &0 ID_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 ID_WIDTH_OVERRIDE [31:0] $end $var wire 32 %0 MASK_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH_INTERNAL [31:0] $end $var wire 32 _/ META_WIDTH [31:0] $end $var wire 2 i0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 #0 mem_in_meta [0:0] $end $var wire 1 >) mem_out_meta [0:0] $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface mem_in $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 9) addr [31:0] $end $var wire 1 M, clk $end $var wire 32 R/ data [31:0] $end $var wire 1 O1 id [0:0] $end $var wire 1 P1 last $end $var wire 1 e/ read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 N1 write_enable [3:0] $end $upscope $end $scope interface mem_out $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 \* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 2) data [31:0] $end $var wire 1 c$ id [0:0] $end $var wire 1 e$ last $end $var wire 1 [* read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 0) write_enable [3:0] $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $scope struct payload $end $var wire 32 7, addr [31:0] $end $var wire 32 8, data [31:0] $end $var wire 1 9, id [0:0] $end $var wire 1 :, last $end $var wire 1 ;, meta [0:0] $end $var wire 1 5, read_enable $end $var wire 4 6, write_enable [3:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $scope struct payload $end $var wire 32 7, addr [31:0] $end $var wire 32 8, data [31:0] $end $var wire 1 9, id [0:0] $end $var wire 1 :, last $end $var wire 1 ;, meta [0:0] $end $var wire 1 5, read_enable $end $var wire 4 6, write_enable [3:0] $end $upscope $end $upscope $end $scope module stream_stage_inst $end $var wire 32 x/ PAYLOAD_WIDTH [31:0] $end $var wire 2 b0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $scope struct payload $end $var wire 32 7, addr [31:0] $end $var wire 32 8, data [31:0] $end $var wire 1 9, id [0:0] $end $var wire 1 :, last $end $var wire 1 ;, meta [0:0] $end $var wire 1 5, read_enable $end $var wire 4 6, write_enable [3:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $scope struct payload $end $var wire 32 7, addr [31:0] $end $var wire 32 8, data [31:0] $end $var wire 1 9, id [0:0] $end $var wire 1 :, last $end $var wire 1 ;, meta [0:0] $end $var wire 1 5, read_enable $end $var wire 4 6, write_enable [3:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface instruction_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 \* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 2) data [31:0] $end $var wire 1 c$ id [0:0] $end $var wire 1 e$ last $end $var wire 1 [* read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 0) write_enable [3:0] $end $upscope $end $scope interface jump_command $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 M% valid $end $scope struct payload $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $upscope $end $scope interface next_instruction_command $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $scope interface next_instruction_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 9) addr [31:0] $end $var wire 1 M, clk $end $var wire 32 R/ data [31:0] $end $var wire 1 O1 id [0:0] $end $var wire 1 P1 last $end $var wire 1 e/ read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 N1 write_enable [3:0] $end $upscope $end $scope module pc_register_inst $end $var wire 32 j0 RESET_VECTOR [31:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 32 d! next [31:0] $end $var wire 1 N, rst $end $var wire 1 k! rst_actual $end $var wire 32 9) value [31:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module pc_updated_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 e! next $end $var wire 1 N, rst $end $var wire 1 l! rst_actual $end $var wire 1 :) value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module predictor $end $var wire 32 41 BRANCH_TAG_WIDTH [31:0] $end $var wire 32 31 TECHNOLOGY [31:0] $end $var wire 5 y" branch_table_write_addr [4:0] $end $var wire 1 x" branch_table_write_enable $end $var wire 1 M, clk $end $var wire 5 V* current_global_history [4:0] $end $var wire 5 W* history_table_addr [4:0] $end $var wire 2 ^, history_table_data [1:0] $end $var wire 5 y" history_table_update_addr [4:0] $end $var wire 2 '# history_table_update_data [1:0] $end $var wire 5 &# local_history_result [4:0] $end $var wire 5 ], local_history_update_read_data [4:0] $end $var wire 5 %# local_history_update_write_data [4:0] $end $var wire 5 $# next_global_history [4:0] $end $var wire 32 9) pc [31:0] $end $var wire 2 i! predictor_history [1:0] $end $var wire 32 h! predictor_prediction [31:0] $end $var wire 1 g! predictor_taken $end $var wire 1 f! predictor_valid $end $var wire 1 8) reset_done $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope struct PREDICTOR_CONFIG $end $var wire 32 Z/ history_width [31:0] $end $var wire 32 [/ local_addr_width [31:0] $end $var wire 2 X/ mode [1:0] $end $var wire 32 Y/ target_addr_width [31:0] $end $upscope $end $scope module branch_history_table_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 Q/ AUTO_RESET $end $var wire 2 _1 AUTO_RESET_VALUE [1:0] $end $var wire 32 b/ DATA_WIDTH [31:0] $end $var wire 32 _/ READ_PORTS [31:0] $end $var wire 32 ^1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 t* read_addr[0] [4:0] $end $var wire 2 ^, read_data_out[0] [1:0] $end $var wire 1 e/ reset_done $end $var wire 1 N, rst $end $var wire 5 y" write_addr [4:0] $end $var wire 5 y" write_addr_internal [4:0] $end $var wire 2 '# write_data_in [1:0] $end $var wire 2 '# write_data_in_internal [1:0] $end $var wire 2 c, write_data_out [1:0] $end $var wire 1 x" write_enable $end $var wire 1 x" write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 b/ DATA_WIDTH [31:0] $end $var wire 32 _/ READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 2 *. data[0] [1:0] $end $var wire 2 4. data[10] [1:0] $end $var wire 2 5. data[11] [1:0] $end $var wire 2 6. data[12] [1:0] $end $var wire 2 7. data[13] [1:0] $end $var wire 2 8. data[14] [1:0] $end $var wire 2 9. data[15] [1:0] $end $var wire 2 :. data[16] [1:0] $end $var wire 2 ;. data[17] [1:0] $end $var wire 2 <. data[18] [1:0] $end $var wire 2 =. data[19] [1:0] $end $var wire 2 +. data[1] [1:0] $end $var wire 2 >. data[20] [1:0] $end $var wire 2 ?. data[21] [1:0] $end $var wire 2 @. data[22] [1:0] $end $var wire 2 A. data[23] [1:0] $end $var wire 2 B. data[24] [1:0] $end $var wire 2 C. data[25] [1:0] $end $var wire 2 D. data[26] [1:0] $end $var wire 2 E. data[27] [1:0] $end $var wire 2 F. data[28] [1:0] $end $var wire 2 G. data[29] [1:0] $end $var wire 2 ,. data[2] [1:0] $end $var wire 2 H. data[30] [1:0] $end $var wire 2 I. data[31] [1:0] $end $var wire 2 -. data[3] [1:0] $end $var wire 2 .. data[4] [1:0] $end $var wire 2 /. data[5] [1:0] $end $var wire 2 0. data[6] [1:0] $end $var wire 2 1. data[7] [1:0] $end $var wire 2 2. data[8] [1:0] $end $var wire 2 3. data[9] [1:0] $end $var wire 5 t* read_addr[0] [4:0] $end $var wire 2 ^, read_data_out[0] [1:0] $end $var wire 1 N, rst $end $var wire 5 y" write_addr [4:0] $end $var wire 2 '# write_data_in [1:0] $end $var wire 2 c, write_data_out [1:0] $end $var wire 2 U$ write_enable [1:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 I i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 )0 i [31:0] $end $upscope $end $upscope $end $upscope $end $scope struct branch_table_read_data $end $var wire 1 ## jump_instruction $end $var wire 32 !# predicted_next [31:0] $end $var wire 25 "# tag [24:0] $end $var wire 1 ~" valid $end $upscope $end $scope struct branch_table_write_data $end $var wire 1 }" jump_instruction $end $var wire 32 {" predicted_next [31:0] $end $var wire 25 |" tag [24:0] $end $var wire 1 z" valid $end $upscope $end $scope module branch_target_table_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 \/ AUTO_RESET $end $var wire 59 Z1 AUTO_RESET_VALUE [58:0] $end $var wire 32 Y1 DATA_WIDTH [31:0] $end $var wire 32 _/ READ_PORTS [31:0] $end $var wire 32 X1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 m* read_addr[0] [4:0] $end $var wire 59 ># read_data_out[0] [58:0] $end $var wire 1 8) reset_done $end $var wire 1 N, rst $end $var wire 5 y" write_addr [4:0] $end $var wire 5 A# write_addr_internal [4:0] $end $var wire 59 <# write_data_in [58:0] $end $var wire 59 B# write_data_in_internal [58:0] $end $var wire 59 a, write_data_out [58:0] $end $var wire 1 x" write_enable $end $var wire 1 @# write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 o* clear_reset_state $end $var wire 5 p* current_reset_counter [4:0] $end $var wire 1 n* current_reset_state $end $var wire 5 q* next_reset_counter [4:0] $end $scope module reset_counter_reg_inst $end $var wire 5 V1 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 n* enable $end $var wire 5 q* next [4:0] $end $var wire 1 N, rst $end $var wire 1 D# rst_actual $end $var wire 5 p* value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module reset_state_reg_inst $end $var wire 1 W1 RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 o* enable $end $var wire 1 }/ next $end $var wire 1 N, rst $end $var wire 1 E# rst_actual $end $var wire 1 n* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 Y1 DATA_WIDTH [31:0] $end $var wire 32 _/ READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 59 (- data[0] [58:0] $end $var wire 59 <- data[10] [58:0] $end $var wire 59 >- data[11] [58:0] $end $var wire 59 @- data[12] [58:0] $end $var wire 59 B- data[13] [58:0] $end $var wire 59 D- data[14] [58:0] $end $var wire 59 F- data[15] [58:0] $end $var wire 59 H- data[16] [58:0] $end $var wire 59 J- data[17] [58:0] $end $var wire 59 L- data[18] [58:0] $end $var wire 59 N- data[19] [58:0] $end $var wire 59 *- data[1] [58:0] $end $var wire 59 P- data[20] [58:0] $end $var wire 59 R- data[21] [58:0] $end $var wire 59 T- data[22] [58:0] $end $var wire 59 V- data[23] [58:0] $end $var wire 59 X- data[24] [58:0] $end $var wire 59 Z- data[25] [58:0] $end $var wire 59 \- data[26] [58:0] $end $var wire 59 ^- data[27] [58:0] $end $var wire 59 `- data[28] [58:0] $end $var wire 59 b- data[29] [58:0] $end $var wire 59 ,- data[2] [58:0] $end $var wire 59 d- data[30] [58:0] $end $var wire 59 f- data[31] [58:0] $end $var wire 59 .- data[3] [58:0] $end $var wire 59 0- data[4] [58:0] $end $var wire 59 2- data[5] [58:0] $end $var wire 59 4- data[6] [58:0] $end $var wire 59 6- data[7] [58:0] $end $var wire 59 8- data[8] [58:0] $end $var wire 59 :- data[9] [58:0] $end $var wire 5 m* read_addr[0] [4:0] $end $var wire 59 ># read_data_out[0] [58:0] $end $var wire 1 N, rst $end $var wire 5 A# write_addr [4:0] $end $var wire 59 B# write_data_in [58:0] $end $var wire 59 a, write_data_out [58:0] $end $var wire 59 R$ write_enable [58:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 G i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 )0 i [31:0] $end $upscope $end $upscope $end $upscope $end $scope module global_history_register_inst $end $var wire 5 51 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 x" enable $end $var wire 5 $# next [4:0] $end $var wire 1 N, rst $end $var wire 1 (# rst_actual $end $var wire 5 V* value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope interface jump_command $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 M% valid $end $scope struct payload $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $upscope $end $scope module local_history_table_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 Q/ AUTO_RESET $end $var wire 5 ]1 AUTO_RESET_VALUE [4:0] $end $var wire 32 T1 DATA_WIDTH [31:0] $end $var wire 32 _/ READ_PORTS [31:0] $end $var wire 32 \1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 s* read_addr[0] [4:0] $end $var wire 5 F# read_data_out[0] [4:0] $end $var wire 1 e/ reset_done $end $var wire 1 N, rst $end $var wire 5 r* write_addr [4:0] $end $var wire 5 r* write_addr_internal [4:0] $end $var wire 5 %# write_data_in [4:0] $end $var wire 5 %# write_data_in_internal [4:0] $end $var wire 5 ], write_data_out [4:0] $end $var wire 1 x" write_enable $end $var wire 1 x" write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 T1 DATA_WIDTH [31:0] $end $var wire 32 _/ READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 5 h- data[0] [4:0] $end $var wire 5 r- data[10] [4:0] $end $var wire 5 s- data[11] [4:0] $end $var wire 5 t- data[12] [4:0] $end $var wire 5 u- data[13] [4:0] $end $var wire 5 v- data[14] [4:0] $end $var wire 5 w- data[15] [4:0] $end $var wire 5 x- data[16] [4:0] $end $var wire 5 y- data[17] [4:0] $end $var wire 5 z- data[18] [4:0] $end $var wire 5 {- data[19] [4:0] $end $var wire 5 i- data[1] [4:0] $end $var wire 5 |- data[20] [4:0] $end $var wire 5 }- data[21] [4:0] $end $var wire 5 ~- data[22] [4:0] $end $var wire 5 !. data[23] [4:0] $end $var wire 5 ". data[24] [4:0] $end $var wire 5 #. data[25] [4:0] $end $var wire 5 $. data[26] [4:0] $end $var wire 5 %. data[27] [4:0] $end $var wire 5 &. data[28] [4:0] $end $var wire 5 '. data[29] [4:0] $end $var wire 5 j- data[2] [4:0] $end $var wire 5 (. data[30] [4:0] $end $var wire 5 ). data[31] [4:0] $end $var wire 5 k- data[3] [4:0] $end $var wire 5 l- data[4] [4:0] $end $var wire 5 m- data[5] [4:0] $end $var wire 5 n- data[6] [4:0] $end $var wire 5 o- data[7] [4:0] $end $var wire 5 p- data[8] [4:0] $end $var wire 5 q- data[9] [4:0] $end $var wire 5 s* read_addr[0] [4:0] $end $var wire 5 F# read_data_out[0] [4:0] $end $var wire 1 N, rst $end $var wire 5 r* write_addr [4:0] $end $var wire 5 %# write_data_in [4:0] $end $var wire 5 ], write_data_out [4:0] $end $var wire 5 T$ write_enable [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 H i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 )0 i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope struct stream_controller_result $end $var wire 1 a! enable $end $var wire 8 _! ready_input [7:0] $end $var wire 8 `! valid_output [7:0] $end $upscope $end $upscope $end $scope module gecko_inst_stage_inst $end $var wire 2 00 PIPELINE_MODE [1:0] $end $var wire 32 _/ STAGES [31:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $scope module stream_stage_inst $end $var wire 32 20 PAYLOAD_WIDTH [31:0] $end $var wire 2 10 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 p payload_enable $end $var wire 1 q valid_enable $end $scope module payload_register_inst $end $var wire 68 30 RESET_VECTOR [67:0] $end $var wire 1 M, clk $end $var wire 1 p enable $end $var wire 68 r next [67:0] $end $var wire 1 1 rst $end $var wire 1 2 rst_actual $end $var wire 68 "& value [67:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 q enable $end $var wire 1 p next $end $var wire 1 N, rst $end $var wire 1 u rst_actual $end $var wire 1 %& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module gecko_system_inst $end $var wire 1 \/ ENABLE_PERFORMANCE_COUNTERS $end $var wire 1 \/ ENABLE_TTY_IO $end $var wire 2 70 PIPELINE_MODE [1:0] $end $var wire 32 60 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 1 && consume_command $end $var wire 1 (& consume_tty $end $var wire 1 v enable $end $var wire 8 b$ exit_code [7:0] $end $var wire 8 ?& exit_code_next [7:0] $end $var wire 1 &% instruction_decoded $end $var wire 1 '% instruction_executed $end $var wire 32 *& perf_counter_increments[0] [31:0] $end $var wire 32 +& perf_counter_increments[1] [31:0] $end $var wire 32 ,& perf_counter_increments[2] [31:0] $end $var wire 32 -& perf_counter_increments[3] [31:0] $end $var wire 32 .& perf_counter_increments[4] [31:0] $end $var wire 32 /& perf_counter_increments[5] [31:0] $end $var wire 32 0& perf_counter_increments[6] [31:0] $end $var wire 64 1& perf_counters[0] [63:0] $end $var wire 64 3& perf_counters[1] [63:0] $end $var wire 64 5& perf_counters[2] [63:0] $end $var wire 64 7& perf_counters[3] [63:0] $end $var wire 64 9& perf_counters[4] [63:0] $end $var wire 64 ;& perf_counters[5] [63:0] $end $var wire 64 =& perf_counters[6] [63:0] $end $var wire 1 '& produce_result $end $var wire 1 )& produce_tty $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module exit_code_register_inst $end $var wire 8 80 RESET_VECTOR [7:0] $end $var wire 1 M, clk $end $var wire 1 v enable $end $var wire 8 ?& next [7:0] $end $var wire 1 N, rst $end $var wire 1 w rst_actual $end $var wire 8 b$ value [7:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module genblk1[0] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 H& carries[0] $end $var wire 1 I& carries[1] $end $var wire 1 N& carries_next[0] $end $var wire 1 O& carries_next[1] $end $var wire 1 M, clk $end $var wire 32 @& increment [31:0] $end $var wire 1 C& overflowed $end $var wire 1 P& overflowed_next $end $var wire 1 N, rst $end $var wire 64 D& stages[0] [63:0] $end $var wire 64 F& stages[1] [63:0] $end $var wire 1 >0 stages_carry[0] $end $var wire 1 ?0 stages_carry[1] $end $var wire 64 J& stages_next[0] [63:0] $end $var wire 64 L& stages_next[1] [63:0] $end $var wire 32 <0 stages_sum[0] [31:0] $end $var wire 32 =0 stages_sum[1] [31:0] $end $var wire 64 A& value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 Q& partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 S& next $end $var wire 1 N, rst $end $var wire 1 x rst_actual $end $var wire 1 T& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 U& next [63:0] $end $var wire 1 N, rst $end $var wire 1 y rst_actual $end $var wire 64 W& value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 Y& partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 [& next $end $var wire 1 N, rst $end $var wire 1 z rst_actual $end $var wire 1 \& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 ]& next [63:0] $end $var wire 1 N, rst $end $var wire 1 { rst_actual $end $var wire 64 _& value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 P& next $end $var wire 1 N, rst $end $var wire 1 | rst_actual $end $var wire 1 C& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 i& carries[0] $end $var wire 1 j& carries[1] $end $var wire 1 o& carries_next[0] $end $var wire 1 p& carries_next[1] $end $var wire 1 M, clk $end $var wire 32 a& increment [31:0] $end $var wire 1 d& overflowed $end $var wire 1 q& overflowed_next $end $var wire 1 N, rst $end $var wire 64 e& stages[0] [63:0] $end $var wire 64 g& stages[1] [63:0] $end $var wire 1 D0 stages_carry[0] $end $var wire 1 E0 stages_carry[1] $end $var wire 64 k& stages_next[0] [63:0] $end $var wire 64 m& stages_next[1] [63:0] $end $var wire 32 B0 stages_sum[0] [31:0] $end $var wire 32 C0 stages_sum[1] [31:0] $end $var wire 64 b& value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 r& partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 t& next $end $var wire 1 N, rst $end $var wire 1 } rst_actual $end $var wire 1 u& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 v& next [63:0] $end $var wire 1 N, rst $end $var wire 1 ~ rst_actual $end $var wire 64 x& value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 z& partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 |& next $end $var wire 1 N, rst $end $var wire 1 !! rst_actual $end $var wire 1 }& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 ~& next [63:0] $end $var wire 1 N, rst $end $var wire 1 "! rst_actual $end $var wire 64 "' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 q& next $end $var wire 1 N, rst $end $var wire 1 #! rst_actual $end $var wire 1 d& value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module genblk1[2] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 ,' carries[0] $end $var wire 1 -' carries[1] $end $var wire 1 2' carries_next[0] $end $var wire 1 3' carries_next[1] $end $var wire 1 M, clk $end $var wire 32 $' increment [31:0] $end $var wire 1 '' overflowed $end $var wire 1 4' overflowed_next $end $var wire 1 N, rst $end $var wire 64 (' stages[0] [63:0] $end $var wire 64 *' stages[1] [63:0] $end $var wire 1 H0 stages_carry[0] $end $var wire 1 I0 stages_carry[1] $end $var wire 64 .' stages_next[0] [63:0] $end $var wire 64 0' stages_next[1] [63:0] $end $var wire 32 F0 stages_sum[0] [31:0] $end $var wire 32 G0 stages_sum[1] [31:0] $end $var wire 64 %' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 5' partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 7' next $end $var wire 1 N, rst $end $var wire 1 $! rst_actual $end $var wire 1 8' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 9' next [63:0] $end $var wire 1 N, rst $end $var wire 1 %! rst_actual $end $var wire 64 ;' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 =' partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 ?' next $end $var wire 1 N, rst $end $var wire 1 &! rst_actual $end $var wire 1 @' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 A' next [63:0] $end $var wire 1 N, rst $end $var wire 1 '! rst_actual $end $var wire 64 C' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 4' next $end $var wire 1 N, rst $end $var wire 1 (! rst_actual $end $var wire 1 '' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module genblk1[3] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 M' carries[0] $end $var wire 1 N' carries[1] $end $var wire 1 S' carries_next[0] $end $var wire 1 T' carries_next[1] $end $var wire 1 M, clk $end $var wire 32 E' increment [31:0] $end $var wire 1 H' overflowed $end $var wire 1 U' overflowed_next $end $var wire 1 N, rst $end $var wire 64 I' stages[0] [63:0] $end $var wire 64 K' stages[1] [63:0] $end $var wire 1 L0 stages_carry[0] $end $var wire 1 M0 stages_carry[1] $end $var wire 64 O' stages_next[0] [63:0] $end $var wire 64 Q' stages_next[1] [63:0] $end $var wire 32 J0 stages_sum[0] [31:0] $end $var wire 32 K0 stages_sum[1] [31:0] $end $var wire 64 F' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 V' partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 X' next $end $var wire 1 N, rst $end $var wire 1 )! rst_actual $end $var wire 1 Y' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 Z' next [63:0] $end $var wire 1 N, rst $end $var wire 1 *! rst_actual $end $var wire 64 \' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 ^' partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 `' next $end $var wire 1 N, rst $end $var wire 1 +! rst_actual $end $var wire 1 a' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 b' next [63:0] $end $var wire 1 N, rst $end $var wire 1 ,! rst_actual $end $var wire 64 d' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 U' next $end $var wire 1 N, rst $end $var wire 1 -! rst_actual $end $var wire 1 H' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module genblk1[4] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 n' carries[0] $end $var wire 1 o' carries[1] $end $var wire 1 t' carries_next[0] $end $var wire 1 u' carries_next[1] $end $var wire 1 M, clk $end $var wire 32 f' increment [31:0] $end $var wire 1 i' overflowed $end $var wire 1 v' overflowed_next $end $var wire 1 N, rst $end $var wire 64 j' stages[0] [63:0] $end $var wire 64 l' stages[1] [63:0] $end $var wire 1 P0 stages_carry[0] $end $var wire 1 Q0 stages_carry[1] $end $var wire 64 p' stages_next[0] [63:0] $end $var wire 64 r' stages_next[1] [63:0] $end $var wire 32 N0 stages_sum[0] [31:0] $end $var wire 32 O0 stages_sum[1] [31:0] $end $var wire 64 g' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 w' partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 y' next $end $var wire 1 N, rst $end $var wire 1 .! rst_actual $end $var wire 1 z' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 {' next [63:0] $end $var wire 1 N, rst $end $var wire 1 /! rst_actual $end $var wire 64 }' value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 !( partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 #( next $end $var wire 1 N, rst $end $var wire 1 0! rst_actual $end $var wire 1 $( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 %( next [63:0] $end $var wire 1 N, rst $end $var wire 1 1! rst_actual $end $var wire 64 '( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 v' next $end $var wire 1 N, rst $end $var wire 1 2! rst_actual $end $var wire 1 i' value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module genblk1[5] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 1( carries[0] $end $var wire 1 2( carries[1] $end $var wire 1 7( carries_next[0] $end $var wire 1 8( carries_next[1] $end $var wire 1 M, clk $end $var wire 32 )( increment [31:0] $end $var wire 1 ,( overflowed $end $var wire 1 9( overflowed_next $end $var wire 1 N, rst $end $var wire 64 -( stages[0] [63:0] $end $var wire 64 /( stages[1] [63:0] $end $var wire 1 T0 stages_carry[0] $end $var wire 1 U0 stages_carry[1] $end $var wire 64 3( stages_next[0] [63:0] $end $var wire 64 5( stages_next[1] [63:0] $end $var wire 32 R0 stages_sum[0] [31:0] $end $var wire 32 S0 stages_sum[1] [31:0] $end $var wire 64 *( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 :( partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 <( next $end $var wire 1 N, rst $end $var wire 1 3! rst_actual $end $var wire 1 =( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 >( next [63:0] $end $var wire 1 N, rst $end $var wire 1 4! rst_actual $end $var wire 64 @( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 B( partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 D( next $end $var wire 1 N, rst $end $var wire 1 5! rst_actual $end $var wire 1 E( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 F( next [63:0] $end $var wire 1 N, rst $end $var wire 1 6! rst_actual $end $var wire 64 H( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 9( next $end $var wire 1 N, rst $end $var wire 1 7! rst_actual $end $var wire 1 ,( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module genblk1[6] $end $scope module counter_inst $end $var wire 32 b/ PIPELINE_COUNT [31:0] $end $var wire 32 `/ PIPELINE_WIDTH [31:0] $end $var wire 64 :0 RESET_VECTOR [63:0] $end $var wire 32 90 WIDTH [31:0] $end $var wire 1 R( carries[0] $end $var wire 1 S( carries[1] $end $var wire 1 X( carries_next[0] $end $var wire 1 Y( carries_next[1] $end $var wire 1 M, clk $end $var wire 32 J( increment [31:0] $end $var wire 1 M( overflowed $end $var wire 1 Z( overflowed_next $end $var wire 1 N, rst $end $var wire 64 N( stages[0] [63:0] $end $var wire 64 P( stages[1] [63:0] $end $var wire 1 X0 stages_carry[0] $end $var wire 1 Y0 stages_carry[1] $end $var wire 64 T( stages_next[0] [63:0] $end $var wire 64 V( stages_next[1] [63:0] $end $var wire 32 V0 stages_sum[0] [31:0] $end $var wire 32 W0 stages_sum[1] [31:0] $end $var wire 64 K( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1[0] $end $var wire 33 [( partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 ]( next $end $var wire 1 N, rst $end $var wire 1 8! rst_actual $end $var wire 1 ^( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 _( next [63:0] $end $var wire 1 N, rst $end $var wire 1 9! rst_actual $end $var wire 64 a( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk1[1] $end $var wire 33 c( partial_sum [32:0] $end $scope module carry_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 e( next $end $var wire 1 N, rst $end $var wire 1 :! rst_actual $end $var wire 1 f( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module stage_register_inst $end $var wire 64 @0 RESET_VECTOR [63:0] $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 64 g( next [63:0] $end $var wire 1 N, rst $end $var wire 1 ;! rst_actual $end $var wire 64 i( value [63:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module overflowed_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 e/ enable $end $var wire 1 Z( next $end $var wire 1 N, rst $end $var wire 1 ! valid_output [1:0] $end $scope module unnamedblk1 $end $var wire 32 Z0 i [31:0] $end $scope module unnamedblk2 $end $var wire 32 Z0 j [31:0] $end $upscope $end $upscope $end $scope module unnamedblk3 $end $var wire 32 Z0 i [31:0] $end $scope module unnamedblk4 $end $var wire 32 Z0 j [31:0] $end $upscope $end $upscope $end $scope module unnamedblk5 $end $var wire 32 Z0 i [31:0] $end $upscope $end $scope module unnamedblk6 $end $var wire 32 Z0 i [31:0] $end $upscope $end $upscope $end $scope interface system_command $end $var wire 89 w1 T_LOGIC [88:0] $end $var wire 1 M, clk $end $var wire 1 w# ready $end $var wire 1 N, rst $end $var wire 1 7* valid $end $scope struct payload $end $var wire 12 P+ csr [11:0] $end $var wire 32 M+ imm_value [31:0] $end $var wire 2 L+ jump_flag [1:0] $end $var wire 5 J+ reg_addr [4:0] $end $var wire 3 K+ reg_status [2:0] $end $var wire 32 N+ rs1_value [31:0] $end $var wire 3 O+ sys_op [2:0] $end $upscope $end $upscope $end $scope interface system_result_next $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 E$ ready $end $var wire 1 N, rst $end $var wire 1 D$ valid $end $scope struct payload $end $var wire 5 |+ addr [4:0] $end $var wire 2 ~+ jump_flag [1:0] $end $var wire 1 ", mispredicted $end $var wire 3 }+ reg_status [2:0] $end $var wire 32 !, value [31:0] $end $upscope $end $upscope $end $scope module system_result_stage_inst $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 [0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 B! payload_enable $end $var wire 1 C! valid_enable $end $scope module payload_register_inst $end $var wire 43 s/ RESET_VECTOR [42:0] $end $var wire 1 M, clk $end $var wire 1 B! enable $end $var wire 43 p( next [42:0] $end $var wire 1 3 rst $end $var wire 1 4 rst_actual $end $var wire 43 r( value [42:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 C! enable $end $var wire 1 B! next $end $var wire 1 N, rst $end $var wire 1 D! rst_actual $end $var wire 1 t( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 E$ ready $end $var wire 1 N, rst $end $var wire 1 D$ valid $end $scope struct payload $end $var wire 5 |+ addr [4:0] $end $var wire 2 ~+ jump_flag [1:0] $end $var wire 1 ", mispredicted $end $var wire 3 }+ reg_status [2:0] $end $var wire 32 !, value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface system_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope interface tty_in_buffered $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 *+ payload [7:0] $end $var wire 1 ]# ready $end $var wire 1 N, rst $end $var wire 1 )+ valid $end $upscope $end $scope module tty_in_stage_inst $end $var wire 32 ]0 PAYLOAD_WIDTH [31:0] $end $var wire 2 \0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 8 y( buffer0 [7:0] $end $var wire 1 K! buffer0_enable $end $var wire 8 z( buffer1 [7:0] $end $var wire 1 L! buffer1_enable $end $var wire 1 I! enable_valid0 $end $var wire 1 J! enable_valid1 $end $var wire 1 u( input_index $end $var wire 1 E! input_index_enable $end $var wire 1 G! next_valid0 $end $var wire 1 H! next_valid1 $end $var wire 1 v( output_index $end $var wire 1 F! output_index_enable $end $var wire 1 w( valid0 $end $var wire 1 x( valid1 $end $scope module buffer0_register_inst $end $var wire 8 ^0 RESET_VECTOR [7:0] $end $var wire 1 M, clk $end $var wire 1 K! enable $end $var wire 8 Q, next [7:0] $end $var wire 1 5 rst $end $var wire 1 6 rst_actual $end $var wire 8 y( value [7:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module buffer1_register_inst $end $var wire 8 ^0 RESET_VECTOR [7:0] $end $var wire 1 M, clk $end $var wire 1 L! enable $end $var wire 8 Q, next [7:0] $end $var wire 1 7 rst $end $var wire 1 8 rst_actual $end $var wire 8 z( value [7:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module input_index_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 E! enable $end $var wire 1 {( next $end $var wire 1 N, rst $end $var wire 1 M! rst_actual $end $var wire 1 u( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module output_index_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 F! enable $end $var wire 1 |( next $end $var wire 1 N, rst $end $var wire 1 N! rst_actual $end $var wire 1 v( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid0_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 I! enable $end $var wire 1 G! next $end $var wire 1 N, rst $end $var wire 1 O! rst_actual $end $var wire 1 w( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid1_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 J! enable $end $var wire 1 H! next $end $var wire 1 N, rst $end $var wire 1 P! rst_actual $end $var wire 1 x( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 Q, payload [7:0] $end $var wire 1 ^$ ready $end $var wire 1 N, rst $end $var wire 1 O, valid $end $upscope $end $scope interface stream_out $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 *+ payload [7:0] $end $var wire 1 ]# ready $end $var wire 1 N, rst $end $var wire 1 )+ valid $end $upscope $end $upscope $end $scope interface tty_in $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 Q, payload [7:0] $end $var wire 1 ^$ ready $end $var wire 1 N, rst $end $var wire 1 O, valid $end $upscope $end $scope interface tty_out_next $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 %) payload [7:0] $end $var wire 1 ++ ready $end $var wire 1 N, rst $end $var wire 1 ^# valid $end $upscope $end $scope module tty_out_stage_inst $end $var wire 32 ]0 PAYLOAD_WIDTH [31:0] $end $var wire 2 _0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 8 #) buffer0 [7:0] $end $var wire 1 W! buffer0_enable $end $var wire 8 $) buffer1 [7:0] $end $var wire 1 X! buffer1_enable $end $var wire 1 U! enable_valid0 $end $var wire 1 V! enable_valid1 $end $var wire 1 }( input_index $end $var wire 1 Q! input_index_enable $end $var wire 1 S! next_valid0 $end $var wire 1 T! next_valid1 $end $var wire 1 ~( output_index $end $var wire 1 R! output_index_enable $end $var wire 1 !) valid0 $end $var wire 1 ") valid1 $end $scope module buffer0_register_inst $end $var wire 8 ^0 RESET_VECTOR [7:0] $end $var wire 1 M, clk $end $var wire 1 W! enable $end $var wire 8 %) next [7:0] $end $var wire 1 9 rst $end $var wire 1 : rst_actual $end $var wire 8 #) value [7:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module buffer1_register_inst $end $var wire 8 ^0 RESET_VECTOR [7:0] $end $var wire 1 M, clk $end $var wire 1 X! enable $end $var wire 8 %) next [7:0] $end $var wire 1 ; rst $end $var wire 1 < rst_actual $end $var wire 8 $) value [7:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module input_index_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 Q! enable $end $var wire 1 &) next $end $var wire 1 N, rst $end $var wire 1 Y! rst_actual $end $var wire 1 }( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module output_index_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 R! enable $end $var wire 1 ') next $end $var wire 1 N, rst $end $var wire 1 Z! rst_actual $end $var wire 1 ~( value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid0_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 U! enable $end $var wire 1 S! next $end $var wire 1 N, rst $end $var wire 1 [! rst_actual $end $var wire 1 !) value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid1_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 V! enable $end $var wire 1 T! next $end $var wire 1 N, rst $end $var wire 1 \! rst_actual $end $var wire 1 ") value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 %) payload [7:0] $end $var wire 1 ++ ready $end $var wire 1 N, rst $end $var wire 1 ^# valid $end $upscope $end $scope interface stream_out $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 `$ payload [7:0] $end $var wire 1 S, ready $end $var wire 1 N, rst $end $var wire 1 _$ valid $end $upscope $end $upscope $end $scope interface tty_out $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 `$ payload [7:0] $end $var wire 1 S, ready $end $var wire 1 N, rst $end $var wire 1 _$ valid $end $upscope $end $scope module unnamedblk1 $end $scope struct command_in $end $var wire 12 .) csr [11:0] $end $var wire 32 +) imm_value [31:0] $end $var wire 2 *) jump_flag [1:0] $end $var wire 5 () reg_addr [4:0] $end $var wire 3 )) reg_status [2:0] $end $var wire 32 ,) rs1_value [31:0] $end $var wire 3 -) sys_op [2:0] $end $upscope $end $upscope $end $upscope $end $scope module gecko_writeback_inst $end $var wire 32 11 GECKO_REG_STATUS_DEPTH [31:0] $end $var wire 32 01 GECKO_REG_STATUS_WIDTH [31:0] $end $var wire 2 /1 PIPELINE_MODE [1:0] $end $var wire 32 a/ PORTS [31:0] $end $var wire 32 .1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 4 b" consume [3:0] $end $var wire 5 R* current_counter [4:0] $end $var wire 1 a" enable $end $var wire 5 k" next_counter [4:0] $end $var wire 1 c" produce $end $var wire 3 g" reg_status[0] [2:0] $end $var wire 3 h" reg_status[1] [2:0] $end $var wire 3 i" reg_status[2] [2:0] $end $var wire 3 j" reg_status[3] [2:0] $end $var wire 1 Q* reset_done $end $var wire 4 `" results_in_ready [3:0] $end $var wire 4 8* results_in_valid [3:0] $end $var wire 1 N, rst $end $var wire 4 l" status_good [3:0] $end $var wire 5 M* status_read_addr[0] [4:0] $end $var wire 5 N* status_read_addr[1] [4:0] $end $var wire 5 O* status_read_addr[2] [4:0] $end $var wire 5 P* status_read_addr[3] [4:0] $end $var wire 5 e" status_write_addr [4:0] $end $var wire 1 d" status_write_enable $end $var wire 3 f" status_write_value [2:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module counter_register_inst $end $var wire 5 z0 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 a" enable $end $var wire 5 k" next [4:0] $end $var wire 1 N, rst $end $var wire 1 m" rst_actual $end $var wire 5 R* value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope interface next_writeback_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 n" valid $end $scope struct payload $end $var wire 5 =$ addr [4:0] $end $var wire 2 ?$ jump_flag [1:0] $end $var wire 1 A$ mispredicted $end $var wire 3 >$ reg_status [2:0] $end $var wire 32 @$ value [31:0] $end $upscope $end $upscope $end $scope module register_status_counters_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 1 \/ AUTO_RESET $end $var wire 3 U1 AUTO_RESET_VALUE [2:0] $end $var wire 32 m0 DATA_WIDTH [31:0] $end $var wire 32 a/ READ_PORTS [31:0] $end $var wire 32 S1 TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 5 M* read_addr[0] [4:0] $end $var wire 5 N* read_addr[1] [4:0] $end $var wire 5 O* read_addr[2] [4:0] $end $var wire 5 P* read_addr[3] [4:0] $end $var wire 3 g" read_data_out[0] [2:0] $end $var wire 3 h" read_data_out[1] [2:0] $end $var wire 3 i" read_data_out[2] [2:0] $end $var wire 3 j" read_data_out[3] [2:0] $end $var wire 1 Q* reset_done $end $var wire 1 N, rst $end $var wire 5 e" write_addr [4:0] $end $var wire 5 8# write_addr_internal [4:0] $end $var wire 3 f" write_data_in [2:0] $end $var wire 3 9# write_data_in_internal [2:0] $end $var wire 3 `, write_data_out [2:0] $end $var wire 1 6# write_enable $end $var wire 1 7# write_enable_internal $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 j* clear_reset_state $end $var wire 5 k* current_reset_counter [4:0] $end $var wire 1 i* current_reset_state $end $var wire 5 l* next_reset_counter [4:0] $end $scope module reset_counter_reg_inst $end $var wire 5 V1 RESET_VECTOR [4:0] $end $var wire 1 M, clk $end $var wire 1 i* enable $end $var wire 5 l* next [4:0] $end $var wire 1 N, rst $end $var wire 1 :# rst_actual $end $var wire 5 k* value [4:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module reset_state_reg_inst $end $var wire 1 W1 RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 j* enable $end $var wire 1 }/ next $end $var wire 1 N, rst $end $var wire 1 ;# rst_actual $end $var wire 1 i* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module xilinx_distributed_ram_inst $end $var wire 32 T1 ADDR_WIDTH [31:0] $end $var wire 32 $0 DATA_LENGTH [31:0] $end $var wire 32 m0 DATA_WIDTH [31:0] $end $var wire 32 a/ READ_PORTS [31:0] $end $var wire 1 M, clk $end $var wire 3 f, data[0] [2:0] $end $var wire 3 p, data[10] [2:0] $end $var wire 3 q, data[11] [2:0] $end $var wire 3 r, data[12] [2:0] $end $var wire 3 s, data[13] [2:0] $end $var wire 3 t, data[14] [2:0] $end $var wire 3 u, data[15] [2:0] $end $var wire 3 v, data[16] [2:0] $end $var wire 3 w, data[17] [2:0] $end $var wire 3 x, data[18] [2:0] $end $var wire 3 y, data[19] [2:0] $end $var wire 3 g, data[1] [2:0] $end $var wire 3 z, data[20] [2:0] $end $var wire 3 {, data[21] [2:0] $end $var wire 3 |, data[22] [2:0] $end $var wire 3 }, data[23] [2:0] $end $var wire 3 ~, data[24] [2:0] $end $var wire 3 !- data[25] [2:0] $end $var wire 3 "- data[26] [2:0] $end $var wire 3 #- data[27] [2:0] $end $var wire 3 $- data[28] [2:0] $end $var wire 3 %- data[29] [2:0] $end $var wire 3 h, data[2] [2:0] $end $var wire 3 &- data[30] [2:0] $end $var wire 3 '- data[31] [2:0] $end $var wire 3 i, data[3] [2:0] $end $var wire 3 j, data[4] [2:0] $end $var wire 3 k, data[5] [2:0] $end $var wire 3 l, data[6] [2:0] $end $var wire 3 m, data[7] [2:0] $end $var wire 3 n, data[8] [2:0] $end $var wire 3 o, data[9] [2:0] $end $var wire 5 M* read_addr[0] [4:0] $end $var wire 5 N* read_addr[1] [4:0] $end $var wire 5 O* read_addr[2] [4:0] $end $var wire 5 P* read_addr[3] [4:0] $end $var wire 3 g" read_data_out[0] [2:0] $end $var wire 3 h" read_data_out[1] [2:0] $end $var wire 3 i" read_data_out[2] [2:0] $end $var wire 3 j" read_data_out[3] [2:0] $end $var wire 1 N, rst $end $var wire 5 8# write_addr [4:0] $end $var wire 3 9# write_data_in [2:0] $end $var wire 3 `, write_data_out [2:0] $end $var wire 3 Q$ write_enable [2:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 F i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 (0 i [31:0] $end $upscope $end $upscope $end $upscope $end $scope struct results_in_operation[0] $end $var wire 5 9* addr [4:0] $end $var wire 2 ;* jump_flag [1:0] $end $var wire 1 =* mispredicted $end $var wire 3 :* reg_status [2:0] $end $var wire 32 <* value [31:0] $end $upscope $end $scope struct results_in_operation[1] $end $var wire 5 >* addr [4:0] $end $var wire 2 @* jump_flag [1:0] $end $var wire 1 B* mispredicted $end $var wire 3 ?* reg_status [2:0] $end $var wire 32 A* value [31:0] $end $upscope $end $scope struct results_in_operation[2] $end $var wire 5 C* addr [4:0] $end $var wire 2 E* jump_flag [1:0] $end $var wire 1 G* mispredicted $end $var wire 3 D* reg_status [2:0] $end $var wire 32 F* value [31:0] $end $upscope $end $scope struct results_in_operation[3] $end $var wire 5 H* addr [4:0] $end $var wire 2 J* jump_flag [1:0] $end $var wire 1 L* mispredicted $end $var wire 3 I* reg_status [2:0] $end $var wire 32 K* value [31:0] $end $upscope $end $scope module stream_controller_inst $end $var wire 32 a/ NUM_INPUTS [31:0] $end $var wire 32 _/ NUM_OUTPUTS [31:0] $end $var wire 1 M, clk $end $var wire 4 b" consume [3:0] $end $var wire 1 a" enable $end $var wire 1 o" input_enable $end $var wire 4 p" input_enables [3:0] $end $var wire 1 e/ output_enable $end $var wire 1 e/ output_enables [0:0] $end $var wire 1 c" produce [0:0] $end $var wire 4 `" ready_input [3:0] $end $var wire 1 e/ ready_output [0:0] $end $var wire 1 N, rst $end $var wire 4 8* valid_input [3:0] $end $var wire 1 n" valid_output [0:0] $end $scope module unnamedblk1 $end $var wire 32 )0 i [31:0] $end $scope module unnamedblk2 $end $var wire 32 )0 j [31:0] $end $upscope $end $upscope $end $scope module unnamedblk3 $end $var wire 32 (0 i [31:0] $end $scope module unnamedblk4 $end $var wire 32 (0 j [31:0] $end $upscope $end $upscope $end $scope module unnamedblk5 $end $var wire 32 )0 i [31:0] $end $upscope $end $scope module unnamedblk6 $end $var wire 32 (0 i [31:0] $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 q" i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 r" i [31:0] $end $upscope $end $scope module writeback_result_stage_inst $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 21 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module genblk1 $end $var wire 1 s" payload_enable $end $var wire 1 t" valid_enable $end $scope module payload_register_inst $end $var wire 43 s/ RESET_VECTOR [42:0] $end $var wire 1 M, clk $end $var wire 1 s" enable $end $var wire 43 u" next [42:0] $end $var wire 1 D rst $end $var wire 1 E rst_actual $end $var wire 43 S* value [42:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_register_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 t" enable $end $var wire 1 s" next $end $var wire 1 N, rst $end $var wire 1 w" rst_actual $end $var wire 1 U* value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 n" valid $end $scope struct payload $end $var wire 5 =$ addr [4:0] $end $var wire 2 ?$ jump_flag [1:0] $end $var wire 1 A$ mispredicted $end $var wire 3 >$ reg_status [2:0] $end $var wire 32 @$ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 U* valid $end $scope struct payload $end $var wire 5 b) addr [4:0] $end $var wire 2 d) jump_flag [1:0] $end $var wire 1 f) mispredicted $end $var wire 3 c) reg_status [2:0] $end $var wire 32 e) value [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface writeback_results_in[0] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope interface writeback_results_in[1] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $scope interface writeback_results_in[2] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope interface writeback_results_in[3] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $scope interface writeback_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 U* valid $end $scope struct payload $end $var wire 5 b) addr [4:0] $end $var wire 2 d) jump_flag [1:0] $end $var wire 1 f) mispredicted $end $var wire 3 c) reg_status [2:0] $end $var wire 32 e) value [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface inst_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 \* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 2) data [31:0] $end $var wire 1 c$ id [0:0] $end $var wire 1 e$ last $end $var wire 1 [* read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 0) write_enable [3:0] $end $upscope $end $scope interface inst_result_break $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 a* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 b* data [31:0] $end $var wire 1 c* id [0:0] $end $var wire 1 d* last $end $var wire 1 _* read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 `* write_enable [3:0] $end $upscope $end $scope interface inst_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 >1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 3) data [31:0] $end $var wire 1 d$ id [0:0] $end $var wire 1 f$ last $end $var wire 1 <1 read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 =1 write_enable [3:0] $end $upscope $end $scope interface instruction_command_break $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $scope interface instruction_command_in $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 G$ ready $end $var wire 1 N, rst $end $var wire 1 F$ valid $end $scope struct payload $end $var wire 32 I$ next_pc [31:0] $end $var wire 32 H$ pc [31:0] $end $var wire 1 L$ pc_updated $end $scope struct prediction $end $var wire 2 K$ history [1:0] $end $var wire 1 J$ miss $end $upscope $end $upscope $end $upscope $end $scope module instruction_command_output_stage_inst $end $var wire 32 20 PAYLOAD_WIDTH [31:0] $end $var wire 2 `0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface instruction_command_out $end $var wire 68 *2 T_LOGIC [67:0] $end $var wire 1 M, clk $end $var wire 1 M$ ready $end $var wire 1 N, rst $end $var wire 1 %& valid $end $scope struct payload $end $var wire 32 U) next_pc [31:0] $end $var wire 32 T) pc [31:0] $end $var wire 1 X) pc_updated $end $scope struct prediction $end $var wire 2 W) history [1:0] $end $var wire 1 V) miss $end $upscope $end $upscope $end $upscope $end $scope module instruction_result_output_stage_inst $end $var wire 32 $0 ADDR_WIDTH [31:0] $end $var wire 32 `/ ADDR_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 ADDR_WIDTH_OVERRIDE [31:0] $end $var wire 32 $0 DATA_WIDTH [31:0] $end $var wire 32 `/ DATA_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 DATA_WIDTH_OVERRIDE [31:0] $end $var wire 32 &0 ID_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH_INTERNAL [31:0] $end $var wire 32 "0 ID_WIDTH_OVERRIDE [31:0] $end $var wire 32 %0 MASK_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH_INTERNAL [31:0] $end $var wire 32 _/ META_WIDTH [31:0] $end $var wire 2 a0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 #0 mem_in_meta [0:0] $end $var wire 1 /) mem_out_meta [0:0] $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface mem_in $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 >1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 3) data [31:0] $end $var wire 1 d$ id [0:0] $end $var wire 1 f$ last $end $var wire 1 <1 read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 =1 write_enable [3:0] $end $upscope $end $scope interface mem_out $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 a* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 b* data [31:0] $end $var wire 1 c* id [0:0] $end $var wire 1 d* last $end $var wire 1 _* read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 `* write_enable [3:0] $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $scope struct payload $end $var wire 32 >, addr [31:0] $end $var wire 32 ?, data [31:0] $end $var wire 1 @, id [0:0] $end $var wire 1 A, last $end $var wire 1 B, meta [0:0] $end $var wire 1 <, read_enable $end $var wire 4 =, write_enable [3:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $scope struct payload $end $var wire 32 >, addr [31:0] $end $var wire 32 ?, data [31:0] $end $var wire 1 @, id [0:0] $end $var wire 1 A, last $end $var wire 1 B, meta [0:0] $end $var wire 1 <, read_enable $end $var wire 4 =, write_enable [3:0] $end $upscope $end $upscope $end $scope module stream_stage_inst $end $var wire 32 x/ PAYLOAD_WIDTH [31:0] $end $var wire 2 b0 PIPELINE_MODE [1:0] $end $var wire 1 M, clk $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $scope struct payload $end $var wire 32 >, addr [31:0] $end $var wire 32 ?, data [31:0] $end $var wire 1 @, id [0:0] $end $var wire 1 A, last $end $var wire 1 B, meta [0:0] $end $var wire 1 <, read_enable $end $var wire 4 =, write_enable [3:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $scope struct payload $end $var wire 32 >, addr [31:0] $end $var wire 32 ?, data [31:0] $end $var wire 1 @, id [0:0] $end $var wire 1 A, last $end $var wire 1 B, meta [0:0] $end $var wire 1 <, read_enable $end $var wire 4 =, write_enable [3:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface jump_command $end $var wire 72 l1 T_LOGIC [71:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 M% valid $end $scope struct payload $end $var wire 32 ]) actual_next_pc [31:0] $end $var wire 1 Z) branched $end $var wire 32 \) current_pc [31:0] $end $var wire 1 `) halt $end $var wire 1 [) jumped $end $var wire 1 a) mispredicted $end $var wire 1 Y) update_pc $end $scope struct prediction $end $var wire 2 _) history [1:0] $end $var wire 1 ^) miss $end $upscope $end $upscope $end $upscope $end $scope interface mem_command_in $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 N$ ready $end $var wire 1 N, rst $end $var wire 1 O% valid $end $scope struct payload $end $var wire 5 #, addr [4:0] $end $var wire 2 %, jump_flag [1:0] $end $var wire 1 (, mispredicted $end $var wire 2 ', offset [1:0] $end $var wire 3 &, op [2:0] $end $var wire 3 $, reg_status [2:0] $end $upscope $end $upscope $end $scope interface mem_command_out $end $var wire 16 -2 T_LOGIC [15:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 *% valid $end $scope struct payload $end $var wire 5 ), addr [4:0] $end $var wire 2 +, jump_flag [1:0] $end $var wire 1 ., mispredicted $end $var wire 2 -, offset [1:0] $end $var wire 3 ,, op [2:0] $end $var wire 3 *, reg_status [2:0] $end $upscope $end $upscope $end $scope struct memory_forwarded $end $var wire 5 !% addr [4:0] $end $var wire 2 "% jump_flag [1:0] $end $var wire 1 %% mispredicted $end $var wire 3 #% reg_status [2:0] $end $var wire 1 ~$ valid $end $var wire 32 $% value [31:0] $end $upscope $end $scope interface memory_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $scope struct performance_stats $end $var wire 1 q$ backend_stalled $end $var wire 1 p$ frontend_stalled $end $var wire 1 o$ instruction_control_stalled $end $var wire 1 n$ instruction_data_stalled $end $var wire 1 m$ instruction_mispredicted $end $upscope $end $scope module stream_connect0 $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope module stream_stage_inst0 $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 c0 PIPELINE_MODE [1:0] $end $var wire 1 }/ clk $end $var wire 1 }/ rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module stream_connect1 $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $scope module stream_stage_inst0 $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 c0 PIPELINE_MODE [1:0] $end $var wire 1 }/ clk $end $var wire 1 }/ rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module stream_connect2 $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope module stream_stage_inst0 $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 c0 PIPELINE_MODE [1:0] $end $var wire 1 }/ clk $end $var wire 1 }/ rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module stream_connect3 $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $scope module stream_stage_inst0 $end $var wire 32 r/ PAYLOAD_WIDTH [31:0] $end $var wire 2 c0 PIPELINE_MODE [1:0] $end $var wire 1 }/ clk $end $var wire 1 }/ rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope interface stream_in $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $scope interface stream_out $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope interface system_command $end $var wire 89 w1 T_LOGIC [88:0] $end $var wire 1 M, clk $end $var wire 1 w# ready $end $var wire 1 N, rst $end $var wire 1 7* valid $end $scope struct payload $end $var wire 12 P+ csr [11:0] $end $var wire 32 M+ imm_value [31:0] $end $var wire 2 L+ jump_flag [1:0] $end $var wire 5 J+ reg_addr [4:0] $end $var wire 3 K+ reg_status [2:0] $end $var wire 32 N+ rs1_value [31:0] $end $var wire 3 O+ sys_op [2:0] $end $upscope $end $upscope $end $scope interface system_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope interface tty_in $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 Q, payload [7:0] $end $var wire 1 ^$ ready $end $var wire 1 N, rst $end $var wire 1 O, valid $end $upscope $end $scope interface tty_out $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 `$ payload [7:0] $end $var wire 1 S, ready $end $var wire 1 N, rst $end $var wire 1 _$ valid $end $upscope $end $scope struct writeback_forwarded $end $var wire 5 y$ addr [4:0] $end $var wire 2 z$ jump_flag [1:0] $end $var wire 1 }$ mispredicted $end $var wire 3 {$ reg_status [2:0] $end $var wire 1 x$ valid $end $var wire 32 |$ value [31:0] $end $upscope $end $scope interface writeback_results_in[0] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 9$ ready $end $var wire 1 N, rst $end $var wire 1 E% valid $end $scope struct payload $end $var wire 5 g+ addr [4:0] $end $var wire 2 i+ jump_flag [1:0] $end $var wire 1 k+ mispredicted $end $var wire 3 h+ reg_status [2:0] $end $var wire 32 j+ value [31:0] $end $upscope $end $upscope $end $scope interface writeback_results_in[1] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 ;$ ready $end $var wire 1 N, rst $end $var wire 1 q+ valid $end $scope struct payload $end $var wire 5 r+ addr [4:0] $end $var wire 2 t+ jump_flag [1:0] $end $var wire 1 v+ mispredicted $end $var wire 3 s+ reg_status [2:0] $end $var wire 32 u+ value [31:0] $end $upscope $end $upscope $end $scope interface writeback_results_in[2] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 :$ ready $end $var wire 1 N, rst $end $var wire 1 t( valid $end $scope struct payload $end $var wire 5 l+ addr [4:0] $end $var wire 2 n+ jump_flag [1:0] $end $var wire 1 p+ mispredicted $end $var wire 3 m+ reg_status [2:0] $end $var wire 32 o+ value [31:0] $end $upscope $end $upscope $end $scope interface writeback_results_in[3] $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 <$ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $scope struct payload $end $var wire 5 %2 addr [4:0] $end $var wire 2 '2 jump_flag [1:0] $end $var wire 1 )2 mispredicted $end $var wire 3 &2 reg_status [2:0] $end $var wire 32 (2 value [31:0] $end $upscope $end $upscope $end $scope interface writeback_result $end $var wire 43 #2 T_LOGIC [42:0] $end $var wire 1 M, clk $end $var wire 1 e/ ready $end $var wire 1 N, rst $end $var wire 1 U* valid $end $scope struct payload $end $var wire 5 b) addr [4:0] $end $var wire 2 d) jump_flag [1:0] $end $var wire 1 f) mispredicted $end $var wire 3 c) reg_status [2:0] $end $var wire 32 e) value [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface data_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 ^* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 6) data [31:0] $end $var wire 1 h$ id [0:0] $end $var wire 1 j$ last $end $var wire 1 ]* read_enable $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $var wire 4 4) write_enable [3:0] $end $upscope $end $scope interface data_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 A1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 7) data [31:0] $end $var wire 1 i$ id [0:0] $end $var wire 1 k$ last $end $var wire 1 ?1 read_enable $end $var wire 1 3# ready $end $var wire 1 N, rst $end $var wire 1 l$ valid $end $var wire 4 @1 write_enable [3:0] $end $upscope $end $scope interface float_mem_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 D1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 E1 data [31:0] $end $var wire 1 F1 id [0:0] $end $var wire 1 G1 last $end $var wire 1 B1 read_enable $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $var wire 4 C1 write_enable [3:0] $end $upscope $end $scope interface float_mem_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 J1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 K1 data [31:0] $end $var wire 1 L1 id [0:0] $end $var wire 1 M1 last $end $var wire 1 H1 read_enable $end $var wire 1 }/ ready $end $var wire 1 N, rst $end $var wire 1 }/ valid $end $var wire 4 I1 write_enable [3:0] $end $upscope $end $scope interface inst_request $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 \* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 2) data [31:0] $end $var wire 1 c$ id [0:0] $end $var wire 1 e$ last $end $var wire 1 [* read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 0) write_enable [3:0] $end $upscope $end $scope interface inst_result $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 >1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 3) data [31:0] $end $var wire 1 d$ id [0:0] $end $var wire 1 f$ last $end $var wire 1 <1 read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 =1 write_enable [3:0] $end $upscope $end $scope module mem $end $var wire 32 _/ ADDR_BYTE_SHIFTED [31:0] $end $var wire 32 b/ ADDR_CORRECTION [31:0] $end $var wire 32 ]/ ADDR_DEFAULT [31:0] $end $var wire 32 c/ ADDR_WIDTH [31:0] $end $var wire 32 d/ DATA_LENGTH [31:0] $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 1 Q/ ENABLE_OUTPUT_REG0 $end $var wire 1 Q/ ENABLE_OUTPUT_REG1 $end $var wire 8 L/ HEX_FILE [7:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 `/ INTERNAL_ADDR_WIDTH [31:0] $end $var wire 32 ]/ MANUAL_ADDR_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 ^/ TECHNOLOGY [31:0] $end $var wire 1 M, clk $end $var wire 1 N enable0 $end $var wire 1 O enable1 $end $var wire 1 e/ enable_output0 $end $var wire 1 e/ enable_output1 $end $var wire 1 N, rst $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module gen_xilinx $end $scope module xilinx_block_ram_double_inst $end $var wire 32 c/ ADDR_WIDTH [31:0] $end $var wire 32 d0 DATA_LENGTH [31:0] $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 1 Q/ ENABLE_OUTPUT_REG0 $end $var wire 1 Q/ ENABLE_OUTPUT_REG1 $end $var wire 8 L/ HEX_FILE [7:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 14 1) addr_in0 [13:0] $end $var wire 14 5) addr_in1 [13:0] $end $var wire 1 M, clk $end $var wire 32 2) data_in0 [31:0] $end $var wire 32 6) data_in1 [31:0] $end $var wire 32 3) data_out0 [31:0] $end $var wire 32 7) data_out1 [31:0] $end $var wire 32 3) data_out_temp0 [31:0] $end $var wire 32 7) data_out_temp1 [31:0] $end $var wire 1 ]! enable0 $end $var wire 1 ^! enable1 $end $var wire 1 e/ enable_output0 $end $var wire 1 e/ enable_output1 $end $var wire 1 N, rst $end $var wire 4 0) write_enable0 [3:0] $end $var wire 4 4) write_enable1 [3:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $scope module unnamedblk1 $end $var wire 32 = i [31:0] $end $upscope $end $upscope $end $upscope $end $scope module genblk2 $end $scope module id_reg_inst $end $var wire 1 f/ RESET_VECTOR [0:0] $end $var wire 1 M, clk $end $var wire 1 N enable $end $var wire 1 c$ next [0:0] $end $var wire 1 N, rst $end $var wire 1 P rst_actual $end $var wire 1 d$ value [0:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module last_reg_inst $end $var wire 1 g/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 N enable $end $var wire 1 e$ next $end $var wire 1 N, rst $end $var wire 1 Q rst_actual $end $var wire 1 f$ value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_reg_inst $end $var wire 1 h/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 R enable $end $var wire 1 Y$ next $end $var wire 1 N, rst $end $var wire 1 S rst_actual $end $var wire 1 g$ value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope module genblk3 $end $scope module id_reg_inst $end $var wire 1 i/ RESET_VECTOR [0:0] $end $var wire 1 M, clk $end $var wire 1 O enable $end $var wire 1 h$ next [0:0] $end $var wire 1 N, rst $end $var wire 1 T rst_actual $end $var wire 1 i$ value [0:0] $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module last_reg_inst $end $var wire 1 j/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 O enable $end $var wire 1 j$ next $end $var wire 1 N, rst $end $var wire 1 U rst_actual $end $var wire 1 k$ value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $scope module valid_reg_inst $end $var wire 1 g/ RESET_VECTOR $end $var wire 1 M, clk $end $var wire 1 V enable $end $var wire 1 Z$ next $end $var wire 1 N, rst $end $var wire 1 W rst_actual $end $var wire 1 l$ value $end $scope struct CLOCK_INFO $end $var wire 1 M/ clock_edge $end $var wire 1 O/ reset_clocking $end $var wire 1 N/ reset_polarity $end $upscope $end $upscope $end $upscope $end $scope interface mem_in0 $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 \* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 2) data [31:0] $end $var wire 1 c$ id [0:0] $end $var wire 1 e$ last $end $var wire 1 [* read_enable $end $var wire 1 0# ready $end $var wire 1 N, rst $end $var wire 1 /# valid $end $var wire 4 0) write_enable [3:0] $end $upscope $end $scope interface mem_in1 $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 ^* addr [31:0] $end $var wire 1 M, clk $end $var wire 32 6) data [31:0] $end $var wire 1 h$ id [0:0] $end $var wire 1 j$ last $end $var wire 1 ]* read_enable $end $var wire 1 2# ready $end $var wire 1 N, rst $end $var wire 1 W% valid $end $var wire 4 4) write_enable [3:0] $end $upscope $end $scope interface mem_out0 $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 >1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 3) data [31:0] $end $var wire 1 d$ id [0:0] $end $var wire 1 f$ last $end $var wire 1 <1 read_enable $end $var wire 1 1# ready $end $var wire 1 N, rst $end $var wire 1 g$ valid $end $var wire 4 =1 write_enable [3:0] $end $upscope $end $scope interface mem_out1 $end $var wire 1 Q/ ADDR_BYTE_SHIFTED $end $var wire 32 `/ ADDR_WIDTH [31:0] $end $var wire 1 Q/ DATA_ONLY $end $var wire 32 `/ DATA_WIDTH [31:0] $end $var wire 32 _/ ID_WIDTH [31:0] $end $var wire 32 a/ MASK_WIDTH [31:0] $end $var wire 32 A1 addr [31:0] $end $var wire 1 M, clk $end $var wire 32 7) data [31:0] $end $var wire 1 i$ id [0:0] $end $var wire 1 k$ last $end $var wire 1 ?1 read_enable $end $var wire 1 3# ready $end $var wire 1 N, rst $end $var wire 1 l$ valid $end $var wire 4 @1 write_enable [3:0] $end $upscope $end $upscope $end $scope interface tty_in $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 Q, payload [7:0] $end $var wire 1 ^$ ready $end $var wire 1 N, rst $end $var wire 1 O, valid $end $upscope $end $scope interface tty_out $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 `$ payload [7:0] $end $var wire 1 S, ready $end $var wire 1 N, rst $end $var wire 1 _$ valid $end $upscope $end $upscope $end $scope interface tty_in $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 Q, payload [7:0] $end $var wire 1 ^$ ready $end $var wire 1 N, rst $end $var wire 1 O, valid $end $upscope $end $scope interface tty_out $end $var wire 8 L/ T_LOGIC [7:0] $end $var wire 1 M, clk $end $var wire 8 `$ payload [7:0] $end $var wire 1 S, ready $end $var wire 1 N, rst $end $var wire 1 _$ valid $end $upscope $end $upscope $end $scope module gecko_pkg $end $var wire 3 81 GECKO_REG_STATUS_FULL [2:0] $end $var wire 3 71 GECKO_REG_STATUS_VALID [2:0] $end $upscope $end $scope module riscv32f_pkg $end $var wire 12 ;1 RISCV32F_CSR_FCSR [11:0] $end $var wire 12 91 RISCV32F_CSR_FFLAGS [11:0] $end $var wire 12 :1 RISCV32F_CSR_FRM [11:0] $end $upscope $end $scope module riscv32i_pkg $end $var wire 12 d1 RISCV32I_CSR_CYCLE [11:0] $end $var wire 12 g1 RISCV32I_CSR_CYCLEH [11:0] $end $var wire 12 k1 RISCV32I_CSR_EBREAK [11:0] $end $var wire 12 j1 RISCV32I_CSR_ECALL [11:0] $end $var wire 12 f1 RISCV32I_CSR_INSTRET [11:0] $end $var wire 12 i1 RISCV32I_CSR_INSTRETH [11:0] $end $var wire 12 e1 RISCV32I_CSR_TIME [11:0] $end $var wire 12 h1 RISCV32I_CSR_TIMEH [11:0] $end $upscope $end $upscope $end $enddefinitions $end #5 0# 0$ 0% 0& 0' 0( 0) 0* 0+ 0, 0- 0. 0/ 00 01 02 03 04 05 06 07 08 09 0: 0; 0< b00000000000000000100000000000000 = 0> 0? 0@ 0A 0B 0C 0D 0E b00000000000000000000000000100000 F b00000000000000000000000000100000 G b00000000000000000000000000100000 H b00000000000000000000000000100000 I b00000000000000000000000000100000 J b00000000000000000000000000100000 K b00000000000000000000000000100000 L 0M 1N 0O 1P 1Q 1R 1S 1T 1U 0V 1W 0X 0Y 1Z 0[ 0\ 0] 1^ 1_ 1` 0a 1b 1c 0d 1e 1f 0g 1h 1i 1j 1k b0000 l b1111 m 1n b1111 o 1p 1q b00000000000000000000000000000000000000000000000000000000000001001000 r 1u 0v 1w 1x 1y 1z 1{ 1| 1} 1~ 1!! 1"! 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1,! 1-! 1.! 1/! 10! 11! 12! 13! 14! 15! 16! 17! 18! 19! 1:! 1;! 1! b11 ?! 1@! b11 A! 0B! 0C! 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