- VHDL Standard
  - [IEEE 1076-1987](http://dx.doi.org/10.1109/IEEESTD.1988.122645)
  - [IEEE 1076-1993](http://dx.doi.org/10.1109/IEEESTD.1994.121433)
  - [IEEE 1076-2000](http://dx.doi.org/10.1109/IEEESTD.2000.92297)
  - [IEEE 1076-2002](http://dx.doi.org/10.1109/IEEESTD.2002.93614)
  - [IEEE 1076-2008](http://dx.doi.org/10.1109/IEEESTD.2009.4772740)

- Multivalue Logic System for VHDL Model Interoperability
  - [IEEE 1164-1993](http://dx.doi.org/10.1109/IEEESTD.1993.115571)

- Verilog Standard
  - [IEEE 1364-1995](http://dx.doi.org/10.1109/IEEESTD.1996.81542)
  - [IEEE 1364-2001](http://dx.doi.org/10.1109/IEEESTD.2001.93352)
  - [IEEE 1364-2005](http://dx.doi.org/10.1109/IEEESTD.2006.99495)

- SystemVerilog Standard
  - [IEEE 1800-2005](http://dx.doi.org/10.1109/IEEESTD.2005.97972)
  - [IEEE 1800-2009](http://dx.doi.org/10.1109/IEEESTD.2009.5354441)
  - [IEEE 1800-2012](http://dx.doi.org/10.1109/IEEESTD.2013.6469140)
  - [IEEE 1800-2017](http://dx.doi.org/10.1109/IEEESTD.2018.8299595)