msp430gen MSP430F2619 v0.4.0 8 16 16 read-write 0 SPECIAL_FUNCTION Special Function 0 IE1 Interrupt Enable 1 0 8 255 WDTIE Watchdog Interrupt Enable 0 1 read-write OFIE Osc. Fault Interrupt Enable 1 1 read-write NMIIE NMI Interrupt Enable 4 1 read-write ACCVIE Flash Access Violation Interrupt Enable 5 1 read-write IE2 Interrupt Enable 2 1 8 255 UCA0RXIE UCA0RXIE 0 1 read-write UCA0TXIE UCA0TXIE 1 1 read-write UCB0RXIE UCB0RXIE 2 1 read-write UCB0TXIE UCB0TXIE 3 1 read-write IFG1 Interrupt Flag 1 2 8 255 WDTIFG Watchdog Interrupt Flag 0 1 read-write OFIFG Osc. Fault Interrupt Flag 1 1 read-write PORIFG Power On Interrupt Flag 2 1 read-write RSTIFG Reset Interrupt Flag 3 1 read-write NMIIFG NMI Interrupt Flag 4 1 read-write IFG2 Interrupt Flag 2 3 8 255 UCA0RXIFG UCA0RXIFG 0 1 read-write UCA0TXIFG UCA0TXIFG 1 1 read-write UCB0RXIFG UCB0RXIFG 2 1 read-write UCB0TXIFG UCB0TXIFG 3 1 read-write UC1IE USCI 1 Interrupt Enable 6 8 255 UCA1RXIE UCA1RXIE 0 1 read-write UCA1TXIE UCA1TXIE 1 1 read-write UCB1RXIE UCB1RXIE 2 1 read-write UCB1TXIE UCB1TXIE 3 1 read-write UC1IFG ISCI 1 Interrupt Flags 7 8 255 UCA1RXIFG UCA1RXIFG 0 1 read-write UCA1TXIFG UCA1TXIFG 1 1 read-write UCB1RXIFG UCB1RXIFG 2 1 read-write UCB1TXIFG UCB1TXIFG 3 1 read-write PORT_3_4 Port 3/4 16 P3REN Port 3 Resistor Enable 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4REN Port 4 Resistor Enable 1 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3IN Port 3 Input 8 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3OUT Port 3 Output 9 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3DIR Port 3 Direction 10 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3SEL Port 3 Selection 11 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4IN Port 4 Input 12 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4OUT Port 4 Output 13 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4DIR Port 4 Direction 14 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4SEL Port 4 Selection 15 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PORT_5_6 Port 5/6 18 P5REN Port 5 Resistor Enable 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6REN Port 6 Resistor Enable 1 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5IN Port 5 Input 30 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5OUT Port 5 Output 31 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5DIR Port 5 Direction 32 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5SEL Port 5 Selection 33 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6IN Port 6 Input 34 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6OUT Port 6 Output 35 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6DIR Port 6 Direction 36 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6SEL Port 6 Selection 37 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PORT_7_8 Port 7/8 20 P7REN Port 7 Resistor Enable 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8REN Port 8 Resistor Enable 1 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7IN Port 7 Input 36 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8IN Port 8 Input 37 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7OUT Port 7 Output 38 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8OUT Port 8 Output 39 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7DIR Port 7 Direction 40 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8DIR Port 8 Direction 41 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7SEL Port 7 Selection 42 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8SEL Port 8 Selection 43 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PORT_1_2 Port 1/2 32 P1IN Port 1 Input 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1OUT Port 1 Output 1 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1DIR Port 1 Direction 2 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IFG Port 1 Interrupt Flag 3 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IES Port 1 Interrupt Edge Select 4 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IE Port 1 Interrupt Enable 5 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SEL Port 1 Selection 6 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1REN Port 1 Resistor Enable 7 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IN Port 2 Input 8 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2OUT Port 2 Output 9 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2DIR Port 2 Direction 10 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IFG Port 2 Interrupt Flag 11 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IES Port 2 Interrupt Edge Select 12 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IE Port 2 Interrupt Enable 13 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SEL Port 2 Selection 14 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2REN Port 2 Resistor Enable 15 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write SYSTEM_CLOCK System Clock 82 BCSCTL3 Basic Clock System Control 3 1 8 255 LFXT1OF Low/high Frequency Oscillator Fault Flag 0 1 read-write XT2OF High frequency oscillator 2 fault flag 1 1 read-write XCAP XIN/XOUT Cap 0 2 2 read-write XCAP_0 XIN/XOUT Cap : 0 pF 0 XCAP_1 XIN/XOUT Cap : 6 pF 1 XCAP_2 XIN/XOUT Cap : 10 pF 2 XCAP_3 XIN/XOUT Cap : 12.5 pF 3 LFXT1S Mode 0 for LFXT1 (XTS = 0) 4 2 read-write LFXT1S_0 Mode 0 for LFXT1 : Normal operation 0 LFXT1S_1 Mode 1 for LFXT1 : Reserved 1 LFXT1S_2 Mode 2 for LFXT1 : VLO 2 LFXT1S_3 Mode 3 for LFXT1 : Digital input signal 3 XT2S Mode 0 for XT2 6 2 read-write XT2S_0 Mode 0 for XT2 : 0.4 - 1 MHz 0 XT2S_1 Mode 1 for XT2 : 1 - 4 MHz 1 XT2S_2 Mode 2 for XT2 : 2 - 16 MHz 2 XT2S_3 Mode 3 for XT2 : Digital input signal 3 DCOCTL DCO Clock Frequency Control 4 8 255 0 255 MOD0 Modulation Bit 0 0 1 read-write MOD1 Modulation Bit 1 1 1 read-write MOD2 Modulation Bit 2 2 1 read-write MOD3 Modulation Bit 3 3 1 read-write MOD4 Modulation Bit 4 4 1 read-write DCO0 DCO Select Bit 0 5 1 read-write DCO1 DCO Select Bit 1 6 1 read-write DCO2 DCO Select Bit 2 7 1 read-write BCSCTL1 Basic Clock System Control 1 5 8 255 RSEL0 Range Select Bit 0 0 1 read-write RSEL1 Range Select Bit 1 1 1 read-write RSEL2 Range Select Bit 2 2 1 read-write RSEL3 Range Select Bit 3 3 1 read-write DIVA ACLK Divider 0 4 2 read-write DIVA_0 ACLK Divider 0: /1 0 DIVA_1 ACLK Divider 1: /2 1 DIVA_2 ACLK Divider 2: /4 2 DIVA_3 ACLK Divider 3: /8 3 XTS LFXTCLK 0:Low Freq. / 1: High Freq. 6 1 read-write XT2OFF Enable XT2CLK 7 1 read-write BCSCTL2 Basic Clock System Control 2 6 8 255 DCOR Enable External Resistor : 1 0 1 read-write DIVS SMCLK Divider 0 1 2 read-write DIVS_0 SMCLK Divider 0: /1 0 DIVS_1 SMCLK Divider 1: /2 1 DIVS_2 SMCLK Divider 2: /4 2 DIVS_3 SMCLK Divider 3: /8 3 SELS SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK 3 1 read-write DIVM MCLK Divider 0 4 2 read-write DIVM_0 MCLK Divider 0: /1 0 DIVM_1 MCLK Divider 1: /2 1 DIVM_2 MCLK Divider 2: /4 2 DIVM_3 MCLK Divider 3: /8 3 SELM MCLK Source Select 0 6 2 read-write SELM_0 MCLK Source Select 0: DCOCLK 0 SELM_1 MCLK Source Select 1: DCOCLK 1 SELM_2 MCLK Source Select 2: XT2CLK/LFXTCLK 2 SELM_3 MCLK Source Select 3: LFXTCLK 3 SUPPLY_VOLTAGE_SUPERVISOR Supply Voltage Supervisor 84 SVSCTL SVS Control 1 8 255 0 255 SVSFG SVS Flag 0 1 read-write SVSOP SVS output (read only) 1 1 read-write SVSON Switches the SVS on/off 2 1 read-write PORON Enable POR Generation if Low Voltage 3 1 read-write VLD0 VLD0 4 1 read-write VLD1 VLD1 5 1 read-write VLD2 VLD2 6 1 read-write VLD3 VLD3 7 1 read-write COMPARATOR_A Comparator A 88 CACTL1 Comparator A Control 1 1 8 255 CAIFG Comp. A Interrupt Flag 0 1 read-write CAIE Comp. A Interrupt Enable 1 1 read-write CAIES Comp. A Int. Edge Select: 0:rising / 1:falling 2 1 read-write CAON Comp. A enable 3 1 read-write CAREF Comp. A Internal Reference Select 0 4 2 read-write CAREF_0 Comp. A Int. Ref. Select 0 : Off 0 CAREF_1 Comp. A Int. Ref. Select 1 : 0.25*Vcc 1 CAREF_2 Comp. A Int. Ref. Select 2 : 0.5*Vcc 2 CAREF_3 Comp. A Int. Ref. Select 3 : Vt 3 CARSEL Comp. A Internal Reference Enable 6 1 read-write CAEX Comp. A Exchange Inputs 7 1 read-write CACTL2 Comparator A Control 2 2 8 255 0 255 CAOUT Comp. A Output 0 1 read-write CAF Comp. A Enable Output Filter 1 1 read-write P2CA0 Comp. A +Terminal Multiplexer 2 1 read-write P2CA1 Comp. A -Terminal Multiplexer 3 1 read-write P2CA2 Comp. A -Terminal Multiplexer 4 1 read-write P2CA3 Comp. A -Terminal Multiplexer 5 1 read-write P2CA4 Comp. A +Terminal Multiplexer 6 1 read-write CASHORT Comp. A Short + and - Terminals 7 1 read-write CAPD Comparator A Port Disable 3 8 255 0 255 CAPD0 Comp. A Disable Input Buffer of Port Register .0 0 1 read-write CAPD1 Comp. A Disable Input Buffer of Port Register .1 1 1 read-write CAPD2 Comp. A Disable Input Buffer of Port Register .2 2 1 read-write CAPD3 Comp. A Disable Input Buffer of Port Register .3 3 1 read-write CAPD4 Comp. A Disable Input Buffer of Port Register .4 4 1 read-write CAPD5 Comp. A Disable Input Buffer of Port Register .5 5 1 read-write CAPD6 Comp. A Disable Input Buffer of Port Register .6 6 1 read-write CAPD7 Comp. A Disable Input Buffer of Port Register .7 7 1 read-write USCI_A0_UART_MODE USCI_A0 UART Mode 92 UCA0ABCTL USCI A0 LIN Control 1 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM0 Break Sync Delimiter 0 4 1 read-write UCDELIM1 Break Sync Delimiter 1 5 1 read-write UCA0IRTCTL USCI A0 IrDA Transmit Control 2 8 255 0 255 UCIREN IRDA Encoder/Decoder enable 0 1 read-write UCIRTXCLK IRDA Transmit Pulse Clock Select 1 1 read-write UCIRTXPL0 IRDA Transmit Pulse Length 0 2 1 read-write UCIRTXPL1 IRDA Transmit Pulse Length 1 3 1 read-write UCIRTXPL2 IRDA Transmit Pulse Length 2 4 1 read-write UCIRTXPL3 IRDA Transmit Pulse Length 3 5 1 read-write UCIRTXPL4 IRDA Transmit Pulse Length 4 6 1 read-write UCIRTXPL5 IRDA Transmit Pulse Length 5 7 1 read-write UCA0IRRCTL USCI A0 IrDA Receive Control 3 8 255 0 255 UCIRRXFE IRDA Receive Filter enable 0 1 read-write UCIRRXPL IRDA Receive Input Polarity 1 1 read-write UCIRRXFL0 IRDA Receive Filter Length 0 2 1 read-write UCIRRXFL1 IRDA Receive Filter Length 1 3 1 read-write UCIRRXFL2 IRDA Receive Filter Length 2 4 1 read-write UCIRRXFL3 IRDA Receive Filter Length 3 5 1 read-write UCIRRXFL4 IRDA Receive Filter Length 4 6 1 read-write UCIRRXFL5 IRDA Receive Filter Length 5 7 1 read-write UCA0CTL0 USCI A0 Control Register 0 4 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Async. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCSPB Async. Mode: Stop Bits 0:one / 1: two 3 1 read-write UC7BIT Async. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Async. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCPAR Async. Mode: Parity 0:odd / 1:even 6 1 read-write UCPEN Async. Mode: Parity enable 7 1 read-write UCA0CTL1 USCI A0 Control Register 1 5 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXBRK Send next Data as Break 1 1 read-write UCTXADDR Send next Data as Address 2 1 read-write UCDORM Dormant (Sleep) Mode 3 1 read-write UCBRKIE Break interrupt enable 4 1 read-write UCRXEIE RX Error interrupt enable 5 1 read-write UCSSEL USCI 0 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA0BR0 USCI A0 Baud Rate 0 6 8 255 UCA0BR1 USCI A0 Baud Rate 1 7 8 255 UCA0MCTL USCI A0 Modulation Control 8 8 255 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRS USCI Second Stage Modulation Select 2 1 3 read-write UCBRS_0 USCI Second Stage Modulation: 0 0 UCBRS_1 USCI Second Stage Modulation: 1 1 UCBRS_2 USCI Second Stage Modulation: 2 2 UCBRS_3 USCI Second Stage Modulation: 3 3 UCBRS_4 USCI Second Stage Modulation: 4 4 UCBRS_5 USCI Second Stage Modulation: 5 5 UCBRS_6 USCI Second Stage Modulation: 6 6 UCBRS_7 USCI Second Stage Modulation: 7 7 UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCA0STAT USCI A0 Status Register 9 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0RXBUF USCI A0 Receive Buffer 10 8 255 UCA0TXBUF USCI A0 Transmit Buffer 11 8 255 USCI_A0_SPI_MODE USCI_A0 SPI Mode 96 UCA0CTL0_SPI USCI A0 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCA0CTL1_SPI USCI A0 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA0BR0_SPI USCI A0 Baud Rate 0 2 8 255 UCA0BR1_SPI USCI A0 Baud Rate 1 3 8 255 UCA0MCTL_SPI USCI A0 Modulation Control 4 8 255 UCA0STAT_SPI USCI A0 Status Register 5 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0RXBUF_SPI USCI A0 Receive Buffer 6 8 255 UCA0TXBUF_SPI USCI A0 Transmit Buffer 7 8 255 USCI_B0_I2C_MODE USCI_B0 I2C Mode 104 UCB0CTL0 USCI B0 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UCMM Multi-Master Environment 5 1 read-write UCSLA10 10-bit Slave Address Mode 6 1 read-write UCA10 10-bit Address Mode 7 1 read-write UCB0CTL1 USCI B0 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXSTT Transmit START 1 1 read-write UCTXSTP Transmit STOP 2 1 read-write UCTXNACK Transmit NACK 3 1 read-write UCTR Transmit/Receive Select/Flag 4 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB0BR0 USCI B0 Baud Rate 0 2 8 255 UCB0BR1 USCI B0 Baud Rate 1 3 8 255 UCB0I2CIE USCI B0 I2C Interrupt Enable Register 4 8 255 UCALIE Arbitration Lost interrupt enable 0 1 read-write UCSTTIE START Condition interrupt enable 1 1 read-write UCSTPIE STOP Condition interrupt enable 2 1 read-write UCNACKIE NACK Condition interrupt enable 3 1 read-write UCB0STAT USCI B0 Status Register 5 8 255 0 255 UCALIFG Arbitration Lost interrupt Flag 0 1 read-write UCSTTIFG START Condition interrupt Flag 1 1 read-write UCSTPIFG STOP Condition interrupt Flag 2 1 read-write UCNACKIFG NAK Condition interrupt Flag 3 1 read-write UCBBUSY Bus Busy Flag 4 1 read-write UCGC General Call address received Flag 5 1 read-write UCSCLLOW SCL low 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB0RXBUF USCI B0 Receive Buffer 6 8 255 UCB0TXBUF USCI B0 Transmit Buffer 7 8 255 UCB0I2COA USCI B0 I2C Own Address 176 16 65535 UCOA0 I2C Own Address 0 0 1 read-write UCOA1 I2C Own Address 1 1 1 read-write UCOA2 I2C Own Address 2 2 1 read-write UCOA3 I2C Own Address 3 3 1 read-write UCOA4 I2C Own Address 4 4 1 read-write UCOA5 I2C Own Address 5 5 1 read-write UCOA6 I2C Own Address 6 6 1 read-write UCOA7 I2C Own Address 7 7 1 read-write UCOA8 I2C Own Address 8 8 1 read-write UCOA9 I2C Own Address 9 9 1 read-write UCGCEN I2C General Call enable 15 1 read-write UCB0I2CSA USCI B0 I2C Slave Address 178 16 65535 UCSA0 I2C Slave Address 0 0 1 read-write UCSA1 I2C Slave Address 1 1 1 read-write UCSA2 I2C Slave Address 2 2 1 read-write UCSA3 I2C Slave Address 3 3 1 read-write UCSA4 I2C Slave Address 4 4 1 read-write UCSA5 I2C Slave Address 5 5 1 read-write UCSA6 I2C Slave Address 6 6 1 read-write UCSA7 I2C Slave Address 7 7 1 read-write UCSA8 I2C Slave Address 8 8 1 read-write UCSA9 I2C Slave Address 9 9 1 read-write USCI_B0_SPI_MODE USCI_B0 SPI Mode 104 UCB0CTL0_SPI USCI B0 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCB0CTL1_SPI USCI B0 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB0BR0_SPI USCI B0 Baud Rate 0 2 8 255 UCB0BR1_SPI USCI B0 Baud Rate 1 3 8 255 UCB0STAT_SPI USCI B0 Status Register 5 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB0RXBUF_SPI USCI B0 Receive Buffer 6 8 255 UCB0TXBUF_SPI USCI B0 Transmit Buffer 7 8 255 ADC12 ADC12 128 ADC12MCTL0 ADC12 Memory Control 0 0 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL1 ADC12 Memory Control 1 1 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL2 ADC12 Memory Control 2 2 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL3 ADC12 Memory Control 3 3 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL4 ADC12 Memory Control 4 4 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL5 ADC12 Memory Control 5 5 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL6 ADC12 Memory Control 6 6 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL7 ADC12 Memory Control 7 7 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL8 ADC12 Memory Control 8 8 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL9 ADC12 Memory Control 9 9 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL10 ADC12 Memory Control 10 10 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL11 ADC12 Memory Control 11 11 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL12 ADC12 Memory Control 12 12 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL13 ADC12 Memory Control 13 13 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL14 ADC12 Memory Control 14 14 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL15 ADC12 Memory Control 15 15 8 255 INCH ADC12 Input Channel Select Bit 0 0 4 read-write INCH_0 ADC12 Input Channel 0 0 INCH_1 ADC12 Input Channel 1 1 INCH_2 ADC12 Input Channel 2 2 INCH_3 ADC12 Input Channel 3 3 INCH_4 ADC12 Input Channel 4 4 INCH_5 ADC12 Input Channel 5 5 INCH_6 ADC12 Input Channel 6 6 INCH_7 ADC12 Input Channel 7 7 INCH_8 ADC12 Input Channel 8 8 INCH_9 ADC12 Input Channel 9 9 INCH_10 ADC12 Input Channel 10 10 INCH_11 ADC12 Input Channel 11 11 INCH_12 ADC12 Input Channel 12 12 INCH_13 ADC12 Input Channel 13 13 INCH_14 ADC12 Input Channel 14 14 INCH_15 ADC12 Input Channel 15 15 SREF ADC12 Select Reference Bit 0 4 3 read-write SREF_0 ADC12 Select Reference 0 0 SREF_1 ADC12 Select Reference 1 1 SREF_2 ADC12 Select Reference 2 2 SREF_3 ADC12 Select Reference 3 3 SREF_4 ADC12 Select Reference 4 4 SREF_5 ADC12 Select Reference 5 5 SREF_6 ADC12 Select Reference 6 6 SREF_7 ADC12 Select Reference 7 7 EOS ADC12 End of Sequence 7 1 read-write ADC12MEM0 ADC12 Conversion Memory 0 192 16 65535 ADC12MEM1 ADC12 Conversion Memory 1 194 16 65535 ADC12MEM2 ADC12 Conversion Memory 2 196 16 65535 ADC12MEM3 ADC12 Conversion Memory 3 198 16 65535 ADC12MEM4 ADC12 Conversion Memory 4 200 16 65535 ADC12MEM5 ADC12 Conversion Memory 5 202 16 65535 ADC12MEM6 ADC12 Conversion Memory 6 204 16 65535 ADC12MEM7 ADC12 Conversion Memory 7 206 16 65535 ADC12MEM8 ADC12 Conversion Memory 8 208 16 65535 ADC12MEM9 ADC12 Conversion Memory 9 210 16 65535 ADC12MEM10 ADC12 Conversion Memory 10 212 16 65535 ADC12MEM11 ADC12 Conversion Memory 11 214 16 65535 ADC12MEM12 ADC12 Conversion Memory 12 216 16 65535 ADC12MEM13 ADC12 Conversion Memory 13 218 16 65535 ADC12MEM14 ADC12 Conversion Memory 14 220 16 65535 ADC12MEM15 ADC12 Conversion Memory 15 222 16 65535 ADC12CTL0 ADC12 Control 0 288 16 65535 ADC12SC ADC12 Start Conversion 0 1 read-write ENC ADC12 Enable Conversion 1 1 read-write ADC12TOVIE ADC12 Timer Overflow interrupt enable 2 1 read-write ADC12OVIE ADC12 Overflow interrupt enable 3 1 read-write ADC12ON ADC12 On/enable 4 1 read-write REFON ADC12 Reference on 5 1 read-write REF2_5V ADC12 Ref 0:1.5V / 1:2.5V 6 1 read-write MSC ADC12 Multiple SampleConversion 7 1 read-write SHT0 ADC12 Sample Hold 0 Select 0 8 4 read-write SHT0_0 ADC12 Sample Hold 0 Select Bit: 0 0 SHT0_1 ADC12 Sample Hold 0 Select Bit: 1 1 SHT0_2 ADC12 Sample Hold 0 Select Bit: 2 2 SHT0_3 ADC12 Sample Hold 0 Select Bit: 3 3 SHT0_4 ADC12 Sample Hold 0 Select Bit: 4 4 SHT0_5 ADC12 Sample Hold 0 Select Bit: 5 5 SHT0_6 ADC12 Sample Hold 0 Select Bit: 6 6 SHT0_7 ADC12 Sample Hold 0 Select Bit: 7 7 SHT0_8 ADC12 Sample Hold 0 Select Bit: 8 8 SHT0_9 ADC12 Sample Hold 0 Select Bit: 9 9 SHT0_10 ADC12 Sample Hold 0 Select Bit: 10 10 SHT0_11 ADC12 Sample Hold 0 Select Bit: 11 11 SHT0_12 ADC12 Sample Hold 0 Select Bit: 12 12 SHT0_13 ADC12 Sample Hold 0 Select Bit: 13 13 SHT0_14 ADC12 Sample Hold 0 Select Bit: 14 14 SHT0_15 ADC12 Sample Hold 0 Select Bit: 15 15 SHT1 ADC12 Sample Hold 0 Select 0 12 4 read-write SHT1_0 ADC12 Sample Hold 1 Select Bit: 0 0 SHT1_1 ADC12 Sample Hold 1 Select Bit: 1 1 SHT1_2 ADC12 Sample Hold 1 Select Bit: 2 2 SHT1_3 ADC12 Sample Hold 1 Select Bit: 3 3 SHT1_4 ADC12 Sample Hold 1 Select Bit: 4 4 SHT1_5 ADC12 Sample Hold 1 Select Bit: 5 5 SHT1_6 ADC12 Sample Hold 1 Select Bit: 6 6 SHT1_7 ADC12 Sample Hold 1 Select Bit: 7 7 SHT1_8 ADC12 Sample Hold 1 Select Bit: 8 8 SHT1_9 ADC12 Sample Hold 1 Select Bit: 9 9 SHT1_10 ADC12 Sample Hold 1 Select Bit: 10 10 SHT1_11 ADC12 Sample Hold 1 Select Bit: 11 11 SHT1_12 ADC12 Sample Hold 1 Select Bit: 12 12 SHT1_13 ADC12 Sample Hold 1 Select Bit: 13 13 SHT1_14 ADC12 Sample Hold 1 Select Bit: 14 14 SHT1_15 ADC12 Sample Hold 1 Select Bit: 15 15 ADC12CTL1 ADC12 Control 1 290 16 65535 ADC12BUSY ADC12 Busy 0 1 read-write CONSEQ ADC12 Conversion Sequence Select 0 1 2 read-write CONSEQ_0 ADC12 Conversion Sequence Select: 0 0 CONSEQ_1 ADC12 Conversion Sequence Select: 1 1 CONSEQ_2 ADC12 Conversion Sequence Select: 2 2 CONSEQ_3 ADC12 Conversion Sequence Select: 3 3 ADC12SSEL ADC12 Clock Source Select 0 3 2 read-write ADC12SSEL_0 ADC12 Clock Source Select: 0 0 ADC12SSEL_1 ADC12 Clock Source Select: 1 1 ADC12SSEL_2 ADC12 Clock Source Select: 2 2 ADC12SSEL_3 ADC12 Clock Source Select: 3 3 ADC12DIV ADC12 Clock Divider Select 0 5 3 read-write ADC12DIV_0 ADC12 Clock Divider Select: 0 0 ADC12DIV_1 ADC12 Clock Divider Select: 1 1 ADC12DIV_2 ADC12 Clock Divider Select: 2 2 ADC12DIV_3 ADC12 Clock Divider Select: 3 3 ADC12DIV_4 ADC12 Clock Divider Select: 4 4 ADC12DIV_5 ADC12 Clock Divider Select: 5 5 ADC12DIV_6 ADC12 Clock Divider Select: 6 6 ADC12DIV_7 ADC12 Clock Divider Select: 7 7 ISSH ADC12 Invert Sample Hold Signal 8 1 read-write SHP ADC12 Sample/Hold Pulse Mode 9 1 read-write SHS ADC12 Sample/Hold Source 0 10 2 read-write SHS_0 ADC12 Sample/Hold Source: 0 0 SHS_1 ADC12 Sample/Hold Source: 1 1 SHS_2 ADC12 Sample/Hold Source: 2 2 SHS_3 ADC12 Sample/Hold Source: 3 3 CSTARTADD ADC12 Conversion Start Address 0 12 4 read-write CSTARTADD_0 ADC12 Conversion Start Address: 0 0 CSTARTADD_1 ADC12 Conversion Start Address: 1 1 CSTARTADD_2 ADC12 Conversion Start Address: 2 2 CSTARTADD_3 ADC12 Conversion Start Address: 3 3 CSTARTADD_4 ADC12 Conversion Start Address: 4 4 CSTARTADD_5 ADC12 Conversion Start Address: 5 5 CSTARTADD_6 ADC12 Conversion Start Address: 6 6 CSTARTADD_7 ADC12 Conversion Start Address: 7 7 CSTARTADD_8 ADC12 Conversion Start Address: 8 8 CSTARTADD_9 ADC12 Conversion Start Address: 9 9 CSTARTADD_10 ADC12 Conversion Start Address: 10 10 CSTARTADD_11 ADC12 Conversion Start Address: 11 11 CSTARTADD_12 ADC12 Conversion Start Address: 12 12 CSTARTADD_13 ADC12 Conversion Start Address: 13 13 CSTARTADD_14 ADC12 Conversion Start Address: 14 14 CSTARTADD_15 ADC12 Conversion Start Address: 15 15 ADC12IFG ADC12 Interrupt Flag 292 16 65535 ADC12IE ADC12 Interrupt Enable 294 16 65535 ADC12IV ADC12 Interrupt Vector Word 296 16 65535 USCI_A1_UART_MODE USCI_A1 UART Mode 204 UCA1ABCTL USCI A1 LIN Control 1 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM0 Break Sync Delimiter 0 4 1 read-write UCDELIM1 Break Sync Delimiter 1 5 1 read-write UCA1IRTCTL USCI A1 IrDA Transmit Control 2 8 255 0 255 UCIREN IRDA Encoder/Decoder enable 0 1 read-write UCIRTXCLK IRDA Transmit Pulse Clock Select 1 1 read-write UCIRTXPL0 IRDA Transmit Pulse Length 0 2 1 read-write UCIRTXPL1 IRDA Transmit Pulse Length 1 3 1 read-write UCIRTXPL2 IRDA Transmit Pulse Length 2 4 1 read-write UCIRTXPL3 IRDA Transmit Pulse Length 3 5 1 read-write UCIRTXPL4 IRDA Transmit Pulse Length 4 6 1 read-write UCIRTXPL5 IRDA Transmit Pulse Length 5 7 1 read-write UCA1IRRCTL USCI A1 IrDA Receive Control 3 8 255 0 255 UCIRRXFE IRDA Receive Filter enable 0 1 read-write UCIRRXPL IRDA Receive Input Polarity 1 1 read-write UCIRRXFL0 IRDA Receive Filter Length 0 2 1 read-write UCIRRXFL1 IRDA Receive Filter Length 1 3 1 read-write UCIRRXFL2 IRDA Receive Filter Length 2 4 1 read-write UCIRRXFL3 IRDA Receive Filter Length 3 5 1 read-write UCIRRXFL4 IRDA Receive Filter Length 4 6 1 read-write UCIRRXFL5 IRDA Receive Filter Length 5 7 1 read-write UCA1CTL0 USCI A1 Control Register 0 4 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Async. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCSPB Async. Mode: Stop Bits 0:one / 1: two 3 1 read-write UC7BIT Async. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Async. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCPAR Async. Mode: Parity 0:odd / 1:even 6 1 read-write UCPEN Async. Mode: Parity enable 7 1 read-write UCA1CTL1 USCI A1 Control Register 1 5 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXBRK Send next Data as Break 1 1 read-write UCTXADDR Send next Data as Address 2 1 read-write UCDORM Dormant (Sleep) Mode 3 1 read-write UCBRKIE Break interrupt enable 4 1 read-write UCRXEIE RX Error interrupt enable 5 1 read-write UCSSEL USCI 0 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA1BR0 USCI A1 Baud Rate 0 6 8 255 UCA1BR1 USCI A1 Baud Rate 1 7 8 255 UCA1MCTL USCI A1 Modulation Control 8 8 255 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRS USCI Second Stage Modulation Select 2 1 3 read-write UCBRS_0 USCI Second Stage Modulation: 0 0 UCBRS_1 USCI Second Stage Modulation: 1 1 UCBRS_2 USCI Second Stage Modulation: 2 2 UCBRS_3 USCI Second Stage Modulation: 3 3 UCBRS_4 USCI Second Stage Modulation: 4 4 UCBRS_5 USCI Second Stage Modulation: 5 5 UCBRS_6 USCI Second Stage Modulation: 6 6 UCBRS_7 USCI Second Stage Modulation: 7 7 UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCA1STAT USCI A1 Status Register 9 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA1RXBUF USCI A1 Receive Buffer 10 8 255 UCA1TXBUF USCI A1 Transmit Buffer 11 8 255 USCI_A1_SPI_MODE USCI_A1 SPI Mode 208 UCA1CTL0_SPI USCI A1 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCA1CTL1_SPI USCI A1 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA1BR0_SPI USCI A1 Baud Rate 0 2 8 255 UCA1BR1_SPI USCI A1 Baud Rate 1 3 8 255 UCA1MCTL_SPI USCI A1 Modulation Control 4 8 255 UCA1STAT_SPI USCI A1 Status Register 5 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA1RXBUF_SPI USCI A1 Receive Buffer 6 8 255 UCA1TXBUF_SPI USCI A1 Transmit Buffer 7 8 255 USCI_B1_I2C_MODE USCI_B1 I2C Mode 216 UCB1CTL0 USCI B1 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UCMM Multi-Master Environment 5 1 read-write UCSLA10 10-bit Slave Address Mode 6 1 read-write UCA10 10-bit Address Mode 7 1 read-write UCB1CTL1 USCI B1 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXSTT Transmit START 1 1 read-write UCTXSTP Transmit STOP 2 1 read-write UCTXNACK Transmit NACK 3 1 read-write UCTR Transmit/Receive Select/Flag 4 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB1BR0 USCI B1 Baud Rate 0 2 8 255 UCB1BR1 USCI B1 Baud Rate 1 3 8 255 UCB1I2CIE USCI B1 I2C Interrupt Enable Register 4 8 255 UCALIE Arbitration Lost interrupt enable 0 1 read-write UCSTTIE START Condition interrupt enable 1 1 read-write UCSTPIE STOP Condition interrupt enable 2 1 read-write UCNACKIE NACK Condition interrupt enable 3 1 read-write UCB1STAT USCI B1 Status Register 5 8 255 0 255 UCALIFG Arbitration Lost interrupt Flag 0 1 read-write UCSTTIFG START Condition interrupt Flag 1 1 read-write UCSTPIFG STOP Condition interrupt Flag 2 1 read-write UCNACKIFG NAK Condition interrupt Flag 3 1 read-write UCBBUSY Bus Busy Flag 4 1 read-write UCGC General Call address received Flag 5 1 read-write UCSCLLOW SCL low 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB1RXBUF USCI B1 Receive Buffer 6 8 255 UCB1TXBUF USCI B1 Transmit Buffer 7 8 255 UCB1I2COA USCI B1 I2C Own Address 164 16 65535 UCOA0 I2C Own Address 0 0 1 read-write UCOA1 I2C Own Address 1 1 1 read-write UCOA2 I2C Own Address 2 2 1 read-write UCOA3 I2C Own Address 3 3 1 read-write UCOA4 I2C Own Address 4 4 1 read-write UCOA5 I2C Own Address 5 5 1 read-write UCOA6 I2C Own Address 6 6 1 read-write UCOA7 I2C Own Address 7 7 1 read-write UCOA8 I2C Own Address 8 8 1 read-write UCOA9 I2C Own Address 9 9 1 read-write UCGCEN I2C General Call enable 15 1 read-write UCB1I2CSA USCI B1 I2C Slave Address 166 16 65535 UCSA0 I2C Slave Address 0 0 1 read-write UCSA1 I2C Slave Address 1 1 1 read-write UCSA2 I2C Slave Address 2 2 1 read-write UCSA3 I2C Slave Address 3 3 1 read-write UCSA4 I2C Slave Address 4 4 1 read-write UCSA5 I2C Slave Address 5 5 1 read-write UCSA6 I2C Slave Address 6 6 1 read-write UCSA7 I2C Slave Address 7 7 1 read-write UCSA8 I2C Slave Address 8 8 1 read-write UCSA9 I2C Slave Address 9 9 1 read-write USCI_B1_SPI_MODE USCI_B1 SPI Mode 216 UCB1CTL0_SPI USCI B1 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCB1CTL1_SPI USCI B1 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB1BR0_SPI USCI B1 Baud Rate 0 2 8 255 UCB1BR1_SPI USCI B1 Baud Rate 1 3 8 255 UCB1STAT_SPI USCI B1 Status Register 5 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB1RXBUF_SPI USCI B1 Receive Buffer 6 8 255 UCB1TXBUF_SPI USCI B1 Transmit Buffer 7 8 255 TLV_CALIBRATION_DATA TLV Calibration Data 4288 TLV_ADC12_1_TAG TLV ADC12_1 TAG 26 8 255 TLV_ADC12_1_LEN TLV ADC12_1 LEN 27 8 255 TLV_DCO_30_TAG TLV TAG_DCO30 TAG 54 8 255 TLV_DCO_30_LEN TLV TAG_DCO30 LEN 55 8 255 TLV_CHECKSUM TLV CHECK SUM 0 16 65535 CALIBRATION_DATA Calibration Data 4344 CALDCO_16MHZ DCOCTL Calibration Data for 16MHz 0 8 255 CALBC1_16MHZ BCSCTL1 Calibration Data for 16MHz 1 8 255 CALDCO_12MHZ DCOCTL Calibration Data for 12MHz 2 8 255 CALBC1_12MHZ BCSCTL1 Calibration Data for 12MHz 3 8 255 CALDCO_8MHZ DCOCTL Calibration Data for 8MHz 4 8 255 CALBC1_8MHZ BCSCTL1 Calibration Data for 8MHz 5 8 255 CALDCO_1MHZ DCOCTL Calibration Data for 1MHz 6 8 255 CALBC1_1MHZ BCSCTL1 Calibration Data for 1MHz 7 8 255 TIMER_B7 Timer B7 286 TBIV Timer B Interrupt Vector Word 0 16 65535 TBCTL Timer B Control 98 16 65535 TBIFG Timer B interrupt flag 0 1 read-write TBIE Timer B interrupt enable 1 1 read-write TBCLR Timer B counter clear 2 1 read-write MC Timer B mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer B clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TBSSEL Clock source 1 8 2 read-write TBSSEL_0 Clock Source: TBCLK 0 TBSSEL_1 Clock Source: ACLK 1 TBSSEL_2 Clock Source: SMCLK 2 TBSSEL_3 Clock Source: INCLK 3 CNTL Counter lenght 1 11 2 read-write CNTL_0 Counter lenght: 16 bit 0 CNTL_1 Counter lenght: 12 bit 1 CNTL_2 Counter lenght: 10 bit 2 CNTL_3 Counter lenght: 8 bit 3 TBCLGRP Timer B Compare latch load group 1 13 2 read-write TBCLGRP_0 Timer B Group: 0 - individually 0 TBCLGRP_1 Timer B Group: 1 - 3 groups (1-2 1 TBCLGRP_2 Timer B Group: 2 - 2 groups (1-3 2 TBCLGRP_3 Timer B Group: 3 - 1 group (all) 3 TBCCTL0 Timer B Capture/Compare Control 0 100 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBCCTL1 Timer B Capture/Compare Control 1 102 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBCCTL2 Timer B Capture/Compare Control 2 104 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBCCTL3 Timer B Capture/Compare Control 3 106 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBCCTL4 Timer B Capture/Compare Control 4 108 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBCCTL5 Timer B Capture/Compare Control 5 110 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBCCTL6 Timer B Capture/Compare Control 6 112 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TBR Timer B Counter Register 114 16 65535 TBCCR0 Timer B Capture/Compare 0 116 16 65535 TBCCR1 Timer B Capture/Compare 1 118 16 65535 TBCCR2 Timer B Capture/Compare 2 120 16 65535 TBCCR3 Timer B Capture/Compare 3 122 16 65535 TBCCR4 Timer B Capture/Compare 4 124 16 65535 TBCCR5 Timer B Capture/Compare 5 126 16 65535 TBCCR6 Timer B Capture/Compare 6 128 16 65535 WATCHDOG_TIMER Watchdog Timer 288 WDTCTL Watchdog Timer Control 0 16 65535 WDTIS0 WDTIS0 0 1 read-write WDTIS1 WDTIS1 1 1 read-write WDTSSEL WDTSSEL 2 1 read-write WDTCNTCL WDTCNTCL 3 1 read-write WDTTMSEL WDTTMSEL 4 1 read-write WDTNMI WDTNMI 5 1 read-write WDTNMIES WDTNMIES 6 1 read-write WDTHOLD WDTHOLD 7 1 read-write DMA DMA 290 DMACTL0 DMA Module Control 0 0 16 65535 DMA0TSEL DMA channel 0 transfer select bit 0 0 4 read-write DMA0TSEL_0 DMA channel 0 transfer select 0: DMA_REQ (sw) 0 DMA0TSEL_1 DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) 1 DMA0TSEL_2 DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) 2 DMA0TSEL_3 DMA channel 0 transfer select 3: USCIA0 receive 3 DMA0TSEL_4 DMA channel 0 transfer select 4: USCIA0 transmit 4 DMA0TSEL_5 DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG 5 DMA0TSEL_6 DMA channel 0 transfer select 6: ADC12 (ADC12IFG) 6 DMA0TSEL_7 DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) 7 DMA0TSEL_8 DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) 8 DMA0TSEL_9 DMA channel 0 transfer select 9: USCIA1 receive 9 DMA0TSEL_10 DMA channel 0 transfer select 10: USCIA1 transmit 10 DMA0TSEL_11 DMA channel 0 transfer select 11: Multiplier ready 11 DMA0TSEL_12 DMA channel 0 transfer select 12: USCIB0 receive 12 DMA0TSEL_13 DMA channel 0 transfer select 13: USCIB0 transmit 13 DMA0TSEL_14 DMA channel 0 transfer select 14: previous DMA channel DMA2IFG 14 DMA0TSEL_15 DMA channel 0 transfer select 15: ext. Trigger (DMAE0) 15 DMA1TSEL DMA channel 1 transfer select bit 0 4 4 read-write DMA1TSEL_0 DMA channel 1 transfer select 0: DMA_REQ 0 DMA1TSEL_1 DMA channel 1 transfer select 1: Timer_A CCRIFG.2 1 DMA1TSEL_2 DMA channel 1 transfer select 2: Timer_B CCRIFG.2 2 DMA1TSEL_3 DMA channel 1 transfer select 3: USCIA0 receive 3 DMA1TSEL_4 DMA channel 1 transfer select 4: USCIA0 transmit 4 DMA1TSEL_5 DMA channel 1 transfer select 5: DAC12.0IFG 5 DMA1TSEL_6 DMA channel 1 transfer select 6: ADC12 (ADC12IFG) 6 DMA1TSEL_7 DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) 7 DMA1TSEL_8 DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) 8 DMA1TSEL_9 DMA channel 1 transfer select 9: USCIA1 receive 9 DMA1TSEL_10 DMA channel 1 transfer select 10: USCIA1 transmit 10 DMA1TSEL_11 DMA channel 1 transfer select 11: Multiplier ready 11 DMA1TSEL_12 DMA channel 1 transfer select 12: USCIB0 receive 12 DMA1TSEL_13 DMA channel 1 transfer select 13: USCIB0 transmit 13 DMA1TSEL_14 DMA channel 1 transfer select 14: previous DMA channel DMA0IFG 14 DMA1TSEL_15 DMA channel 1 transfer select 15: ext. Trigger (DMAE0) 15 DMA2TSEL DMA channel 2 transfer select bit 0 8 4 read-write DMA2TSEL_0 DMA channel 2 transfer select 0: DMA_REQ 0 DMA2TSEL_1 DMA channel 2 transfer select 1: Timer_A CCRIFG.2 1 DMA2TSEL_2 DMA channel 2 transfer select 2: Timer_B CCRIFG.2 2 DMA2TSEL_3 DMA channel 2 transfer select 3: USCIA0 receive 3 DMA2TSEL_4 DMA channel 2 transfer select 4: USCIA0 transmit 4 DMA2TSEL_5 DMA channel 2 transfer select 5: DAC12.0IFG 5 DMA2TSEL_6 DMA channel 2 transfer select 6: ADC12 (ADC12IFG) 6 DMA2TSEL_7 DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) 7 DMA2TSEL_8 DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) 8 DMA2TSEL_9 DMA channel 2 transfer select 9: USCIA1 receive 9 DMA2TSEL_10 DMA channel 2 transfer select 10: USCIA1 transmit 10 DMA2TSEL_11 DMA channel 2 transfer select 11: Multiplier ready 11 DMA2TSEL_12 DMA channel 2 transfer select 12: USCIB0 receive 12 DMA2TSEL_13 DMA channel 2 transfer select 13: USCIB0 transmit 13 DMA2TSEL_14 DMA channel 2 transfer select 14: previous DMA channel DMA1IFG 14 DMA2TSEL_15 DMA channel 2 transfer select 15: ext. Trigger (DMAE0) 15 DMACTL1 DMA Module Control 1 2 16 65535 ENNMI Enable NMI interruption of DMA 0 1 read-write ROUNDROBIN Round-Robin DMA channel priorities 1 1 read-write DMAONFETCH DMA transfer on instruction fetch 2 1 read-write DMAIV DMA Interrupt Vector Word 4 16 65535 DMA0CTL DMA Channel 0 Control 174 16 65535 DMAREQ Initiate DMA transfer with DMATSEL 0 1 read-write DMAABORT DMA transfer aborted by NMI 1 1 read-write DMAIE DMA interrupt enable 2 1 read-write DMAIFG DMA interrupt flag 3 1 read-write DMAEN DMA enable 4 1 read-write DMALEVEL DMA level sensitive trigger select 5 1 read-write DMASRCBYTE DMA source byte 6 1 read-write DMADSTBYTE DMA destination byte 7 1 read-write DMASRCINCR DMA source increment bit 0 8 2 read-write DMASRCINCR_0 DMA source increment 0: source address unchanged 0 DMASRCINCR_1 DMA source increment 1: source address unchanged 1 DMASRCINCR_2 DMA source increment 2: source address decremented 2 DMASRCINCR_3 DMA source increment 3: source address incremented 3 DMADSTINCR DMA destination increment bit 0 10 2 read-write DMADSTINCR_0 DMA destination increment 0: destination address unchanged 0 DMADSTINCR_1 DMA destination increment 1: destination address unchanged 1 DMADSTINCR_2 DMA destination increment 2: destination address decremented 2 DMADSTINCR_3 DMA destination increment 3: destination address incremented 3 DMADT DMA transfer mode bit 0 12 3 read-write DMADT_0 DMA transfer mode 0: single 0 DMADT_1 DMA transfer mode 1: block 1 DMADT_2 DMA transfer mode 2: interleaved 2 DMADT_3 DMA transfer mode 3: interleaved 3 DMADT_4 DMA transfer mode 4: single 4 DMADT_5 DMA transfer mode 5: block 5 DMADT_6 DMA transfer mode 6: interleaved 6 DMADT_7 DMA transfer mode 7: interleaved 7 DMA0SAL DMA Channel 0 Source Address 176 16 65535 DMA0DAL DMA Channel 0 Destination Address 180 16 65535 DMA0SZ DMA Channel 0 Transfer Size 184 16 65535 DMA1CTL DMA Channel 1 Control 186 16 65535 DMAREQ Initiate DMA transfer with DMATSEL 0 1 read-write DMAABORT DMA transfer aborted by NMI 1 1 read-write DMAIE DMA interrupt enable 2 1 read-write DMAIFG DMA interrupt flag 3 1 read-write DMAEN DMA enable 4 1 read-write DMALEVEL DMA level sensitive trigger select 5 1 read-write DMASRCBYTE DMA source byte 6 1 read-write DMADSTBYTE DMA destination byte 7 1 read-write DMASRCINCR DMA source increment bit 0 8 2 read-write DMASRCINCR_0 DMA source increment 0: source address unchanged 0 DMASRCINCR_1 DMA source increment 1: source address unchanged 1 DMASRCINCR_2 DMA source increment 2: source address decremented 2 DMASRCINCR_3 DMA source increment 3: source address incremented 3 DMADSTINCR DMA destination increment bit 0 10 2 read-write DMADSTINCR_0 DMA destination increment 0: destination address unchanged 0 DMADSTINCR_1 DMA destination increment 1: destination address unchanged 1 DMADSTINCR_2 DMA destination increment 2: destination address decremented 2 DMADSTINCR_3 DMA destination increment 3: destination address incremented 3 DMADT DMA transfer mode bit 0 12 3 read-write DMADT_0 DMA transfer mode 0: single 0 DMADT_1 DMA transfer mode 1: block 1 DMADT_2 DMA transfer mode 2: interleaved 2 DMADT_3 DMA transfer mode 3: interleaved 3 DMADT_4 DMA transfer mode 4: single 4 DMADT_5 DMA transfer mode 5: block 5 DMADT_6 DMA transfer mode 6: interleaved 6 DMADT_7 DMA transfer mode 7: interleaved 7 DMA1SAL DMA Channel 1 Source Address 188 16 65535 DMA1DAL DMA Channel 1 Destination Address 192 16 65535 DMA1SZ DMA Channel 1 Transfer Size 196 16 65535 DMA2CTL DMA Channel 2 Control 198 16 65535 DMAREQ Initiate DMA transfer with DMATSEL 0 1 read-write DMAABORT DMA transfer aborted by NMI 1 1 read-write DMAIE DMA interrupt enable 2 1 read-write DMAIFG DMA interrupt flag 3 1 read-write DMAEN DMA enable 4 1 read-write DMALEVEL DMA level sensitive trigger select 5 1 read-write DMASRCBYTE DMA source byte 6 1 read-write DMADSTBYTE DMA destination byte 7 1 read-write DMASRCINCR DMA source increment bit 0 8 2 read-write DMASRCINCR_0 DMA source increment 0: source address unchanged 0 DMASRCINCR_1 DMA source increment 1: source address unchanged 1 DMASRCINCR_2 DMA source increment 2: source address decremented 2 DMASRCINCR_3 DMA source increment 3: source address incremented 3 DMADSTINCR DMA destination increment bit 0 10 2 read-write DMADSTINCR_0 DMA destination increment 0: destination address unchanged 0 DMADSTINCR_1 DMA destination increment 1: destination address unchanged 1 DMADSTINCR_2 DMA destination increment 2: destination address decremented 2 DMADSTINCR_3 DMA destination increment 3: destination address incremented 3 DMADT DMA transfer mode bit 0 12 3 read-write DMADT_0 DMA transfer mode 0: single 0 DMADT_1 DMA transfer mode 1: block 1 DMADT_2 DMA transfer mode 2: interleaved 2 DMADT_3 DMA transfer mode 3: interleaved 3 DMADT_4 DMA transfer mode 4: single 4 DMADT_5 DMA transfer mode 5: block 5 DMADT_6 DMA transfer mode 6: interleaved 6 DMADT_7 DMA transfer mode 7: interleaved 7 DMA2SAL DMA Channel 2 Source Address 200 16 65535 DMA2DAL DMA Channel 2 Destination Address 204 16 65535 DMA2SZ DMA Channel 2 Transfer Size 208 16 65535 FLASH Flash 296 FCTL1 FLASH Control 1 0 16 65535 ERASE Enable bit for Flash segment erase 1 1 read-write MERAS Enable bit for Flash mass erase 2 1 read-write EEI Enable Erase Interrupts 3 1 read-write EEIEX Enable Emergency Interrupt Exit 4 1 read-write WRT Enable bit for Flash write 6 1 read-write BLKWRT Enable bit for Flash segment write 7 1 read-write FCTL2 FLASH Control 2 2 16 65535 FN0 Divide Flash clock by 1 to 64 using FN0 to FN5 according to: 0 1 read-write FN1 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 1 1 read-write FN2 FN2 2 1 read-write FN3 FN3 3 1 read-write FN4 FN4 4 1 read-write FN5 FN5 5 1 read-write FSSEL Flash clock select 0 */ /* to distinguish from USART SSELx 6 2 read-write FSSEL_0 Flash clock select: 0 - ACLK 0 FSSEL_1 Flash clock select: 1 - MCLK 1 FSSEL_2 Flash clock select: 2 - SMCLK 2 FSSEL_3 Flash clock select: 3 - SMCLK 3 FCTL3 FLASH Control 3 4 16 65535 BUSY Flash busy: 1 0 1 read-write KEYV Flash Key violation flag 1 1 read-write ACCVIFG Flash Access violation flag 2 1 read-write WAIT Wait flag for segment write 3 1 read-write LOCK Lock bit: 1 - Flash is locked (read only) 4 1 read-write EMEX Flash Emergency Exit 5 1 read-write LOCKA Segment A Lock bit: read = 1 - Segment is locked (read only) 6 1 read-write FAIL Last Program or Erase failed 7 1 read-write FCTL4 FLASH Control 4 150 16 65535 MGR0 Marginal read 0 mode. 4 1 read-write MGR1 Marginal read 1 mode. 5 1 read-write TIMER_A3 Timer A3 302 TAIV Timer A Interrupt Vector Word 0 16 65535 TACTL Timer A Control 50 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TACCTL0 Timer A Capture/Compare Control 0 52 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TACCTL1 Timer A Capture/Compare Control 1 54 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TACCTL2 Timer A Capture/Compare Control 2 56 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TAR Timer A Counter Register 66 16 65535 TACCR0 Timer A Capture/Compare 0 68 16 65535 TACCR1 Timer A Capture/Compare 1 70 16 65535 TACCR2 Timer A Capture/Compare 2 72 16 65535 MULTIPLIER Multiplier 304 MPY Multiply Unsigned/Operand 1 0 16 65535 MPYS Multiply Signed/Operand 1 2 16 65535 MAC Multiply Unsigned and Accumulate/Operand 1 4 16 65535 MACS Multiply Signed and Accumulate/Operand 1 6 16 65535 OP2 Operand 2 8 16 65535 RESLO Result Low Word 10 16 65535 RESHI Result High Word 12 16 65535 SUMEXT Sum Extend 14 16 65535 DAC12 DAC12 448 DAC12_0CTL DAC12_0 Control 0 16 65535 DAC12GRP DAC12 group 0 1 read-write DAC12ENC DAC12 enable conversion 1 1 read-write DAC12IFG DAC12 interrupt flag 2 1 read-write DAC12IE DAC12 interrupt enable 3 1 read-write DAC12DF DAC12 data format 4 1 read-write DAC12AMP DAC12 amplifier bit 0 5 3 read-write DAC12AMP_0 DAC12 amplifier 0: off 0 DAC12AMP_1 DAC12 amplifier 1: off 1 DAC12AMP_2 DAC12 amplifier 2: low 2 DAC12AMP_3 DAC12 amplifier 3: low 3 DAC12AMP_4 DAC12 amplifier 4: low 4 DAC12AMP_5 DAC12 amplifier 5: medium 5 DAC12AMP_6 DAC12 amplifier 6: medium 6 DAC12AMP_7 DAC12 amplifier 7: high 7 DAC12IR DAC12 input reference and output range 8 1 read-write DAC12CALON DAC12 calibration 9 1 read-write DAC12LSEL DAC12 load select bit 0 10 2 read-write DAC12LSEL_0 DAC12 load select 0: direct 0 DAC12LSEL_1 DAC12 load select 1: latched with DAT 1 DAC12LSEL_2 DAC12 load select 2: latched with pos. Timer_A3.OUT1 2 DAC12LSEL_3 DAC12 load select 3: latched with pos. Timer_B7.OUT1 3 DAC12RES DAC12 resolution 12 1 read-write DAC12SREF DAC12 reference bit 0 13 2 read-write DAC12SREF_0 DAC12 reference 0: Vref+ 0 DAC12SREF_1 DAC12 reference 1: Vref+ 1 DAC12SREF_2 DAC12 reference 2: Veref+ 2 DAC12SREF_3 DAC12 reference 3: Veref+ 3 DAC12OPS DAC12 Operation Amp. 15 1 read-write DAC12_1CTL DAC12_1 Control 2 16 65535 DAC12GRP DAC12 group 0 1 read-write DAC12ENC DAC12 enable conversion 1 1 read-write DAC12IFG DAC12 interrupt flag 2 1 read-write DAC12IE DAC12 interrupt enable 3 1 read-write DAC12DF DAC12 data format 4 1 read-write DAC12AMP DAC12 amplifier bit 0 5 3 read-write DAC12AMP_0 DAC12 amplifier 0: off 0 DAC12AMP_1 DAC12 amplifier 1: off 1 DAC12AMP_2 DAC12 amplifier 2: low 2 DAC12AMP_3 DAC12 amplifier 3: low 3 DAC12AMP_4 DAC12 amplifier 4: low 4 DAC12AMP_5 DAC12 amplifier 5: medium 5 DAC12AMP_6 DAC12 amplifier 6: medium 6 DAC12AMP_7 DAC12 amplifier 7: high 7 DAC12IR DAC12 input reference and output range 8 1 read-write DAC12CALON DAC12 calibration 9 1 read-write DAC12LSEL DAC12 load select bit 0 10 2 read-write DAC12LSEL_0 DAC12 load select 0: direct 0 DAC12LSEL_1 DAC12 load select 1: latched with DAT 1 DAC12LSEL_2 DAC12 load select 2: latched with pos. Timer_A3.OUT1 2 DAC12LSEL_3 DAC12 load select 3: latched with pos. Timer_B7.OUT1 3 DAC12RES DAC12 resolution 12 1 read-write DAC12SREF DAC12 reference bit 0 13 2 read-write DAC12SREF_0 DAC12 reference 0: Vref+ 0 DAC12SREF_1 DAC12 reference 1: Vref+ 1 DAC12SREF_2 DAC12 reference 2: Veref+ 2 DAC12SREF_3 DAC12 reference 3: Veref+ 3 DAC12OPS DAC12 Operation Amp. 15 1 read-write DAC12_0DAT DAC12_0 Data 8 16 65535 DAC12_1DAT DAC12_1 Data 10 16 65535 _INTERRUPTS 65472 RESERVED0 0xFFC0 Reserved Int. Vector 0 0 RESERVED1 0xFFC2 Reserved Int. Vector 1 1 RESERVED2 0xFFC4 Reserved Int. Vector 2 2 RESERVED3 0xFFC6 Reserved Int. Vector 3 3 RESERVED4 0xFFC8 Reserved Int. Vector 4 4 RESERVED5 0xFFCA Reserved Int. Vector 5 5 RESERVED6 0xFFCC Reserved Int. Vector 6 6 RESERVED7 0xFFCE Reserved Int. Vector 7 7 RESERVED8 0xFFD0 Reserved Int. Vector 8 8 RESERVED9 0xFFD2 Reserved Int. Vector 9 9 RESERVED10 0xFFD4 Reserved Int. Vector 10 10 RESERVED11 0xFFD6 Reserved Int. Vector 11 11 RESERVED12 0xFFD8 Reserved Int. Vector 12 12 RESERVED13 0xFFDA Reserved Int. Vector 13 13 DAC12 0xFFDC DAC12 14 DMA 0xFFDE DMA 15 USCIAB1TX 0xFFE0 USCI A1/B1 Transmit 16 USCIAB1RX 0xFFE2 USCI A1/B1 Receive 17 PORT1 0xFFE4 Port 1 18 PORT2 0xFFE6 Port 2 19 RESERVED20 0xFFE8 Reserved Int. Vector 20 20 ADC12 0xFFEA ADC 21 USCIAB0TX 0xFFEC USCI A0/B0 Transmit 22 USCIAB0RX 0xFFEE USCI A0/B0 Receive 23 TIMERA1 0xFFF0 Timer A CC1-2, TA 24 TIMERA0 0xFFF2 Timer A CC0 25 WDT 0xFFF4 Watchdog Timer 26 COMPARATORA 0xFFF6 Comparator A 27 TIMERB1 0xFFF8 Timer B CC1-6, TB 28 TIMERB0 0xFFFA Timer B CC0 29 NMI 0xFFFC Non-maskable 30