MSP430F5529 2 read-write 0 PORT_MAPPING_PORT_4 Port Mapping Port 4 480 P4MAP0 Port P4.0 mapping register 0 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP1 Port P4.1 mapping register 1 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP2 Port P4.2 mapping register 2 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP3 Port P4.3 mapping register 3 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP4 Port P4.4 mapping register 4 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP5 Port P4.5 mapping register 5 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP6 Port P4.6 mapping register 6 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write P4MAP7 Port P4.7 mapping register 7 8 255 0 255 PMAP0 PMAP0 0 1 read-write PMAP1 PMAP1 1 1 read-write PMAP2 PMAP2 2 1 read-write PMAP3 PMAP3 3 1 read-write PMAP4 PMAP4 4 1 read-write PMAP5 PMAP5 5 1 read-write PMAP6 PMAP6 6 1 read-write PMAP7 PMAP7 7 1 read-write PORT_1_2 Port 1/2 512 P1IN Port 1 Input 0 8 255 0 255 P1IN0 P1IN0 0 1 read-write P1IN1 P1IN1 1 1 read-write P1IN2 P1IN2 2 1 read-write P1IN3 P1IN3 3 1 read-write P1IN4 P1IN4 4 1 read-write P1IN5 P1IN5 5 1 read-write P1IN6 P1IN6 6 1 read-write P1IN7 P1IN7 7 1 read-write P2IN Port 2 Input 1 8 255 0 255 P2IN0 P2IN0 0 1 read-write P2IN1 P2IN1 1 1 read-write P2IN2 P2IN2 2 1 read-write P2IN3 P2IN3 3 1 read-write P2IN4 P2IN4 4 1 read-write P2IN5 P2IN5 5 1 read-write P2IN6 P2IN6 6 1 read-write P2IN7 P2IN7 7 1 read-write P1OUT Port 1 Output 2 8 255 0 255 P1OUT0 P1OUT0 0 1 read-write P1OUT1 P1OUT1 1 1 read-write P1OUT2 P1OUT2 2 1 read-write P1OUT3 P1OUT3 3 1 read-write P1OUT4 P1OUT4 4 1 read-write P1OUT5 P1OUT5 5 1 read-write P1OUT6 P1OUT6 6 1 read-write P1OUT7 P1OUT7 7 1 read-write P2OUT Port 2 Output 3 8 255 0 255 P2OUT0 P2OUT0 0 1 read-write P2OUT1 P2OUT1 1 1 read-write P2OUT2 P2OUT2 2 1 read-write P2OUT3 P2OUT3 3 1 read-write P2OUT4 P2OUT4 4 1 read-write P2OUT5 P2OUT5 5 1 read-write P2OUT6 P2OUT6 6 1 read-write P2OUT7 P2OUT7 7 1 read-write P1DIR Port 1 Direction 4 8 255 0 255 P1DIR0 P1DIR0 0 1 read-write P1DIR1 P1DIR1 1 1 read-write P1DIR2 P1DIR2 2 1 read-write P1DIR3 P1DIR3 3 1 read-write P1DIR4 P1DIR4 4 1 read-write P1DIR5 P1DIR5 5 1 read-write P1DIR6 P1DIR6 6 1 read-write P1DIR7 P1DIR7 7 1 read-write P2DIR Port 2 Direction 5 8 255 0 255 P2DIR0 P2DIR0 0 1 read-write P2DIR1 P2DIR1 1 1 read-write P2DIR2 P2DIR2 2 1 read-write P2DIR3 P2DIR3 3 1 read-write P2DIR4 P2DIR4 4 1 read-write P2DIR5 P2DIR5 5 1 read-write P2DIR6 P2DIR6 6 1 read-write P2DIR7 P2DIR7 7 1 read-write P1REN Port 1 Resistor Enable 6 8 255 0 255 P1REN0 P1REN0 0 1 read-write P1REN1 P1REN1 1 1 read-write P1REN2 P1REN2 2 1 read-write P1REN3 P1REN3 3 1 read-write P1REN4 P1REN4 4 1 read-write P1REN5 P1REN5 5 1 read-write P1REN6 P1REN6 6 1 read-write P1REN7 P1REN7 7 1 read-write P2REN Port 2 Resistor Enable 7 8 255 0 255 P2REN0 P2REN0 0 1 read-write P2REN1 P2REN1 1 1 read-write P2REN2 P2REN2 2 1 read-write P2REN3 P2REN3 3 1 read-write P2REN4 P2REN4 4 1 read-write P2REN5 P2REN5 5 1 read-write P2REN6 P2REN6 6 1 read-write P2REN7 P2REN7 7 1 read-write P1DS Port 1 Drive Strenght 8 8 255 0 255 P1DS0 P1DS0 0 1 read-write P1DS1 P1DS1 1 1 read-write P1DS2 P1DS2 2 1 read-write P1DS3 P1DS3 3 1 read-write P1DS4 P1DS4 4 1 read-write P1DS5 P1DS5 5 1 read-write P1DS6 P1DS6 6 1 read-write P1DS7 P1DS7 7 1 read-write P2DS Port 2 Drive Strenght 9 8 255 0 255 P2DS0 P2DS0 0 1 read-write P2DS1 P2DS1 1 1 read-write P2DS2 P2DS2 2 1 read-write P2DS3 P2DS3 3 1 read-write P2DS4 P2DS4 4 1 read-write P2DS5 P2DS5 5 1 read-write P2DS6 P2DS6 6 1 read-write P2DS7 P2DS7 7 1 read-write P1SEL Port 1 Selection 10 8 255 0 255 P1SEL0 P1SEL0 0 1 read-write P1SEL1 P1SEL1 1 1 read-write P1SEL2 P1SEL2 2 1 read-write P1SEL3 P1SEL3 3 1 read-write P1SEL4 P1SEL4 4 1 read-write P1SEL5 P1SEL5 5 1 read-write P1SEL6 P1SEL6 6 1 read-write P1SEL7 P1SEL7 7 1 read-write P2SEL Port 2 Selection 11 8 255 0 255 P2SEL0 P2SEL0 0 1 read-write P2SEL1 P2SEL1 1 1 read-write P2SEL2 P2SEL2 2 1 read-write P2SEL3 P2SEL3 3 1 read-write P2SEL4 P2SEL4 4 1 read-write P2SEL5 P2SEL5 5 1 read-write P2SEL6 P2SEL6 6 1 read-write P2SEL7 P2SEL7 7 1 read-write P1IES Port 1 Interrupt Edge Select 24 8 255 0 255 P1IES0 P1IES0 0 1 read-write P1IES1 P1IES1 1 1 read-write P1IES2 P1IES2 2 1 read-write P1IES3 P1IES3 3 1 read-write P1IES4 P1IES4 4 1 read-write P1IES5 P1IES5 5 1 read-write P1IES6 P1IES6 6 1 read-write P1IES7 P1IES7 7 1 read-write P2IES Port 2 Interrupt Edge Select 25 8 255 0 255 P2IES0 P2IES0 0 1 read-write P2IES1 P2IES1 1 1 read-write P2IES2 P2IES2 2 1 read-write P2IES3 P2IES3 3 1 read-write P2IES4 P2IES4 4 1 read-write P2IES5 P2IES5 5 1 read-write P2IES6 P2IES6 6 1 read-write P2IES7 P2IES7 7 1 read-write P1IE Port 1 Interrupt Enable 26 8 255 0 255 P1IE0 P1IE0 0 1 read-write P1IE1 P1IE1 1 1 read-write P1IE2 P1IE2 2 1 read-write P1IE3 P1IE3 3 1 read-write P1IE4 P1IE4 4 1 read-write P1IE5 P1IE5 5 1 read-write P1IE6 P1IE6 6 1 read-write P1IE7 P1IE7 7 1 read-write P2IE Port 2 Interrupt Enable 27 8 255 0 255 P2IE0 P2IE0 0 1 read-write P2IE1 P2IE1 1 1 read-write P2IE2 P2IE2 2 1 read-write P2IE3 P2IE3 3 1 read-write P2IE4 P2IE4 4 1 read-write P2IE5 P2IE5 5 1 read-write P2IE6 P2IE6 6 1 read-write P2IE7 P2IE7 7 1 read-write P1IFG Port 1 Interrupt Flag 28 8 255 0 255 P1IFG0 P1IFG0 0 1 read-write P1IFG1 P1IFG1 1 1 read-write P1IFG2 P1IFG2 2 1 read-write P1IFG3 P1IFG3 3 1 read-write P1IFG4 P1IFG4 4 1 read-write P1IFG5 P1IFG5 5 1 read-write P1IFG6 P1IFG6 6 1 read-write P1IFG7 P1IFG7 7 1 read-write P2IFG Port 2 Interrupt Flag 29 8 255 0 255 P2IFG0 P2IFG0 0 1 read-write P2IFG1 P2IFG1 1 1 read-write P2IFG2 P2IFG2 2 1 read-write P2IFG3 P2IFG3 3 1 read-write P2IFG4 P2IFG4 4 1 read-write P2IFG5 P2IFG5 5 1 read-write P2IFG6 P2IFG6 6 1 read-write P2IFG7 P2IFG7 7 1 read-write P1IV Port 1 Interrupt Vector Word 14 16 65535 P2IV Port 2 Interrupt Vector Word 30 16 65535 PORT_3_4 Port 3/4 544 P3IN Port 3 Input 0 8 255 0 255 P3IN0 P3IN0 0 1 read-write P3IN1 P3IN1 1 1 read-write P3IN2 P3IN2 2 1 read-write P3IN3 P3IN3 3 1 read-write P3IN4 P3IN4 4 1 read-write P3IN5 P3IN5 5 1 read-write P3IN6 P3IN6 6 1 read-write P3IN7 P3IN7 7 1 read-write P4IN Port 4 Input 1 8 255 0 255 P4IN0 P4IN0 0 1 read-write P4IN1 P4IN1 1 1 read-write P4IN2 P4IN2 2 1 read-write P4IN3 P4IN3 3 1 read-write P4IN4 P4IN4 4 1 read-write P4IN5 P4IN5 5 1 read-write P4IN6 P4IN6 6 1 read-write P4IN7 P4IN7 7 1 read-write P3OUT Port 3 Output 2 8 255 0 255 P3OUT0 P3OUT0 0 1 read-write P3OUT1 P3OUT1 1 1 read-write P3OUT2 P3OUT2 2 1 read-write P3OUT3 P3OUT3 3 1 read-write P3OUT4 P3OUT4 4 1 read-write P3OUT5 P3OUT5 5 1 read-write P3OUT6 P3OUT6 6 1 read-write P3OUT7 P3OUT7 7 1 read-write P4OUT Port 4 Output 3 8 255 0 255 P4OUT0 P4OUT0 0 1 read-write P4OUT1 P4OUT1 1 1 read-write P4OUT2 P4OUT2 2 1 read-write P4OUT3 P4OUT3 3 1 read-write P4OUT4 P4OUT4 4 1 read-write P4OUT5 P4OUT5 5 1 read-write P4OUT6 P4OUT6 6 1 read-write P4OUT7 P4OUT7 7 1 read-write P3DIR Port 3 Direction 4 8 255 0 255 P3DIR0 P3DIR0 0 1 read-write P3DIR1 P3DIR1 1 1 read-write P3DIR2 P3DIR2 2 1 read-write P3DIR3 P3DIR3 3 1 read-write P3DIR4 P3DIR4 4 1 read-write P3DIR5 P3DIR5 5 1 read-write P3DIR6 P3DIR6 6 1 read-write P3DIR7 P3DIR7 7 1 read-write P4DIR Port 4 Direction 5 8 255 0 255 P4DIR0 P4DIR0 0 1 read-write P4DIR1 P4DIR1 1 1 read-write P4DIR2 P4DIR2 2 1 read-write P4DIR3 P4DIR3 3 1 read-write P4DIR4 P4DIR4 4 1 read-write P4DIR5 P4DIR5 5 1 read-write P4DIR6 P4DIR6 6 1 read-write P4DIR7 P4DIR7 7 1 read-write P3REN Port 3 Resistor Enable 6 8 255 0 255 P3REN0 P3REN0 0 1 read-write P3REN1 P3REN1 1 1 read-write P3REN2 P3REN2 2 1 read-write P3REN3 P3REN3 3 1 read-write P3REN4 P3REN4 4 1 read-write P3REN5 P3REN5 5 1 read-write P3REN6 P3REN6 6 1 read-write P3REN7 P3REN7 7 1 read-write P4REN Port 4 Resistor Enable 7 8 255 0 255 P4REN0 P4REN0 0 1 read-write P4REN1 P4REN1 1 1 read-write P4REN2 P4REN2 2 1 read-write P4REN3 P4REN3 3 1 read-write P4REN4 P4REN4 4 1 read-write P4REN5 P4REN5 5 1 read-write P4REN6 P4REN6 6 1 read-write P4REN7 P4REN7 7 1 read-write P3DS Port 3 Drive Strenght 8 8 255 0 255 P3DS0 P3DS0 0 1 read-write P3DS1 P3DS1 1 1 read-write P3DS2 P3DS2 2 1 read-write P3DS3 P3DS3 3 1 read-write P3DS4 P3DS4 4 1 read-write P3DS5 P3DS5 5 1 read-write P3DS6 P3DS6 6 1 read-write P3DS7 P3DS7 7 1 read-write P4DS Port 4 Drive Strenght 9 8 255 0 255 P4DS0 P4DS0 0 1 read-write P4DS1 P4DS1 1 1 read-write P4DS2 P4DS2 2 1 read-write P4DS3 P4DS3 3 1 read-write P4DS4 P4DS4 4 1 read-write P4DS5 P4DS5 5 1 read-write P4DS6 P4DS6 6 1 read-write P4DS7 P4DS7 7 1 read-write P3SEL Port 3 Selection 10 8 255 0 255 P3SEL0 P3SEL0 0 1 read-write P3SEL1 P3SEL1 1 1 read-write P3SEL2 P3SEL2 2 1 read-write P3SEL3 P3SEL3 3 1 read-write P3SEL4 P3SEL4 4 1 read-write P3SEL5 P3SEL5 5 1 read-write P3SEL6 P3SEL6 6 1 read-write P3SEL7 P3SEL7 7 1 read-write P4SEL Port 4 Selection 11 8 255 0 255 P4SEL0 P4SEL0 0 1 read-write P4SEL1 P4SEL1 1 1 read-write P4SEL2 P4SEL2 2 1 read-write P4SEL3 P4SEL3 3 1 read-write P4SEL4 P4SEL4 4 1 read-write P4SEL5 P4SEL5 5 1 read-write P4SEL6 P4SEL6 6 1 read-write P4SEL7 P4SEL7 7 1 read-write PORT_5_6 Port 5/6 576 P5IN Port 5 Input 0 8 255 0 255 P5IN0 P5IN0 0 1 read-write P5IN1 P5IN1 1 1 read-write P5IN2 P5IN2 2 1 read-write P5IN3 P5IN3 3 1 read-write P5IN4 P5IN4 4 1 read-write P5IN5 P5IN5 5 1 read-write P5IN6 P5IN6 6 1 read-write P5IN7 P5IN7 7 1 read-write P6IN Port 6 Input 1 8 255 0 255 P6IN0 P6IN0 0 1 read-write P6IN1 P6IN1 1 1 read-write P6IN2 P6IN2 2 1 read-write P6IN3 P6IN3 3 1 read-write P6IN4 P6IN4 4 1 read-write P6IN5 P6IN5 5 1 read-write P6IN6 P6IN6 6 1 read-write P6IN7 P6IN7 7 1 read-write P5OUT Port 5 Output 2 8 255 0 255 P5OUT0 P5OUT0 0 1 read-write P5OUT1 P5OUT1 1 1 read-write P5OUT2 P5OUT2 2 1 read-write P5OUT3 P5OUT3 3 1 read-write P5OUT4 P5OUT4 4 1 read-write P5OUT5 P5OUT5 5 1 read-write P5OUT6 P5OUT6 6 1 read-write P5OUT7 P5OUT7 7 1 read-write P6OUT Port 6 Output 3 8 255 0 255 P6OUT0 P6OUT0 0 1 read-write P6OUT1 P6OUT1 1 1 read-write P6OUT2 P6OUT2 2 1 read-write P6OUT3 P6OUT3 3 1 read-write P6OUT4 P6OUT4 4 1 read-write P6OUT5 P6OUT5 5 1 read-write P6OUT6 P6OUT6 6 1 read-write P6OUT7 P6OUT7 7 1 read-write P5DIR Port 5 Direction 4 8 255 0 255 P5DIR0 P5DIR0 0 1 read-write P5DIR1 P5DIR1 1 1 read-write P5DIR2 P5DIR2 2 1 read-write P5DIR3 P5DIR3 3 1 read-write P5DIR4 P5DIR4 4 1 read-write P5DIR5 P5DIR5 5 1 read-write P5DIR6 P5DIR6 6 1 read-write P5DIR7 P5DIR7 7 1 read-write P6DIR Port 6 Direction 5 8 255 0 255 P6DIR0 P6DIR0 0 1 read-write P6DIR1 P6DIR1 1 1 read-write P6DIR2 P6DIR2 2 1 read-write P6DIR3 P6DIR3 3 1 read-write P6DIR4 P6DIR4 4 1 read-write P6DIR5 P6DIR5 5 1 read-write P6DIR6 P6DIR6 6 1 read-write P6DIR7 P6DIR7 7 1 read-write P5REN Port 5 Resistor Enable 6 8 255 0 255 P5REN0 P5REN0 0 1 read-write P5REN1 P5REN1 1 1 read-write P5REN2 P5REN2 2 1 read-write P5REN3 P5REN3 3 1 read-write P5REN4 P5REN4 4 1 read-write P5REN5 P5REN5 5 1 read-write P5REN6 P5REN6 6 1 read-write P5REN7 P5REN7 7 1 read-write P6REN Port 6 Resistor Enable 7 8 255 0 255 P6REN0 P6REN0 0 1 read-write P6REN1 P6REN1 1 1 read-write P6REN2 P6REN2 2 1 read-write P6REN3 P6REN3 3 1 read-write P6REN4 P6REN4 4 1 read-write P6REN5 P6REN5 5 1 read-write P6REN6 P6REN6 6 1 read-write P6REN7 P6REN7 7 1 read-write P5DS Port 5 Drive Strenght 8 8 255 0 255 P5DS0 P5DS0 0 1 read-write P5DS1 P5DS1 1 1 read-write P5DS2 P5DS2 2 1 read-write P5DS3 P5DS3 3 1 read-write P5DS4 P5DS4 4 1 read-write P5DS5 P5DS5 5 1 read-write P5DS6 P5DS6 6 1 read-write P5DS7 P5DS7 7 1 read-write P6DS Port 6 Drive Strenght 9 8 255 0 255 P6DS0 P6DS0 0 1 read-write P6DS1 P6DS1 1 1 read-write P6DS2 P6DS2 2 1 read-write P6DS3 P6DS3 3 1 read-write P6DS4 P6DS4 4 1 read-write P6DS5 P6DS5 5 1 read-write P6DS6 P6DS6 6 1 read-write P6DS7 P6DS7 7 1 read-write P5SEL Port 5 Selection 10 8 255 0 255 P5SEL0 P5SEL0 0 1 read-write P5SEL1 P5SEL1 1 1 read-write P5SEL2 P5SEL2 2 1 read-write P5SEL3 P5SEL3 3 1 read-write P5SEL4 P5SEL4 4 1 read-write P5SEL5 P5SEL5 5 1 read-write P5SEL6 P5SEL6 6 1 read-write P5SEL7 P5SEL7 7 1 read-write P6SEL Port 6 Selection 11 8 255 0 255 P6SEL0 P6SEL0 0 1 read-write P6SEL1 P6SEL1 1 1 read-write P6SEL2 P6SEL2 2 1 read-write P6SEL3 P6SEL3 3 1 read-write P6SEL4 P6SEL4 4 1 read-write P6SEL5 P6SEL5 5 1 read-write P6SEL6 P6SEL6 6 1 read-write P6SEL7 P6SEL7 7 1 read-write PORT_7_8 Port 7/8 608 P7IN Port 7 Input 0 8 255 0 255 P7IN0 P7IN0 0 1 read-write P7IN1 P7IN1 1 1 read-write P7IN2 P7IN2 2 1 read-write P7IN3 P7IN3 3 1 read-write P7IN4 P7IN4 4 1 read-write P7IN5 P7IN5 5 1 read-write P7IN6 P7IN6 6 1 read-write P7IN7 P7IN7 7 1 read-write P8IN Port 8 Input 1 8 255 0 255 P8IN0 P8IN0 0 1 read-write P8IN1 P8IN1 1 1 read-write P8IN2 P8IN2 2 1 read-write P8IN3 P8IN3 3 1 read-write P8IN4 P8IN4 4 1 read-write P8IN5 P8IN5 5 1 read-write P8IN6 P8IN6 6 1 read-write P8IN7 P8IN7 7 1 read-write P7OUT Port 7 Output 2 8 255 0 255 P7OUT0 P7OUT0 0 1 read-write P7OUT1 P7OUT1 1 1 read-write P7OUT2 P7OUT2 2 1 read-write P7OUT3 P7OUT3 3 1 read-write P7OUT4 P7OUT4 4 1 read-write P7OUT5 P7OUT5 5 1 read-write P7OUT6 P7OUT6 6 1 read-write P7OUT7 P7OUT7 7 1 read-write P8OUT Port 8 Output 3 8 255 0 255 P8OUT0 P8OUT0 0 1 read-write P8OUT1 P8OUT1 1 1 read-write P8OUT2 P8OUT2 2 1 read-write P8OUT3 P8OUT3 3 1 read-write P8OUT4 P8OUT4 4 1 read-write P8OUT5 P8OUT5 5 1 read-write P8OUT6 P8OUT6 6 1 read-write P8OUT7 P8OUT7 7 1 read-write P7DIR Port 7 Direction 4 8 255 0 255 P7DIR0 P7DIR0 0 1 read-write P7DIR1 P7DIR1 1 1 read-write P7DIR2 P7DIR2 2 1 read-write P7DIR3 P7DIR3 3 1 read-write P7DIR4 P7DIR4 4 1 read-write P7DIR5 P7DIR5 5 1 read-write P7DIR6 P7DIR6 6 1 read-write P7DIR7 P7DIR7 7 1 read-write P8DIR Port 8 Direction 5 8 255 0 255 P8DIR0 P8DIR0 0 1 read-write P8DIR1 P8DIR1 1 1 read-write P8DIR2 P8DIR2 2 1 read-write P8DIR3 P8DIR3 3 1 read-write P8DIR4 P8DIR4 4 1 read-write P8DIR5 P8DIR5 5 1 read-write P8DIR6 P8DIR6 6 1 read-write P8DIR7 P8DIR7 7 1 read-write P7REN Port 7 Resistor Enable 6 8 255 0 255 P7REN0 P7REN0 0 1 read-write P7REN1 P7REN1 1 1 read-write P7REN2 P7REN2 2 1 read-write P7REN3 P7REN3 3 1 read-write P7REN4 P7REN4 4 1 read-write P7REN5 P7REN5 5 1 read-write P7REN6 P7REN6 6 1 read-write P7REN7 P7REN7 7 1 read-write P8REN Port 8 Resistor Enable 7 8 255 0 255 P8REN0 P8REN0 0 1 read-write P8REN1 P8REN1 1 1 read-write P8REN2 P8REN2 2 1 read-write P8REN3 P8REN3 3 1 read-write P8REN4 P8REN4 4 1 read-write P8REN5 P8REN5 5 1 read-write P8REN6 P8REN6 6 1 read-write P8REN7 P8REN7 7 1 read-write P7DS Port 7 Drive Strenght 8 8 255 0 255 P7DS0 P7DS0 0 1 read-write P7DS1 P7DS1 1 1 read-write P7DS2 P7DS2 2 1 read-write P7DS3 P7DS3 3 1 read-write P7DS4 P7DS4 4 1 read-write P7DS5 P7DS5 5 1 read-write P7DS6 P7DS6 6 1 read-write P7DS7 P7DS7 7 1 read-write P8DS Port 8 Drive Strenght 9 8 255 0 255 P8DS0 P8DS0 0 1 read-write P8DS1 P8DS1 1 1 read-write P8DS2 P8DS2 2 1 read-write P8DS3 P8DS3 3 1 read-write P8DS4 P8DS4 4 1 read-write P8DS5 P8DS5 5 1 read-write P8DS6 P8DS6 6 1 read-write P8DS7 P8DS7 7 1 read-write P7SEL Port 7 Selection 10 8 255 0 255 P7SEL0 P7SEL0 0 1 read-write P7SEL1 P7SEL1 1 1 read-write P7SEL2 P7SEL2 2 1 read-write P7SEL3 P7SEL3 3 1 read-write P7SEL4 P7SEL4 4 1 read-write P7SEL5 P7SEL5 5 1 read-write P7SEL6 P7SEL6 6 1 read-write P7SEL7 P7SEL7 7 1 read-write P8SEL Port 8 Selection 11 8 255 0 255 P8SEL0 P8SEL0 0 1 read-write P8SEL1 P8SEL1 1 1 read-write P8SEL2 P8SEL2 2 1 read-write P8SEL3 P8SEL3 3 1 read-write P8SEL4 P8SEL4 4 1 read-write P8SEL5 P8SEL5 5 1 read-write P8SEL6 P8SEL6 6 1 read-write P8SEL7 P8SEL7 7 1 read-write RTC RTC Real Time Clock 1184 RTCSEC Real Time Clock Seconds 16 8 255 SECONDS0 Real Time Clock Seconds Bit: 0 0 1 read-write SECONDS1 Real Time Clock Seconds Bit: 1 1 1 read-write SECONDS2 Real Time Clock Seconds Bit: 2 2 1 read-write SECONDS3 Real Time Clock Seconds Bit: 3 3 1 read-write SECONDS4 Real Time Clock Seconds Bit: 4 4 1 read-write SECONDS5 Real Time Clock Seconds Bit: 5 5 1 read-write SECONDS6 Real Time Clock Seconds Bit: 6 6 1 read-write RTCMIN Real Time Clock Minutes 17 8 255 MINUTES0 Real Time Clock Minutes Bit: 0 0 1 read-write MINUTES1 Real Time Clock Minutes Bit: 1 1 1 read-write MINUTES2 Real Time Clock Minutes Bit: 2 2 1 read-write MINUTES3 Real Time Clock Minutes Bit: 3 3 1 read-write MINUTES4 Real Time Clock Minutes Bit: 4 4 1 read-write MINUTES5 Real Time Clock Minutes Bit: 5 5 1 read-write MINUTES6 Real Time Clock Minutes Bit: 6 6 1 read-write RTCHOUR Real Time Clock Hour 18 8 255 HOUR0 Real Time Clock Hour Bit: 0 0 1 read-write HOUR1 Real Time Clock Hour Bit: 1 1 1 read-write HOUR2 Real Time Clock Hour Bit: 2 2 1 read-write HOUR3 Real Time Clock Hour Bit: 3 3 1 read-write HOUR4 Real Time Clock Hour Bit: 4 4 1 read-write HOUR5 Real Time Clock Hour Bit: 5 5 1 read-write HOUR6 Real Time Clock Hour Bit: 6 6 1 read-write RTCDOW Real Time Clock Day of week 19 8 255 DOW0 Real Time Clock DOW Bit: 0 0 1 read-write DOW1 Real Time Clock DOW Bit: 1 1 1 read-write DOW2 Real Time Clock DOW Bit: 2 2 1 read-write DOW3 Real Time Clock DOW Bit: 3 3 1 read-write DOW4 Real Time Clock DOW Bit: 4 4 1 read-write DOW5 Real Time Clock DOW Bit: 5 5 1 read-write DOW6 Real Time Clock DOW Bit: 6 6 1 read-write RTCDAY Real Time Clock Day 20 8 255 DAY0 Real Time Clock Day Bit: 0 0 1 read-write DAY1 Real Time Clock Day Bit: 1 1 1 read-write DAY2 Real Time Clock Day Bit: 2 2 1 read-write DAY3 Real Time Clock Day Bit: 3 3 1 read-write DAY4 Real Time Clock Day Bit: 4 4 1 read-write DAY5 Real Time Clock Day Bit: 5 5 1 read-write DAY6 Real Time Clock Day Bit: 6 6 1 read-write RTCMON Real Time Clock Month 21 8 255 MONTH0 Real Time Clock Month Bit: 0 0 1 read-write MONTH1 Real Time Clock Month Bit: 1 1 1 read-write MONTH2 Real Time Clock Month Bit: 2 2 1 read-write MONTH3 Real Time Clock Month Bit: 3 3 1 read-write MONTH4 Real Time Clock Month Bit: 4 4 1 read-write MONTH5 Real Time Clock Month Bit: 5 5 1 read-write MONTH6 Real Time Clock Month Bit: 6 6 1 read-write RTCAMIN Real Time Clock Alarm Min 24 8 255 0 255 MINUTES0 Real Time Clock Minutes Bit: 0 0 1 read-write MINUTES1 Real Time Clock Minutes Bit: 1 1 1 read-write MINUTES2 Real Time Clock Minutes Bit: 2 2 1 read-write MINUTES3 Real Time Clock Minutes Bit: 3 3 1 read-write MINUTES4 Real Time Clock Minutes Bit: 4 4 1 read-write MINUTES5 Real Time Clock Minutes Bit: 5 5 1 read-write MINUTES6 Real Time Clock Minutes Bit: 6 6 1 read-write RTCAE Real Time Clock Alarm enable 7 1 read-write RTCAHOUR Real Time Clock Alarm Hour 25 8 255 0 255 HOUR0 Real Time Clock Hour Bit: 0 0 1 read-write HOUR1 Real Time Clock Hour Bit: 1 1 1 read-write HOUR2 Real Time Clock Hour Bit: 2 2 1 read-write HOUR3 Real Time Clock Hour Bit: 3 3 1 read-write HOUR4 Real Time Clock Hour Bit: 4 4 1 read-write HOUR5 Real Time Clock Hour Bit: 5 5 1 read-write HOUR6 Real Time Clock Hour Bit: 6 6 1 read-write RTCAE Real Time Clock Alarm enable 7 1 read-write RTCADOW Real Time Clock Alarm Day of week 26 8 255 0 255 DOW0 Real Time Clock DOW Bit: 0 0 1 read-write DOW1 Real Time Clock DOW Bit: 1 1 1 read-write DOW2 Real Time Clock DOW Bit: 2 2 1 read-write DOW3 Real Time Clock DOW Bit: 3 3 1 read-write DOW4 Real Time Clock DOW Bit: 4 4 1 read-write DOW5 Real Time Clock DOW Bit: 5 5 1 read-write DOW6 Real Time Clock DOW Bit: 6 6 1 read-write RTCAE Real Time Clock Alarm enable 7 1 read-write RTCADAY Real Time Clock Alarm Day 27 8 255 0 255 DAY0 Real Time Clock Day Bit: 0 0 1 read-write DAY1 Real Time Clock Day Bit: 1 1 1 read-write DAY2 Real Time Clock Day Bit: 2 2 1 read-write DAY3 Real Time Clock Day Bit: 3 3 1 read-write DAY4 Real Time Clock Day Bit: 4 4 1 read-write DAY5 Real Time Clock Day Bit: 5 5 1 read-write DAY6 Real Time Clock Day Bit: 6 6 1 read-write RTCAE Real Time Clock Alarm enable 7 1 read-write RTCCTL01 Real Timer Control 0/1 0 16 65535 RTCRDYIFG RTC Ready Interrupt Flag 0 1 read-write RTCAIFG RTC Alarm Interrupt Flag 1 1 read-write RTCTEVIFG RTC Time Event Interrupt Flag 2 1 read-write RTCRDYIE RTC Ready Interrupt Enable Flag 4 1 read-write RTCAIE RTC Alarm Interrupt Enable Flag 5 1 read-write RTCTEVIE RTC Time Event Interrupt Enable Flag 6 1 read-write RTCTEV RTC Time Event 1 8 2 read-write RTCTEV_0 RTC Time Event: 0 (Min. changed) 0 RTCTEV_1 RTC Time Event: 1 (Hour changed) 1 RTCTEV_2 RTC Time Event: 2 (12:00 changed) 2 RTCTEV_3 RTC Time Event: 3 (00:00 changed) 3 RTCSSEL RTC Source Select 1 10 2 read-write RTCSSEL_0 RTC Source Select ACLK 0 RTCSSEL_1 RTC Source Select SMCLK 1 RTCSSEL_2 RTC Source Select RT1PS 2 RTCSSEL_3 RTC Source Select RT1PS 3 RTCRDY RTC Ready 12 1 read-write RTCMODE RTC Mode 0:Counter / 1: Calendar 13 1 read-write RTCHOLD RTC Hold 14 1 read-write RTCBCD RTC BCD 0:Binary / 1:BCD 15 1 read-write RTCCTL23 Real Timer Control 2/3 2 16 65535 RTCCAL0 RTC Calibration Bit 0 0 1 read-write RTCCAL1 RTC Calibration Bit 1 1 1 read-write RTCCAL2 RTC Calibration Bit 2 2 1 read-write RTCCAL3 RTC Calibration Bit 3 3 1 read-write RTCCAL4 RTC Calibration Bit 4 4 1 read-write RTCCAL5 RTC Calibration Bit 5 5 1 read-write RTCCALS RTC Calibration Sign 7 1 read-write RTCCALF RTC Calibration Frequency Bit 1 8 2 read-write RTCCALF_0 RTC Calibration Frequency: No Output 0 RTCCALF_1 RTC Calibration Frequency: 512 Hz 1 RTCCALF_2 RTC Calibration Frequency: 256 Hz 2 RTCCALF_3 RTC Calibration Frequency: 1 Hz 3 RTCPS0CTL Real Timer Prescale Timer 0 Control 8 16 65535 RT0PSIFG RTC Prescale Timer 0 Interrupt Flag 0 1 read-write RT0PSIE RTC Prescale Timer 0 Interrupt Enable Flag 1 1 read-write RT0IP RTC Prescale Timer 0 Interrupt Interval Bit: 2 2 3 read-write RT0IP_0 RTC Prescale Timer 0 Interrupt Interval /2 0 RT0IP_1 RTC Prescale Timer 0 Interrupt Interval /4 1 RT0IP_2 RTC Prescale Timer 0 Interrupt Interval /8 2 RT0IP_3 RTC Prescale Timer 0 Interrupt Interval /16 3 RT0IP_4 RTC Prescale Timer 0 Interrupt Interval /32 4 RT0IP_5 RTC Prescale Timer 0 Interrupt Interval /64 5 RT0IP_6 RTC Prescale Timer 0 Interrupt Interval /128 6 RT0IP_7 RTC Prescale Timer 0 Interrupt Interval /256 7 RT0PSHOLD RTC Prescale Timer 0 Hold 8 1 read-write RT0PSDIV RTC Prescale Timer 0 Clock Divide Bit: 2 11 3 read-write RT0PSDIV_0 RTC Prescale Timer 0 Clock Divide /2 0 RT0PSDIV_1 RTC Prescale Timer 0 Clock Divide /4 1 RT0PSDIV_2 RTC Prescale Timer 0 Clock Divide /8 2 RT0PSDIV_3 RTC Prescale Timer 0 Clock Divide /16 3 RT0PSDIV_4 RTC Prescale Timer 0 Clock Divide /32 4 RT0PSDIV_5 RTC Prescale Timer 0 Clock Divide /64 5 RT0PSDIV_6 RTC Prescale Timer 0 Clock Divide /128 6 RT0PSDIV_7 RTC Prescale Timer 0 Clock Divide /256 7 RT0SSEL RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK 14 1 read-write RTCPS1CTL Real Timer Prescale Timer 1 Control 10 16 65535 RT1PSIFG RTC Prescale Timer 1 Interrupt Flag 0 1 read-write RT1PSIE RTC Prescale Timer 1 Interrupt Enable Flag 1 1 read-write RT1IP RTC Prescale Timer 1 Interrupt Interval Bit: 2 2 3 read-write RT1IP_0 RTC Prescale Timer 1 Interrupt Interval /2 0 RT1IP_1 RTC Prescale Timer 1 Interrupt Interval /4 1 RT1IP_2 RTC Prescale Timer 1 Interrupt Interval /8 2 RT1IP_3 RTC Prescale Timer 1 Interrupt Interval /16 3 RT1IP_4 RTC Prescale Timer 1 Interrupt Interval /32 4 RT1IP_5 RTC Prescale Timer 1 Interrupt Interval /64 5 RT1IP_6 RTC Prescale Timer 1 Interrupt Interval /128 6 RT1IP_7 RTC Prescale Timer 1 Interrupt Interval /256 7 RT1PSHOLD RTC Prescale Timer 1 Hold 8 1 read-write RT1PSDIV RTC Prescale Timer 1 Clock Divide Bit: 2 11 3 read-write RT1PSDIV_0 RTC Prescale Timer 1 Clock Divide /2 0 RT1PSDIV_1 RTC Prescale Timer 1 Clock Divide /4 1 RT1PSDIV_2 RTC Prescale Timer 1 Clock Divide /8 2 RT1PSDIV_3 RTC Prescale Timer 1 Clock Divide /16 3 RT1PSDIV_4 RTC Prescale Timer 1 Clock Divide /32 4 RT1PSDIV_5 RTC Prescale Timer 1 Clock Divide /64 5 RT1PSDIV_6 RTC Prescale Timer 1 Clock Divide /128 6 RT1PSDIV_7 RTC Prescale Timer 1 Clock Divide /256 7 RT1SSEL RTC Prescale Timer 1 Source Select Bit 1 14 2 read-write RT1SSEL_0 RTC Prescale Timer Source Select ACLK 0 RT1SSEL_1 RTC Prescale Timer Source Select SMCLK 1 RT1SSEL_2 RTC Prescale Timer Source Select RT0PS 2 RT1SSEL_3 RTC Prescale Timer Source Select RT0PS 3 RTCPS Real Timer Prescale Timer Control 12 16 65535 RTCIV Real Time Clock Interrupt Vector 14 16 65535 RTCYEAR Real Time Clock Year 22 16 65535 USCI_A0_UART_MODE USCI_A0 UART Mode 1472 UCA0CTL1 USCI A0 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXBRK Send next Data as Break 1 1 read-write UCTXADDR Send next Data as Address 2 1 read-write UCDORM Dormant (Sleep) Mode 3 1 read-write UCBRKIE Break interrupt enable 4 1 read-write UCRXEIE RX Error interrupt enable 5 1 read-write UCSSEL USCI 0 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA0CTL0 USCI A0 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Async. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCSPB Async. Mode: Stop Bits 0:one / 1: two 3 1 read-write UC7BIT Async. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Async. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCPAR Async. Mode: Parity 0:odd / 1:even 6 1 read-write UCPEN Async. Mode: Parity enable 7 1 read-write UCA0BR0 USCI A0 Baud Rate 0 6 8 255 UCA0BR1 USCI A0 Baud Rate 1 7 8 255 UCA0MCTL USCI A0 Modulation Control 8 8 255 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRS USCI Second Stage Modulation Select 2 1 3 read-write UCBRS_0 USCI Second Stage Modulation: 0 0 UCBRS_1 USCI Second Stage Modulation: 1 1 UCBRS_2 USCI Second Stage Modulation: 2 2 UCBRS_3 USCI Second Stage Modulation: 3 3 UCBRS_4 USCI Second Stage Modulation: 4 4 UCBRS_5 USCI Second Stage Modulation: 5 5 UCBRS_6 USCI Second Stage Modulation: 6 6 UCBRS_7 USCI Second Stage Modulation: 7 7 UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCA0STAT USCI A0 Status Register 10 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0RXBUF USCI A0 Receive Buffer 12 8 255 UCA0TXBUF USCI A0 Transmit Buffer 14 8 255 UCA0ABCTL USCI A0 LIN Control 16 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM0 Break Sync Delimiter 0 4 1 read-write UCDELIM1 Break Sync Delimiter 1 5 1 read-write UCA0IRTCTL USCI A0 IrDA Transmit Control 18 8 255 0 255 UCIREN IRDA Encoder/Decoder enable 0 1 read-write UCIRTXCLK IRDA Transmit Pulse Clock Select 1 1 read-write UCIRTXPL0 IRDA Transmit Pulse Length 0 2 1 read-write UCIRTXPL1 IRDA Transmit Pulse Length 1 3 1 read-write UCIRTXPL2 IRDA Transmit Pulse Length 2 4 1 read-write UCIRTXPL3 IRDA Transmit Pulse Length 3 5 1 read-write UCIRTXPL4 IRDA Transmit Pulse Length 4 6 1 read-write UCIRTXPL5 IRDA Transmit Pulse Length 5 7 1 read-write UCA0IRRCTL USCI A0 IrDA Receive Control 19 8 255 0 255 UCIRRXFE IRDA Receive Filter enable 0 1 read-write UCIRRXPL IRDA Receive Input Polarity 1 1 read-write UCIRRXFL0 IRDA Receive Filter Length 0 2 1 read-write UCIRRXFL1 IRDA Receive Filter Length 1 3 1 read-write UCIRRXFL2 IRDA Receive Filter Length 2 4 1 read-write UCIRRXFL3 IRDA Receive Filter Length 3 5 1 read-write UCIRRXFL4 IRDA Receive Filter Length 4 6 1 read-write UCIRRXFL5 IRDA Receive Filter Length 5 7 1 read-write UCA0IE USCI A0 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCA0IFG USCI A0 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCA0IV USCI A0 Interrupt Vector Register 30 16 65535 USCI_A0_SPI_MODE USCI_A0 SPI Mode 1472 UCA0CTL1_SPI USCI A0 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA0CTL0_SPI USCI A0 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCA0BR0_SPI USCI A0 Baud Rate 0 6 8 255 UCA0BR1_SPI USCI A0 Baud Rate 1 7 8 255 UCA0MCTL_SPI USCI A0 Modulation Control 8 8 255 UCA0STAT_SPI USCI A0 Status Register 10 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0RXBUF_SPI USCI A0 Receive Buffer 12 8 255 UCA0TXBUF_SPI USCI A0 Transmit Buffer 14 8 255 UCA0IE_SPI USCI A0 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCSTTIE START Condition interrupt enable 2 1 read-write UCSTPIE STOP Condition interrupt enable 3 1 read-write UCALIE Arbitration Lost interrupt enable 4 1 read-write UCNACKIE NACK Condition interrupt enable 5 1 read-write UCA0IFG_SPI USCI A0 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCA0IV_SPI USCI A0 Interrupt Vector Register 30 16 65535 USCI_B0_I2C_MODE USCI_B0 I2C Mode 1504 UCB0CTL1 USCI B0 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXSTT Transmit START 1 1 read-write UCTXSTP Transmit STOP 2 1 read-write UCTXNACK Transmit NACK 3 1 read-write UCTR Transmit/Receive Select/Flag 4 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB0CTL0 USCI B0 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UCMM Multi-Master Environment 5 1 read-write UCSLA10 10-bit Slave Address Mode 6 1 read-write UCA10 10-bit Address Mode 7 1 read-write UCB0BR0 USCI B0 Baud Rate 0 6 8 255 UCB0BR1 USCI B0 Baud Rate 1 7 8 255 UCB0STAT USCI B0 Status Register 10 8 255 UCBBUSY Bus Busy Flag 4 1 read-write UCGC General Call address received Flag 5 1 read-write UCSCLLOW SCL low 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB0RXBUF USCI B0 Receive Buffer 12 8 255 UCB0TXBUF USCI B0 Transmit Buffer 14 8 255 UCB0IE USCI B0 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCSTTIE START Condition interrupt enable 2 1 read-write UCSTPIE STOP Condition interrupt enable 3 1 read-write UCALIE Arbitration Lost interrupt enable 4 1 read-write UCNACKIE NACK Condition interrupt enable 5 1 read-write UCB0IFG USCI B0 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCSTTIFG START Condition interrupt Flag 2 1 read-write UCSTPIFG STOP Condition interrupt Flag 3 1 read-write UCALIFG Arbitration Lost interrupt Flag 4 1 read-write UCNACKIFG NAK Condition interrupt Flag 5 1 read-write UCB0I2COA USCI B0 I2C Own Address 16 16 65535 UCOA0 I2C Own Address 0 0 1 read-write UCOA1 I2C Own Address 1 1 1 read-write UCOA2 I2C Own Address 2 2 1 read-write UCOA3 I2C Own Address 3 3 1 read-write UCOA4 I2C Own Address 4 4 1 read-write UCOA5 I2C Own Address 5 5 1 read-write UCOA6 I2C Own Address 6 6 1 read-write UCOA7 I2C Own Address 7 7 1 read-write UCOA8 I2C Own Address 8 8 1 read-write UCOA9 I2C Own Address 9 9 1 read-write UCGCEN I2C General Call enable 15 1 read-write UCB0I2CSA USCI B0 I2C Slave Address 18 16 65535 UCSA0 I2C Slave Address 0 0 1 read-write UCSA1 I2C Slave Address 1 1 1 read-write UCSA2 I2C Slave Address 2 2 1 read-write UCSA3 I2C Slave Address 3 3 1 read-write UCSA4 I2C Slave Address 4 4 1 read-write UCSA5 I2C Slave Address 5 5 1 read-write UCSA6 I2C Slave Address 6 6 1 read-write UCSA7 I2C Slave Address 7 7 1 read-write UCSA8 I2C Slave Address 8 8 1 read-write UCSA9 I2C Slave Address 9 9 1 read-write UCB0IV USCI B0 Interrupt Vector Register 30 16 65535 USCI_B0_SPI_MODE USCI_B0 SPI Mode 1504 UCB0CTL1_SPI USCI B0 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB0CTL0_SPI USCI B0 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCB0BR0_SPI USCI B0 Baud Rate 0 6 8 255 UCB0BR1_SPI USCI B0 Baud Rate 1 7 8 255 UCB0STAT_SPI USCI B0 Status Register 10 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB0RXBUF_SPI USCI B0 Receive Buffer 12 8 255 UCB0TXBUF_SPI USCI B0 Transmit Buffer 14 8 255 UCB0IE_SPI USCI B0 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCSTTIE START Condition interrupt enable 2 1 read-write UCSTPIE STOP Condition interrupt enable 3 1 read-write UCALIE Arbitration Lost interrupt enable 4 1 read-write UCNACKIE NACK Condition interrupt enable 5 1 read-write UCB0IFG_SPI USCI B0 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCB0IV_SPI USCI B0 Interrupt Vector Register 30 16 65535 USCI_A1_UART_MODE USCI_A1 UART Mode 1536 UCA1CTL1 USCI A1 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXBRK Send next Data as Break 1 1 read-write UCTXADDR Send next Data as Address 2 1 read-write UCDORM Dormant (Sleep) Mode 3 1 read-write UCBRKIE Break interrupt enable 4 1 read-write UCRXEIE RX Error interrupt enable 5 1 read-write UCSSEL USCI 0 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA1CTL0 USCI A1 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Async. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCSPB Async. Mode: Stop Bits 0:one / 1: two 3 1 read-write UC7BIT Async. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Async. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCPAR Async. Mode: Parity 0:odd / 1:even 6 1 read-write UCPEN Async. Mode: Parity enable 7 1 read-write UCA1BR0 USCI A1 Baud Rate 0 6 8 255 UCA1BR1 USCI A1 Baud Rate 1 7 8 255 UCA1MCTL USCI A1 Modulation Control 8 8 255 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRS USCI Second Stage Modulation Select 2 1 3 read-write UCBRS_0 USCI Second Stage Modulation: 0 0 UCBRS_1 USCI Second Stage Modulation: 1 1 UCBRS_2 USCI Second Stage Modulation: 2 2 UCBRS_3 USCI Second Stage Modulation: 3 3 UCBRS_4 USCI Second Stage Modulation: 4 4 UCBRS_5 USCI Second Stage Modulation: 5 5 UCBRS_6 USCI Second Stage Modulation: 6 6 UCBRS_7 USCI Second Stage Modulation: 7 7 UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCA1STAT USCI A1 Status Register 10 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA1RXBUF USCI A1 Receive Buffer 12 8 255 UCA1TXBUF USCI A1 Transmit Buffer 14 8 255 UCA1ABCTL USCI A1 LIN Control 16 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM0 Break Sync Delimiter 0 4 1 read-write UCDELIM1 Break Sync Delimiter 1 5 1 read-write UCA1IRTCTL USCI A1 IrDA Transmit Control 18 8 255 0 255 UCIREN IRDA Encoder/Decoder enable 0 1 read-write UCIRTXCLK IRDA Transmit Pulse Clock Select 1 1 read-write UCIRTXPL0 IRDA Transmit Pulse Length 0 2 1 read-write UCIRTXPL1 IRDA Transmit Pulse Length 1 3 1 read-write UCIRTXPL2 IRDA Transmit Pulse Length 2 4 1 read-write UCIRTXPL3 IRDA Transmit Pulse Length 3 5 1 read-write UCIRTXPL4 IRDA Transmit Pulse Length 4 6 1 read-write UCIRTXPL5 IRDA Transmit Pulse Length 5 7 1 read-write UCA1IRRCTL USCI A1 IrDA Receive Control 19 8 255 0 255 UCIRRXFE IRDA Receive Filter enable 0 1 read-write UCIRRXPL IRDA Receive Input Polarity 1 1 read-write UCIRRXFL0 IRDA Receive Filter Length 0 2 1 read-write UCIRRXFL1 IRDA Receive Filter Length 1 3 1 read-write UCIRRXFL2 IRDA Receive Filter Length 2 4 1 read-write UCIRRXFL3 IRDA Receive Filter Length 3 5 1 read-write UCIRRXFL4 IRDA Receive Filter Length 4 6 1 read-write UCIRRXFL5 IRDA Receive Filter Length 5 7 1 read-write UCA1IE USCI A1 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCA1IFG USCI A1 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCA1IV USCI A1 Interrupt Vector Register 30 16 65535 USCI_A1_SPI_MODE USCI_A1 SPI Mode 1536 UCA1CTL1_SPI USCI A1 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA1CTL0_SPI USCI A1 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCA1BR0_SPI USCI A1 Baud Rate 0 6 8 255 UCA1BR1_SPI USCI A1 Baud Rate 1 7 8 255 UCA1MCTL_SPI USCI A1 Modulation Control 8 8 255 UCA1STAT_SPI USCI A1 Status Register 10 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA1RXBUF_SPI USCI A1 Receive Buffer 12 8 255 UCA1TXBUF_SPI USCI A1 Transmit Buffer 14 8 255 UCA1IE_SPI USCI A1 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCSTTIE START Condition interrupt enable 2 1 read-write UCSTPIE STOP Condition interrupt enable 3 1 read-write UCALIE Arbitration Lost interrupt enable 4 1 read-write UCNACKIE NACK Condition interrupt enable 5 1 read-write UCA1IFG_SPI USCI A1 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCA1IV_SPI USCI A1 Interrupt Vector Register 30 16 65535 USCI_B1_I2C_MODE USCI_B1 I2C Mode 1568 UCB1CTL1 USCI B1 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXSTT Transmit START 1 1 read-write UCTXSTP Transmit STOP 2 1 read-write UCTXNACK Transmit NACK 3 1 read-write UCTR Transmit/Receive Select/Flag 4 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB1CTL0 USCI B1 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UCMM Multi-Master Environment 5 1 read-write UCSLA10 10-bit Slave Address Mode 6 1 read-write UCA10 10-bit Address Mode 7 1 read-write UCB1BR0 USCI B1 Baud Rate 0 6 8 255 UCB1BR1 USCI B1 Baud Rate 1 7 8 255 UCB1STAT USCI B1 Status Register 10 8 255 UCBBUSY Bus Busy Flag 4 1 read-write UCGC General Call address received Flag 5 1 read-write UCSCLLOW SCL low 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB1RXBUF USCI B1 Receive Buffer 12 8 255 UCB1TXBUF USCI B1 Transmit Buffer 14 8 255 UCB1IE USCI B1 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCSTTIE START Condition interrupt enable 2 1 read-write UCSTPIE STOP Condition interrupt enable 3 1 read-write UCALIE Arbitration Lost interrupt enable 4 1 read-write UCNACKIE NACK Condition interrupt enable 5 1 read-write UCB1IFG USCI B1 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCSTTIFG START Condition interrupt Flag 2 1 read-write UCSTPIFG STOP Condition interrupt Flag 3 1 read-write UCALIFG Arbitration Lost interrupt Flag 4 1 read-write UCNACKIFG NAK Condition interrupt Flag 5 1 read-write UCB1I2COA USCI B1 I2C Own Address 16 16 65535 UCOA0 I2C Own Address 0 0 1 read-write UCOA1 I2C Own Address 1 1 1 read-write UCOA2 I2C Own Address 2 2 1 read-write UCOA3 I2C Own Address 3 3 1 read-write UCOA4 I2C Own Address 4 4 1 read-write UCOA5 I2C Own Address 5 5 1 read-write UCOA6 I2C Own Address 6 6 1 read-write UCOA7 I2C Own Address 7 7 1 read-write UCOA8 I2C Own Address 8 8 1 read-write UCOA9 I2C Own Address 9 9 1 read-write UCGCEN I2C General Call enable 15 1 read-write UCB1I2CSA USCI B1 I2C Slave Address 18 16 65535 UCSA0 I2C Slave Address 0 0 1 read-write UCSA1 I2C Slave Address 1 1 1 read-write UCSA2 I2C Slave Address 2 2 1 read-write UCSA3 I2C Slave Address 3 3 1 read-write UCSA4 I2C Slave Address 4 4 1 read-write UCSA5 I2C Slave Address 5 5 1 read-write UCSA6 I2C Slave Address 6 6 1 read-write UCSA7 I2C Slave Address 7 7 1 read-write UCSA8 I2C Slave Address 8 8 1 read-write UCSA9 I2C Slave Address 9 9 1 read-write UCB1IV USCI B1 Interrupt Vector Register 30 16 65535 USCI_B1_SPI_MODE USCI_B1 SPI Mode 1568 UCB1CTL1_SPI USCI B1 Control Register 1 0 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB1CTL0_SPI USCI B1 Control Register 0 1 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCB1BR0_SPI USCI B1 Baud Rate 0 6 8 255 UCB1BR1_SPI USCI B1 Baud Rate 1 7 8 255 UCB1STAT_SPI USCI B1 Status Register 10 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB1RXBUF_SPI USCI B1 Receive Buffer 12 8 255 UCB1TXBUF_SPI USCI B1 Transmit Buffer 14 8 255 UCB1IE_SPI USCI B1 Interrupt Enable Register 28 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCSTTIE START Condition interrupt enable 2 1 read-write UCSTPIE STOP Condition interrupt enable 3 1 read-write UCALIE Arbitration Lost interrupt enable 4 1 read-write UCNACKIE NACK Condition interrupt enable 5 1 read-write UCB1IFG_SPI USCI B1 Interrupt Flags Register 29 8 255 UCRXIFG USCI Receive Interrupt Flag 0 1 read-write UCTXIFG USCI Transmit Interrupt Flag 1 1 read-write UCB1IV_SPI USCI B1 Interrupt Vector Register 30 16 65535 ADC12 ADC12 1792 ADC12MCTL0 ADC12 Memory Control 0 16 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL1 ADC12 Memory Control 1 17 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL2 ADC12 Memory Control 2 18 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL3 ADC12 Memory Control 3 19 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL4 ADC12 Memory Control 4 20 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL5 ADC12 Memory Control 5 21 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL6 ADC12 Memory Control 6 22 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL7 ADC12 Memory Control 7 23 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL8 ADC12 Memory Control 8 24 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL9 ADC12 Memory Control 9 25 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL10 ADC12 Memory Control 10 26 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL11 ADC12 Memory Control 11 27 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL12 ADC12 Memory Control 12 28 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL13 ADC12 Memory Control 13 29 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL14 ADC12 Memory Control 14 30 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12MCTL15 ADC12 Memory Control 15 31 8 255 ADC12INCH ADC12 Input Channel Select Bit 0 0 4 read-write ADC12INCH_0 ADC12 Input Channel 0 0 ADC12INCH_1 ADC12 Input Channel 1 1 ADC12INCH_2 ADC12 Input Channel 2 2 ADC12INCH_3 ADC12 Input Channel 3 3 ADC12INCH_4 ADC12 Input Channel 4 4 ADC12INCH_5 ADC12 Input Channel 5 5 ADC12INCH_6 ADC12 Input Channel 6 6 ADC12INCH_7 ADC12 Input Channel 7 7 ADC12INCH_8 ADC12 Input Channel 8 8 ADC12INCH_9 ADC12 Input Channel 9 9 ADC12INCH_10 ADC12 Input Channel 10 10 ADC12INCH_11 ADC12 Input Channel 11 11 ADC12INCH_12 ADC12 Input Channel 12 12 ADC12INCH_13 ADC12 Input Channel 13 13 ADC12INCH_14 ADC12 Input Channel 14 14 ADC12INCH_15 ADC12 Input Channel 15 15 ADC12SREF ADC12 Select Reference Bit 0 4 3 read-write ADC12SREF_0 ADC12 Select Reference 0 0 ADC12SREF_1 ADC12 Select Reference 1 1 ADC12SREF_2 ADC12 Select Reference 2 2 ADC12SREF_3 ADC12 Select Reference 3 3 ADC12SREF_4 ADC12 Select Reference 4 4 ADC12SREF_5 ADC12 Select Reference 5 5 ADC12SREF_6 ADC12 Select Reference 6 6 ADC12SREF_7 ADC12 Select Reference 7 7 ADC12EOS ADC12 End of Sequence 7 1 read-write ADC12CTL0 ADC12+ Control 0 0 16 65535 ADC12SC ADC12 Start Conversion 0 1 read-write ADC12ENC ADC12 Enable Conversion 1 1 read-write ADC12TOVIE ADC12 Timer Overflow interrupt enable 2 1 read-write ADC12OVIE ADC12 Overflow interrupt enable 3 1 read-write ADC12ON ADC12 On/enable 4 1 read-write ADC12REFON ADC12 Reference on 5 1 read-write ADC12REF2_5V ADC12 Ref 0:1.5V / 1:2.5V 6 1 read-write ADC12MSC ADC12 Multiple SampleConversion 7 1 read-write ADC12SHT0 ADC12 Sample Hold 0 Select Bit: 0 8 4 read-write ADC12SHT0_0 ADC12 Sample Hold 0 Select Bit: 0 0 ADC12SHT0_1 ADC12 Sample Hold 0 Select Bit: 1 1 ADC12SHT0_2 ADC12 Sample Hold 0 Select Bit: 2 2 ADC12SHT0_3 ADC12 Sample Hold 0 Select Bit: 3 3 ADC12SHT0_4 ADC12 Sample Hold 0 Select Bit: 4 4 ADC12SHT0_5 ADC12 Sample Hold 0 Select Bit: 5 5 ADC12SHT0_6 ADC12 Sample Hold 0 Select Bit: 6 6 ADC12SHT0_7 ADC12 Sample Hold 0 Select Bit: 7 7 ADC12SHT0_8 ADC12 Sample Hold 0 Select Bit: 8 8 ADC12SHT0_9 ADC12 Sample Hold 0 Select Bit: 9 9 ADC12SHT0_10 ADC12 Sample Hold 0 Select Bit: 10 10 ADC12SHT0_11 ADC12 Sample Hold 0 Select Bit: 11 11 ADC12SHT0_12 ADC12 Sample Hold 0 Select Bit: 12 12 ADC12SHT0_13 ADC12 Sample Hold 0 Select Bit: 13 13 ADC12SHT0_14 ADC12 Sample Hold 0 Select Bit: 14 14 ADC12SHT0_15 ADC12 Sample Hold 0 Select Bit: 15 15 ADC12SHT1 ADC12 Sample Hold 1 Select Bit: 0 12 4 read-write ADC12SHT1_0 ADC12 Sample Hold 1 Select Bit: 0 0 ADC12SHT1_1 ADC12 Sample Hold 1 Select Bit: 1 1 ADC12SHT1_2 ADC12 Sample Hold 1 Select Bit: 2 2 ADC12SHT1_3 ADC12 Sample Hold 1 Select Bit: 3 3 ADC12SHT1_4 ADC12 Sample Hold 1 Select Bit: 4 4 ADC12SHT1_5 ADC12 Sample Hold 1 Select Bit: 5 5 ADC12SHT1_6 ADC12 Sample Hold 1 Select Bit: 6 6 ADC12SHT1_7 ADC12 Sample Hold 1 Select Bit: 7 7 ADC12SHT1_8 ADC12 Sample Hold 1 Select Bit: 8 8 ADC12SHT1_9 ADC12 Sample Hold 1 Select Bit: 9 9 ADC12SHT1_10 ADC12 Sample Hold 1 Select Bit: 10 10 ADC12SHT1_11 ADC12 Sample Hold 1 Select Bit: 11 11 ADC12SHT1_12 ADC12 Sample Hold 1 Select Bit: 12 12 ADC12SHT1_13 ADC12 Sample Hold 1 Select Bit: 13 13 ADC12SHT1_14 ADC12 Sample Hold 1 Select Bit: 14 14 ADC12SHT1_15 ADC12 Sample Hold 1 Select Bit: 15 15 ADC12CTL1 ADC12+ Control 1 2 16 65535 ADC12BUSY ADC12 Busy 0 1 read-write ADC12CONSEQ ADC12 Conversion Sequence Select Bit: 0 1 2 read-write ADC12CONSEQ_0 ADC12 Conversion Sequence Select: 0 0 ADC12CONSEQ_1 ADC12 Conversion Sequence Select: 1 1 ADC12CONSEQ_2 ADC12 Conversion Sequence Select: 2 2 ADC12CONSEQ_3 ADC12 Conversion Sequence Select: 3 3 ADC12SSEL ADC12 Clock Source Select Bit: 0 3 2 read-write ADC12SSEL_0 ADC12 Clock Source Select: 0 0 ADC12SSEL_1 ADC12 Clock Source Select: 1 1 ADC12SSEL_2 ADC12 Clock Source Select: 2 2 ADC12SSEL_3 ADC12 Clock Source Select: 3 3 ADC12DIV ADC12 Clock Divider Select Bit: 0 5 3 read-write ADC12DIV_0 ADC12 Clock Divider Select: 0 0 ADC12DIV_1 ADC12 Clock Divider Select: 1 1 ADC12DIV_2 ADC12 Clock Divider Select: 2 2 ADC12DIV_3 ADC12 Clock Divider Select: 3 3 ADC12DIV_4 ADC12 Clock Divider Select: 4 4 ADC12DIV_5 ADC12 Clock Divider Select: 5 5 ADC12DIV_6 ADC12 Clock Divider Select: 6 6 ADC12DIV_7 ADC12 Clock Divider Select: 7 7 ADC12ISSH ADC12 Invert Sample Hold Signal 8 1 read-write ADC12SHP ADC12 Sample/Hold Pulse Mode 9 1 read-write ADC12SHS ADC12 Sample/Hold Source Bit: 0 10 2 read-write ADC12SHS_0 ADC12 Sample/Hold Source: 0 0 ADC12SHS_1 ADC12 Sample/Hold Source: 1 1 ADC12SHS_2 ADC12 Sample/Hold Source: 2 2 ADC12SHS_3 ADC12 Sample/Hold Source: 3 3 ADC12CSTARTADD ADC12 Conversion Start Address Bit: 0 12 4 read-write ADC12CSTARTADD_0 ADC12 Conversion Start Address: 0 0 ADC12CSTARTADD_1 ADC12 Conversion Start Address: 1 1 ADC12CSTARTADD_2 ADC12 Conversion Start Address: 2 2 ADC12CSTARTADD_3 ADC12 Conversion Start Address: 3 3 ADC12CSTARTADD_4 ADC12 Conversion Start Address: 4 4 ADC12CSTARTADD_5 ADC12 Conversion Start Address: 5 5 ADC12CSTARTADD_6 ADC12 Conversion Start Address: 6 6 ADC12CSTARTADD_7 ADC12 Conversion Start Address: 7 7 ADC12CSTARTADD_8 ADC12 Conversion Start Address: 8 8 ADC12CSTARTADD_9 ADC12 Conversion Start Address: 9 9 ADC12CSTARTADD_10 ADC12 Conversion Start Address: 10 10 ADC12CSTARTADD_11 ADC12 Conversion Start Address: 11 11 ADC12CSTARTADD_12 ADC12 Conversion Start Address: 12 12 ADC12CSTARTADD_13 ADC12 Conversion Start Address: 13 13 ADC12CSTARTADD_14 ADC12 Conversion Start Address: 14 14 ADC12CSTARTADD_15 ADC12 Conversion Start Address: 15 15 ADC12CTL2 ADC12+ Control 2 4 16 65535 ADC12REFBURST ADC12+ Reference Burst 0 1 read-write ADC12REFOUT ADC12+ Reference Out 1 1 read-write ADC12SR ADC12+ Sampling Rate 2 1 read-write ADC12DF ADC12+ Data Format 3 1 read-write ADC12RES ADC12+ Resolution Bit: 0 4 2 read-write ADC12RES_0 ADC12+ Resolution : 8 Bit 0 ADC12RES_1 ADC12+ Resolution : 10 Bit 1 ADC12RES_2 ADC12+ Resolution : 12 Bit 2 ADC12RES_3 ADC12+ Resolution : reserved 3 ADC12TCOFF ADC12+ Temperature Sensor Off 7 1 read-write ADC12PDIV ADC12+ predivider 0:/1 1:/4 8 1 read-write ADC12IFG ADC12+ Interrupt Flag 10 16 65535 0 65535 ADC12IFG0 ADC12 Memory 0 Interrupt Flag 0 1 read-write ADC12IFG1 ADC12 Memory 1 Interrupt Flag 1 1 read-write ADC12IFG2 ADC12 Memory 2 Interrupt Flag 2 1 read-write ADC12IFG3 ADC12 Memory 3 Interrupt Flag 3 1 read-write ADC12IFG4 ADC12 Memory 4 Interrupt Flag 4 1 read-write ADC12IFG5 ADC12 Memory 5 Interrupt Flag 5 1 read-write ADC12IFG6 ADC12 Memory 6 Interrupt Flag 6 1 read-write ADC12IFG7 ADC12 Memory 7 Interrupt Flag 7 1 read-write ADC12IFG8 ADC12 Memory 8 Interrupt Flag 8 1 read-write ADC12IFG9 ADC12 Memory 9 Interrupt Flag 9 1 read-write ADC12IFG10 ADC12 Memory 10 Interrupt Flag 10 1 read-write ADC12IFG11 ADC12 Memory 11 Interrupt Flag 11 1 read-write ADC12IFG12 ADC12 Memory 12 Interrupt Flag 12 1 read-write ADC12IFG13 ADC12 Memory 13 Interrupt Flag 13 1 read-write ADC12IFG14 ADC12 Memory 14 Interrupt Flag 14 1 read-write ADC12IFG15 ADC12 Memory 15 Interrupt Flag 15 1 read-write ADC12IE ADC12+ Interrupt Enable 12 16 65535 0 65535 ADC12IE0 ADC12 Memory 0 Interrupt Enable 0 1 read-write ADC12IE1 ADC12 Memory 1 Interrupt Enable 1 1 read-write ADC12IE2 ADC12 Memory 2 Interrupt Enable 2 1 read-write ADC12IE3 ADC12 Memory 3 Interrupt Enable 3 1 read-write ADC12IE4 ADC12 Memory 4 Interrupt Enable 4 1 read-write ADC12IE5 ADC12 Memory 5 Interrupt Enable 5 1 read-write ADC12IE6 ADC12 Memory 6 Interrupt Enable 6 1 read-write ADC12IE7 ADC12 Memory 7 Interrupt Enable 7 1 read-write ADC12IE8 ADC12 Memory 8 Interrupt Enable 8 1 read-write ADC12IE9 ADC12 Memory 9 Interrupt Enable 9 1 read-write ADC12IE10 ADC12 Memory 10 Interrupt Enable 10 1 read-write ADC12IE11 ADC12 Memory 11 Interrupt Enable 11 1 read-write ADC12IE12 ADC12 Memory 12 Interrupt Enable 12 1 read-write ADC12IE13 ADC12 Memory 13 Interrupt Enable 13 1 read-write ADC12IE14 ADC12 Memory 14 Interrupt Enable 14 1 read-write ADC12IE15 ADC12 Memory 15 Interrupt Enable 15 1 read-write ADC12IV ADC12+ Interrupt Vector Word 14 16 65535 ADC12MEM0 ADC12 Conversion Memory 0 32 16 65535 ADC12MEM1 ADC12 Conversion Memory 1 34 16 65535 ADC12MEM2 ADC12 Conversion Memory 2 36 16 65535 ADC12MEM3 ADC12 Conversion Memory 3 38 16 65535 ADC12MEM4 ADC12 Conversion Memory 4 40 16 65535 ADC12MEM5 ADC12 Conversion Memory 5 42 16 65535 ADC12MEM6 ADC12 Conversion Memory 6 44 16 65535 ADC12MEM7 ADC12 Conversion Memory 7 46 16 65535 ADC12MEM8 ADC12 Conversion Memory 8 48 16 65535 ADC12MEM9 ADC12 Conversion Memory 9 50 16 65535 ADC12MEM10 ADC12 Conversion Memory 10 52 16 65535 ADC12MEM11 ADC12 Conversion Memory 11 54 16 65535 ADC12MEM12 ADC12 Conversion Memory 12 56 16 65535 ADC12MEM13 ADC12 Conversion Memory 13 58 16 65535 ADC12MEM14 ADC12 Conversion Memory 14 60 16 65535 ADC12MEM15 ADC12 Conversion Memory 15 62 16 65535 USB_CONTROL USB Control 2304 USBIEPCNF_0 USB Input endpoint_0: Configuration 32 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPCNT_0 USB Input endpoint_0: Byte Count 33 8 255 USBOEPCNF_0 USB Output endpoint_0: Configuration 34 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPCNT_0 USB Output endpoint_0: byte count 35 8 255 USBIEPIE USB Input endpoint interrupt enable flags 46 8 255 USBOEPIE USB Output endpoint interrupt enable flags 47 8 255 USBIEPIFG USB Input endpoint interrupt flags 48 8 255 USBOEPIFG USB Output endpoint interrupt flags 49 8 255 USBCTL USB control register 60 8 255 DIR USB - Data Response Bit 0 1 read-write FRSTE USB - Function Reset Connection Enable 4 1 read-write RWUP USB - Device Remote Wakeup Request 5 1 read-write FEN USB - Function Enable Bit 6 1 read-write USBIE USB interrupt enable register 61 8 255 STPOWIE USB - Setup Overwrite Interrupt Enable 0 1 read-write SETUPIE USB - Setup Interrupt Enable 2 1 read-write RESRIE USB - Function Resume Request Interrupt Enable 5 1 read-write SUSRIE USB - Function Suspend Request Interrupt Enable 6 1 read-write RSTRIE USB - Function Reset Request Interrupt Enable 7 1 read-write USBIFG USB interrupt flag register 62 8 255 STPOWIFG USB - Setup Overwrite Interrupt Flag 0 1 read-write SETUPIFG USB - Setup Interrupt Flag 2 1 read-write RESRIFG USB - Function Resume Request Interrupt Flag 5 1 read-write SUSRIFG USB - Function Suspend Request Interrupt Flag 6 1 read-write RSTRIFG USB - Function Reset Request Interrupt Flag 7 1 read-write USBFUNADR USB Function address register 63 8 255 USBKEYID USB Controller key register 0 16 65535 USBCNF USB Module configuration register 2 16 65535 USB_EN USB - Module enable 0 1 read-write PUR_EN USB - PUR pin enable 1 1 read-write PUR_IN USB - PUR pin input value 2 1 read-write BLKRDY USB - Block ready signal for DMA 3 1 read-write FNTEN USB - Frame Number receive Trigger enable for DMA 4 1 read-write USBPHYCTL USB PHY control register 4 16 65535 PUOUT0 USB - USB Port Output Signal Bit 0 0 1 read-write PUOUT1 USB - USB Port Output Signal Bit 1 1 1 read-write PUIN0 USB - PU0/DP Input Data 2 1 read-write PUIN1 USB - PU1/DM Input Data 3 1 read-write PUOPE USB - USB Port Output Enable 5 1 read-write PUSEL USB - USB Port Function Select 7 1 read-write PUIPE USB - PHY Single Ended Input enable 8 1 read-write USBPWRCTL USB Power control register 8 16 65535 VUOVLIFG USB - VUSB Overload Interrupt Flag 0 1 read-write VBONIFG USB - VBUS "Coming ON" Interrupt Flag 1 1 read-write VBOFFIFG USB - VBUS "Going OFF" Interrupt Flag 2 1 read-write USBBGVBV USB - USB Bandgap and VBUS valid 3 1 read-write USBDETEN USB - VBUS on/off events enable 4 1 read-write OVLAOFF USB - LDO overload auto off enable 5 1 read-write SLDOAON USB - Secondary LDO auto on enable 6 1 read-write VUOVLIE USB - Overload indication Interrupt Enable 8 1 read-write VBONIE USB - VBUS "Coming ON" Interrupt Enable 9 1 read-write VBOFFIE USB - VBUS "Going OFF" Interrupt Enable 10 1 read-write VUSBEN USB - LDO Enable (3.3V) 11 1 read-write SLDOEN USB - Secondary LDO Enable (1.8V) 12 1 read-write USBPLLCTL USB PLL control register 16 16 65535 UCLKSEL USB - Module Clock Select Bit 0 6 2 read-write UCLKSEL_0 USB - Module Clock Select: 0 0 UCLKSEL_1 USB - Module Clock Select: 1 1 UCLKSEL_2 USB - Module Clock Select: 2 2 UCLKSEL_3 USB - Module Clock Select: 3 (Reserved) 3 UPLLEN USB - PLL enable 8 1 read-write UPFDEN USB - Phase Freq. Discriminator enable 9 1 read-write USBPLLDIVB USB PLL Clock Divider Buffer control register 18 16 65535 UPMB0 USB - PLL feedback divider buffer Bit 0 0 1 read-write UPMB1 USB - PLL feedback divider buffer Bit 1 1 1 read-write UPMB2 USB - PLL feedback divider buffer Bit 2 2 1 read-write UPMB3 USB - PLL feedback divider buffer Bit 3 3 1 read-write UPMB4 USB - PLL feedback divider buffer Bit 4 4 1 read-write UPMB5 USB - PLL feedback divider buffer Bit 5 5 1 read-write UPQB0 USB - PLL prescale divider buffer Bit 0 8 1 read-write UPQB1 USB - PLL prescale divider buffer Bit 1 9 1 read-write UPQB2 USB - PLL prescale divider buffer Bit 2 10 1 read-write USBPLLIR USB PLL Interrupt control register 20 16 65535 USBOOLIFG USB - PLL out of lock Interrupt Flag 0 1 read-write USBLOSIFG USB - PLL loss of signal Interrupt Flag 1 1 read-write USBOORIFG USB - PLL out of range Interrupt Flag 2 1 read-write USBOOLIE USB - PLL out of lock Interrupt enable 8 1 read-write USBLOSIE USB - PLL loss of signal Interrupt enable 9 1 read-write USBOORIE USB - PLL out of range Interrupt enable 10 1 read-write USBVECINT USB Vector interrupt register 50 16 65535 USBMAINT USB maintenance register 54 16 65535 UTIFG USB - Timer Interrupt Flag 0 1 read-write UTIE USB - Timer Interrupt Enable 1 1 read-write TSGEN USB - Time Stamp Generator Enable 8 1 read-write TSESEL USB - Time Stamp Event Select Bit 0 9 2 read-write TSESEL_0 USB - Time Stamp Event Select: 0 0 TSESEL_1 USB - Time Stamp Event Select: 1 1 TSESEL_2 USB - Time Stamp Event Select: 2 2 TSESEL_3 USB - Time Stamp Event Select: 3 3 TSE3 USB - Time Stamp Event #3 Bit 11 1 read-write UTSEL USB - Timer Select Bit 0 13 3 read-write UTSEL_0 USB - Timer Select: 0 0 UTSEL_1 USB - Timer Select: 1 1 UTSEL_2 USB - Timer Select: 2 2 UTSEL_3 USB - Timer Select: 3 3 UTSEL_4 USB - Timer Select: 4 4 UTSEL_5 USB - Timer Select: 5 5 UTSEL_6 USB - Timer Select: 6 6 UTSEL_7 USB - Timer Select: 7 7 USBTSREG USB Time Stamp register 56 16 65535 USBFN USB Frame number 58 16 65535 USB_OPERATION USB Operation 7168 USBSTABUFF Start of buffer space 0 8 255 USBTOPBUFF Top of buffer space 1903 8 255 USBOEP0BUF Output endpoint_0 buffer 1904 8 255 USBIEP0BUF Input endpoint_0 buffer 1912 8 255 USBSUBLK Setup Packet Block 1920 8 255 USBOEPCNF_1 Output Endpoint_1: Configuration 1928 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_1 Output Endpoint_1: X-buffer base addr. 1929 8 255 USBOEPBCTX_1 Output Endpoint_1: X-byte count 1930 8 255 USBOEPBBAY_1 Output Endpoint_1: Y-buffer base addr. 1933 8 255 USBOEPBCTY_1 Output Endpoint_1: Y-byte count 1934 8 255 USBOEPSIZXY_1 Output Endpoint_1: X/Y-buffer size 1935 8 255 USBOEPCNF_2 Output Endpoint_2: Configuration 1936 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_2 Output Endpoint_2: X-buffer base addr. 1937 8 255 USBOEPBCTX_2 Output Endpoint_2: X-byte count 1938 8 255 USBOEPBBAY_2 Output Endpoint_2: Y-buffer base addr. 1941 8 255 USBOEPBCTY_2 Output Endpoint_2: Y-byte count 1942 8 255 USBOEPSIZXY_2 Output Endpoint_2: X/Y-buffer size 1943 8 255 USBOEPCNF_3 Output Endpoint_3: Configuration 1944 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_3 Output Endpoint_3: X-buffer base addr. 1945 8 255 USBOEPBCTX_3 Output Endpoint_3: X-byte count 1946 8 255 USBOEPBBAY_3 Output Endpoint_3: Y-buffer base addr. 1949 8 255 USBOEPBCTY_3 Output Endpoint_3: Y-byte count 1950 8 255 USBOEPSIZXY_3 Output Endpoint_3: X/Y-buffer size 1951 8 255 USBOEPCNF_4 Output Endpoint_4: Configuration 1952 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_4 Output Endpoint_4: X-buffer base addr. 1953 8 255 USBOEPBCTX_4 Output Endpoint_4: X-byte count 1954 8 255 USBOEPBBAY_4 Output Endpoint_4: Y-buffer base addr. 1957 8 255 USBOEPBCTY_4 Output Endpoint_4: Y-byte count 1958 8 255 USBOEPSIZXY_4 Output Endpoint_4: X/Y-buffer size 1959 8 255 USBOEPCNF_5 Output Endpoint_5: Configuration 1960 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_5 Output Endpoint_5: X-buffer base addr. 1961 8 255 USBOEPBCTX_5 Output Endpoint_5: X-byte count 1962 8 255 USBOEPBBAY_5 Output Endpoint_5: Y-buffer base addr. 1965 8 255 USBOEPBCTY_5 Output Endpoint_5: Y-byte count 1966 8 255 USBOEPSIZXY_5 Output Endpoint_5: X/Y-buffer size 1967 8 255 USBOEPCNF_6 Output Endpoint_6: Configuration 1968 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_6 Output Endpoint_6: X-buffer base addr. 1969 8 255 USBOEPBCTX_6 Output Endpoint_6: X-byte count 1970 8 255 USBOEPBBAY_6 Output Endpoint_6: Y-buffer base addr. 1973 8 255 USBOEPBCTY_6 Output Endpoint_6: Y-byte count 1974 8 255 USBOEPSIZXY_6 Output Endpoint_6: X/Y-buffer size 1975 8 255 USBOEPCNF_7 Output Endpoint_7: Configuration 1976 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBOEPBBAX_7 Output Endpoint_7: X-buffer base addr. 1977 8 255 USBOEPBCTX_7 Output Endpoint_7: X-byte count 1978 8 255 USBOEPBBAY_7 Output Endpoint_7: Y-buffer base addr. 1981 8 255 USBOEPBCTY_7 Output Endpoint_7: Y-byte count 1982 8 255 USBOEPSIZXY_7 Output Endpoint_7: X/Y-buffer size 1983 8 255 USBIEPCNF_1 Input Endpoint_1: Configuration 1992 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_1 Input Endpoint_1: X-buffer base addr. 1993 8 255 USBIEPBCTX_1 Input Endpoint_1: X-byte count 1994 8 255 USBIEPBBAY_1 Input Endpoint_1: Y-buffer base addr. 1997 8 255 USBIEPBCTY_1 Input Endpoint_1: Y-byte count 1998 8 255 USBIEPSIZXY_1 Input Endpoint_1: X/Y-buffer size 1999 8 255 USBIEPCNF_2 Input Endpoint_2: Configuration 2000 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_2 Input Endpoint_2: X-buffer base addr. 2001 8 255 USBIEPBCTX_2 Input Endpoint_2: X-byte count 2002 8 255 USBIEPBBAY_2 Input Endpoint_2: Y-buffer base addr. 2005 8 255 USBIEPBCTY_2 Input Endpoint_2: Y-byte count 2006 8 255 USBIEPSIZXY_2 Input Endpoint_2: X/Y-buffer size 2007 8 255 USBIEPCNF_3 Input Endpoint_3: Configuration 2008 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_3 Input Endpoint_3: X-buffer base addr. 2009 8 255 USBIEPBCTX_3 Input Endpoint_3: X-byte count 2010 8 255 USBIEPBBAY_3 Input Endpoint_3: Y-buffer base addr. 2013 8 255 USBIEPBCTY_3 Input Endpoint_3: Y-byte count 2014 8 255 USBIEPSIZXY_3 Input Endpoint_3: X/Y-buffer size 2015 8 255 USBIEPCNF_4 Input Endpoint_4: Configuration 2016 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_4 Input Endpoint_4: X-buffer base addr. 2017 8 255 USBIEPBCTX_4 Input Endpoint_4: X-byte count 2018 8 255 USBIEPBBAY_4 Input Endpoint_4: Y-buffer base addr. 2021 8 255 USBIEPBCTY_4 Input Endpoint_4: Y-byte count 2022 8 255 USBIEPSIZXY_4 Input Endpoint_4: X/Y-buffer size 2023 8 255 USBIEPCNF_5 Input Endpoint_5: Configuration 2024 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_5 Input Endpoint_5: X-buffer base addr. 2025 8 255 USBIEPBCTX_5 Input Endpoint_5: X-byte count 2026 8 255 USBIEPBBAY_5 Input Endpoint_5: Y-buffer base addr. 2029 8 255 USBIEPBCTY_5 Input Endpoint_5: Y-byte count 2030 8 255 USBIEPSIZXY_5 Input Endpoint_5: X/Y-buffer size 2031 8 255 USBIEPCNF_6 Input Endpoint_6: Configuration 2032 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_6 Input Endpoint_6: X-buffer base addr. 2033 8 255 USBIEPBCTX_6 Input Endpoint_6: X-byte count 2034 8 255 USBIEPBBAY_6 Input Endpoint_6: Y-buffer base addr. 2037 8 255 USBIEPBCTY_6 Input Endpoint_6: Y-byte count 2038 8 255 USBIEPSIZXY_6 Input Endpoint_6: X/Y-buffer size 2039 8 255 USBIEPCNF_7 Input Endpoint_7: Configuration 2040 8 255 USBIIE USB - Transaction Interrupt indication enable 2 1 read-write STALL USB - Stall Condition 3 1 read-write DBUF USB - Double Buffer Enable 4 1 read-write TOGGLE USB - Toggle Bit 5 1 read-write UBME USB - UBM In-Endpoint Enable 7 1 read-write USBIEPBBAX_7 Input Endpoint_7: X-buffer base addr. 2041 8 255 USBIEPBCTX_7 Input Endpoint_7: X-byte count 2042 8 255 USBIEPBBAY_7 Input Endpoint_7: Y-buffer base addr. 2045 8 255 USBIEPBCTY_7 Input Endpoint_7: Y-byte count 2046 8 255 USBIEPSIZXY_7 Input Endpoint_7: X/Y-buffer size 2047 8 255 SFR SFR Special Function Registers 256 SFRIE1 Interrupt Enable 1 0 16 65535 WDTIE WDT Interrupt Enable 0 1 read-write OFIE Osc Fault Enable 1 1 read-write VMAIE Vacant Memory Interrupt Enable 3 1 read-write NMIIE NMI Interrupt Enable 4 1 read-write ACCVIE Flash Access Violation Interrupt Enable 5 1 read-write JMBINIE JTAG Mail Box input Interrupt Enable 6 1 read-write JMBOUTIE JTAG Mail Box output Interrupt Enable 7 1 read-write SFRIFG1 Interrupt Flag 1 2 16 65535 WDTIFG WDT Interrupt Flag 0 1 read-write OFIFG Osc Fault Flag 1 1 read-write VMAIFG Vacant Memory Interrupt Flag 3 1 read-write NMIIFG NMI Interrupt Flag 4 1 read-write JMBINIFG JTAG Mail Box input Interrupt Flag 6 1 read-write JMBOUTIFG JTAG Mail Box output Interrupt Flag 7 1 read-write SFRRPCR RESET Pin Control Register 4 16 65535 SYSNMI NMI select 0 1 read-write SYSNMIIES NMI edge select 1 1 read-write SYSRSTUP RESET Pin pull down/up select 2 1 read-write SYSRSTRE RESET Pin Resistor enable 3 1 read-write PMM PMM Power Management System 288 PMMCTL0 PMM Control 0 0 16 65535 PMMCOREV PMM Core Voltage Bit: 0 0 2 read-write PMMCOREV_0 PMM Core Voltage 0 (1.35V) 0 PMMCOREV_1 PMM Core Voltage 1 (1.55V) 1 PMMCOREV_2 PMM Core Voltage 2 (1.75V) 2 PMMCOREV_3 PMM Core Voltage 3 (1.85V) 3 PMMSWBOR PMM Software BOR 2 1 read-write PMMSWPOR PMM Software POR 3 1 read-write PMMREGOFF PMM Turn Regulator off 4 1 read-write PMMHPMRE PMM Global High Power Module Request Enable 7 1 read-write PMMCTL1 PMM Control 1 2 16 65535 PMMREFMD PMM Reference Mode 0 1 read-write PMMCMD0 PMM Voltage Regulator Current Mode Bit: 0 4 1 read-write PMMCMD1 PMM Voltage Regulator Current Mode Bit: 1 5 1 read-write SVSMHCTL SVS and SVM high side control register 4 16 65535 SVSMHRRL SVS and SVM high side Reset Release Voltage Level Bit: 0 0 3 read-write SVSMHRRL_0 SVS and SVM high side Reset Release Voltage Level 0 0 SVSMHRRL_1 SVS and SVM high side Reset Release Voltage Level 1 1 SVSMHRRL_2 SVS and SVM high side Reset Release Voltage Level 2 2 SVSMHRRL_3 SVS and SVM high side Reset Release Voltage Level 3 3 SVSMHRRL_4 SVS and SVM high side Reset Release Voltage Level 4 4 SVSMHRRL_5 SVS and SVM high side Reset Release Voltage Level 5 5 SVSMHRRL_6 SVS and SVM high side Reset Release Voltage Level 6 6 SVSMHRRL_7 SVS and SVM high side Reset Release Voltage Level 7 7 SVSMHDLYST SVS and SVM high side delay status 3 1 read-write SVSHMD SVS high side mode 4 1 read-write SVSMHEVM SVS and SVM high side event mask 6 1 read-write SVSMHACE SVS and SVM high side auto control enable 7 1 read-write SVSHRVL SVS high side reset voltage level Bit: 0 8 2 read-write SVSHRVL_0 SVS high side Reset Release Voltage Level 0 0 SVSHRVL_1 SVS high side Reset Release Voltage Level 1 1 SVSHRVL_2 SVS high side Reset Release Voltage Level 2 2 SVSHRVL_3 SVS high side Reset Release Voltage Level 3 3 SVSHE SVS high side enable 10 1 read-write SVSHFP SVS high side full performace mode 11 1 read-write SVMHOVPE SVM high side over-voltage enable 12 1 read-write SVMHE SVM high side enable 14 1 read-write SVMHFP SVM high side full performace mode 15 1 read-write SVSMLCTL SVS and SVM low side control register 6 16 65535 SVSMLRRL SVS and SVM low side Reset Release Voltage Level Bit: 0 0 3 read-write SVSMLRRL_0 SVS and SVM low side Reset Release Voltage Level 0 0 SVSMLRRL_1 SVS and SVM low side Reset Release Voltage Level 1 1 SVSMLRRL_2 SVS and SVM low side Reset Release Voltage Level 2 2 SVSMLRRL_3 SVS and SVM low side Reset Release Voltage Level 3 3 SVSMLRRL_4 SVS and SVM low side Reset Release Voltage Level 4 4 SVSMLRRL_5 SVS and SVM low side Reset Release Voltage Level 5 5 SVSMLRRL_6 SVS and SVM low side Reset Release Voltage Level 6 6 SVSMLRRL_7 SVS and SVM low side Reset Release Voltage Level 7 7 SVSMLDLYST SVS and SVM low side delay status 3 1 read-write SVSLMD SVS low side mode 4 1 read-write SVSMLEVM SVS and SVM low side event mask 6 1 read-write SVSMLACE SVS and SVM low side auto control enable 7 1 read-write SVSLRVL SVS low side reset voltage level Bit: 0 8 2 read-write SVSLRVL_0 SVS low side Reset Release Voltage Level 0 0 SVSLRVL_1 SVS low side Reset Release Voltage Level 1 1 SVSLRVL_2 SVS low side Reset Release Voltage Level 2 2 SVSLRVL_3 SVS low side Reset Release Voltage Level 3 3 SVSLE SVS low side enable 10 1 read-write SVSLFP SVS low side full performace mode 11 1 read-write SVMLOVPE SVM low side over-voltage enable 12 1 read-write SVMLE SVM low side enable 14 1 read-write SVMLFP SVM low side full performace mode 15 1 read-write SVSMIO SVSIN and SVSOUT control register 8 16 65535 SVMLOE SVM low side output enable 3 1 read-write SVMLVLROE SVM low side voltage level reached output enable 4 1 read-write SVMOUTPOL SVMOUT pin polarity 5 1 read-write SVMHOE SVM high side output enable 11 1 read-write SVMHVLROE SVM high side voltage level reached output enable 12 1 read-write PMMIFG PMM Interrupt Flag 12 16 65535 SVSMLDLYIFG SVS and SVM low side Delay expired interrupt flag 0 1 read-write SVMLIFG SVM low side interrupt flag 1 1 read-write SVMLVLRIFG SVM low side Voltage Level Reached interrupt flag 2 1 read-write SVSMHDLYIFG SVS and SVM high side Delay expired interrupt flag 4 1 read-write SVMHIFG SVM high side interrupt flag 5 1 read-write SVMHVLRIFG SVM high side Voltage Level Reached interrupt flag 6 1 read-write PMMBORIFG PMM Software BOR interrupt flag 8 1 read-write PMMRSTIFG PMM RESET pin interrupt flag 9 1 read-write PMMPORIFG PMM Software POR interrupt flag 10 1 read-write SVSHIFG SVS low side interrupt flag 12 1 read-write SVSLIFG SVS high side interrupt flag 13 1 read-write PMMLPM5IFG LPM5 indication Flag 15 1 read-write PMMRIE PMM and RESET Interrupt Enable 14 16 65535 SVSMLDLYIE SVS and SVM low side Delay expired interrupt enable 0 1 read-write SVMLIE SVM low side interrupt enable 1 1 read-write SVMLVLRIE SVM low side Voltage Level Reached interrupt enable 2 1 read-write SVSMHDLYIE SVS and SVM high side Delay expired interrupt enable 4 1 read-write SVMHIE SVM high side interrupt enable 5 1 read-write SVMHVLRIE SVM high side Voltage Level Reached interrupt enable 6 1 read-write SVSLPE SVS low side POR enable 8 1 read-write SVMLVLRPE SVM low side Voltage Level reached POR enable 9 1 read-write SVSHPE SVS high side POR enable 12 1 read-write SVMHVLRPE SVM high side Voltage Level reached POR enable 13 1 read-write PM5CTL0 PMM Power Mode 5 Control Register 0 16 16 65535 LOCKLPM5 Lock I/O pin configuration upon entry/exit to/from LPM5 0 1 read-write FLASH Flash 320 FCTL1 FLASH Control 1 0 16 65535 ERASE Enable bit for Flash segment erase 1 1 read-write MERAS Enable bit for Flash mass erase 2 1 read-write SWRT Smart Write enable 5 1 read-write WRT Enable bit for Flash write 6 1 read-write BLKWRT Enable bit for Flash segment write 7 1 read-write FCTL3 FLASH Control 3 4 16 65535 BUSY Flash busy: 1 0 1 read-write KEYV Flash Key violation flag 1 1 read-write ACCVIFG Flash Access violation flag 2 1 read-write WAIT Wait flag for segment write 3 1 read-write LOCK Lock bit: 1 - Flash is locked (read only) 4 1 read-write EMEX Flash Emergency Exit 5 1 read-write LOCKA Segment A Lock bit: read = 1 - Segment is locked (read only) 6 1 read-write FCTL4 FLASH Control 4 6 16 65535 VPE Voltage Changed during Program Error Flag 0 1 read-write MGR0 Marginal read 0 mode. 4 1 read-write MGR1 Marginal read 1 mode. 5 1 read-write LOCKINFO Lock INFO Memory bit: read = 1 - Segment is locked (read only) 7 1 read-write CRC16 CRC16 336 CRCDI CRC Data In Register 0 16 65535 CRCDIRB CRC data in reverse byte Register 2 16 65535 CRCINIRES CRC Initialisation Register and Result Register 4 16 65535 CRCRESR CRC reverse result Register 6 16 65535 RC RC RAM Control Module 344 RCCTL0 Ram Controller Control Register 0 16 65535 RCRS0OFF RAM Controller RAM Sector 0 Off 0 1 read-write RCRS1OFF RAM Controller RAM Sector 1 Off 1 1 read-write RCRS2OFF RAM Controller RAM Sector 2 Off 2 1 read-write RCRS3OFF RAM Controller RAM Sector 3 Off 3 1 read-write RCRS7OFF RAM Controller RAM Sector 7 (USB) Off 7 1 read-write WATCHDOG_TIMER Watchdog Timer 348 WDTCTL Watchdog Timer Control 0 16 65535 WDTIS WDT - Timer Interval Select 0 0 3 read-write WDTIS_0 WDT - Timer Interval Select: /2G 0 WDTIS_1 WDT - Timer Interval Select: /128M 1 WDTIS_2 WDT - Timer Interval Select: /8192k 2 WDTIS_3 WDT - Timer Interval Select: /512k 3 WDTIS_4 WDT - Timer Interval Select: /32k 4 WDTIS_5 WDT - Timer Interval Select: /8192 5 WDTIS_6 WDT - Timer Interval Select: /512 6 WDTIS_7 WDT - Timer Interval Select: /64 7 WDTCNTCL WDT - Timer Clear 3 1 read-write WDTTMSEL WDT - Timer Mode Select 4 1 read-write WDTSSEL WDT - Timer Clock Source Select 0 5 2 read-write WDTSSEL_0 WDT - Timer Clock Source Select: SMCLK 0 WDTSSEL_1 WDT - Timer Clock Source Select: ACLK 1 WDTSSEL_2 WDT - Timer Clock Source Select: VLO_CLK 2 WDTSSEL_3 WDT - Timer Clock Source Select: reserved 3 WDTHOLD WDT - Timer hold 7 1 read-write UCS UCS Unified System Clock 352 UCSCTL0 UCS Control Register 0 0 16 65535 MOD0 Modulation Bit Counter Bit : 0 3 1 read-write MOD1 Modulation Bit Counter Bit : 1 4 1 read-write MOD2 Modulation Bit Counter Bit : 2 5 1 read-write MOD3 Modulation Bit Counter Bit : 3 6 1 read-write MOD4 Modulation Bit Counter Bit : 4 7 1 read-write DCO0 DCO TAP Bit : 0 8 1 read-write DCO1 DCO TAP Bit : 1 9 1 read-write DCO2 DCO TAP Bit : 2 10 1 read-write DCO3 DCO TAP Bit : 3 11 1 read-write DCO4 DCO TAP Bit : 4 12 1 read-write UCSCTL1 UCS Control Register 1 2 16 65535 DISMOD Disable Modulation 0 1 read-write DCORSEL DCO Freq. Range Select Bit : 0 4 3 read-write DCORSEL_0 DCO RSEL 0 0 DCORSEL_1 DCO RSEL 1 1 DCORSEL_2 DCO RSEL 2 2 DCORSEL_3 DCO RSEL 3 3 DCORSEL_4 DCO RSEL 4 4 DCORSEL_5 DCO RSEL 5 5 DCORSEL_6 DCO RSEL 6 6 DCORSEL_7 DCO RSEL 7 7 UCSCTL2 UCS Control Register 2 4 16 65535 FLLN0 FLL Multipier Bit : 0 0 1 read-write FLLN1 FLL Multipier Bit : 1 1 1 read-write FLLN2 FLL Multipier Bit : 2 2 1 read-write FLLN3 FLL Multipier Bit : 3 3 1 read-write FLLN4 FLL Multipier Bit : 4 4 1 read-write FLLN5 FLL Multipier Bit : 5 5 1 read-write FLLN6 FLL Multipier Bit : 6 6 1 read-write FLLN7 FLL Multipier Bit : 7 7 1 read-write FLLN8 FLL Multipier Bit : 8 8 1 read-write FLLN9 FLL Multipier Bit : 9 9 1 read-write FLLD Loop Divider Bit : 0 12 3 read-write FLLD_0 Multiply Selected Loop Freq. 1 0 FLLD_1 Multiply Selected Loop Freq. 2 1 FLLD_2 Multiply Selected Loop Freq. 4 2 FLLD_3 Multiply Selected Loop Freq. 8 3 FLLD_4 Multiply Selected Loop Freq. 16 4 FLLD_5 Multiply Selected Loop Freq. 32 5 FLLD_6 Multiply Selected Loop Freq. 32 6 FLLD_7 Multiply Selected Loop Freq. 32 7 UCSCTL3 UCS Control Register 3 6 16 65535 FLLREFDIV Reference Divider Bit : 0 0 3 read-write FLLREFDIV_0 Reference Divider: f(LFCLK)/1 0 FLLREFDIV_1 Reference Divider: f(LFCLK)/2 1 FLLREFDIV_2 Reference Divider: f(LFCLK)/4 2 FLLREFDIV_3 Reference Divider: f(LFCLK)/8 3 FLLREFDIV_4 Reference Divider: f(LFCLK)/12 4 FLLREFDIV_5 Reference Divider: f(LFCLK)/16 5 FLLREFDIV_6 Reference Divider: f(LFCLK)/16 6 FLLREFDIV_7 Reference Divider: f(LFCLK)/16 7 SELREF FLL Reference Clock Select Bit : 0 4 3 read-write SELREF_0 FLL Reference Clock Select 0 0 SELREF_1 FLL Reference Clock Select 1 1 SELREF_2 FLL Reference Clock Select 2 2 SELREF_3 FLL Reference Clock Select 3 3 SELREF_4 FLL Reference Clock Select 4 4 SELREF_5 FLL Reference Clock Select 5 5 SELREF_6 FLL Reference Clock Select 6 6 SELREF_7 FLL Reference Clock Select 7 7 UCSCTL4 UCS Control Register 4 8 16 65535 SELM MCLK Source Select Bit: 0 0 3 read-write SELM_0 MCLK Source Select 0 0 SELM_1 MCLK Source Select 1 1 SELM_2 MCLK Source Select 2 2 SELM_3 MCLK Source Select 3 3 SELM_4 MCLK Source Select 4 4 SELM_5 MCLK Source Select 5 5 SELM_6 MCLK Source Select 6 6 SELM_7 MCLK Source Select 7 7 SELS SMCLK Source Select Bit: 0 4 3 read-write SELS_0 SMCLK Source Select 0 0 SELS_1 SMCLK Source Select 1 1 SELS_2 SMCLK Source Select 2 2 SELS_3 SMCLK Source Select 3 3 SELS_4 SMCLK Source Select 4 4 SELS_5 SMCLK Source Select 5 5 SELS_6 SMCLK Source Select 6 6 SELS_7 SMCLK Source Select 7 7 SELA ACLK Source Select Bit: 0 8 3 read-write SELA_0 ACLK Source Select 0 0 SELA_1 ACLK Source Select 1 1 SELA_2 ACLK Source Select 2 2 SELA_3 ACLK Source Select 3 3 SELA_4 ACLK Source Select 4 4 SELA_5 ACLK Source Select 5 5 SELA_6 ACLK Source Select 6 6 SELA_7 ACLK Source Select 7 7 UCSCTL5 UCS Control Register 5 10 16 65535 DIVM MCLK Divider Bit: 0 0 3 read-write DIVM_0 MCLK Source Divider 0 0 DIVM_1 MCLK Source Divider 1 1 DIVM_2 MCLK Source Divider 2 2 DIVM_3 MCLK Source Divider 3 3 DIVM_4 MCLK Source Divider 4 4 DIVM_5 MCLK Source Divider 5 5 DIVM_6 MCLK Source Divider 6 6 DIVM_7 MCLK Source Divider 7 7 DIVS SMCLK Divider Bit: 0 4 3 read-write DIVS_0 SMCLK Source Divider 0 0 DIVS_1 SMCLK Source Divider 1 1 DIVS_2 SMCLK Source Divider 2 2 DIVS_3 SMCLK Source Divider 3 3 DIVS_4 SMCLK Source Divider 4 4 DIVS_5 SMCLK Source Divider 5 5 DIVS_6 SMCLK Source Divider 6 6 DIVS_7 SMCLK Source Divider 7 7 DIVA ACLK Divider Bit: 0 8 3 read-write DIVA_0 ACLK Source Divider 0 0 DIVA_1 ACLK Source Divider 1 1 DIVA_2 ACLK Source Divider 2 2 DIVA_3 ACLK Source Divider 3 3 DIVA_4 ACLK Source Divider 4 4 DIVA_5 ACLK Source Divider 5 5 DIVA_6 ACLK Source Divider 6 6 DIVA_7 ACLK Source Divider 7 7 DIVPA ACLK from Pin Divider Bit: 0 12 3 read-write DIVPA_0 ACLK from Pin Source Divider 0 0 DIVPA_1 ACLK from Pin Source Divider 1 1 DIVPA_2 ACLK from Pin Source Divider 2 2 DIVPA_3 ACLK from Pin Source Divider 3 3 DIVPA_4 ACLK from Pin Source Divider 4 4 DIVPA_5 ACLK from Pin Source Divider 5 5 DIVPA_6 ACLK from Pin Source Divider 6 6 DIVPA_7 ACLK from Pin Source Divider 7 7 UCSCTL6 UCS Control Register 6 12 16 65535 XT1OFF High Frequency Oscillator 1 (XT1) disable 0 1 read-write SMCLKOFF SMCLK Off 1 1 read-write XCAP XIN/XOUT Cap Bit: 0 2 2 read-write XCAP_0 XIN/XOUT Cap 0 0 XCAP_1 XIN/XOUT Cap 1 1 XCAP_2 XIN/XOUT Cap 2 2 XCAP_3 XIN/XOUT Cap 3 3 XT1BYPASS XT1 bypass mode : 0: internal 1:sourced from external pin 4 1 read-write XTS 1: Selects high-freq. oscillator 5 1 read-write XT1DRIVE XT1 Drive Level mode Bit 0 6 2 read-write XT1DRIVE_0 XT1 Drive Level mode: 0 0 XT1DRIVE_1 XT1 Drive Level mode: 1 1 XT1DRIVE_2 XT1 Drive Level mode: 2 2 XT1DRIVE_3 XT1 Drive Level mode: 3 3 XT2OFF High Frequency Oscillator 2 (XT2) disable 8 1 read-write XT2BYPASS XT2 bypass mode : 0: internal 1:sourced from external pin 12 1 read-write XT2DRIVE XT2 Drive Level mode Bit 0 14 2 read-write XT2DRIVE_0 XT2 Drive Level mode: 0 0 XT2DRIVE_1 XT2 Drive Level mode: 1 1 XT2DRIVE_2 XT2 Drive Level mode: 2 2 XT2DRIVE_3 XT2 Drive Level mode: 3 3 UCSCTL7 UCS Control Register 7 14 16 65535 DCOFFG DCO Fault Flag 0 1 read-write XT1LFOFFG XT1 Low Frequency Oscillator Fault Flag 1 1 read-write XT2OFFG High Frequency Oscillator 2 Fault Flag 3 1 read-write UCSCTL8 UCS Control Register 8 16 16 65535 ACLKREQEN ACLK Clock Request Enable 0 1 read-write MCLKREQEN MCLK Clock Request Enable 1 1 read-write SMCLKREQEN SMCLK Clock Request Enable 2 1 read-write MODOSCREQEN MODOSC Clock Request Enable 3 1 read-write SYS SYS System Module 384 SYSCTL System control 0 16 65535 SYSRIVECT SYS - RAM based interrupt vectors 0 1 read-write SYSPMMPE SYS - PMM access protect 2 1 read-write SYSBSLIND SYS - TCK/RST indication detected 4 1 read-write SYSJTAGPIN SYS - Dedicated JTAG pins enabled 5 1 read-write SYSBSLC Boot strap configuration area 2 16 65535 SYSBSLSIZE0 SYS - BSL Protection Size 0 0 1 read-write SYSBSLSIZE1 SYS - BSL Protection Size 1 1 1 read-write SYSBSLR SYS - RAM assigned to BSL 2 1 read-write SYSBSLOFF SYS - BSL Memory disabled 14 1 read-write SYSBSLPE SYS - BSL Memory protection enabled 15 1 read-write SYSJMBC JTAG mailbox control 6 16 65535 JMBIN0FG SYS - Incoming JTAG Mailbox 0 Flag 0 1 read-write JMBIN1FG SYS - Incoming JTAG Mailbox 1 Flag 1 1 read-write JMBOUT0FG SYS - Outgoing JTAG Mailbox 0 Flag 2 1 read-write JMBOUT1FG SYS - Outgoing JTAG Mailbox 1 Flag 3 1 read-write JMBMODE SYS - JMB 16/32 Bit Mode 4 1 read-write JMBCLR0OFF SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe 6 1 read-write JMBCLR1OFF SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe 7 1 read-write SYSJMBI0 JTAG mailbox input 0 8 16 65535 SYSJMBI1 JTAG mailbox input 1 10 16 65535 SYSJMBO0 JTAG mailbox output 0 12 16 65535 SYSJMBO1 JTAG mailbox output 1 14 16 65535 SYSBERRIV Bus Error vector generator 24 16 65535 SYSUNIV User NMI vector generator 26 16 65535 SYSSNIV System NMI vector generator 28 16 65535 SYSRSTIV Reset vector generator 30 16 65535 SHARED_REFERENCE Shared Reference 432 REFCTL0 REF Shared Reference control register 0 0 16 65535 REFON REF Reference On 0 1 read-write REFOUT REF Reference output Buffer On 1 1 read-write REFTCOFF REF Temp.Sensor off 3 1 read-write REFVSEL REF Reference Voltage Level Select Bit:0 4 2 read-write REFVSEL_0 REF Reference Voltage Level Select 1.5V 0 REFVSEL_1 REF Reference Voltage Level Select 2.0V 1 REFVSEL_2 REF Reference Voltage Level Select 2.5V 2 REFVSEL_3 REF Reference Voltage Level Select 2.5V 3 REFMSTR REF Master Control 7 1 read-write REFGENACT REF Reference generator active 8 1 read-write REFBGACT REF Reference bandgap active 9 1 read-write REFGENBUSY REF Reference generator busy 10 1 read-write BGMODE REF Bandgap mode 11 1 read-write PORT_MAPPING_CONTROL Port Mapping Control 448 PMAPKEYID Port Mapping Key register 0 16 65535 PMAPCTL Port Mapping control register 2 16 65535 PMAPLOCKED Port Mapping Lock bit. Read only 0 1 read-write PMAPRECFG Port Mapping re-configuration control bit 1 1 read-write PORT_J Port J 800 PJIN Port J Input 0 16 65535 PJIN0 PJIN0 0 1 read-write PJIN1 PJIN1 1 1 read-write PJIN2 PJIN2 2 1 read-write PJIN3 PJIN3 3 1 read-write PJOUT Port J Output 2 16 65535 PJOUT0 PJOUT0 0 1 read-write PJOUT1 PJOUT1 1 1 read-write PJOUT2 PJOUT2 2 1 read-write PJOUT3 PJOUT3 3 1 read-write PJDIR Port J Direction 4 16 65535 PJDIR0 PJDIR0 0 1 read-write PJDIR1 PJDIR1 1 1 read-write PJDIR2 PJDIR2 2 1 read-write PJDIR3 PJDIR3 3 1 read-write PJREN Port J Resistor Enable 6 16 65535 PJREN0 PJREN0 0 1 read-write PJREN1 PJREN1 1 1 read-write PJREN2 PJREN2 2 1 read-write PJREN3 PJREN3 3 1 read-write PJDS Port J Drive Strenght 8 16 65535 PJDS0 PJDS0 0 1 read-write PJDS1 PJDS1 1 1 read-write PJDS2 PJDS2 2 1 read-write PJDS3 PJDS3 3 1 read-write TIMER_0_A5 Timer0_A5 832 TA0CTL Timer0_A5 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA0CCTL0 Timer0_A5 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0CCTL1 Timer0_A5 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0CCTL2 Timer0_A5 Capture/Compare Control 2 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0CCTL3 Timer0_A5 Capture/Compare Control 3 8 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0CCTL4 Timer0_A5 Capture/Compare Control 4 10 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0R Timer0_A5 16 16 65535 TA0CCR0 Timer0_A5 Capture/Compare 0 18 16 65535 TA0CCR1 Timer0_A5 Capture/Compare 1 20 16 65535 TA0CCR2 Timer0_A5 Capture/Compare 2 22 16 65535 TA0CCR3 Timer0_A5 Capture/Compare 3 24 16 65535 TA0CCR4 Timer0_A5 Capture/Compare 4 26 16 65535 TA0EX0 Timer0_A5 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA0IV Timer0_A5 Interrupt Vector Word 46 16 65535 TIMER_1_A3 Timer1_A3 896 TA1CTL Timer1_A3 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA1CCTL0 Timer1_A3 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA1CCTL1 Timer1_A3 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA1CCTL2 Timer1_A3 Capture/Compare Control 2 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA1R Timer1_A3 16 16 65535 TA1CCR0 Timer1_A3 Capture/Compare 0 18 16 65535 TA1CCR1 Timer1_A3 Capture/Compare 1 20 16 65535 TA1CCR2 Timer1_A3 Capture/Compare 2 22 16 65535 TA1EX0 Timer1_A3 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA1IV Timer1_A3 Interrupt Vector Word 46 16 65535 TIMER_0_B7 Timer0_B7 960 TB0CTL Timer0_B7 Control 0 16 65535 TBIFG Timer0_B7 interrupt flag 0 1 read-write TBIE Timer0_B7 interrupt enable 1 1 read-write TBCLR Timer0_B7 counter clear 2 1 read-write MC Timer0_B7 mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer0_B7 clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TBSSEL Clock source 1 8 2 read-write TBSSEL_0 Clock Source: TBCLK 0 TBSSEL_1 Clock Source: ACLK 1 TBSSEL_2 Clock Source: SMCLK 2 TBSSEL_3 Clock Source: INCLK 3 CNTL Counter lenght 1 11 2 read-write CNTL_0 Counter lenght: 16 bit 0 CNTL_1 Counter lenght: 12 bit 1 CNTL_2 Counter lenght: 10 bit 2 CNTL_3 Counter lenght: 8 bit 3 TBCLGRP Timer0_B7 Compare latch load group 1 13 2 read-write TBCLGRP_0 Timer0_B7 Group: 0 - individually 0 TBCLGRP_1 Timer0_B7 Group: 1 - 3 groups (1-2 1 TBCLGRP_2 Timer0_B7 Group: 2 - 2 groups (1-3 2 TBCLGRP_3 Timer0_B7 Group: 3 - 1 group (all) 3 TB0CCTL0 Timer0_B7 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0CCTL1 Timer0_B7 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0CCTL2 Timer0_B7 Capture/Compare Control 2 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0CCTL3 Timer0_B7 Capture/Compare Control 3 8 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0CCTL4 Timer0_B7 Capture/Compare Control 4 10 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0CCTL5 Timer0_B7 Capture/Compare Control 5 12 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0CCTL6 Timer0_B7 Capture/Compare Control 6 14 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write CLLD Compare latch load source 1 9 2 read-write CLLD_0 Compare latch load sourec : 0 - immediate 0 CLLD_1 Compare latch load sourec : 1 - TBR counts to 0 1 CLLD_2 Compare latch load sourec : 2 - up/down 2 CLLD_3 Compare latch load sourec : 3 - TBR counts to TBCTL0 3 SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TB0R Timer0_B7 16 16 65535 TB0CCR0 Timer0_B7 Capture/Compare 0 18 16 65535 TB0CCR1 Timer0_B7 Capture/Compare 1 20 16 65535 TB0CCR2 Timer0_B7 Capture/Compare 2 22 16 65535 TB0CCR3 Timer0_B7 Capture/Compare 3 24 16 65535 TB0CCR4 Timer0_B7 Capture/Compare 4 26 16 65535 TB0CCR5 Timer0_B7 Capture/Compare 5 28 16 65535 TB0CCR6 Timer0_B7 Capture/Compare 6 30 16 65535 TB0EX0 Timer0_B7 Expansion Register 0 32 16 65535 TBIDEX Timer0_B7 Input divider expansion Bit: 0 0 3 read-write TBIDEX_0 Timer0_B7 Input divider expansion : /1 0 TBIDEX_1 Timer0_B7 Input divider expansion : /2 1 TBIDEX_2 Timer0_B7 Input divider expansion : /3 2 TBIDEX_3 Timer0_B7 Input divider expansion : /4 3 TBIDEX_4 Timer0_B7 Input divider expansion : /5 4 TBIDEX_5 Timer0_B7 Input divider expansion : /6 5 TBIDEX_6 Timer0_B7 Input divider expansion : /7 6 TBIDEX_7 Timer0_B7 Input divider expansion : /8 7 TB0IV Timer0_B7 Interrupt Vector Word 46 16 65535 TIMER_2_A3 Timer2_A3 1024 TA2CTL Timer2_A3 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA2CCTL0 Timer2_A3 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA2CCTL1 Timer2_A3 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA2CCTL2 Timer2_A3 Capture/Compare Control 2 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA2R Timer2_A3 16 16 65535 TA2CCR0 Timer2_A3 Capture/Compare 0 18 16 65535 TA2CCR1 Timer2_A3 Capture/Compare 1 20 16 65535 TA2CCR2 Timer2_A3 Capture/Compare 2 22 16 65535 TA2EX0 Timer2_A3 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA2IV Timer2_A3 Interrupt Vector Word 46 16 65535 MPY_16 MPY 16 Multiplier 16 Bit Mode 1216 MPY Multiply Unsigned/Operand 1 0 16 65535 MPYS Multiply Signed/Operand 1 2 16 65535 MAC Multiply Unsigned and Accumulate/Operand 1 4 16 65535 MACS Multiply Signed and Accumulate/Operand 1 6 16 65535 OP2 Operand 2 8 16 65535 RESLO Result Low Word 10 16 65535 RESHI Result High Word 12 16 65535 SUMEXT Sum Extend 14 16 65535 MPY32CTL0 MPY32 Control Register 0 44 16 65535 MPYC Carry of the multiplier 0 1 read-write MPYFRAC Fractional mode 2 1 read-write MPYSAT Saturation mode 3 1 read-write MPYM Multiplier mode Bit:0 4 2 read-write MPYM_0 Multiplier mode: MPY 0 MPYM_1 Multiplier mode: MPYS 1 MPYM_2 Multiplier mode: MAC 2 MPYM_3 Multiplier mode: MACS 3 OP1_32 Bit-width of operand 1 0:16Bit / 1:32Bit 6 1 read-write OP2_32 Bit-width of operand 2 0:16Bit / 1:32Bit 7 1 read-write MPYDLYWRTEN Delayed write enable 8 1 read-write MPYDLY32 Delayed write mode 9 1 read-write MPY_32 MPY 32 Multiplier 32 Bit Mode 1232 MPY32L 32-bit operand 1 - multiply - low word 0 16 65535 MPY32H 32-bit operand 1 - multiply - high word 2 16 65535 MPYS32L 32-bit operand 1 - signed multiply - low word 4 16 65535 MPYS32H 32-bit operand 1 - signed multiply - high word 6 16 65535 MAC32L 32-bit operand 1 - multiply accumulate - low word 8 16 65535 MAC32H 32-bit operand 1 - multiply accumulate - high word 10 16 65535 MACS32L 32-bit operand 1 - signed multiply accumulate - low word 12 16 65535 MACS32H 32-bit operand 1 - signed multiply accumulate - high word 14 16 65535 OP2L 32-bit operand 2 - low word 16 16 65535 OP2H 32-bit operand 2 - high word 18 16 65535 RES0 32x32-bit result 0 - least significant word 20 16 65535 RES1 32x32-bit result 1 22 16 65535 RES2 32x32-bit result 2 24 16 65535 RES3 32x32-bit result 3 - most significant word 26 16 65535 DMA DMA 1280 DMACTL0 DMA Module Control 0 0 16 65535 DMA0TSEL DMA channel 0 transfer select bit 0 0 5 read-write DMA0TSEL_0 DMA channel 0 transfer select 0: DMA_REQ (sw) 0 DMA0TSEL_1 DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) 1 DMA0TSEL_2 DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) 2 DMA0TSEL_3 DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) 3 DMA0TSEL_4 DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) 4 DMA0TSEL_5 DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) 5 DMA0TSEL_6 DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) 6 DMA0TSEL_7 DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) 7 DMA0TSEL_8 DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) 8 DMA0TSEL_9 DMA channel 0 transfer select 9: Reserved 9 DMA0TSEL_10 DMA channel 0 transfer select 10: Reserved 10 DMA0TSEL_11 DMA channel 0 transfer select 11: Reserved 11 DMA0TSEL_12 DMA channel 0 transfer select 12: Reserved 12 DMA0TSEL_13 DMA channel 0 transfer select 13: Reserved 13 DMA0TSEL_14 DMA channel 0 transfer select 14: Reserved 14 DMA0TSEL_15 DMA channel 0 transfer select 15: Reserved 15 DMA0TSEL_16 DMA channel 0 transfer select 16: USCIA0 receive 16 DMA0TSEL_17 DMA channel 0 transfer select 17: USCIA0 transmit 17 DMA0TSEL_18 DMA channel 0 transfer select 18: USCIB0 receive 18 DMA0TSEL_19 DMA channel 0 transfer select 19: USCIB0 transmit 19 DMA0TSEL_20 DMA channel 0 transfer select 20: USCIA1 receive 20 DMA0TSEL_21 DMA channel 0 transfer select 21: USCIA1 transmit 21 DMA0TSEL_22 DMA channel 0 transfer select 22: USCIB1 receive 22 DMA0TSEL_23 DMA channel 0 transfer select 23: USCIB1 transmit 23 DMA0TSEL_24 DMA channel 0 transfer select 24: ADC12IFGx 24 DMA0TSEL_25 DMA channel 0 transfer select 25: Reserved 25 DMA0TSEL_26 DMA channel 0 transfer select 26: Reserved 26 DMA0TSEL_27 DMA channel 0 transfer select 27: USB FNRXD 27 DMA0TSEL_28 DMA channel 0 transfer select 28: USB ready 28 DMA0TSEL_29 DMA channel 0 transfer select 29: Multiplier ready 29 DMA0TSEL_30 DMA channel 0 transfer select 30: previous DMA channel DMA2IFG 30 DMA0TSEL_31 DMA channel 0 transfer select 31: ext. Trigger (DMAE0) 31 DMA1TSEL DMA channel 1 transfer select bit 0 8 5 read-write DMA1TSEL_0 DMA channel 1 transfer select 0: DMA_REQ (sw) 0 DMA1TSEL_1 DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) 1 DMA1TSEL_2 DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) 2 DMA1TSEL_3 DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) 3 DMA1TSEL_4 DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) 4 DMA1TSEL_5 DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) 5 DMA1TSEL_6 DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) 6 DMA1TSEL_7 DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) 7 DMA1TSEL_8 DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) 8 DMA1TSEL_9 DMA channel 1 transfer select 9: Reserved 9 DMA1TSEL_10 DMA channel 1 transfer select 10: Reserved 10 DMA1TSEL_11 DMA channel 1 transfer select 11: Reserved 11 DMA1TSEL_12 DMA channel 1 transfer select 12: Reserved 12 DMA1TSEL_13 DMA channel 1 transfer select 13: Reserved 13 DMA1TSEL_14 DMA channel 1 transfer select 14: Reserved 14 DMA1TSEL_15 DMA channel 1 transfer select 15: Reserved 15 DMA1TSEL_16 DMA channel 1 transfer select 16: USCIA0 receive 16 DMA1TSEL_17 DMA channel 1 transfer select 17: USCIA0 transmit 17 DMA1TSEL_18 DMA channel 1 transfer select 18: USCIB0 receive 18 DMA1TSEL_19 DMA channel 1 transfer select 19: USCIB0 transmit 19 DMA1TSEL_20 DMA channel 1 transfer select 20: USCIA1 receive 20 DMA1TSEL_21 DMA channel 1 transfer select 21: USCIA1 transmit 21 DMA1TSEL_22 DMA channel 1 transfer select 22: USCIB1 receive 22 DMA1TSEL_23 DMA channel 1 transfer select 23: USCIB1 transmit 23 DMA1TSEL_24 DMA channel 1 transfer select 24: ADC12IFGx 24 DMA1TSEL_25 DMA channel 1 transfer select 25: Reserved 25 DMA1TSEL_26 DMA channel 1 transfer select 26: Reserved 26 DMA1TSEL_27 DMA channel 1 transfer select 27: USB FNRXD 27 DMA1TSEL_28 DMA channel 1 transfer select 28: USB ready 28 DMA1TSEL_29 DMA channel 1 transfer select 29: Multiplier ready 29 DMA1TSEL_30 DMA channel 1 transfer select 30: previous DMA channel DMA0IFG 30 DMA1TSEL_31 DMA channel 1 transfer select 31: ext. Trigger (DMAE0) 31 DMACTL1 DMA Module Control 1 2 16 65535 DMA2TSEL DMA channel 2 transfer select bit 0 0 5 read-write DMA2TSEL_0 DMA channel 2 transfer select 0: DMA_REQ (sw) 0 DMA2TSEL_1 DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) 1 DMA2TSEL_2 DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) 2 DMA2TSEL_3 DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) 3 DMA2TSEL_4 DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) 4 DMA2TSEL_5 DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) 5 DMA2TSEL_6 DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) 6 DMA2TSEL_7 DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) 7 DMA2TSEL_8 DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) 8 DMA2TSEL_9 DMA channel 2 transfer select 9: Reserved 9 DMA2TSEL_10 DMA channel 2 transfer select 10: Reserved 10 DMA2TSEL_11 DMA channel 2 transfer select 11: Reserved 11 DMA2TSEL_12 DMA channel 2 transfer select 12: Reserved 12 DMA2TSEL_13 DMA channel 2 transfer select 13: Reserved 13 DMA2TSEL_14 DMA channel 2 transfer select 14: Reserved 14 DMA2TSEL_15 DMA channel 2 transfer select 15: Reserved 15 DMA2TSEL_16 DMA channel 2 transfer select 16: USCIA0 receive 16 DMA2TSEL_17 DMA channel 2 transfer select 17: USCIA0 transmit 17 DMA2TSEL_18 DMA channel 2 transfer select 18: USCIB0 receive 18 DMA2TSEL_19 DMA channel 2 transfer select 19: USCIB0 transmit 19 DMA2TSEL_20 DMA channel 2 transfer select 20: USCIA1 receive 20 DMA2TSEL_21 DMA channel 2 transfer select 21: USCIA1 transmit 21 DMA2TSEL_22 DMA channel 2 transfer select 22: USCIB1 receive 22 DMA2TSEL_23 DMA channel 2 transfer select 23: USCIB1 transmit 23 DMA2TSEL_24 DMA channel 2 transfer select 24: ADC12IFGx 24 DMA2TSEL_25 DMA channel 2 transfer select 25: Reserved 25 DMA2TSEL_26 DMA channel 2 transfer select 26: Reserved 26 DMA2TSEL_27 DMA channel 2 transfer select 27: USB FNRXD 27 DMA2TSEL_28 DMA channel 2 transfer select 28: USB ready 28 DMA2TSEL_29 DMA channel 2 transfer select 29: Multiplier ready 29 DMA2TSEL_30 DMA channel 2 transfer select 30: previous DMA channel DMA1IFG 30 DMA2TSEL_31 DMA channel 2 transfer select 31: ext. Trigger (DMAE0) 31 DMACTL2 DMA Module Control 2 4 16 65535 DMACTL3 DMA Module Control 3 6 16 65535 DMACTL4 DMA Module Control 4 8 16 65535 ENNMI Enable NMI interruption of DMA 0 1 read-write ROUNDROBIN Round-Robin DMA channel priorities 1 1 read-write DMARMWDIS Inhibited DMA transfers during read-modify-write CPU operations 2 1 read-write DMAIV DMA Interrupt Vector Word 14 16 65535 DMA0CTL DMA Channel 0 Control 16 16 65535 DMAREQ Initiate DMA transfer with DMATSEL 0 1 read-write DMAABORT DMA transfer aborted by NMI 1 1 read-write DMAIE DMA interrupt enable 2 1 read-write DMAIFG DMA interrupt flag 3 1 read-write DMAEN DMA enable 4 1 read-write DMALEVEL DMA level sensitive trigger select 5 1 read-write DMASRCBYTE DMA source byte 6 1 read-write DMADSTBYTE DMA destination byte 7 1 read-write DMASRCINCR DMA source increment bit 0 8 2 read-write DMASRCINCR_0 DMA source increment 0: source address unchanged 0 DMASRCINCR_1 DMA source increment 1: source address unchanged 1 DMASRCINCR_2 DMA source increment 2: source address decremented 2 DMASRCINCR_3 DMA source increment 3: source address incremented 3 DMADSTINCR DMA destination increment bit 0 10 2 read-write DMADSTINCR_0 DMA destination increment 0: destination address unchanged 0 DMADSTINCR_1 DMA destination increment 1: destination address unchanged 1 DMADSTINCR_2 DMA destination increment 2: destination address decremented 2 DMADSTINCR_3 DMA destination increment 3: destination address incremented 3 DMADT DMA transfer mode bit 0 12 3 read-write DMADT_0 DMA transfer mode 0: Single transfer 0 DMADT_1 DMA transfer mode 1: Block transfer 1 DMADT_2 DMA transfer mode 2: Burst-Block transfer 2 DMADT_3 DMA transfer mode 3: Burst-Block transfer 3 DMADT_4 DMA transfer mode 4: Repeated Single transfer 4 DMADT_5 DMA transfer mode 5: Repeated Block transfer 5 DMADT_6 DMA transfer mode 6: Repeated Burst-Block transfer 6 DMADT_7 DMA transfer mode 7: Repeated Burst-Block transfer 7 DMA0SZ DMA Channel 0 Transfer Size 26 16 65535 DMA1CTL DMA Channel 1 Control 32 16 65535 DMAREQ Initiate DMA transfer with DMATSEL 0 1 read-write DMAABORT DMA transfer aborted by NMI 1 1 read-write DMAIE DMA interrupt enable 2 1 read-write DMAIFG DMA interrupt flag 3 1 read-write DMAEN DMA enable 4 1 read-write DMALEVEL DMA level sensitive trigger select 5 1 read-write DMASRCBYTE DMA source byte 6 1 read-write DMADSTBYTE DMA destination byte 7 1 read-write DMASRCINCR DMA source increment bit 0 8 2 read-write DMASRCINCR_0 DMA source increment 0: source address unchanged 0 DMASRCINCR_1 DMA source increment 1: source address unchanged 1 DMASRCINCR_2 DMA source increment 2: source address decremented 2 DMASRCINCR_3 DMA source increment 3: source address incremented 3 DMADSTINCR DMA destination increment bit 0 10 2 read-write DMADSTINCR_0 DMA destination increment 0: destination address unchanged 0 DMADSTINCR_1 DMA destination increment 1: destination address unchanged 1 DMADSTINCR_2 DMA destination increment 2: destination address decremented 2 DMADSTINCR_3 DMA destination increment 3: destination address incremented 3 DMADT DMA transfer mode bit 0 12 3 read-write DMADT_0 DMA transfer mode 0: Single transfer 0 DMADT_1 DMA transfer mode 1: Block transfer 1 DMADT_2 DMA transfer mode 2: Burst-Block transfer 2 DMADT_3 DMA transfer mode 3: Burst-Block transfer 3 DMADT_4 DMA transfer mode 4: Repeated Single transfer 4 DMADT_5 DMA transfer mode 5: Repeated Block transfer 5 DMADT_6 DMA transfer mode 6: Repeated Burst-Block transfer 6 DMADT_7 DMA transfer mode 7: Repeated Burst-Block transfer 7 DMA1SZ DMA Channel 1 Transfer Size 42 16 65535 DMA2CTL DMA Channel 2 Control 48 16 65535 DMAREQ Initiate DMA transfer with DMATSEL 0 1 read-write DMAABORT DMA transfer aborted by NMI 1 1 read-write DMAIE DMA interrupt enable 2 1 read-write DMAIFG DMA interrupt flag 3 1 read-write DMAEN DMA enable 4 1 read-write DMALEVEL DMA level sensitive trigger select 5 1 read-write DMASRCBYTE DMA source byte 6 1 read-write DMADSTBYTE DMA destination byte 7 1 read-write DMASRCINCR DMA source increment bit 0 8 2 read-write DMASRCINCR_0 DMA source increment 0: source address unchanged 0 DMASRCINCR_1 DMA source increment 1: source address unchanged 1 DMASRCINCR_2 DMA source increment 2: source address decremented 2 DMASRCINCR_3 DMA source increment 3: source address incremented 3 DMADSTINCR DMA destination increment bit 0 10 2 read-write DMADSTINCR_0 DMA destination increment 0: destination address unchanged 0 DMADSTINCR_1 DMA destination increment 1: destination address unchanged 1 DMADSTINCR_2 DMA destination increment 2: destination address decremented 2 DMADSTINCR_3 DMA destination increment 3: destination address incremented 3 DMADT DMA transfer mode bit 0 12 3 read-write DMADT_0 DMA transfer mode 0: Single transfer 0 DMADT_1 DMA transfer mode 1: Block transfer 1 DMADT_2 DMA transfer mode 2: Burst-Block transfer 2 DMADT_3 DMA transfer mode 3: Burst-Block transfer 3 DMADT_4 DMA transfer mode 4: Repeated Single transfer 4 DMADT_5 DMA transfer mode 5: Repeated Block transfer 5 DMADT_6 DMA transfer mode 6: Repeated Burst-Block transfer 6 DMADT_7 DMA transfer mode 7: Repeated Burst-Block transfer 7 DMA2SZ DMA Channel 2 Transfer Size 58 16 65535 DMA0SA DMA Channel 0 Source Address 18 32 4294967295 DMA0DA DMA Channel 0 Destination Address 22 32 4294967295 DMA1SA DMA Channel 1 Source Address 34 32 4294967295 DMA1DA DMA Channel 1 Destination Address 38 32 4294967295 DMA2SA DMA Channel 2 Source Address 50 32 4294967295 DMA2DA DMA Channel 2 Destination Address 54 32 4294967295 COMPARATOR_B Comparator B 2240 CBCTL0 Comparator B Control Register 0 0 16 65535 CBIPSEL Comp. B Pos. Channel Input Select 0 0 4 read-write CBIPSEL_0 Comp. B V+ terminal Input Select: Channel 0 0 CBIPSEL_1 Comp. B V+ terminal Input Select: Channel 1 1 CBIPSEL_2 Comp. B V+ terminal Input Select: Channel 2 2 CBIPSEL_3 Comp. B V+ terminal Input Select: Channel 3 3 CBIPSEL_4 Comp. B V+ terminal Input Select: Channel 4 4 CBIPSEL_5 Comp. B V+ terminal Input Select: Channel 5 5 CBIPSEL_6 Comp. B V+ terminal Input Select: Channel 6 6 CBIPSEL_7 Comp. B V+ terminal Input Select: Channel 7 7 CBIPSEL_8 Comp. B V+ terminal Input Select: Channel 8 8 CBIPSEL_9 Comp. B V+ terminal Input Select: Channel 9 9 CBIPSEL_10 Comp. B V+ terminal Input Select: Channel 10 10 CBIPSEL_11 Comp. B V+ terminal Input Select: Channel 11 11 CBIPSEL_12 Comp. B V+ terminal Input Select: Channel 12 12 CBIPSEL_13 Comp. B V+ terminal Input Select: Channel 13 13 CBIPSEL_14 Comp. B V+ terminal Input Select: Channel 14 14 CBIPSEL_15 Comp. B V+ terminal Input Select: Channel 15 15 CBIPEN Comp. B Pos. Channel Input Enable 7 1 read-write CBIMSEL Comp. B Neg. Channel Input Select 0 8 4 read-write CBIMSEL_0 Comp. B V- Terminal Input Select: Channel 0 0 CBIMSEL_1 Comp. B V- Terminal Input Select: Channel 1 1 CBIMSEL_2 Comp. B V- Terminal Input Select: Channel 2 2 CBIMSEL_3 Comp. B V- Terminal Input Select: Channel 3 3 CBIMSEL_4 Comp. B V- Terminal Input Select: Channel 4 4 CBIMSEL_5 Comp. B V- Terminal Input Select: Channel 5 5 CBIMSEL_6 Comp. B V- Terminal Input Select: Channel 6 6 CBIMSEL_7 Comp. B V- Terminal Input Select: Channel 7 7 CBIMSEL_8 Comp. B V- terminal Input Select: Channel 8 8 CBIMSEL_9 Comp. B V- terminal Input Select: Channel 9 9 CBIMSEL_10 Comp. B V- terminal Input Select: Channel 10 10 CBIMSEL_11 Comp. B V- terminal Input Select: Channel 11 11 CBIMSEL_12 Comp. B V- terminal Input Select: Channel 12 12 CBIMSEL_13 Comp. B V- terminal Input Select: Channel 13 13 CBIMSEL_14 Comp. B V- terminal Input Select: Channel 14 14 CBIMSEL_15 Comp. B V- terminal Input Select: Channel 15 15 CBIMEN Comp. B Neg. Channel Input Enable 15 1 read-write CBCTL1 Comparator B Control Register 1 2 16 65535 CBOUT Comp. B Output 0 1 read-write CBOUTPOL Comp. B Output Polarity 1 1 read-write CBF Comp. B Enable Output Filter 2 1 read-write CBIES Comp. B Interrupt Edge Select 3 1 read-write CBSHORT Comp. B Input Short 4 1 read-write CBEX Comp. B Exchange Inputs 5 1 read-write CBFDLY Comp. B Filter delay Bit 0 6 2 read-write CBFDLY_0 Comp. B Filter delay 0 : 450ns 0 CBFDLY_1 Comp. B Filter delay 1 : 900ns 1 CBFDLY_2 Comp. B Filter delay 2 : 1800ns 2 CBFDLY_3 Comp. B Filter delay 3 : 3600ns 3 CBPWRMD Comp. B Power Mode Bit 0 8 2 read-write CBPWRMD_0 Comp. B Power Mode 0 : High speed 0 CBPWRMD_1 Comp. B Power Mode 1 : Normal 1 CBPWRMD_2 Comp. B Power Mode 2 : Ultra-Low 2 CBPWRMD_3 Comp. B Power Mode 3 : Reserved 3 CBON Comp. B enable 10 1 read-write CBMRVL Comp. B CBMRV Level 11 1 read-write CBMRVS Comp. B Output selects between VREF0 or VREF1 12 1 read-write CBCTL2 Comparator B Control Register 2 4 16 65535 CBREF0 Comp. B Reference 0 Resistor Select Bit : 0 0 5 read-write CBREF0_0 Comp. B Int. Ref.0 Select 0 : 1/32 0 CBREF0_1 Comp. B Int. Ref.0 Select 1 : 2/32 1 CBREF0_2 Comp. B Int. Ref.0 Select 2 : 3/32 2 CBREF0_3 Comp. B Int. Ref.0 Select 3 : 4/32 3 CBREF0_4 Comp. B Int. Ref.0 Select 4 : 5/32 4 CBREF0_5 Comp. B Int. Ref.0 Select 5 : 6/32 5 CBREF0_6 Comp. B Int. Ref.0 Select 6 : 7/32 6 CBREF0_7 Comp. B Int. Ref.0 Select 7 : 8/32 7 CBREF0_8 Comp. B Int. Ref.0 Select 0 : 9/32 8 CBREF0_9 Comp. B Int. Ref.0 Select 1 : 10/32 9 CBREF0_10 Comp. B Int. Ref.0 Select 2 : 11/32 10 CBREF0_11 Comp. B Int. Ref.0 Select 3 : 12/32 11 CBREF0_12 Comp. B Int. Ref.0 Select 4 : 13/32 12 CBREF0_13 Comp. B Int. Ref.0 Select 5 : 14/32 13 CBREF0_14 Comp. B Int. Ref.0 Select 6 : 15/32 14 CBREF0_15 Comp. B Int. Ref.0 Select 7 : 16/32 15 CBREF0_16 Comp. B Int. Ref.0 Select 0 : 17/32 16 CBREF0_17 Comp. B Int. Ref.0 Select 1 : 18/32 17 CBREF0_18 Comp. B Int. Ref.0 Select 2 : 19/32 18 CBREF0_19 Comp. B Int. Ref.0 Select 3 : 20/32 19 CBREF0_20 Comp. B Int. Ref.0 Select 4 : 21/32 20 CBREF0_21 Comp. B Int. Ref.0 Select 5 : 22/32 21 CBREF0_22 Comp. B Int. Ref.0 Select 6 : 23/32 22 CBREF0_23 Comp. B Int. Ref.0 Select 7 : 24/32 23 CBREF0_24 Comp. B Int. Ref.0 Select 0 : 25/32 24 CBREF0_25 Comp. B Int. Ref.0 Select 1 : 26/32 25 CBREF0_26 Comp. B Int. Ref.0 Select 2 : 27/32 26 CBREF0_27 Comp. B Int. Ref.0 Select 3 : 28/32 27 CBREF0_28 Comp. B Int. Ref.0 Select 4 : 29/32 28 CBREF0_29 Comp. B Int. Ref.0 Select 5 : 30/32 29 CBREF0_30 Comp. B Int. Ref.0 Select 6 : 31/32 30 CBREF0_31 Comp. B Int. Ref.0 Select 7 : 32/32 31 CBRSEL Comp. B Reference select 5 1 read-write CBRS Comp. B Reference Source Bit : 0 6 2 read-write CBRS_0 Comp. B Reference Source 0 : Off 0 CBRS_1 Comp. B Reference Source 1 : Vcc 1 CBRS_2 Comp. B Reference Source 2 : Shared Ref. 2 CBRS_3 Comp. B Reference Source 3 : Shared Ref. / Off 3 CBREF1 Comp. B Reference 1 Resistor Select Bit : 0 8 5 read-write CBREF1_0 Comp. B Int. Ref.1 Select 0 : 1/32 0 CBREF1_1 Comp. B Int. Ref.1 Select 1 : 2/32 1 CBREF1_2 Comp. B Int. Ref.1 Select 2 : 3/32 2 CBREF1_3 Comp. B Int. Ref.1 Select 3 : 4/32 3 CBREF1_4 Comp. B Int. Ref.1 Select 4 : 5/32 4 CBREF1_5 Comp. B Int. Ref.1 Select 5 : 6/32 5 CBREF1_6 Comp. B Int. Ref.1 Select 6 : 7/32 6 CBREF1_7 Comp. B Int. Ref.1 Select 7 : 8/32 7 CBREF1_8 Comp. B Int. Ref.1 Select 0 : 9/32 8 CBREF1_9 Comp. B Int. Ref.1 Select 1 : 10/32 9 CBREF1_10 Comp. B Int. Ref.1 Select 2 : 11/32 10 CBREF1_11 Comp. B Int. Ref.1 Select 3 : 12/32 11 CBREF1_12 Comp. B Int. Ref.1 Select 4 : 13/32 12 CBREF1_13 Comp. B Int. Ref.1 Select 5 : 14/32 13 CBREF1_14 Comp. B Int. Ref.1 Select 6 : 15/32 14 CBREF1_15 Comp. B Int. Ref.1 Select 7 : 16/32 15 CBREF1_16 Comp. B Int. Ref.1 Select 0 : 17/32 16 CBREF1_17 Comp. B Int. Ref.1 Select 1 : 18/32 17 CBREF1_18 Comp. B Int. Ref.1 Select 2 : 19/32 18 CBREF1_19 Comp. B Int. Ref.1 Select 3 : 20/32 19 CBREF1_20 Comp. B Int. Ref.1 Select 4 : 21/32 20 CBREF1_21 Comp. B Int. Ref.1 Select 5 : 22/32 21 CBREF1_22 Comp. B Int. Ref.1 Select 6 : 23/32 22 CBREF1_23 Comp. B Int. Ref.1 Select 7 : 24/32 23 CBREF1_24 Comp. B Int. Ref.1 Select 0 : 25/32 24 CBREF1_25 Comp. B Int. Ref.1 Select 1 : 26/32 25 CBREF1_26 Comp. B Int. Ref.1 Select 2 : 27/32 26 CBREF1_27 Comp. B Int. Ref.1 Select 3 : 28/32 27 CBREF1_28 Comp. B Int. Ref.1 Select 4 : 29/32 28 CBREF1_29 Comp. B Int. Ref.1 Select 5 : 30/32 29 CBREF1_30 Comp. B Int. Ref.1 Select 6 : 31/32 30 CBREF1_31 Comp. B Int. Ref.1 Select 7 : 32/32 31 CBREFL Comp. B Reference voltage level Bit : 0 13 2 read-write CBREFL_0 Comp. B Reference voltage level 0 : None 0 CBREFL_1 Comp. B Reference voltage level 1 : 1.5V 1 CBREFL_2 Comp. B Reference voltage level 2 : 2.0V 2 CBREFL_3 Comp. B Reference voltage level 3 : 2.5V 3 CBREFACC Comp. B Reference Accuracy 15 1 read-write CBCTL3 Comparator B Control Register 3 6 16 65535 0 65535 CBPD0 Comp. B Disable Input Buffer of Port Register .0 0 1 read-write CBPD1 Comp. B Disable Input Buffer of Port Register .1 1 1 read-write CBPD2 Comp. B Disable Input Buffer of Port Register .2 2 1 read-write CBPD3 Comp. B Disable Input Buffer of Port Register .3 3 1 read-write CBPD4 Comp. B Disable Input Buffer of Port Register .4 4 1 read-write CBPD5 Comp. B Disable Input Buffer of Port Register .5 5 1 read-write CBPD6 Comp. B Disable Input Buffer of Port Register .6 6 1 read-write CBPD7 Comp. B Disable Input Buffer of Port Register .7 7 1 read-write CBPD8 Comp. B Disable Input Buffer of Port Register .8 8 1 read-write CBPD9 Comp. B Disable Input Buffer of Port Register .9 9 1 read-write CBPD10 Comp. B Disable Input Buffer of Port Register .10 10 1 read-write CBPD11 Comp. B Disable Input Buffer of Port Register .11 11 1 read-write CBPD12 Comp. B Disable Input Buffer of Port Register .12 12 1 read-write CBPD13 Comp. B Disable Input Buffer of Port Register .13 13 1 read-write CBPD14 Comp. B Disable Input Buffer of Port Register .14 14 1 read-write CBPD15 Comp. B Disable Input Buffer of Port Register .15 15 1 read-write CBINT Comparator B Interrupt Register 12 16 65535 CBIFG Comp. B Interrupt Flag 0 1 read-write CBIIFG Comp. B Interrupt Flag Inverted Polarity 1 1 read-write CBIE Comp. B Interrupt Enable 8 1 read-write CBIIE Comp. B Interrupt Enable Inverted Polarity 9 1 read-write CBIV Comparator B Interrupt Vector Word 14 16 65535 _INTERRUPTS 65408 RTC 0xFFD2 RTC 41 PORT2 0xFFD4 Port 2 42 TIMER2_A1 0xFFD6 Timer2_A5 CC1-4, TA 43 TIMER2_A0 0xFFD8 Timer2_A5 CC0 44 USCI_B1 0xFFDA USCI B1 Receive/Transmit 45 USCI_A1 0xFFDC USCI A1 Receive/Transmit 46 PORT1 0xFFDE Port 1 47 TIMER1_A1 0xFFE0 Timer1_A3 CC1-2, TA1 48 TIMER1_A0 0xFFE2 Timer1_A3 CC0 49 DMA 0xFFE4 DMA 50 USB_UBM 0xFFE6 USB Timer / cable event / USB reset 51 TIMER0_A1 0xFFE8 Timer0_A5 CC1-4, TA 52 TIMER0_A0 0xFFEA Timer0_A5 CC0 53 ADC12 0xFFEC ADC 54 USCI_B0 0xFFEE USCI B0 Receive/Transmit 55 USCI_A0 0xFFF0 USCI A0 Receive/Transmit 56 WDT 0xFFF2 Watchdog Timer 57 TIMER0_B1 0xFFF4 Timer0_B7 CC1-6, TB 58 TIMER0_B0 0xFFF6 Timer0_B7 CC0 59 COMP_B 0xFFF8 Comparator B 60 UNMI 0xFFFA User Non-maskable 61 SYSNMI 0xFFFC System Non-maskable 62 0.2.0 31091a0