MSP430FR2355 2 0 read-write P1 P1 512 P1IN Port 1 Input 0 8 255 P1OUT Port 1 Output 2 8 255 P1DIR Port 1 Direction 4 8 255 P1REN Port 1 Resistor Enable 6 8 255 P1SEL0 Port 1 Select 0 10 8 255 P1SEL1 Port 1 Select 1 12 8 255 P1SELC Port 1 Complement Select 22 8 255 P1IES Port 1 Interrupt Edge Select 24 8 255 P1IE Port 1 Interrupt Enable 26 8 255 P1IFG Port 1 Interrupt Flag 28 8 255 P1IV Port 1 Interrupt Vector Register 14 16 65535 P1IV Port 1 interrupt vector value 0 5 read-only NONE No interrupt pending 0 P1IFG0 Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest 2 P1IFG1 Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 4 P1IFG2 Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 6 P1IFG3 Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 8 P1IFG4 Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 10 P1IFG5 Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 12 P1IFG6 Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 14 P1IFG7 Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest 16 P2 P2 512 P2IN Port 2 Input 1 8 255 P2OUT Port 2 Output 3 8 255 P2DIR Port 2 Direction 5 8 255 P2REN Port 2 Resistor Enable 7 8 255 P2SEL0 Port 2 Select 0 11 8 255 P2SEL1 Port 2 Select 1 13 8 255 P2SELC Port 2 Complement Select 23 8 255 P2IES Port 2 Interrupt Edge Select 25 8 255 P2IE Port 2 Interrupt Enable 27 8 255 P2IFG Port 2 Interrupt Flag 29 8 255 P2IV Port 2 Interrupt Vector Register 30 16 65535 P2IV Port 2 interrupt vector value 0 5 read-only NONE No interrupt pending 0 P2IFG0 Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest 2 P2IFG1 Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 4 P2IFG2 Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 6 P2IFG3 Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 8 P2IFG4 Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 10 P2IFG5 Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 12 P2IFG6 Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 14 P2IFG7 Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest 16 P3 P3 544 P3IN Port 3 Input 0 8 255 P3OUT Port 3 Output 2 8 255 P3DIR Port 3 Direction 4 8 255 P3REN Port 3 Resistor Enable 6 8 255 P3SEL0 Port 3 Select 0 10 8 255 P3SEL1 Port 3 Select 1 12 8 255 P3SELC Port 3 Complement Select 22 8 255 P3IES Port 3 Interrupt Edge Select 24 8 255 P3IE Port 3 Interrupt Enable 26 8 255 P3IFG Port 3 Interrupt Flag 28 8 255 P3IV Port 3 Interrupt Vector Register 14 16 65535 P3IV Port 3 interrupt vector value 0 5 read-only NONE No interrupt pending 0 P3IFG0 Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest 2 P3IFG1 Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 4 P3IFG2 Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 6 P3IFG3 Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 8 P3IFG4 Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 10 P3IFG5 Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 12 P3IFG6 Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 14 P3IFG7 Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest 16 P4 P4 544 P4IN Port 4 Input 1 8 255 P4OUT Port 4 Output 3 8 255 P4DIR Port 4 Direction 5 8 255 P4REN Port 4 Resistor Enable 7 8 255 P4SEL0 Port 4 Select 0 11 8 255 P4SEL1 Port 4 Select 1 13 8 255 P4SELC Port 4 Complement Select 23 8 255 P4IES Port 4 Interrupt Edge Select 25 8 255 P4IE Port 4 Interrupt Enable 27 8 255 P4IFG Port 4 Interrupt Flag 29 8 255 P4IV Port 4 Interrupt Vector Register 30 16 65535 P4IV Port 4 interrupt vector value 0 5 read-only NONE No interrupt pending 0 P4IFG0 Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest 2 P4IFG1 Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 4 P4IFG2 Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 6 P4IFG3 Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 8 P4IFG4 Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 10 P4IFG5 Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 12 P4IFG6 Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 14 P4IFG7 Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest 16 P5 P5 576 P5IN Port 5 Input 0 8 255 P5OUT Port 5 Output 2 8 255 P5DIR Port 5 Direction 4 8 255 P5REN Port 5 Resistor Enable 6 8 255 P5SEL0 Port 5 Select 0 10 8 255 P5SEL1 Port 5 Select 1 12 8 255 P5SELC Port 5 Complement Select 22 8 255 P6 P6 576 P6IN Port 6 Input 1 8 255 P6OUT Port 6 Output 3 8 255 P6DIR Port 6 Direction 5 8 255 P6REN Port 6 Resistor Enable 7 8 255 P6SEL0 Port 6 Select 0 11 8 255 P6SEL1 Port 6 Select 1 13 8 255 P6SELC Port 6 Complement Select 23 8 255 SFR SFR 256 SFRIE1 Interrupt Enable 0 16 65535 WDTIE Watchdog timer interrupt enable 0 1 read-write DISABLE Interrupts disabled 0 ENABLE Interrupts enabled 1 OFIE Oscillator fault interrupt enable 1 1 read-write DISABLE Interrupts disabled 0 ENABLE Interrupts enabled 1 VMAIE Vacant memory access interrupt enable 3 1 read-write DISABLE Interrupts disabled 0 ENABLE Interrupts enabled 1 NMIIE NMI pin interrupt enable 4 1 read-write DISABLE Interrupts disabled 0 ENABLE Interrupts enabled 1 JMBINIE JTAG mailbox input interrupt enable 6 1 read-write DISABLE Interrupts disabled 0 ENABLE Interrupts enabled 1 JMBOUTIE JTAG mailbox output interrupt enable 7 1 read-write DISABLE Interrupts disabled 0 ENABLE Interrupts enabled 1 SFRIFG1 Interrupt Flag 2 16 65535 OFIFG Oscillator fault interrupt flag 1 1 read-write OFIFG_0 No interrupt pending 0 OFIFG_1 Interrupt pending 1 VMAIFG Vacant memory access interrupt flag 3 1 read-write VMAIFG_0 No interrupt pending 0 VMAIFG_1 Interrupt pending 1 NMIIFG NMI pin interrupt flag 4 1 read-write NMIIFG_0 No interrupt pending 0 NMIIFG_1 Interrupt pending 1 WDTIFG Watchdog timer interrupt flag 0 1 read-write WDTIFG_0 No interrupt pending 0 WDTIFG_1 Interrupt pending 1 JMBINIFG JTAG mailbox input interrupt flag 6 1 read-write JMBINIFG_0 No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically when JMBI0 is read by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared automatically when both JMBI0 and JMBI1 have been read by the CPU. This bit is also cleared when the associated vector in SYSUNIV has been read 0 JMBINIFG_1 Interrupt pending. A message is waiting in the JMBIN registers. In 16-bit mode (JMBMODE = 0) when JMBI0 has been written by the JTAG module. In 32-bit mode (JMBMODE = 1) when JMBI0 and JMBI1 have been written by the JTAG module. 1 JMBOUTIFG JTAG mailbox output interrupt flag 7 1 read-write JMBOUTIFG_0 No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically when JMBO0 has been written with a new message to the JTAG module by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared automatically when both JMBO0 and JMBO1 have been written with new messages to the JTAG module by the CPU. This bit is also cleared when the associated vector in SYSUNIV has been read. 0 JMBOUTIFG_1 Interrupt pending. JMBO registers are ready for new messages. In 16-bit mode (JMBMODE = 0), JMBO0 has been received by the JTAG module and is ready for a new message from the CPU. In 32-bit mode (JMBMODE = 1), JMBO0 and JMBO1 have been received by the JTAG module and are ready for new messages from the CPU. 1 SFRRPCR Reset Pin Control 4 16 65535 SYSNMI NMI select 0 1 read-write RESET Reset function 0 NMI NMI function 1 SYSNMIIES NMI edge select 1 1 read-write RISING NMI on rising edge 0 FALLING NMI on falling edge 1 SYSRSTUP Reset resistor pin pullup or pulldown 2 1 read-write PULLDOWN Pulldown is selected 0 PULLUP Pullup is selected 1 SYSRSTRE Reset pin resistor enable 3 1 read-write DISABLE Pullup or pulldown resistor at the RST/NMI pin is disabled 0 ENABLE Pullup or pulldown resistor at the RST/NMI pin is enabled 1 PMM PMM 288 PMMCTL0 Power Management Module control register 0 0 16 65535 REFLOW Reflow pre-conditioning. Prepares device for reflow soldering. Write as 0 during normal operation. 0 1 read-write REFLOW_0 Normal operation 0 REFLOW_1 Enable reflow pre-conditioning 1 PMMSWBOR Software brownout reset. 2 1 read-write PMMSWBOR_0 Normal operation 0 PMMSWBOR_1 Set to 1 to trigger a BOR 1 PMMSWPOR Software POR. 3 1 read-write PMMSWPOR_0 Normal operation 0 PMMSWPOR_1 Set to 1 to trigger a POR 1 PMMREGOFF Regulator off 4 1 read-write PMMREGOFF_0 Regulator remains on when going into LPM3 or LPM4 0 PMMREGOFF_1 Regulator is turned off when going to LPM3 or LPM4. System enters LPM3.5 or LPM4.5, respectively. 1 SVSHE High-side SVS enable. 6 1 read-write SVSHE_0 High-side SVS (SVSH) is disabled in LPM2, LPM3, LPM4, LPM3.5, and LPM4.5. SVSH is always enabled in active mode, LPM0, and LPM1. 0 SVSHE_1 SVSH is always enabled. 1 PMMPW PMM password. 8 8 read-write PMMCTL2 Power Management Module Control Register 2 4 16 65535 INTREFEN Internal reference enable 0 1 read-write INTREFEN_0 Disable internal reference 0 INTREFEN_1 Enable internal reference 1 EXTREFEN External reference output enable 1 1 read-write EXTREFEN_0 Disable external reference output 0 EXTREFEN_1 Enable internal reference output 1 PWRMODE Power Mode Selection. The two bits are used to select the power supply in multi power supply systems. A single power supply system is not affected by the bits. Reserved for future use. 14 2 read-write TSENSOREN Temperature sensor enable 3 1 read-write TSENSOREN_0 Disable temperature sensor 0 TSENSOREN_1 Enable temperature sensor 1 REFGENACT Reference generator active. Read only. 8 1 read-only REFGENACT_0 Reference generator not active 0 REFGENACT_1 Reference generator active 1 REFBGACT Reference bandgap active. Ready only. 9 1 read-only REFBGACT_0 Reference bandgap buffer not active 0 REFBGACT_1 Reference bandgap buffer active 1 BGMODE Bandgap mode. Ready only. 11 1 read-write BGMODE_0 Static mode (higher precision) 0 BGMODE_1 Sampled mode (lower power consumption) 1 REFGENRDY Variable reference voltage ready status. 12 1 read-write REFGENRDY_0 Reference voltage output is not ready to be used. 0 REFGENRDY_1 Reference voltage output is ready to be used 1 REFBGRDY Buffered bandgap voltage ready status. 13 1 read-write REFBGRDY_0 Buffered bandgap voltage is not ready to be used 0 REFBGRDY_1 Buffered bandgap voltage is ready to be used 1 REFVSEL Reference voltage level select. Can be modified only when REFGENBUSY = 0. 4 2 read-write REFVSEL_0 00b = 1.5V 0 REFVSEL_1 01b = 2.0V 1 REFVSEL_2 10b = 2.5V 2 REFVSEL_3 11b = Reserved 3 REFGEN Reference generator one-time trigger. If written with a 1, the generation of the variable reference voltage is started. When the reference voltage request is set, this bit is cleared by hardware. 6 1 read-write REFGEN_0 No trigger 0 REFGEN_1 Generation of the reference voltage is started by writing 1 or by a hardware trigger 1 REFBGEN Bandgap and bandgap buffer one-time trigger. If written with a 1, the generation of the buffered bandgap voltage is started. When the bandgap buffer voltage request is set, this bit is cleared by hardware. 7 1 read-write REFBG_0 No trigger 0 REFBG_1 Generation of the bandgap voltage is started by writing 1 or by a hardware trigger 1 PMMIFG PMM interrupt flag register 10 16 65535 PMMBORIFG PMM software brownout reset interrupt flag. 8 1 read-write PMMBORIFG_0 Reset not due to PMMSWBOR 0 PMMBORIFG_1 Reset due to PMMSWBOR 1 PMMRSTIFG PMM reset pin interrupt flag. 9 1 read-write PMMBORIFG_0 Reset not due to reset pin 0 PMMBORIFG_1 Reset due to reset pin 1 PMMPORIFG PMM software POR interrupt flag. 10 1 read-write PMMBORIFG_0 Reset not due to PMMSWPOR 0 PMMBORIFG_1 Reset due to PMMSWPOR 1 SPWRIFG Secondary Power interrupt flag. This bit only works in multi power supply systems. When the secondary power is ready to use, this bit is set., In single power supply systems, this bit does not work. 11 1 read-only SVSHIFG High-side SVS interrupt flag. 13 1 read-write SVSHIFG_0 Reset not due to SVSH 0 SVSHIFG_1 Reset due to SVSH 1 PMMLPM5IFG LPMx.5 flag. 15 1 read-write PMMLPM5IFG_0 Reset not due to wake-up from LPMx.5 0 PMMLPM5IFG_1 Reset due to wake-up from LPMx.5 1 PMMSPSIFG PMM secondary power supply interrupt flag. Reserved for future multi power supply systems. 0 1 read-only PPWRIFG Primary Power interrupt flag. This bit only works in multi power supply systems. When the primary power is ready to use, this bit is set. In single power supply systems, this bit does not work 12 1 read-only PM5CTL0 Power mode 5 control register 0 16 16 65535 LOCKLPM5 LPMx.5 Lock Bit 0 1 read-write LOCKLPM5_0 LPMx.5 configuration is not locked and defaults to its reset condition. 0 LOCKLPM5_1 LPMx.5 configuration remains locked. Pin state is held during LPMx.5 entry and exit. 1 LPM5SW Reports or sets the LPM3.5 switch connection upon the switch mode set by LPM5SM. When this bit is set, the VLPM3.5 domain can accept full-speed read and write operation by CPU MCLK. If the switch is disconnected, all peripherals within this domain can only accept the operation no more than 40 kHz. In automatic mode (LPM5SM = 0), this bit represents the switch connection between Vcore and VLPM3.5. Any write to this bit has no effect. In manual mode (LPM5SM = 1), this bit can be fully read and written by software. When this bit is set, the switch connection between Vcore and VLPM3.5 is connected. Otherwise, the switch is disconnected. 4 1 read-write LPM5SW_0 LPMx.5 switch disconnected 0 LPM5SW_1 LPMx.5 switch connected 1 LPM5SM Specifies the operation mode of the LPM3.5 switch. 5 1 read-write LPM5SM_0 Automatic mode for LPM3.5 switch that the switch is fully handled by the circuitry during mode switch. 0 LPM5SM_1 Manual mode for LPM3.5 switch that the switch is specified by LPM5SW bit setting in software. 1 SYS SYS 320 SYSCTL System Control 0 16 65535 SYSRIVECT RAM-based interrupt vectors 0 1 read-write FRAM Interrupt vectors generated with end address TOP of lower 64K FRAM FFFFh 0 RAM Interrupt vectors generated with end address TOP of RAM, when RAM available 1 SYSPMMPE PMM access protect 2 1 read-write SYSPMMPE_0 Access from anywhere in memory 0 SYSPMMPE_1 Access only from the BSL segments 1 SYSBSLIND BSL entry indication 4 1 read-only SYSBSLIND_0 No BSL entry sequence detected 0 SYSBSLIND_1 BSL entry sequence detected 1 SYSJTAGPIN Dedicated JTAG pins enable 5 1 read-write SHARED Shared JTAG pins (JTAG mode selectable using SBW sequence) 0 DEDICATED Dedicated JTAG pins (explicit 4-wire JTAG mode selection) 1 SYSBSLC Bootstrap Loader Configuration Register 2 16 65535 SYSBSLR RAM assigned to BSL 2 1 read-write SYSBSLR_0 No RAM assigned to BSL area 0 SYSBSLR_1 Lowest 16 bytes of RAM assigned to BSL 1 SYSBSLOFF Bootstrap loader memory disable for the size covered in SYSBSLSIZE 14 1 read-write SYSBSLOFF_0 BSL memory is addressed when this area is read. 0 SYSBSLOFF_1 BSL memory behaves like vacant memory. Reads cause 3FFFh to be read. Fetches cause JMP $ to be executed. 1 SYSBSLPE Bootstrap loader memory protection enable for the size covered in SYSBSLSIZE. By default, this bit is cleared by hardware with a BOR event (as indicated above); however, the boot code that checks for an available BSL may set this bit in software to protect the BSL. Because devices normally come with a TI BSL preprogrammed and protected, the boot code sets this bit. 15 1 read-write SYSBSLPE_0 Area not protected. Read, program, and erase of BSL memory is possible. 0 SYSBSLPE_1 Area protected 1 SYSJMBC JTAG Mailbox Control 6 16 65535 JMBIN0FG Incoming JTAG Mailbox 0 flag 0 1 read-write JMBIN0FG_0 JMBI0 has no new data 0 JMBIN0FG_1 JMBI0 has new data available 1 JMBIN1FG Incoming JTAG Mailbox 1 flag 1 1 read-write JMBIN1FG_0 JMBI1 has no new data 0 JMBIN1FG_1 JMBI1 has new data available 1 JMBOUT0FG Outgoing JTAG Mailbox 0 flag 2 1 read-only JMBOUT0FG_0 JMBO0 is not ready to receive new data 0 JMBOUT0FG_1 JMBO0 is ready to receive new data 1 JMBOUT1FG Outgoing JTAG Mailbox 1 flag 3 1 read-only JMBOUT1FG_0 JMBO1 is not ready to receive new data 0 JMBOUT1FG_1 JMBO1 is ready to receive new data 1 JMBMODE Operation mode of JMB 4 1 read-write 16BIT 16-bit transfers using JMBO0 and JMBI0 only 0 32BIT 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 1 JMBCLR0OFF Incoming JTAG Mailbox 0 flag auto-clear disable 6 1 read-write JMBCLR0OFF_0 JMBIN0FG cleared on read of JMB0IN register 0 JMBCLR0OFF_1 JMBIN0FG cleared by software 1 JMBCLR1OFF Incoming JTAG Mailbox 1 flag auto-clear disable 7 1 read-write JMBCLR1OFF_0 JMBIN1FG cleared on read of JMB1IN register 0 JMBCLR1OFF_1 JMBIN1FG cleared by software 1 SYSJMBI0 JTAG Mailbox Input 8 16 65535 MSGLO JTAG mailbox incoming message low byte 0 8 read-write MSGHI JTAG mailbox incoming message high byte 8 8 read-write SYSJMBI1 JTAG Mailbox Input 1 Register 10 16 65535 MSGLO JTAG mailbox incoming message low byte 0 8 read-write MSGHI JTAG mailbox incoming message high byte 8 8 read-write SYSJMBO0 JTAG Mailbox Output 12 16 65535 MSGLO JTAG mailbox outgoing message low byte 0 8 read-write MSGHI JTAG mailbox outgoing message high byte 8 8 read-write SYSJMBO1 JTAG Mailbox Output 1 Register 14 16 65535 MSGLO JTAG mailbox outgoing message low byte 0 8 read-write MSGHI JTAG mailbox outgoing message high byte 8 8 read-write SYSUNIV User NMI Vector Generator 26 16 65535 SYSUNIV User NMI vector 0 16 read-only NONE No interrupt pending 0 NMIIFG NMIIFG NMI pin 2 OFIFG OFIFG oscillator fault 4 SYSSNIV System NMI Vector Generator 28 16 65535 SYSSNIV System NMI vector 0 16 read-only NONE No interrupt pending 0 SVSLIFG SVS low-power reset entry 2 UBDIFG Uncorrectable FRAM bit error detection 4 ACCTEIFG FRAM Access Time Error 6 SYSSNIV_8 Reserved 8 SYSSNIV_10 Reserved 10 SYSSNIV_12 Reserved 12 SYSSNIV_14 Reserved 14 SYSSNIV_16 Reserved 16 VMAIFG VMAIFG Vacant memory access 18 JMBINIFG JMBINIFG JTAG mailbox input 20 JMBOUTIFG JMBOUTIFG JTAG mailbox output 22 CBDIFG Correctable FRAM bit error detection 24 SYSRSTIV Reset Vector Generator 30 16 65535 SYSRSTIV Reset interrupt vector 0 16 read-only NONE No interrupt pending 0 BOR Brownout 2 RSTNMI RSTIFG RST/NMI 4 PMMSWBOR PMMSWBOR software BOR 6 LPM5WU LPMx.5 wakeup 8 SECYV Security violation 10 SYSRSTIV_12 Reserved 12 SVSHIFG SVSHIFG SVSH event 14 SYSRSTIV_16 Reserved 16 SYSRSTIV_18 Reserved 18 PMMSWPOR PMMSWPOR software POR 20 WDTIFG WDTIFG watchdog timeout 22 WDTPW WDTPW watchdog password violation 24 FRCTLPW FRCTLPW password violation 26 UBDIFG Uncorrectable FRAM bit error detection 28 PERF Peripheral area fetch 30 PMMPW PMM password violation 32 SYSRSTIV_34 Reserved 34 FLLUL FLL unlock (PUC) 36 SYSCFG0 System Configuration Register 0 32 16 65535 PFWP Program FRAM write protection 0 1 read-write PFWP_0 Program FRAM write enable 0 PFWP_1 Program FRAM write protected (not writable) 1 DFWP Data FRAM write protection 1 1 read-write DFWP_0 Data FRAM write enable 0 DFWP_1 Data FRAM write protected (not writable) 1 FRWPPW FRAM protection password, FRAM protection password. Write with 0A5h to unlock the FRAM protection registers. Always reads as 096h 8 8 read-write FRWPOA Program FRAM write protection offset address from the beginning of Program FRAM. The offset increases by 1KB resolution 2 6 read-write SYSCFG1 System Configuration Register 1 34 16 65535 IREN Infrared enable 0 1 read-write IREN_0 Infrared function disabled 0 IREN_1 Infrared function enabled 1 IRPSEL Infrared polarity select 1 1 read-write IRPSEL_0 Normal polarity 0 IRPSEL_1 Inverted polarity 1 IRMSEL Infrared mode select 2 1 read-write IRMSEL_0 FSK mode 0 IRMSEL_1 ASK mode 1 IRDSSEL Infrared data source select 3 1 read-write IRDSSEL_0 From hardware peripherals upon device configuration 0 IRDSSEL_1 From IRDATA bit 1 IRDATA Infrared data 4 1 read-write IRDATA_0 Infrared data logic 0 0 IRDATA_1 Infrared data logic 1 1 SYNCSEL Captivate Conversion triggered Source Selection 6 2 read-write SYNCSEL_0 External source is selected 0 SYNCSEL_1 ADC as the source is selected 1 SYNCSEL_2 internal source is selected 2 SYNCSEL_3 Reserved 3 SYSCFG2 System Configuration Register 2 36 16 65535 ADCPCTL0 ADC input A0 pin select 0 1 read-write ADCPCTL0_0 ADC input A0 disabled 0 ADCPCTL0_1 ADC input A0 enabled 1 ADCPCTL1 ADC input A1 pin select 1 1 read-write ADCPCTL1_0 ADC input A1 disabled 0 ADCPCTL1_1 ADC input A1 enabled 1 ADCPCTL2 ADC input A2 pin select 2 1 read-write ADCPCTL2_0 ADC input A2 disabled 0 ADCPCTL2_1 ADC input A2 enabled 1 ADCPCTL3 ADC input A3 pin select 3 1 read-write ADCPCTL3_0 ADC input A3 disabled 0 ADCPCTL3_1 ADC input A3 enabled 1 ADCPCTL4 ADC input A4 pin select 4 1 read-write ADCPCTL4_0 ADC input A4 disabled 0 ADCPCTL4_1 ADC input A4 enabled 1 ADCPCTL5 ADC input A5 pin select 5 1 read-write ADCPCTL5_0 ADC input A5 disabled 0 ADCPCTL5_1 ADC input A5 enabled 1 ADCPCTL6 ADC input A6 pin select 6 1 read-write ADCPCTL6_0 ADC input A6 disabled 0 ADCPCTL6_1 ADC input A6 enabled 1 ADCPCTL7 ADC input A7 pin select 7 1 read-write ADCPCTL7_0 ADC input A7 disabled 0 ADCPCTL7_1 ADC input A7 enabled 1 ADCPCTL8 ADC input A8 pin select 8 1 read-write ADCPCTL8_0 ADC input A8 disabled 0 ADCPCTL8_1 ADC input A8 enabled 1 ADCPCTL9 ADC input A9 pin select 9 1 read-write ADCPCTL9_0 ADC input A9 disabled 0 ADCPCTL9_1 ADC input A9 enabled 1 USCIBRMP eUSCIB Remapping source selection , please refer to device specific for details 11 1 read-write USCIBRMP_0 P1.x is selected, please refer to device specific for details 0 USCIBRMP_1 other port is selected, please refer to device specific for details 1 RTCCKSEL RTC clock selection 10 1 read-write RTC_SMCLK SMCLK is selected 0 RTC_ACLK ACLK is selected 1 SYSCFG3 System Configuration Register 3 38 16 65535 USCIARMP eUSCIA remapping source selection, please refer to device specific for details 0 1 read-write USCIARMP_0 P1.x is selected, please refer to device specific for details 0 USCIARMP_1 other port is selected, please refer to device specific for details 1 CS CS 384 CSCTL0 Clock System Control 0 0 16 65535 DCO DCO tap selection. These bits select the DCO tap and are modified automatically during FLL operation. 0 9 read-write MOD Modulation bit counter. These bits select the modulation pattern. All MOD bits are modified automatically during FLL operation. The DCO register value is incremented when the modulation bit counter rolls over from 31 to 0. If the modulation bit counter decrements from 0 to the maximum count, the DCO register value is also decreased. 9 5 read-write CSCTL1 Clock System Control 1 2 16 65535 DISMOD Modulation. This bit enables/disables the modulation. 0 1 read-write DISMOD_0 Modulation enabled 0 DISMOD_1 Modulation disabled 1 DCORSEL DCO Range Select 1 3 read-write DCORSEL_0 1 MHz 0 DCORSEL_1 2 MHz 1 DCORSEL_2 4 MHz 2 DCORSEL_3 8 MHz 3 DCORSEL_4 12 MHz 4 DCORSEL_5 16 MHz 5 DCORSEL_6 20 MHz(Only avaliable in 24MHz clock system) 6 DCORSEL_7 24 MHz(Only avaliable in 24MHz clock system) 7 DCOFTRIM DCO frequency trim. These bits trims the DCO frequency. By default, it is chipspecific trimmed. These bits can also be trimmed by user code. 4 3 read-write DCOFTRIMEN DCO Frequency Trim Enable. When this bit is set, DCOFTRIM value is selected to set DCO frequency. Otherwise, DCOFTRIM value is bypassed and DCO applies default settings in manufacture. 7 1 read-write DCOFTRIMEN_0 Disable frequency trim 0 DCOFTRIMEN_1 Enable frequency trim 1 CSCTL2 Clock System Control 2 4 16 65535 FLLN Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1. 0 10 read-write FLLD FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits. 12 3 read-write 1 fDCOCLK / 1 0 2 fDCOCLK / 2 1 4 fDCOCLK / 4 2 8 fDCOCLK / 8 3 16 fDCOCLK / 16 4 32 fDCOCLK / 32 5 FLLD_6 fDCOCLK / 40(Only avaliable in 24MHz clock system) 6 FLLD_7 fDCOCLK / 48(Only avaliable in 24MHz clock system) 7 CSCTL3 Clock System Control 3 6 16 65535 FLLREFDIV FLL reference divider. These bits define the divide factor for f(FLLREFCLK). If XT1 supports high frequency input higher than 32 kHz, the divided frequency is used as the FLL reference frequency. If XT1 only supports 32-kHz clock, FLLREFDIV is always read and written as zero, 000b = fFLLREFCLK / 1 0 3 read-write 1 fFLLREFCLK / 1 0 32 fFLLREFCLK / 32 1 64 fFLLREFCLK / 64 2 128 fFLLREFCLK / 128 3 256 fFLLREFCLK / 256 4 512 fFLLREFCLK / 512 5 FLLREFDIV_6 fFLLREFCLK / 640 (only available in 24MHz clock system) 6 FLLREFDIV_7 fFLLREFCLK / 768(only available in 24MHz clock system) 7 SELREF FLL reference select. These bits select the FLL reference clock source. 4 2 read-write XT1CLK XT1CLK 0 REFOCLK REFOCLK 1 SELREF_2 served for future use 2 SELREF_3 served for future use 3 REFOLP REFO Low Power Enable. This bit turns on REFO low-power mode. During switch, the low-power mode will be invalid until REFOREADY is set. 7 1 read-write REFOLP_0 REFO Low Power Disabled (High Power Mode) 0 REFOLP_1 REFO Low Power Enabled 1 CSCTL4 Clock System Control 4 8 16 65535 SELMS Selects the MCLK and SMCLK source 0 3 read-write DCOCLKDIV DCOCLKDIV 0 REFOCLK REFOCLK 1 XT1CLK XT1CLK 2 VLOCLK VLOCLK 3 SELMS_4 Reserved for future use 4 SELMS_5 Reserved for future use 5 SELMS_6 Reserved for future use 6 SELMS_7 Reserved for future use 7 SELA Selects the ACLK source 8 2 read-write XT1CLK XT1CLK with divider (must be no more than 40 kHz) 0 REFOCLK REFO (internal 32-kHz clock source) 1 VLOCLK VLO (internal 10-kHz clock source) 2 RESERVED Reserved 3 CSCTL5 Clock System Control 5 10 16 65535 DIVM MCLK source divider 0 3 read-write 1 /1 0 2 /2 1 4 /4 2 8 /8 3 16 /16 4 32 /32 5 64 /64 6 128 /128 7 DIVS SMCLK source divider. SMCLK directly derives from MCLK. SMCLK frequency is the combination of DIVM and DIVS out of selected clock source. 4 2 read-write 1 /1 0 2 /2 1 4 /4 2 8 /8 3 SMCLKOFF SMCLK off. This bit turns off SMCLK clock 8 1 read-write SMCLKOFF_0 SMCLK on 0 SMCLKOFF_1 SMCLK off 1 VLOAUTOOFF VLO automatic off enable. This bit turns off VLO, if VLO is not used. 12 1 read-write VLOAUTOOFF_0 VLO always on 0 VLOAUTOOFF_1 VLO automatically turned off if not used(default) 1 CSCTL6 Clock System Control 6 12 16 65535 XT1AUTOOFF XT1 automatic off enable. This bit allows XT1 turned turns off when it is not used 0 1 read-write XT1AUTOOFF_0 XT1 is on if XT1 is selected by the port selection and XT1 is not in bypass mode of operation. 0 XT1AUTOOFF_1 XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation. 1 XT1AGCOFF Automatic Gain Control (AGC) disable. 1 1 read-write XT1AGCOFF_0 AGC on 0 XT1AGCOFF_1 AGC off 1 XT1HFFREQ The XT1 High-frequency selection. These bits must be set to appropriate frequency for crystal or bypass modes of operation. 2 2 read-write XT1HFFREQ_0 1 to 4 MHz 0 XT1HFFREQ_1 4 MHz to 6 MHz 1 XT1HFFREQ_2 6 MHz to 16 MHz 2 XT1HFFREQ_3 16 MHz to 24 MHz 3 XT1BYPASS XT1 bypass select 4 1 read-write XT1BYPASS_0 XT1 source internally 0 XT1BYPASS_1 XT1 sources externally from pin 1 XTS XT1 mode select 5 1 read-write XTS_0 Low-frequency mode. 0 XTS_1 High-frequency mode. 1 XT1DRIVE The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. The configuration of these bits is retained during LPM3.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore, reconfiguration after wake-up from LPM3.5 before clearing LOCKLPM5 is required. 6 2 read-write XT1DRIVE_0 Lowest drive strength and current consumption 0 XT1DRIVE_1 Lower drive strength and current consumption 1 XT1DRIVE_2 Higher drive strength and current consumption 2 XT1DRIVE_3 Highest drive strength and current consumption 3 DIVA ACLK source divider. 8 4 read-write 1 /1 0 16 /16 1 32 /32 2 64 /64 3 128 /128 4 256 /256 5 384 /384 6 512 /512 7 768 /768(Only available in 24MHz clock system, 24 MHz preference) 8 1024 /1024(Only available in 24MHz clock system, 24 MHz preference) 9 108 /108(Only available in 24MHz clock system, 24 MHz preference) 10 338 338(Only available in 24MHz clock system, 24 MHz preference) 11 414 414(Only available in 24MHz clock system, 24 MHz preference) 12 640 640(Only available in 24MHz clock system, 24 MHz preference) 13 DIVA_14 Reserved 14 DIVA_15 Reserved 15 XT1FAULTOFF The XT1 oscillator fault detection off 13 1 read-write XT1FAULTOFF_0 Enabling XT1 fault to switch ACLK to REFO 0 XT1FAULTOFF_1 Disabling XT1 fault to switch ACLK to REFO 1 CSCTL7 Clock System Control Register 7 14 16 65535 REFOREADY REFO ready flag. This bit reflects the REFO readiness whent REFO is good for operation (such as FLL reference) 2 1 read-only REFOREADY_0 REFO unstable 0 REFOREADY_1 REFO ready to go 1 DCOFFG DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or DCO = {511}. DCOFFG can be cleared by software. If the DCO fault condition still remains, DCOFFG is set. As long as DCOFFG is set, FLLUNLOCK shows the DCOERROR condition. 0 1 read-write DCOFFG_0 No fault condition occurred after the last reset. 0 DCOFFG_1 DCO fault. A DCO fault occurred after the last reset. 1 XT1OFFG T1 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT1OFFG is set if a XT1 fault condition exists. XT1OFFG can be cleared by software. If the XT1 fault condition still remains, XT1OFFG is set. 1 1 read-write XT1OFFG_0 No fault condition occurred after the last reset. 0 XT1OFFG_1 XT1 fault. An XT1 fault occurred after the last reset. 1 FLLULIFG FLL unlock interrupt flag. This flag is set when FLLUNLOCK bits equal 10b (DCO too fast). If FLLULPUC is also set, a PUC is triggered when FLLUIFG is set. 4 1 read-write FLLULIFG_0 FLLUNLOCK bits not equal to 10b 0 FLLULIFG_1 FLLUNLOCK bits equal to 10b 1 ENSTFCNT1 Enable start counter for XT1. 6 1 read-write ENSTFCNT1_0 Startup fault counter disabled. Counter is cleared.. 0 ENSTFCNT1_1 Startup fault counter enabled. 1 FLLUNLOCK Unlock. These bits indicate the current FLL unlock condition. These bits are both set as long as the DCOFFG flag is set. 8 2 read-write FLLUNLOCK_0 FLL is locked. No unlock condition currently active. 0 FLLUNLOCK_1 DCOCLK is currently too slow. 1 FLLUNLOCK_2 DCOCLK is currently too fast. 2 FLLUNLOCK_3 DCOERROR. DCO out of range. 3 FLLUNLOCKHIS Unlock history bits. These bits indicate the FLL unlock condition history. As soon as any unlock condition happens, the respective bits are set and remain set until cleared by software by writing 0 to it or by a POR. 10 2 read-write FLLUNLOCKHIS_0 FLL is locked. No unlock situation has been detected since the last reset of these bits. 0 FLLUNLOCKHIS_1 DCOCLK has been too slow since the bits were cleared. 1 FLLUNLOCKHIS_2 DCOCLK has been too fast since the bits were cleared. 2 FLLUNLOCKHIS_3 DCOCLK has been both too fast and too slow since the bits were cleared. 3 FLLULPUC FLL unlock PUC enable. If the FLLULPUC bit is set, a reset (PUC) is triggered if FLLULIFG is set. FLLULIFG indicates when FLLUNLOCK bits equal 10 (too fast). FLLULPUC is automatically cleared upon servicing the event. If FLLULPUC is cleared (0), no PUC can be triggered by FLLULIFG. 12 1 read-write FLLWARNEN Warning enable. If this bit is set, an interrupt is generated based on the FLLUNLOCKHIS bits. If FLLUNLOCKHIS is not equal to 00, an OFIFG is generated. 13 1 read-write FLLWARNEN_0 FLLUNLOCKHIS status cannot set OFIFG. 0 FLLWARNEN_1 FLLUNLOCKHIS status can set OFIFG. 1 CSCTL8 Clock System Control Register 8 16 16 65535 ACLKREQEN ACLK clock request enable. Setting this enables conditional module requests for ACLK 0 1 read-write ACLKREQEN_0 ACLK conditional requests are disabled. 0 ACLKREQEN_1 ACLK conditional requests are enabled. 1 MCLKREQEN MCLK clock request enable. Setting this enables conditional module requests for MCLK 1 1 read-write MCLKREQEN_0 MCLK conditional requests are disabled. 0 MCLKREQEN_1 MCLK conditional requests are enabled. 1 SMCLKREQEN SMCLK clock request enable. Setting this enables conditional module requests for SMCLK 2 1 read-write SMCLKREQEN_0 SMCLK conditional requests are disabled. 0 SMCLKREQEN_1 SMCLK conditional requests are enabled. 1 MODOSCREQEN MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 3 1 read-write MODOSCREQEN_0 MODOSC conditional requests are disabled. 0 MODOSCREQEN_1 MODOSC conditional requests are enabled. 1 FRCTL FRCTL 416 FRCTL0 FRAM Controller Control Register 0 0 16 65535 NWAITS Wait state numbers 4 3 read-write NWAITS_0 FRAM wait states: 0 0 NWAITS_1 FRAM wait states: 1 1 NWAITS_2 FRAM wait states: 2 2 NWAITS_3 FRAM wait states: 3 3 NWAITS_4 FRAM wait states: 4 4 NWAITS_5 FRAM wait states: 5 5 NWAITS_6 FRAM wait states: 6 6 NWAITS_7 FRAM wait states: 7 7 FRCTLPW FRCTLPW password 8 8 read-write GCCTL0 General Control Register 0 4 16 65535 UBDRSTEN Enable Power Up Clear (PUC) reset for the uncorrectable bit error detection flag (UBDIFG) 7 1 read-write UBDRSTEN_0 PUC not initiated on uncorrectable bit error detection flag. 0 UBDRSTEN_1 PUC initiated on uncorrectable bit error detection flag. Generates vector in SYSRSTIV. Clear the UBDIE bit. 1 UBDIE Enable NMI event for the uncorrectable bit error detection flag (UBDIFG) 6 1 read-write UBDIE_0 Disable NMI for the uncorrectable bit error detection flag (UBDIFG). 0 UBDIE_1 Enable NMI for the uncorrectable bit error detection flag (UBDIFG). Generates vector in SYSSNIV. Clear the UBDRSTEN bit. 1 CBDIE Enable NMI event for the correctable bit error detection flag (CBDIFG) 5 1 read-write CBDIE_0 Disable NMI for the correctable bit error detection flag (CBDIFG). 0 CBDIE_1 Disable NMI for the correctable bit error detection flag (CBDIFG). Generates vector in SYSSNIV. 1 FRPWR FRAM Memory Power Control Request 2 1 read-write FRPWR_0 Enable INACTIVE mode. 0 FRPWR_1 Enable ACTIVE mode. 1 FRLPMPWR Enables FRAM auto power up after LPM 1 1 read-write FRLPMPWR_0 FRAM startup is delayed to the first FRAM access after exit from LPM 0 FRLPMPWR_1 FRAM is powered up immediately on exit from LPM 1 GCCTL1 General Control Register 1 6 16 65535 ACCTEIFG Access time error flag 3 1 read-write ACCTEIFG_0 No interrupt pending. 0 ACCTEIFG_1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV when it is the highest pending interrupt. 1 UBDIFG FRAM uncorrectable bit error detection flag 2 1 read-write UBDIFG_0 No interrupt pending. 0 UBDIFG_1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV when it is the highest pending interrupt. 1 CBDIFG FRAM correctable bit error detection flag 1 1 read-write CBDIFG_0 No interrupt is pending 0 CBDIFG_1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV if it is the highest pending interrupt. 1 CRC CRC 448 CRCDI CRC Data In 0 16 65535 CRCDIRB CRC Data In Reverse Byte 2 16 65535 CRCINIRES CRC Initialization and Result 4 16 65535 CRCRESR CRC Result Reverse 6 16 65535 WDT_A WDT_A 460 WDTCTL Watchdog Timer Control Register 0 16 65535 WDTIS Watchdog timer interval select 0 3 read-write 2G Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) 0 128M Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) 1 8192K Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) 2 512K Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) 3 32K Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) 4 8192 Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) 5 512 Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) 6 64 Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) 7 WDTCNTCL Watchdog timer counter clear 3 1 read-write WDTCNTCL_0 No action 0 WDTCNTCL_1 WDTCNT = 0000h 1 WDTTMSEL Watchdog timer mode select 4 1 read-write WDTTMSEL_0 Watchdog mode 0 WDTTMSEL_1 Interval timer mode 1 WDTSSEL Watchdog timer clock source select 5 2 read-write SMCLK SMCLK 0 ACLK ACLK 1 VLOCLK VLOCLK 2 BCLK BCLK 3 WDTHOLD Watchdog timer hold 7 1 read-write UNHOLD Watchdog timer is not stopped 0 HOLD Watchdog timer is stopped 1 WDTPW Watchdog timer password 8 8 read-write RTC RTC 768 RTCCTL RTCCTL0 Register 0 16 65535 RTCIFG Real-time interrupt flag. This bit reports the status of a pending interrupt. This read only bit can be cleared by reading RTCIV register. 0 1 read-only RTCIFG_0 No interrupt pending 0 RTCIFG_1 Interrupt pending 1 RTCIE Real-time interrupt enable 1 1 read-write RTCIE_0 Interrupt disabled 0 RTCIE_1 Interrupt enabled 1 RTCSR Real-time software reset. This is a write only bit and is always read with logic 0. 0b = Write 0 has no effect 6 1 read-write RTCSR_0 Write 0 has no effect 0 RTCSR_1 Write 1 to this bit clears the counter value and reloads the shadow register value from the modulo register at the next tick of the selected source clock. No overflow event or interrupt is generated. 1 RTCPS Real-time clock pre-divider select 8 3 read-write 1 /1 0 10 /10 1 100 /100 2 1000 /1000 3 16 /16 4 64 /64 5 256 /256 6 1024 /1024 7 RTCSS Real-time clock source select 12 2 read-write DISABLED Disabled 0 SMCLK SMCLK 1 XT1CLK XT1CLK 2 VLOCLK VLOCLK 3 RTCIV Real-Time Clock Interrupt Vector Register 4 16 65535 RTCIV Real-time clock interrupt vector value 0 16 read-only NONE No interrupt pending 0 RTCIFG upt Source: RTC Counter Overflow; Interrupt Flag: RTCIFG 2 RTCMOD RTC Counter Modulo Register 8 16 65535 RTCCNT RTC Counter Register 12 16 65535 TB0 TB0 896 TB0CTL Timer_B Control Register 0 16 65535 TBIFG TimerB interrupt flag 0 1 read-write TBIFG_0 No interrupt pending 0 TBIFG_1 Interrupt pending 1 TBIE TimerB interrupt enable 1 1 read-write TBIE_0 Interrupt disabled 0 TBIE_1 Interrupt enabled 1 TBCLR TimerB clear 2 1 read-write MC Mode control 4 2 read-write STOP Stop mode: Timer is halted 0 UP Up mode: Timer counts up to TBxCL0 1 CONTINUOUS Continuous mode: Timer counts up to the value set by CNTL 2 UPDOWN Up/down mode: Timer counts up to TBxCL0 then down to 0000h 3 ID Input divider 6 2 read-write 1 /1 0 2 /2 1 4 /4 2 8 /8 3 TBSSEL TimerB clock source select 8 2 read-write TBCLK TBxCLK 0 ACLK ACLK 1 SMCLK SMCLK 2 INCLK INCLK 3 CNTL Counter length 11 2 read-write 16 16-bit, TBxR(max) = 0FFFFh 0 12 12-bit, TBxR(max) = 0FFFh 1 10 10-bit, TBxR(max) = 03FFh 2 8 8-bit, TBxR(max) = 0FFh 3 TBCLGRP TBxCLn group 13 2 read-write TBCLGRP_0 Each TBxCLn latch loads independently 0 TBCLGRP_1 TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 independent 1 TBCLGRP_2 TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); TBxCL0 independent 2 TBCLGRP_3 TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD bits control the update) 3 TB0CCTL0 Timer_B Capture/Compare Control Register 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB0CCTL1 Timer_B Capture/Compare Control Register 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB0CCTL2 Timer_B Capture/Compare Control Register 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB0R Timer_B count register 16 16 65535 TB0CCR0 Timer_B Capture/Compare Register 18 16 65535 TB0CCR1 Timer_B Capture/Compare Register 20 16 65535 TB0CCR2 Timer_B Capture/Compare Register 22 16 65535 TB0EX0 Timer_Bx Expansion Register 0 32 16 65535 TBIDEX Input divider expansion 0 3 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 5 Divide by 5 4 6 Divide by 6 5 7 Divide by 7 6 8 Divide by 8 7 TB0IV Timer_Bx Interrupt Vector Register 46 16 65535 TBIV Timer_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 TBCCR1 Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 CCIFG; Interrupt Priority: Highest 2 TBCCR2 Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 CCIFG 4 TBCCR3 Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 CCIFG 6 TBCCR4 Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 CCIFG 8 TBCCR5 Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 CCIFG 10 TBCCR6 Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 12 TBIFG Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest 14 TB1 TB1 960 TB1CTL Timer_B Control Register 0 16 65535 TBIFG TimerB interrupt flag 0 1 read-write TBIFG_0 No interrupt pending 0 TBIFG_1 Interrupt pending 1 TBIE TimerB interrupt enable 1 1 read-write TBIE_0 Interrupt disabled 0 TBIE_1 Interrupt enabled 1 TBCLR TimerB clear 2 1 read-write MC Mode control 4 2 read-write STOP Stop mode: Timer is halted 0 UP Up mode: Timer counts up to TBxCL0 1 CONTINUOUS Continuous mode: Timer counts up to the value set by CNTL 2 UPDOWN Up/down mode: Timer counts up to TBxCL0 then down to 0000h 3 ID Input divider 6 2 read-write 1 /1 0 2 /2 1 4 /4 2 8 /8 3 TBSSEL TimerB clock source select 8 2 read-write TBCLK TBxCLK 0 ACLK ACLK 1 SMCLK SMCLK 2 INCLK INCLK 3 CNTL Counter length 11 2 read-write 16 16-bit, TBxR(max) = 0FFFFh 0 12 12-bit, TBxR(max) = 0FFFh 1 10 10-bit, TBxR(max) = 03FFh 2 8 8-bit, TBxR(max) = 0FFh 3 TBCLGRP TBxCLn group 13 2 read-write TBCLGRP_0 Each TBxCLn latch loads independently 0 TBCLGRP_1 TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 independent 1 TBCLGRP_2 TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); TBxCL0 independent 2 TBCLGRP_3 TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD bits control the update) 3 TB1CCTL0 Timer_B Capture/Compare Control Register 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB1CCTL1 Timer_B Capture/Compare Control Register 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB1CCTL2 Timer_B Capture/Compare Control Register 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB1R Timer_B count register 16 16 65535 TB1CCR0 Timer_B Capture/Compare Register 18 16 65535 TB1CCR1 Timer_B Capture/Compare Register 20 16 65535 TB1CCR2 Timer_B Capture/Compare Register 22 16 65535 TB1EX0 Timer_Bx Expansion Register 0 32 16 65535 TBIDEX Input divider expansion 0 3 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 5 Divide by 5 4 6 Divide by 6 5 7 Divide by 7 6 8 Divide by 8 7 TB1IV Timer_Bx Interrupt Vector Register 46 16 65535 TBIV Timer_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 TBCCR1 Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 CCIFG; Interrupt Priority: Highest 2 TBCCR2 Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 CCIFG 4 TBCCR3 Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 CCIFG 6 TBCCR4 Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 CCIFG 8 TBCCR5 Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 CCIFG 10 TBCCR6 Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 12 TBIFG Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest 14 TB2 TB2 1024 TB2CTL Timer_B Control Register 0 16 65535 TBIFG TimerB interrupt flag 0 1 read-write TBIFG_0 No interrupt pending 0 TBIFG_1 Interrupt pending 1 TBIE TimerB interrupt enable 1 1 read-write TBIE_0 Interrupt disabled 0 TBIE_1 Interrupt enabled 1 TBCLR TimerB clear 2 1 read-write MC Mode control 4 2 read-write STOP Stop mode: Timer is halted 0 UP Up mode: Timer counts up to TBxCL0 1 CONTINUOUS Continuous mode: Timer counts up to the value set by CNTL 2 UPDOWN Up/down mode: Timer counts up to TBxCL0 then down to 0000h 3 ID Input divider 6 2 read-write 1 /1 0 2 /2 1 4 /4 2 8 /8 3 TBSSEL TimerB clock source select 8 2 read-write TBCLK TBxCLK 0 ACLK ACLK 1 SMCLK SMCLK 2 INCLK INCLK 3 CNTL Counter length 11 2 read-write 16 16-bit, TBxR(max) = 0FFFFh 0 12 12-bit, TBxR(max) = 0FFFh 1 10 10-bit, TBxR(max) = 03FFh 2 8 8-bit, TBxR(max) = 0FFh 3 TBCLGRP TBxCLn group 13 2 read-write TBCLGRP_0 Each TBxCLn latch loads independently 0 TBCLGRP_1 TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 independent 1 TBCLGRP_2 TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); TBxCL0 independent 2 TBCLGRP_3 TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD bits control the update) 3 TB2CCTL0 Timer_B Capture/Compare Control Register 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB2CCTL1 Timer_B Capture/Compare Control Register 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB2CCTL2 Timer_B Capture/Compare Control Register 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB2R Timer_B count register 16 16 65535 TB2CCR0 Timer_B Capture/Compare Register 18 16 65535 TB2CCR1 Timer_B Capture/Compare Register 20 16 65535 TB2CCR2 Timer_B Capture/Compare Register 22 16 65535 TB2EX0 Timer_Bx Expansion Register 0 32 16 65535 TBIDEX Input divider expansion 0 3 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 5 Divide by 5 4 6 Divide by 6 5 7 Divide by 7 6 8 Divide by 8 7 TB2IV Timer_Bx Interrupt Vector Register 46 16 65535 TBIV Timer_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 TBCCR1 Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 CCIFG; Interrupt Priority: Highest 2 TBCCR2 Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 CCIFG 4 TBCCR3 Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 CCIFG 6 TBCCR4 Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 CCIFG 8 TBCCR5 Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 CCIFG 10 TBCCR6 Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 12 TBIFG Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest 14 TB3 TB3 1088 TB3CTL Timer_B Control Register 0 16 65535 TBIFG TimerB interrupt flag 0 1 read-write TBIFG_0 No interrupt pending 0 TBIFG_1 Interrupt pending 1 TBIE TimerB interrupt enable 1 1 read-write TBIE_0 Interrupt disabled 0 TBIE_1 Interrupt enabled 1 TBCLR TimerB clear 2 1 read-write MC Mode control 4 2 read-write STOP Stop mode: Timer is halted 0 UP Up mode: Timer counts up to TBxCL0 1 CONTINUOUS Continuous mode: Timer counts up to the value set by CNTL 2 UPDOWN Up/down mode: Timer counts up to TBxCL0 then down to 0000h 3 ID Input divider 6 2 read-write 1 /1 0 2 /2 1 4 /4 2 8 /8 3 TBSSEL TimerB clock source select 8 2 read-write TBCLK TBxCLK 0 ACLK ACLK 1 SMCLK SMCLK 2 INCLK INCLK 3 CNTL Counter length 11 2 read-write 16 16-bit, TBxR(max) = 0FFFFh 0 12 12-bit, TBxR(max) = 0FFFh 1 10 10-bit, TBxR(max) = 03FFh 2 8 8-bit, TBxR(max) = 0FFh 3 TBCLGRP TBxCLn group 13 2 read-write TBCLGRP_0 Each TBxCLn latch loads independently 0 TBCLGRP_1 TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 independent 1 TBCLGRP_2 TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); TBxCL0 independent 2 TBCLGRP_3 TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD bits control the update) 3 TB3CCTL0 Timer_B Capture/Compare Control Register 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3CCTL1 Timer_B Capture/Compare Control Register 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3CCTL2 Timer_B Capture/Compare Control Register 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3CCTL3 Timer_B Capture/Compare Control Register 8 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3CCTL4 Timer_B Capture/Compare Control Register 10 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3CCTL5 Timer_B Capture/Compare Control Register 12 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3CCTL6 Timer_B Capture/Compare Control Register 14 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 1 1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 2 1 read-write LOW Output low 0 HIGH Output high 1 CCI Capture/compare input 3 1 read-only CCIE Capture/compare interrupt enable 4 1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 5 3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 8 1 read-write COMPARE Compare mode 0 CAPTURE Capture mode 1 CLLD Compare latch load 9 2 read-write CLLD_0 TBxCLn loads on write to TBxCCRn 0 CLLD_1 TBxCLn loads when TBxR counts to 0 1 CLLD_2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). 2 CLLD_3 TBxCLn loads when TBxR counts to TBxCLn 3 SCS Synchronize capture source 11 1 read-write ASYNC Asynchronous capture 0 SYNC Synchronous capture 1 CCIS Capture/compare input select 12 2 read-write CCIA CCIxA 0 CCIB CCIxB 1 GND GND 2 VCC VCC 3 CM Capture mode 14 2 read-write NONE No capture 0 RISING Capture on rising edge 1 FALLING Capture on falling edge 2 BOTH Capture on both rising and falling edges 3 TB3R Timer_B count register 16 16 65535 TB3CCR0 Timer_B Capture/Compare Register 18 16 65535 TB3CCR1 Timer_B Capture/Compare Register 20 16 65535 TB3CCR2 Timer_B Capture/Compare Register 22 16 65535 TB3CCR3 Timer_B Capture/Compare Register 24 16 65535 TB3CCR4 Timer_B Capture/Compare Register 26 16 65535 TB3CCR5 Timer_B Capture/Compare Register 28 16 65535 TB3CCR6 Timer_B Capture/Compare Register 30 16 65535 TB3EX0 Timer_Bx Expansion Register 0 32 16 65535 TBIDEX Input divider expansion 0 3 read-write 1 Divide by 1 0 2 Divide by 2 1 3 Divide by 3 2 4 Divide by 4 3 5 Divide by 5 4 6 Divide by 6 5 7 Divide by 7 6 8 Divide by 8 7 TB3IV Timer_Bx Interrupt Vector Register 46 16 65535 TBIV Timer_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 TBCCR1 Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 CCIFG; Interrupt Priority: Highest 2 TBCCR2 Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 CCIFG 4 TBCCR3 Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 CCIFG 6 TBCCR4 Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 CCIFG 8 TBCCR5 Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 CCIFG 10 TBCCR6 Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG 12 TBIFG Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest 14 MPY32 MPY32 1216 MPY 16-bit operand one multiply 0 16 65535 MPYS 16-bit operand one signed multiply 2 16 65535 MAC 16-bit operand one multiply accumulate 4 16 65535 MACS 16-bit operand one signed multiply accumulate 6 16 65535 OP2 16-bit operand two 8 16 65535 RESLO 16x16-bit result low word 10 16 65535 RESHI 16x16-bit result high word 12 16 65535 SUMEXT 16x16-bit sum extension register 14 16 65535 MPY32L 32-bit operand 1 multiply low word 16 16 65535 MPY32H 32-bit operand 1 multiply high word 18 16 65535 MPYS32L 32-bit operand 1 signed multiply low word 20 16 65535 MPYS32H 32-bit operand 1 signed multiply high word 22 16 65535 MAC32L 32-bit operand 1 multiply accumulate low word 24 16 65535 MAC32H 32-bit operand 1 multiply accumulate high word 26 16 65535 MACS32L 32-bit operand 1 signed multiply accumulate low word 28 16 65535 MACS32H 32-bit operand 1 signed multiply accumulate high word 30 16 65535 MACS32H 32-bit operand 1 signed multiply accumulate high word 8 8 read-write OP2L 32-bit operand 2 low word 32 16 65535 OP2H 32-bit operand 2 high word 34 16 65535 RES0 32x32-bit result 0 least significant word 36 16 65535 RES1 32x32-bit result 1 38 16 65535 RES2 32x32-bit result 2 40 16 65535 RES3 32x32-bit result 3 most significant word 42 16 65535 MPY32CTL0 MPY32 control register 0 44 16 65535 MPYDLY32 Delayed write mode. 9 1 read-write MPYDLY32_0 Writes are delayed until 64-bit result (RES0 to RES3) is available. 0 MPYDLY32_1 Writes are delayed until 32-bit result (RES0 to RES1) is available. 8 MPYDLYWRTEN 1 MPYDLYWRTEN Delayed write enable. 8 1 read-write MPYDLYWRTEN_0 Writes are not delayed. 0 MPYDLYWRTEN_1 Writes are delayed. 1 MPYOP2_32 Multiplier bit width of operand 2 7 1 read-write 16 16 bits. 0 32 32 bits. 1 MPYOP1_32 Multiplier bit width of operand 1 6 1 read-write 16 16 bits. 0 32 32 bits. 1 MPYM Multiplier mode 4 2 read-write MPY MPY Multiply 0 MPYS MPYS Signed multiply 1 MAC MAC Multiply accumulate 2 MACS MACS Signed multiply accumulate 3 MPYSAT Saturation mode 3 1 read-write DISABLE Saturation mode disabled. 0 ENABLE Saturation mode enabled. 1 MPYFRAC Fractional mode. 2 1 read-write DISABLE Fractional mode disabled. 0 ENABLE Fractional mode enabled. 1 MPYC Carry of the multiplier 0 1 read-write MPYC_0 No carry for result. 0 MPYC_1 Result has a carry. 1 E_USCI_A0 eUSCI_A0 1280 UCA0CTLW0 eUSCI_Ax Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_A reset released for operation 0 ENABLE Enabled. eUSCI_A logic held in reset state 1 UCTXBRK Transmit break 1 1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCTXADDR Transmit address 2 1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCDORM Dormant 3 1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCBRKIE Receive break character interrupt enable 4 1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCRXEIE Receive erroneous-character interrupt enable 5 1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCLK UCLK 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI_A mode 9 2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCSPB Stop bit select 11 1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UC7BIT Character length 12 1 read-write 8BIT 8-bit data 0 7BIT 7-bit data 1 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 14 1 read-write ODD Odd parity 0 EVEN Even parity 1 UCPEN Parity enable 15 1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCA0CTLW0_SPI eUSCI_Ax Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_A reset released for operation 0 ENABLE Enabled. eUSCI_A logic held in reset state 1 UCSTEM STE mode select in master mode. 1 1 read-write UCSTEM_0 STE pin is used to prevent conflicts with other masters 0 UCSTEM_1 STE pin is used to generate the enable signal for a 4-wire slave 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCSSEL_0 Reserved 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 1 UCMODE_2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write SLAVE Slave mode 0 MASTER Master mode 1 UC7BIT Character length 12 1 read-write 8BIT 8-bit data 0 7BIT 7-bit data 1 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCCKPL Clock polarity select 14 1 read-write LOW The inactive state is low 0 HIGH The inactive state is high 1 UCCKPH Clock phase select 15 1 read-write UCCKPH_0 Data is changed on the first UCLK edge and captured on the following edge. 0 UCCKPH_1 Data is captured on the first UCLK edge and changed on the following edge. 1 UCA0CTLW0 UCA0CTLW1 eUSCI_Ax Control Word Register 1 2 16 65535 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCA0BRW eUSCI_Ax Baud Rate Control Word Register 6 16 65535 UCA0BRW_SPI eUSCI_Ax Bit Rate Control Register 1 6 16 65535 UCA0BRW UCA0MCTLW eUSCI_Ax Modulation Control Word Register 8 16 65535 UCOS16 Oversampling mode enabled 0 1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCBRF First modulation stage select 4 4 read-write UCBRS Second modulation stage select 8 8 read-write UCA0STATW eUSCI_Ax Status Register 10 16 65535 UCBUSY eUSCI_A busy 0 1 read-only IDLE eUSCI_A inactive 0 BUSY eUSCI_A transmitting or receiving 1 UCADDR_UCIDLE Address received / Idle line detected 1 1 read-write UCADDR_UCIDLE_0 UCADDR: Received character is data. UCIDLE: No idle line detected 0 UCADDR_UCIDLE_1 UCADDR: Received character is an address. UCIDLE: Idle line detected 1 UCRXERR Receive error flag 2 1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCBRK Break detect flag 3 1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 4 1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCA0STATW_SPI UCA0STATW_SPI 10 16 65535 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Bus conflict occurred 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCA0STATW UCA0RXBUF eUSCI_Ax Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCA0RXBUF_SPI eUSCI_Ax Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCA0RXBUF UCA0TXBUF eUSCI_Ax Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCA0TXBUF_SPI eUSCI_Ax Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCA0TXBUF UCA0ABCTL eUSCI_Ax Auto Baud Rate Control Register 16 16 65535 UCABDEN Automatic baud-rate detect enable 0 1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 2 1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCSTOE Synch field time out error 3 1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCDELIM Break/synch delimiter length 4 2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCA0IRCTL eUSCI_Ax IrDA Control Word Register 18 16 65535 UCIREN IrDA encoder/decoder enable 0 1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRTXCLK IrDA transmit pulse clock select 1 1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 2 6 read-write UCIRRXFE IrDA receive filter enabled 8 1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXPL IrDA receive input UCAxRXD polarity 9 1 read-write HIGH IrDA transceiver delivers a high pulse when a light pulse is seen 0 LOW IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRRXFL Receive filter length 10 6 read-write UCA0IE eUSCI_Ax Interrupt Enable Register 26 16 65535 UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 3 1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCA0IE_SPI eUSCI_Ax Interrupt Enable Register 26 16 65535 UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCA0IE UCA0IFG eUSCI_Ax Interrupt Flag Register 28 16 65535 UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 3 1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCA0IFG_SPI eUSCI_Ax Interrupt Flag Register 28 16 65535 UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCA0IFG UCA0IV eUSCI_Ax Interrupt Vector Register 30 16 65535 UCIV eUSCI_A interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCRXIFG Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCTXIFG Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG 4 UCSTTIFG Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 6 UCTXCPTIFG Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 8 UCA0IV_SPI eUSCI_Ax Interrupt Vector Register 30 16 65535 UCIV eUSCI_A interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCRXIFG Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCTXIFG Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 4 UCA0IV E_USCI_B0 eUSCI_B0 1344 UCB0CTLW0 eUSCI_Bx Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_B reset released for operation 0 ENABLE Enabled. eUSCI_B logic held in reset state 1 UCTXSTT Transmit START condition in master mode 1 1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCTXSTP Transmit STOP condition in master mode 2 1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXNACK Transmit a NACK 3 1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTR Transmitter/receiver 4 1 read-write RX Receiver 0 TX Transmitter 1 UCTXACK Transmit ACK condition in slave mode 5 1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCLKI UCLKI 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI_B mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write SLAVE Slave mode 0 MASTER Master mode 1 UCMM Multi-master environment select 13 1 read-write SINGLE Single master environment. There is no other master in the system. The address compare unit is disabled. 0 MULTI Multi-master environment 1 UCSLA10 Slave addressing mode select 14 1 read-write 7BIT Address slave with 7-bit address 0 10BIT Address slave with 10-bit address 1 UCA10 Own addressing mode select 15 1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCB0CTLW0_SPI eUSCI_Bx Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_B reset released for operation 0 ENABLE Enabled. eUSCI_B logic held in reset state 1 UCSTEM STE mode select in master mode. 1 1 read-write UCSTEM_0 STE pin is used to prevent conflicts with other masters 0 UCSTEM_1 STE pin is used to generate the enable signal for a 4-wire slave 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCSSEL_0 Reserved 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 1 UCMODE_2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write SLAVE Slave mode 0 MASTER Master mode 1 UC7BIT Character length 12 1 read-write 8BIT 8-bit data 0 7BIT 7-bit data 1 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCCKPL Clock polarity select 14 1 read-write LOW The inactive state is low 0 HIGH The inactive state is high 1 UCCKPH Clock phase select 15 1 read-write UCCKPH_0 Data is changed on the first UCLK edge and captured on the following edge. 0 UCCKPH_1 Data is captured on the first UCLK edge and changed on the following edge. 1 UCB0CTLW0 UCB0CTLW1 eUSCI_Bx Control Word Register 1 2 16 65535 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCASTP Automatic STOP condition generation 2 2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCASTP_3 Reserved 3 UCSWACK SW or HW ACK control 4 1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCSTPNACK ACK all master bytes 5 1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCCLTO Clock low timeout select 6 2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 8 1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCB0BRW eUSCI_Bx Baud Rate Control Word Register 6 16 65535 UCB0BRW_SPI eUSCI_Bx Bit Rate Control Register 1 6 16 65535 UCB0BRW UCB0STATW eUSCI_Bx Status Register 8 16 65535 UCBBUSY Bus busy 4 1 read-only IDLE Bus inactive 0 BUSY Bus busy 1 UCGC General call address received 5 1 read-only UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 6 1 read-only UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBCNT Hardware byte counter value 8 8 read-only UCB0STATW_SPI UCB0STATW_SPI 8 16 65535 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Bus conflict occurred 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCBxTXD is internally fed back to the receiver 1 UCB0STATW UCB0TBCNT eUSCI_Bx Byte Counter Threshold Register 10 16 65535 UCTBCNT Byte counter threshold value 0 8 read-write UCB0RXBUF eUSCI_Bx Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCB0RXBUF_SPI eUSCI_Bx Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCB0RXBUF UCB0TXBUF eUSCI_Bx Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCB0TXBUF_SPI eUSCI_Bx Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCB0TXBUF UCB0I2COA0 eUSCI_Bx I2C Own Address 0 Register 20 16 65535 I2COA0 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA0 is disabled 0 ENABLE The slave address defined in I2COA0 is enabled 1 UCGCEN General call response enable 15 1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCB0I2COA1 eUSCI_Bx I2C Own Address 1 Register 22 16 65535 I2COA1 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA1 is disabled 0 ENABLE The slave address defined in I2COA1 is enabled 1 UCB0I2COA2 eUSCI_Bx I2C Own Address 2 Register 24 16 65535 I2COA2 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA2 is disabled 0 ENABLE The slave address defined in I2COA2 is enabled 1 UCB0I2COA3 eUSCI_Bx I2C Own Address 3 Register 26 16 65535 I2COA3 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA3 is disabled 0 ENABLE The slave address defined in I2COA3 is enabled 1 UCB0ADDRX eUSCI_Bx I2C Received Address Register 28 16 65535 ADDRX Received Address Register 0 10 read-only UCB0ADDMASK eUSCI_Bx I2C Address Mask Register 30 16 65535 ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0 10 read-write UCB0I2CSA eUSCI_Bx I2C Slave Address Register 32 16 65535 I2CSA I2C slave address 0 10 read-write UCB0IE eUSCI_Bx Interrupt Enable Register 42 16 65535 UCRXIE0 Receive interrupt enable 0 0 1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 1 1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 3 1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCALIE Arbitration lost interrupt enable 4 1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 5 1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 6 1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 7 1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 8 1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 9 1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 10 1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 11 1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 12 1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 13 1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 14 1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCB0IE_SPI eUSCI_Bx Interrupt Enable Register 42 16 65535 UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCB0IE UCB0IFG eUSCI_Bx Interrupt Flag Register 44 16 65535 UCRXIFG0 eUSCI_B receive interrupt flag 0 0 1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 1 1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 3 1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCALIFG Arbitration lost interrupt flag 4 1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 5 1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 6 1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 7 1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 8 1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 9 1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 10 1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 11 1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 12 1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 13 1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 14 1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCB0IFG_SPI eUSCI_Bx Interrupt Flag Register 44 16 65535 UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCB0IFG UCB0IV eUSCI_Bx Interrupt Vector Register 46 16 65535 UCIV eUSCI_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCALIFG Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest 2 UCNACKIFG Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG 4 UCSTTIFG Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 6 UCSTPIFG Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG 8 UCRXIFG3 Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 10 UCTXIFG3 Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 12 UCRXIFG2 Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 14 UCTXIFG2 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 16 UCRXIFG1 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 18 UCTXIFG1 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 20 UCRXIFG0 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 22 UCTXIFG0 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 24 UCBCNTIFG Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG 26 UCCLTOIFG Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 28 UCBIT9IFG Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 30 UCB0IV_SPI eUSCI_Bx Interrupt Vector Register 46 16 65535 UCIV eUSCI_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCRXIFG Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCTXIFG Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 4 UCB0IV E_USCI_A1 eUSCI_A1 1408 UCA1CTLW0 eUSCI_Ax Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_A reset released for operation 0 ENABLE Enabled. eUSCI_A logic held in reset state 1 UCTXBRK Transmit break 1 1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCTXADDR Transmit address 2 1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCDORM Dormant 3 1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCBRKIE Receive break character interrupt enable 4 1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCRXEIE Receive erroneous-character interrupt enable 5 1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCLK UCLK 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI_A mode 9 2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCSPB Stop bit select 11 1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UC7BIT Character length 12 1 read-write 8BIT 8-bit data 0 7BIT 7-bit data 1 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 14 1 read-write ODD Odd parity 0 EVEN Even parity 1 UCPEN Parity enable 15 1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCA1CTLW0_SPI eUSCI_Ax Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_A reset released for operation 0 ENABLE Enabled. eUSCI_A logic held in reset state 1 UCSTEM STE mode select in master mode. 1 1 read-write UCSTEM_0 STE pin is used to prevent conflicts with other masters 0 UCSTEM_1 STE pin is used to generate the enable signal for a 4-wire slave 1 UCSSEL eUSCI_A clock source select 6 2 read-write UCSSEL_0 Reserved 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 1 UCMODE_2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write SLAVE Slave mode 0 MASTER Master mode 1 UC7BIT Character length 12 1 read-write 8BIT 8-bit data 0 7BIT 7-bit data 1 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCCKPL Clock polarity select 14 1 read-write LOW The inactive state is low 0 HIGH The inactive state is high 1 UCCKPH Clock phase select 15 1 read-write UCCKPH_0 Data is changed on the first UCLK edge and captured on the following edge. 0 UCCKPH_1 Data is captured on the first UCLK edge and changed on the following edge. 1 UCA1CTLW0 UCA1CTLW1 eUSCI_Ax Control Word Register 1 2 16 65535 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCA1BRW eUSCI_Ax Baud Rate Control Word Register 6 16 65535 UCA1BRW_SPI eUSCI_Ax Bit Rate Control Register 1 6 16 65535 UCA1BRW UCA1MCTLW eUSCI_Ax Modulation Control Word Register 8 16 65535 UCOS16 Oversampling mode enabled 0 1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCBRF First modulation stage select 4 4 read-write UCBRS Second modulation stage select 8 8 read-write UCA1STATW eUSCI_Ax Status Register 10 16 65535 UCBUSY eUSCI_A busy 0 1 read-only IDLE eUSCI_A inactive 0 BUSY eUSCI_A transmitting or receiving 1 UCADDR_UCIDLE Address received / Idle line detected 1 1 read-write UCADDR_UCIDLE_0 UCADDR: Received character is data. UCIDLE: No idle line detected 0 UCADDR_UCIDLE_1 UCADDR: Received character is an address. UCIDLE: Idle line detected 1 UCRXERR Receive error flag 2 1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCBRK Break detect flag 3 1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 4 1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCA1STATW_SPI UCA1STATW_SPI 10 16 65535 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Bus conflict occurred 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCA1STATW UCA1RXBUF eUSCI_Ax Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCA1RXBUF_SPI eUSCI_Ax Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCA1RXBUF UCA1TXBUF eUSCI_Ax Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCA1TXBUF_SPI eUSCI_Ax Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCA1TXBUF UCA1ABCTL eUSCI_Ax Auto Baud Rate Control Register 16 16 65535 UCABDEN Automatic baud-rate detect enable 0 1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 2 1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCSTOE Synch field time out error 3 1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCDELIM Break/synch delimiter length 4 2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCA1IRCTL eUSCI_Ax IrDA Control Word Register 18 16 65535 UCIREN IrDA encoder/decoder enable 0 1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRTXCLK IrDA transmit pulse clock select 1 1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 2 6 read-write UCIRRXFE IrDA receive filter enabled 8 1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXPL IrDA receive input UCAxRXD polarity 9 1 read-write HIGH IrDA transceiver delivers a high pulse when a light pulse is seen 0 LOW IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRRXFL Receive filter length 10 6 read-write UCA1IE eUSCI_Ax Interrupt Enable Register 26 16 65535 UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 3 1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCA1IE_SPI eUSCI_Ax Interrupt Enable Register 26 16 65535 UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCA1IE UCA1IFG eUSCI_Ax Interrupt Flag Register 28 16 65535 UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 3 1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCA1IFG_SPI eUSCI_Ax Interrupt Flag Register 28 16 65535 UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCA1IFG UCA1IV eUSCI_Ax Interrupt Vector Register 30 16 65535 UCIV eUSCI_A interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCRXIFG Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCTXIFG Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG 4 UCSTTIFG Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 6 UCTXCPTIFG Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 8 UCA1IV_SPI eUSCI_Ax Interrupt Vector Register 30 16 65535 UCIV eUSCI_A interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCRXIFG Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCTXIFG Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 4 UCA1IV E_USCI_B1 eUSCI_B1 1472 UCB1CTLW0 eUSCI_Bx Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_B reset released for operation 0 ENABLE Enabled. eUSCI_B logic held in reset state 1 UCTXSTT Transmit START condition in master mode 1 1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCTXSTP Transmit STOP condition in master mode 2 1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXNACK Transmit a NACK 3 1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTR Transmitter/receiver 4 1 read-write RX Receiver 0 TX Transmitter 1 UCTXACK Transmit ACK condition in slave mode 5 1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCLKI UCLKI 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI_B mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write SLAVE Slave mode 0 MASTER Master mode 1 UCMM Multi-master environment select 13 1 read-write SINGLE Single master environment. There is no other master in the system. The address compare unit is disabled. 0 MULTI Multi-master environment 1 UCSLA10 Slave addressing mode select 14 1 read-write 7BIT Address slave with 7-bit address 0 10BIT Address slave with 10-bit address 1 UCA10 Own addressing mode select 15 1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCB1CTLW0_SPI eUSCI_Bx Control Word Register 0 0 16 65535 UCSWRST Software reset enable 0 1 read-write DISABLE Disabled. eUSCI_B reset released for operation 0 ENABLE Enabled. eUSCI_B logic held in reset state 1 UCSTEM STE mode select in master mode. 1 1 read-write UCSTEM_0 STE pin is used to prevent conflicts with other masters 0 UCSTEM_1 STE pin is used to generate the enable signal for a 4-wire slave 1 UCSSEL eUSCI_B clock source select 6 2 read-write UCSSEL_0 Reserved 0 ACLK ACLK 1 SMCLK SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 8 1 read-write ASYNC Asynchronous mode 0 SYNC Synchronous mode 1 UCMODE eUSCI mode 9 2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 1 UCMODE_2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 2 UCMODE_3 I2C mode 3 UCMST Master mode select 11 1 read-write SLAVE Slave mode 0 MASTER Master mode 1 UC7BIT Character length 12 1 read-write 8BIT 8-bit data 0 7BIT 7-bit data 1 UCMSB MSB first select 13 1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCCKPL Clock polarity select 14 1 read-write LOW The inactive state is low 0 HIGH The inactive state is high 1 UCCKPH Clock phase select 15 1 read-write UCCKPH_0 Data is changed on the first UCLK edge and captured on the following edge. 0 UCCKPH_1 Data is captured on the first UCLK edge and changed on the following edge. 1 UCB1CTLW0 UCB1CTLW1 eUSCI_Bx Control Word Register 1 2 16 65535 UCGLIT Deglitch time 0 2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCASTP Automatic STOP condition generation 2 2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCASTP_3 Reserved 3 UCSWACK SW or HW ACK control 4 1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCSTPNACK ACK all master bytes 5 1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCCLTO Clock low timeout select 6 2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 8 1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCB1BRW eUSCI_Bx Baud Rate Control Word Register 6 16 65535 UCB1BRW_SPI eUSCI_Bx Bit Rate Control Register 1 6 16 65535 UCB1BRW UCB1STATW eUSCI_Bx Status Register 8 16 65535 UCBBUSY Bus busy 4 1 read-only IDLE Bus inactive 0 BUSY Bus busy 1 UCGC General call address received 5 1 read-only UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 6 1 read-only UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBCNT Hardware byte counter value 8 8 read-only UCB1STATW_SPI UCB1STATW_SPI 8 16 65535 UCOE Overrun error flag 5 1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 6 1 read-write UCFE_0 No error 0 UCFE_1 Bus conflict occurred 1 UCLISTEN Listen enable 7 1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCBxTXD is internally fed back to the receiver 1 UCB1STATW UCB1TBCNT eUSCI_Bx Byte Counter Threshold Register 10 16 65535 UCTBCNT Byte counter threshold value 0 8 read-write UCB1RXBUF eUSCI_Bx Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCB1RXBUF_SPI eUSCI_Bx Receive Buffer Register 12 16 65535 UCRXBUF Receive data buffer 0 8 read-only UCB1RXBUF UCB1TXBUF eUSCI_Bx Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCB1TXBUF_SPI eUSCI_Bx Transmit Buffer Register 14 16 65535 UCTXBUF Transmit data buffer 0 8 read-write UCB1TXBUF UCB1I2COA0 eUSCI_Bx I2C Own Address 0 Register 20 16 65535 I2COA0 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA0 is disabled 0 ENABLE The slave address defined in I2COA0 is enabled 1 UCGCEN General call response enable 15 1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCB1I2COA1 eUSCI_Bx I2C Own Address 1 Register 22 16 65535 I2COA1 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA1 is disabled 0 ENABLE The slave address defined in I2COA1 is enabled 1 UCB1I2COA2 eUSCI_Bx I2C Own Address 2 Register 24 16 65535 I2COA2 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA2 is disabled 0 ENABLE The slave address defined in I2COA2 is enabled 1 UCB1I2COA3 eUSCI_Bx I2C Own Address 3 Register 26 16 65535 I2COA3 I2C own address 0 10 read-write UCOAEN Own Address enable register 10 1 read-write DISABLE The slave address defined in I2COA3 is disabled 0 ENABLE The slave address defined in I2COA3 is enabled 1 UCB1ADDRX eUSCI_Bx I2C Received Address Register 28 16 65535 ADDRX Received Address Register 0 10 read-only UCB1ADDMASK eUSCI_Bx I2C Address Mask Register 30 16 65535 ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0 10 read-write UCB1I2CSA eUSCI_Bx I2C Slave Address Register 32 16 65535 I2CSA I2C slave address 0 10 read-write UCB1IE eUSCI_Bx Interrupt Enable Register 42 16 65535 UCRXIE0 Receive interrupt enable 0 0 1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 1 1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 2 1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 3 1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCALIE Arbitration lost interrupt enable 4 1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 5 1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 6 1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 7 1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 8 1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 9 1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 10 1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 11 1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 12 1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 13 1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 14 1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCB1IE_SPI eUSCI_Bx Interrupt Enable Register 42 16 65535 UCRXIE Receive interrupt enable 0 1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 1 1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCB1IE UCB1IFG eUSCI_Bx Interrupt Flag Register 44 16 65535 UCRXIFG0 eUSCI_B receive interrupt flag 0 0 1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 1 1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 2 1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 3 1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCALIFG Arbitration lost interrupt flag 4 1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 5 1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 6 1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 7 1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 8 1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 9 1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 10 1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 11 1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 12 1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 13 1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 14 1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCB1IFG_SPI eUSCI_Bx Interrupt Flag Register 44 16 65535 UCRXIFG Receive interrupt flag 0 1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 1 1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCB1IFG UCB1IV eUSCI_Bx Interrupt Vector Register 46 16 65535 UCIV eUSCI_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCALIFG Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest 2 UCNACKIFG Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG 4 UCSTTIFG Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 6 UCSTPIFG Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG 8 UCRXIFG3 Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 10 UCTXIFG3 Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 12 UCRXIFG2 Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 14 UCTXIFG2 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 16 UCRXIFG1 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 18 UCTXIFG1 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 20 UCRXIFG0 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 22 UCTXIFG0 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 24 UCBCNTIFG Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG 26 UCCLTOIFG Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 28 UCBIT9IFG Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 30 UCB1IV_SPI eUSCI_Bx Interrupt Vector Register 46 16 65535 UCIV eUSCI_B interrupt vector value 0 16 read-only NONE No interrupt pending 0 UCRXIFG Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCTXIFG Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 4 UCB1IV BKMEM BKMEM 1632 BAKMEM0 Backup Memory registers. Backup Memory 0. 0 16 65535 BAKMEM1 Backup Memory 1. 2 16 65535 BAKMEM2 Backup Memory 2. 4 16 65535 BAKMEM3 Backup Memory 3. 6 16 65535 BAKMEM4 Backup Memory 4. 8 16 65535 BAKMEM5 Backup Memory 5. 10 16 65535 BAKMEM6 Backup Memory 6. 12 16 65535 BAKMEM7 Backup Memory 7. 14 16 65535 BAKMEM8 Backup Memory 8. 16 16 65535 BAKMEM9 Backup Memory 9. 18 16 65535 BAKMEM10 Backup Memory registers. Backup Memory 10. 20 16 65535 BAKMEM11 Backup Memory 11. 22 16 65535 BAKMEM12 Backup Memory 12. 24 16 65535 BAKMEM13 Backup Memory 13. 26 16 65535 BAKMEM14 Backup Memory 14. 28 16 65535 BAKMEM15 Backup Memory 15. 30 16 65535 ICC ICC 1728 ICCSC ICCSC 0 16 65535 ICMC Current Interrupt Compare Mask of virtual stack specifies the current ICM at the top of virtual stack If ICM[1:0] is less than the priority level (ILSRx[1:0]) of the new interrupt, the corresponding source is sent to the CPU. Note that the ICMC is the element stack that the stack pointer is pointing to. 0 2 read-only VSFFLG Virtual stack full flag This bit indicates whether or not the virtual stack is full. It is automatically updated when the stack is pushed or popped. 4 1 read-only VSFFLG_0 ICCMVS register is not full 0 VSFFLG_1 ICCMVS register is full 1 VSEFLG Virtual stack empty flag.This bit indicates whether or not the virtual stack is empty. It is automatically updated when the stack is pushed or popped. 5 1 read-only VSEFLG_0 Stack has valid data 0 VSEFLG_1 Stack has no valid data 1 ICCEN ICC enable 7 1 read-write ICCEN_0 ICC module disabled 0 ICCEN_1 ICC module enabled 1 ICCMVS ICCMVS 2 16 65535 ICM0 Interrupt compare mask virtual stack position 0 This field is the virtual stack register for ICM0. 0 2 read-only ICM1 Interrupt compare mask virtual stack position 1 This field is the virtual stack register for ICM1. 2 2 read-only ICM3 Interrupt compare mask virtual stack position 3 This field is the virtual stack register for ICM3. 6 2 read-only MVSSP MVS stack pointer indicate register 8 3 read-only MVSSP_0 000b = Stack empty 0 MVSSP_1 001b = ICM0 affected 1 MVSSP_2 010b = ICM0 and ICM1 affected 2 MVSSP_3 011b = ICM0, ICM1, and ICM2 affected 3 MVSSP_4 100b = ICM0, ICM1, ICM2, and ICM3 affected. Also means the stack is full. 4 ICM2 Interrupt compare mask virtual stack position 2 This field is the virtual stack register for ICM2. 4 2 read-only ICCILSR0 ICCILSR0 4 16 65535 ILSR0 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 0 2 read-write ILSR1 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 2 2 read-write ILSR2 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 4 2 read-write ILSR3 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 6 2 read-write ILSR4 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 8 2 read-write ILSR5 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 10 2 read-write ILSR6 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 12 2 read-write ILSR7 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit. 14 2 read-write ICCILSR1 ICCILSR1 6 16 65535 ILSR8 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 0 2 read-write ILSR9 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 2 2 read-write ILSR10 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 4 2 read-write ILSR11 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit 6 2 read-write ILSR12 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 8 2 read-write ILSR13 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 10 2 read-write ILSR14 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 12 2 read-write ILSR15 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 14 2 read-write ICCILSR2 ICCILSR2 8 16 65535 ILSR16 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 0 2 read-write ILSR17 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit 2 2 read-write ILSR18 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 4 2 read-write ILSR19 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 6 2 read-write ILSR20 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 8 2 read-write ILSR21 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 10 2 read-write ILSR22 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each 12 2 read-write ILSR23 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each 14 2 read-write ICCILSR3 ICCILSR3 10 16 65535 ILSR24 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 0 2 read-write ILSR25 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 2 2 read-write ILSR26 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 4 2 read-write ILSR27 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 6 2 read-write ILSR28 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 8 2 read-write ILSR29 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 10 2 read-write ILSR30 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 12 2 read-write ILSR31 Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit. 14 2 read-write ADC ADC 1792 ADCCTL0 ADC Control 0 0 16 65535 ADCSC start conversion 0 1 read-write ADCSC_0 No sample-and-conversion-start 0 ADCSC_1 Start sample-and-conversion 1 ADCENC enable conversion 1 1 read-write ADCENC_0 ADC disabled 0 ADCENC_1 ADC enabled 1 ADCON ADC on 4 1 read-write ADCON_0 ADC off 0 ADCON_1 ADC on 1 ADCMSC sample-and-hold time. 7 1 read-write ADCMSC_0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert. 0 ADCMSC_1 The incidence of a positive(or for devices first rising edge of the) SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed. 1 ADCSHT sample-and-hold time. 8 4 read-write ADCSHT_0 4 ADCCLK cycles 0 ADCSHT_1 8 ADCCLK cycles 1 ADCSHT_2 16 ADCCLK cycles 2 ADCSHT_3 32 ADCCLK cycles 3 ADCSHT_4 64 ADCCLK cycles 4 ADCSHT_5 96 ADCCLK cycles 5 ADCSHT_6 128 ADCCLK cycles 6 ADCSHT_7 192 ADCCLK cycles 7 ADCSHT_8 256 ADCCLK cycles 8 ADCSHT_9 384 ADCCLK cycles 9 ADCSHT_10 512 ADCCLK cycles 10 ADCSHT_11 768 ADCCLK cycles 11 ADCSHT_12 1024 ADCCLK cycles 12 ADCSHT_13 1024 ADCCLK cycles 13 ADCSHT_14 1024 ADCCLK cycles 14 ADCSHT_15 1024 ADCCLK cycles 15 ADCCTL1 ADC Control 1 2 16 65535 ADCBUSY ADC busy 0 1 read-only ADCBUSY_0 No operation is active. 0 ADCBUSY_1 A sequence, sample, or conversion is active. 1 ADCCONSEQ conversion sequence mode select 1 2 read-write ADCCONSEQ_0 Single-channel, single-conversion 0 ADCCONSEQ_1 Sequence-of-channels 1 ADCCONSEQ_2 Repeat-single-channel 2 ADCCONSEQ_3 Repeat-sequence-of-channels 3 ADCSSEL clock source select 3 2 read-write ADCSSEL_0 ADCOSC (MODOSC) 0 ADCSSEL_1 ACLK 1 ADCSSEL_2 MCLK 2 ADCSSEL_3 SMCLK 3 ADCDIV clock divider 5 3 read-write ADCDIV_0 /1 0 ADCDIV_1 /2 1 ADCDIV_2 /3 2 ADCDIV_3 /4 3 ADCDIV_4 /5 4 ADCDIV_5 /6 5 ADCDIV_6 /7 6 ADCDIV_7 /8 7 ADCISSH invert signal sample-and-hold 8 1 read-write ADCISSH_0 The sample-input signal is not inverted. 0 ADCISSH_1 The sample-input signal is inverted. 1 ADCSHP sample-and-hold pulse-mode select 9 1 read-write ADCSHP_0 SAMPCON signal is sourced from the sample-input signal. 0 ADCSHP_1 SAMPCON signal is sourced from the sampling timer. 1 ADCSHS sample-and-hold source select 10 2 read-write ADCSHS_0 ADCSC bit 0 ADCSHS_1 see the device-specific data sheet for source 1 ADCSHS_2 see the device-specific data sheet for source 2 ADCSHS_3 see the device-specific data sheet for source 3 ADCCTL2 ADC Control 2 4 16 65535 ADCDF data read-back format 3 1 read-write ADCDF_0 Binary unsigned. Theoretically the analog input voltage V(REF) results in 0000h, the analog input voltage +V(REF) results in 03FFh. 0 ADCDF_1 Signed binary (2s complement), left aligned. Theoretically the analog input voltage V(REF) results in 8000h, the analog input voltage +V(REF) results in 7FC0h. 1 ADCRES resolution 4 2 read-write ADCRES_0 8 bit 0 ADCRES_1 10 bit 1 ADCRES_2 12 bit 2 ADCRES_3 Reserved 3 ADCSR ADC sampling rate. 2 1 read-write ADCPDIV ADC predivider. This bit predivides the selected ADC clock source before it gets divided again using ADCDIVx. 8 2 read-write 1 Predivide by 1 0 4 Predivide by 4 1 64 Predivide by 64 2 ADCPDIV_3 Reserved 3 ADCLO ADC Window Comparator Low Threshold Register 6 16 65535 ADCHI ADC Window Comparator High Threshold Register 8 16 65535 ADCMCTL0 ADC Conversion Memory Control Register 10 16 65535 ADCINCH Input channel select 0 4 read-write ADCINCH_0 A0 - see device-specific data sheet 0 ADCINCH_1 A1 - see device-specific data sheet 1 ADCINCH_2 A2 - see device-specific data sheet 2 ADCINCH_3 A3 - see device-specific data sheet 3 ADCINCH_4 A4 - see device-specific data sheet 4 ADCINCH_5 A5 - see device-specific data sheet 5 ADCINCH_6 A2 - see device-specific data sheet 6 ADCINCH_7 A7 - see device-specific data sheet 7 ADCINCH_8 A8 - see device-specific data sheet 8 ADCINCH_9 A9 - see device-specific data sheet 9 ADCINCH_10 A10 - see device-specific data sheet 10 ADCINCH_11 A11 - see device-specific data sheet 11 ADCINCH_12 A12 - see device-specific data sheet 12 ADCINCH_13 A13 - see device-specific data sheet 13 ADCINCH_14 A14 - see device-specific data sheet 14 ADCINCH_15 A15 - see device-specific data sheet 15 ADCSREF Select reference. It is not recommended to change this setting while a conversion is ongoing. Can be modified only when ADCENC = 0. Resetting ADCENC = 0 by software and changing these fields immediately shows an effect when a conversion is active. 4 3 read-write ADCSREF_0 000b = V(R+) = AVCC and V(R-) = AVSS 0 ADCSREF_1 001b = V(R+) = VREF and V(R-) = AVSS 1 ADCSREF_2 010b = V(R+) = VEREF+ buffered and V(R-) = AVSS 2 ADCSREF_3 011b =V(R+) = VEREF+ and V(R-) = AVSS 3 ADCSREF_4 100b = V(R+) = AVCC and V(R-) = VEREF- 4 ADCSREF_5 101b = V(R+) = VREF and V(R-) = VEREF- 5 ADCSREF_6 110b = V(R+) = VEREF+ buffered and V(R-) = VEREF- 6 ADCSREF_7 111b = V(R+) = VEREF+ and V(R-) = VEREF- 7 EXPCHEN ADC input channels expanded 8 1 read-write EXPCHEN_0 ADC channel expanded disable 0 EXPCHEN_1 ADC channel expanded enable 1 ADCMEM0 ADC Conversion Memory Register 18 16 65535 ADCIE ADC Interrupt Enable 0 26 16 65535 ADCIE0 Interrupt enable. This bits enable or disable the interrupt request for a completed ADC conversion. 0 1 read-write ADCIE0_0 0b = Interrupt disabled 0 ADCIE0_1 1b = Interrupt enabled 1 ADCINIE Interrupt enable for the inside of window interrupt of the window comparator. 1 1 read-write ADCINIE_0 0b = Inside of window interrupt disabled 0 ADCINIE_1 1b = Inside of window interrupt enabled 1 ADCLOIE Interrupt enable for the below lower threshold interrupt of the window comparator. 2 1 read-write ADCLOIE_0 0b = Below lower threshold interrupt disabled 0 ADCLOIE_1 1b = Below lower threshold interrupt enabled 1 ADCHIIE Interrupt enable for the above upper threshold interrupt of the window comparator. 3 1 read-write ADCHIIE_0 0b = Above upper threshold interrupt disabled 0 ADCHIIE_1 1b = Above upper threshold interrupt enabled 1 ADCOVIE ADCMEM0 overflow interrupt enable. 4 1 read-write ADCOVIE_0 0b = Overflow interrupt disabled 0 ADCOVIE_1 1b = Overflow interrupt enabled 1 ADCTOVIE ADC conversion-time-overflow interrupt enable. 5 1 read-write ADCTOVIE_0 0b = Conversion time overflow interrupt disabled 0 ADCTOVIE_1 1b = Conversion time overflow interrupt enabled 1 ADCIFG ADC Interrupt Flag 28 16 65535 ADCIFG0 ADCMEM0 interrupt flag 0 1 read-write ADCIFG0_0 No interrupt pending 0 ADCIFG0_1 Interrupt pending 1 ADCINIFG The ADCINIFG is set when the result of the current ADC conversion is within the thresholds defined by the window comparator threshold registers. 1 1 read-write ADCINIFG_0 No interrupt pending 0 ADCINIFG_1 Interrupt pending 1 ADCLOIFG The ADCLOIFG is set when the result of the current ADC conversion is below the lower threshold defined by the window comparator lower threshold register. 2 1 read-write ADCLOIFG_0 No interrupt pending 0 ADCLOIFG_1 Interrupt pending 1 ADCHIIFG The ADCHIIFG is set when the result of the current ADC conversion is greater than the upper threshold defined by the window comparator upper threshold register. 3 1 read-write ADCHIIFG_0 No interrupt pending 0 ADCHIIFG_1 Interrupt pending 1 ADCOVIFG The ADCOVIFG is set when the ADCMEM0 register is written before the last conversion result has been read. 4 1 read-write ADCOVIFG_0 No interrupt pending 0 ADCOVIFG_1 Interrupt pending 1 ADCTOVIFG The ADCTOVIFG is set when an ADC conversion is triggered before the actual conversion has completed. 5 1 read-write ADCOVIFG_0 No interrupt pending 0 ADCTOVIFG_1 Interrupt pending 1 ADCIV ADC Interrupt Vector 30 16 65535 ADCIV interrupt vector value 0 16 read-write NONE No interrupt pending 0 ADCOVIFG Interrupt Source: ADCMEM0 overflow; Interrupt Flag: ADCOVIFG; Interrupt Priority: Highest 2 ADCTOVIFG Interrupt Source: Conversion time overflow; Interrupt Flag: ADCTOVIFG 4 ADCHIIFG Interrupt Source: ADCHI Interrupt flag; Interrupt Flag: ADCHIIFG 6 ADCLOIFG Interrupt Source: ADCLO Interrupt flag; Interrupt Flag: ADCLOIFG 8 ADCINIFG nterrupt Source: ADCIN Interrupt flag; Interrupt Flag: ADCINIFG 10 ADCIFG0 Interrupt Source: ADC memory Interrupt flag; Interrupt Flag: ADCIFG0; Interrupt Priority: Lowest 12 E_COMP0 eCOMP0 2272 CPCTL0 Comparator Control Register 0 0 16 65535 CPPEN Channel input enable for the V+ terminal 4 1 read-write CPPEN_0 Selected analog input channel for V+ terminal is disabled. 0 CPPEN_1 Selected analog input channel for V+ terminal is enabled. 1 CPNSEL Channel input selected for the - terminal 8 3 read-write CPNSEL_0 select external input source 0 CPNSEL_1 select external input source 1 CPNSEL_2 select external input source 2 CPNSEL_3 select external input source 3 CPNSEL_4 device specific, please refer to device data sheet for details 4 CPNSEL_5 device specific, please refer to device data sheet for details 5 CPNSEL_6 6-bit DAC 6 CPNSEL_7 Reserved 7 CPNEN Channel input enable for the - terminal 12 1 read-write CPNEN_0 Selected analog input channel for V- terminal is disabled. 0 CPNEN_1 Selected analog input channel for V- terminal is enabled. 1 CPPSEL Channel input selected for the V+ terminal 0 3 read-write CPPSEL_0 select external input source 0 CPPSEL_1 select external input source 1 CPPSEL_2 select external input source 2 CPPSEL_3 select external input source 3 CPPSEL_4 device specific, please refer to device data sheet for details 4 CPPSEL_5 device specific, please refer to device data sheet for details 5 CPPSEL_6 6-bit DAC 6 CPPSEL_7 Reserved 7 CPCTL1 Comparator Control Register 1 2 16 65535 CPOUT Comparator output value 0 1 read-only CPINV Comparator output polarity 1 1 read-write CPINV_0 Comparator output is non-inverted 0 CPINV_1 Comparator output is inverted 1 CPIES Interrupt edge select for CEIIFG and CEIFG 4 1 read-write CPIES_0 Rising edge for CPIFG, falling edge for CPIIFG 0 CPIES_1 Falling edge for CPIFG, rising edge for CPIIFG 1 CPFLT Analog Output Low Pass filter Selection. Changing CPFLT might set interrupt flag. 5 1 read-write CPFLT_0 Comparator output is not filtered 0 CPFLT_1 Comparator output is filtered 1 CPFLTDLY Analog Filter Delay selection. These bits are used to select the analog filter delay 6 2 read-write CPFLTDLY_0 Typical filter delay of 450ns 0 CPFLTDLY_1 Typical filter delay of 900ns 1 CPFLTDLY_2 Typical filter delay of 1800ns 2 CPFLTDLY_3 Typical filter delay of 3600ns 3 CPMSEL Power mode selection. 8 1 read-write CPMSEL_0 High-power & High speed mode (500nA) 0 CPMSEL_1 Low-power & Low speed mode (10nA) 1 CPEN Comparator enable/disable. This bit is used to disable/enable the comparator. When the comparator is disabled, the Comparator consumes no power. 9 1 read-write CPEN_0 Comparator is disabled 0 CPEN_1 Comparator is enabled 1 CPHSEL Programable Hysteresis mode. These bits are used to select the Hysteresis mode. 10 2 read-write CPHSEL_0 disable 0 CPHSEL_1 10mV 1 CPHSEL_2 20mV 2 CPHSEL_3 30mV 3 CPIE Comparator interrupt output enable bit 14 1 read-write CPIE_0 Interrupt output is disabled 0 CPIE_1 Interrupt output is enabled 1 CPIIE Comparator inverted interrupt output enable bit 15 1 read-write CPIIE_0 Interrupt inverted output is disabled 0 CPIIE_1 Interrupt inverted output is enabled 1 CPINT Comparator Interrupt Control Register 6 16 65535 CPIFG Comparator output interrupt flag 0 1 read-write CPIFG_0 No interrupt pending. 0 CPIFG_1 Output interrupt pending. 1 CPIIFG Comparator output inverted interrupt flag 1 1 read-write CPIIFG_0 No interrupt pending. 0 CPIIFG_1 Output interrupt pending. 1 CPIV Comparator Interrupt Vector Word Register 8 16 65535 CPIV Comparator interrupt vector word register 0 16 read-only NONE No interrupt pending 0 CPIFG CPIFG 2 CPIIFG CPIIFG 4 CPDACCTL 6-bit Comparator built-in DAC Control Register 16 16 65535 CPDACSW This bit is only valid when CPDACBUFS is set to 1. 0 1 read-write CPDACSW_0 CPDACBUF1 selected 0 CPDACSW_1 CPDACBUF2 selected 1 CPDACBUFS Comparator built-in DAC buffer controlled source selection. 1 1 read-write CPDACBUFS_0 Comparator output is selected as the buffer control source 0 CPDACBUFS_1 CPDACSW bit is selected as the buffer control source 1 CPDACREFS Comparator built-in DAC reference voltage selection 2 1 read-write CPDACREFS_0 VDD selected 0 CPDACREFS_1 on-chip VREF selected 1 CPDACEN Comparator built-in DAC output control bit. 7 1 read-write CPDACEN_0 DAC output is disabled. 0 CPDACEN_1 DAC output is enabled. 1 CPDACDATA 6-bit Comparator built-in DAC Data Register 18 16 65535 CPDACBUF1 1st 6-bit DAC buffer Data 0 6 read-write CPDACBUF1_0 0v 0 CPDACBUF1_1 selected reference voltage * 1/64 1 CPDACBUF1_2 selected reference voltage * 2/64 2 CPDACBUF1_3 selected reference voltage * 3/64 3 CPDACBUF1_4 selected reference voltage * 4/64 4 CPDACBUF1_5 selected reference voltage * 5/64 5 CPDACBUF1_6 selected reference voltage * 6/64 6 CPDACBUF1_7 selected reference voltage * 7/64 7 CPDACBUF1_8 selected reference voltage * 8/64 8 CPDACBUF1_9 selected reference voltage *9/64 9 CPDACBUF1_10 selected reference voltage * 10/64 10 CPDACBUF1_11 selected reference voltage * 11/64 11 CPDACBUF1_12 selected reference voltage * 12/64 12 CPDACBUF1_13 selected reference voltage * 13/64 13 CPDACBUF1_14 selected reference voltage * 14/64 14 CPDACBUF1_15 selected reference voltage * 15/64 15 CPDACBUF1_16 selected reference voltage * 16/64 16 CPDACBUF1_17 selected reference voltage * 17/64 17 CPDACBUF1_18 selected reference voltage * 18/64 18 CPDACBUF1_19 selected reference voltage * 19/64 19 CPDACBUF1_20 selected reference voltage * 20/64 20 CPDACBUF1_21 selected reference voltage * 21/64 21 CPDACBUF1_22 selected reference voltage * 22/64 22 CPDACBUF1_23 selected reference voltage * 23/64 23 CPDACBUF1_24 selected reference voltage * 24/64 24 CPDACBUF1_25 selected reference voltage * 25/64 25 CPDACBUF1_26 selected reference voltage * 26/64 26 CPDACBUF1_27 selected reference voltage * 27/64 27 CPDACBUF1_28 selected reference voltage * 28/64 28 CPDACBUF1_29 selected reference voltage * 29/64 29 CPDACBUF1_30 selected reference voltage * 30/64 30 CPDACBUF1_31 selected reference voltage * 31/64 31 CPDACBUF1_32 selected reference voltage * 32/64 32 CPDACBUF1_33 selected reference voltage * 33/64 33 CPDACBUF1_34 selected reference voltage * 34/64 34 CPDACBUF1_35 selected reference voltage * 35/64 35 CPDACBUF1_36 selected reference voltage * 36/64 36 CPDACBUF1_37 selected reference voltage * 37/64 37 CPDACBUF1_38 selected reference voltage * 38/64 38 CPDACBUF1_39 selected reference voltage * 39/64 39 CPDACBUF1_40 selected reference voltage * 40/64 40 CPDACBUF1_41 selected reference voltage * 41/64 41 CPDACBUF1_42 selected reference voltage * 42/64 42 CPDACBUF1_43 selected reference voltage * 43/64 43 CPDACBUF1_44 selected reference voltage * 44/64 44 CPDACBUF1_45 selected reference voltage * 45/64 45 CPDACBUF1_46 selected reference voltage * 46/64 46 CPDACBUF1_47 selected reference voltage * 47/64 47 CPDACBUF1_48 selected reference voltage * 48/64 48 CPDACBUF1_49 selected reference voltage * 49/64 49 CPDACBUF1_50 selected reference voltage * 50/64 50 CPDACBUF1_51 selected reference voltage * 51/64 51 CPDACBUF1_52 selected reference voltage * 52/64 52 CPDACBUF1_53 selected reference voltage * 53/64 53 CPDACBUF1_54 selected reference voltage * 54/64 54 CPDACBUF1_55 selected reference voltage * 55/64 55 CPDACBUF1_56 selected reference voltage * 56/64 56 CPDACBUF1_57 selected reference voltage * 57/64 57 CPDACBUF1_58 selected reference voltage * 58/64 58 CPDACBUF1_59 selected reference voltage * 59/64 59 CPDACBUF1_60 selected reference voltage * 60/64 60 CPDACBUF1_61 selected reference voltage * 61/64 61 CPDACBUF1_62 selected reference voltage * 62/64 62 CPDACBUF1_63 selected reference voltage * 63/64 63 CPDACBUF2 2nd 6-bit DAC buffer Data 8 6 read-write CPDACBUF2_0 0v 0 CPDACBUF2_1 selected reference voltage * 1/64 1 CPDACBUF2_2 selected reference voltage * 2/64 2 CPDACBUF2_3 selected reference voltage * 3/64 3 CPDACBUF2_4 selected reference voltage * 4/64 4 CPDACBUF2_5 selected reference voltage * 5/64 5 CPDACBUF2_6 selected reference voltage * 6/64 6 CPDACBUF2_7 selected reference voltage * 7/64 7 CPDACBUF2_8 selected reference voltage * 8/64 8 CPDACBUF2_9 selected reference voltage * 9/64 9 CPDACBUF2_10 selected reference voltage * 10/64 10 CPDACBUF2_11 selected reference voltage * 11/64 11 CPDACBUF2_12 selected reference voltage * 12/64 12 CPDACBUF2_13 selected reference voltage * 13/64 13 CPDACBUF2_14 selected reference voltage * 14/64 14 CPDACBUF2_15 selected reference voltage * 15/64 15 CPDACBUF2_16 selected reference voltage * 16/64 16 CPDACBUF2_17 selected reference voltage * 17/64 17 CPDACBUF2_18 selected reference voltage * 18/64 18 CPDACBUF2_19 selected reference voltage * 19/64 19 CPDACBUF2_20 selected reference voltage * 20/64 20 CPDACBUF2_21 selected reference voltage * 21/64 21 CPDACBUF2_22 selected reference voltage * 22/64 22 CPDACBUF2_23 selected reference voltage * 23/64 23 CPDACBUF2_24 selected reference voltage * 24/64 24 CPDACBUF2_25 selected reference voltage * 25/64 25 CPDACBUF2_26 selected reference voltage * 26/64 26 CPDACBUF2_27 selected reference voltage * 27/64 27 CPDACBUF2_28 selected reference voltage * 28/64 28 CPDACBUF2_29 selected reference voltage * 29/64 29 CPDACBUF2_30 selected reference voltage * 30/64 30 CPDACBUF2_31 selected reference voltage * 31/64 31 CPDACBUF2_32 selected reference voltage * 32/64 32 CPDACBUF2_33 selected reference voltage * 33/64 33 CPDACBUF2_34 selected reference voltage * 34/64 34 CPDACBUF2_35 selected reference voltage * 35/64 35 CPDACBUF2_36 selected reference voltage * 36/64 36 CPDACBUF2_37 selected reference voltage * 37/64 37 CPDACBUF2_38 selected reference voltage * 38/64 38 CPDACBUF2_39 selected reference voltage * 39/64 39 CPDACBUF2_40 selected reference voltage * 40/64 40 CPDACBUF2_41 selected reference voltage * 41/64 41 CPDACBUF2_42 selected reference voltage * 42/64 42 CPDACBUF2_43 selected reference voltage * 43/64 43 CPDACBUF2_44 selected reference voltage * 44/64 44 CPDACBUF2_45 selected reference voltage * 45/64 45 CPDACBUF2_46 selected reference voltage * 46/64 46 CPDACBUF2_47 selected reference voltage * 47/64 47 CPDACBUF2_48 selected reference voltage * 48/64 48 CPDACBUF2_49 selected reference voltage * 49/64 49 CPDACBUF2_50 selected reference voltage * 50/64 50 CPDACBUF2_51 selected reference voltage * 51/64 51 CPDACBUF2_52 selected reference voltage * 52/64 52 CPDACBUF2_53 selected reference voltage * 53/64 53 CPDACBUF2_54 selected reference voltage * 54/64 54 CPDACBUF2_55 selected reference voltage * 55/64 55 CPDACBUF2_56 selected reference voltage * 56/64 56 CPDACBUF2_57 selected reference voltage * 57/64 57 CPDACBUF2_58 selected reference voltage * 58/64 58 CPDACBUF2_59 selected reference voltage * 59/64 59 CPDACBUF2_60 selected reference voltage * 60/64 60 CPDACBUF2_61 selected reference voltage * 61/64 61 CPDACBUF2_62 selected reference voltage * 62/64 62 CPDACBUF2_63 selected reference voltage * 63/64 63 E_COMP1 eCOMP1 2304 CP1CTL0 Comparator Control Register 0 0 16 65535 CPPEN Channel input enable for the V+ terminal 4 1 read-write CPPEN_0 Selected analog input channel for V+ terminal is disabled. 0 CPPEN_1 Selected analog input channel for V+ terminal is enabled. 1 CPNSEL Channel input selected for the - terminal 8 3 read-write CPNSEL_0 select external input source 0 CPNSEL_1 select external input source 1 CPNSEL_2 select external input source 2 CPNSEL_3 select external input source 3 CPNSEL_4 device specific, please refer to device data sheet for details 4 CPNSEL_5 device specific, please refer to device data sheet for details 5 CPNSEL_6 6-bit DAC 6 CPNSEL_7 Reserved 7 CPNEN Channel input enable for the - terminal 12 1 read-write CPNEN_0 Selected analog input channel for V- terminal is disabled. 0 CPNEN_1 Selected analog input channel for V- terminal is enabled. 1 CPPSEL Channel input selected for the V+ terminal 0 3 read-write CPPSEL_0 select external input source 0 CPPSEL_1 select external input source 1 CPPSEL_2 select external input source 2 CPPSEL_3 select external input source 3 CPPSEL_4 device specific, please refer to device data sheet for details 4 CPPSEL_5 device specific, please refer to device data sheet for details 5 CPPSEL_6 6-bit DAC 6 CPPSEL_7 Reserved 7 CP1CTL1 Comparator Control Register 1 2 16 65535 CPOUT Comparator output value 0 1 read-only CPINV Comparator output polarity 1 1 read-write CPINV_0 Comparator output is non-inverted 0 CPINV_1 Comparator output is inverted 1 CPIES Interrupt edge select for CEIIFG and CEIFG 4 1 read-write CPIES_0 Rising edge for CPIFG, falling edge for CPIIFG 0 CPIES_1 Falling edge for CPIFG, rising edge for CPIIFG 1 CPFLT Analog Output Low Pass filter Selection. Changing CPFLT might set interrupt flag. 5 1 read-write CPFLT_0 Comparator output is not filtered 0 CPFLT_1 Comparator output is filtered 1 CPFLTDLY Analog Filter Delay selection. These bits are used to select the analog filter delay 6 2 read-write CPFLTDLY_0 Typical filter delay of 450ns 0 CPFLTDLY_1 Typical filter delay of 900ns 1 CPFLTDLY_2 Typical filter delay of 1800ns 2 CPFLTDLY_3 Typical filter delay of 3600ns 3 CPMSEL Power mode selection. 8 1 read-write CPMSEL_0 High-power & High speed mode (500nA) 0 CPMSEL_1 Low-power & Low speed mode (10nA) 1 CPEN Comparator enable/disable. This bit is used to disable/enable the comparator. When the comparator is disabled, the Comparator consumes no power. 9 1 read-write CPEN_0 Comparator is disabled 0 CPEN_1 Comparator is enabled 1 CPHSEL Programable Hysteresis mode. These bits are used to select the Hysteresis mode. 10 2 read-write CPHSEL_0 disable 0 CPHSEL_1 10mV 1 CPHSEL_2 20mV 2 CPHSEL_3 30mV 3 CPIE Comparator interrupt output enable bit 14 1 read-write CPIE_0 Interrupt output is disabled 0 CPIE_1 Interrupt output is enabled 1 CPIIE Comparator inverted interrupt output enable bit 15 1 read-write CPIIE_0 Interrupt inverted output is disabled 0 CPIIE_1 Interrupt inverted output is enabled 1 CP1INT Comparator Interrupt Control Register 6 16 65535 CPIFG Comparator output interrupt flag 0 1 read-write CPIFG_0 No interrupt pending. 0 CPIFG_1 Output interrupt pending. 1 CPIIFG Comparator output inverted interrupt flag 1 1 read-write CPIIFG_0 No interrupt pending. 0 CPIIFG_1 Output interrupt pending. 1 CP1IV Comparator Interrupt Vector Word Register 8 16 65535 CPIV Comparator interrupt vector word register 0 16 read-only NONE No interrupt pending 0 CPIFG CPIFG 2 CPIIFG CPIIFG 4 CP1DACCTL 6-bit Comparator built-in DAC Control Register 16 16 65535 CPDACSW This bit is only valid when CPDACBUFS is set to 1. 0 1 read-write CPDACSW_0 CPDACBUF1 selected 0 CPDACSW_1 CPDACBUF2 selected 1 CPDACBUFS Comparator built-in DAC buffer controlled source selection. 1 1 read-write CPDACBUFS_0 Comparator output is selected as the buffer control source 0 CPDACBUFS_1 CPDACSW bit is selected as the buffer control source 1 CPDACREFS Comparator built-in DAC reference voltage selection 2 1 read-write CPDACREFS_0 VDD selected 0 CPDACREFS_1 on-chip VREF selected 1 CPDACEN Comparator built-in DAC output control bit. 7 1 read-write CPDACEN_0 DAC output is disabled. 0 CPDACEN_1 DAC output is enabled. 1 CP1DACDATA 6-bit Comparator built-in DAC Data Register 18 16 65535 CPDACBUF1 1st 6-bit DAC buffer Data 0 6 read-write CPDACBUF1_0 0v 0 CPDACBUF1_1 selected reference voltage * 1/64 1 CPDACBUF1_2 selected reference voltage * 2/64 2 CPDACBUF1_3 selected reference voltage * 3/64 3 CPDACBUF1_4 selected reference voltage * 4/64 4 CPDACBUF1_5 selected reference voltage * 5/64 5 CPDACBUF1_6 selected reference voltage * 6/64 6 CPDACBUF1_7 selected reference voltage * 7/64 7 CPDACBUF1_8 selected reference voltage * 8/64 8 CPDACBUF1_9 selected reference voltage *9/64 9 CPDACBUF1_10 selected reference voltage * 10/64 10 CPDACBUF1_11 selected reference voltage * 11/64 11 CPDACBUF1_12 selected reference voltage * 12/64 12 CPDACBUF1_13 selected reference voltage * 13/64 13 CPDACBUF1_14 selected reference voltage * 14/64 14 CPDACBUF1_15 selected reference voltage * 15/64 15 CPDACBUF1_16 selected reference voltage * 16/64 16 CPDACBUF1_17 selected reference voltage * 17/64 17 CPDACBUF1_18 selected reference voltage * 18/64 18 CPDACBUF1_19 selected reference voltage * 19/64 19 CPDACBUF1_20 selected reference voltage * 20/64 20 CPDACBUF1_21 selected reference voltage * 21/64 21 CPDACBUF1_22 selected reference voltage * 22/64 22 CPDACBUF1_23 selected reference voltage * 23/64 23 CPDACBUF1_24 selected reference voltage * 24/64 24 CPDACBUF1_25 selected reference voltage * 25/64 25 CPDACBUF1_26 selected reference voltage * 26/64 26 CPDACBUF1_27 selected reference voltage * 27/64 27 CPDACBUF1_28 selected reference voltage * 28/64 28 CPDACBUF1_29 selected reference voltage * 29/64 29 CPDACBUF1_30 selected reference voltage * 30/64 30 CPDACBUF1_31 selected reference voltage * 31/64 31 CPDACBUF1_32 selected reference voltage * 32/64 32 CPDACBUF1_33 selected reference voltage * 33/64 33 CPDACBUF1_34 selected reference voltage * 34/64 34 CPDACBUF1_35 selected reference voltage * 35/64 35 CPDACBUF1_36 selected reference voltage * 36/64 36 CPDACBUF1_37 selected reference voltage * 37/64 37 CPDACBUF1_38 selected reference voltage * 38/64 38 CPDACBUF1_39 selected reference voltage * 39/64 39 CPDACBUF1_40 selected reference voltage * 40/64 40 CPDACBUF1_41 selected reference voltage * 41/64 41 CPDACBUF1_42 selected reference voltage * 42/64 42 CPDACBUF1_43 selected reference voltage * 43/64 43 CPDACBUF1_44 selected reference voltage * 44/64 44 CPDACBUF1_45 selected reference voltage * 45/64 45 CPDACBUF1_46 selected reference voltage * 46/64 46 CPDACBUF1_47 selected reference voltage * 47/64 47 CPDACBUF1_48 selected reference voltage * 48/64 48 CPDACBUF1_49 selected reference voltage * 49/64 49 CPDACBUF1_50 selected reference voltage * 50/64 50 CPDACBUF1_51 selected reference voltage * 51/64 51 CPDACBUF1_52 selected reference voltage * 52/64 52 CPDACBUF1_53 selected reference voltage * 53/64 53 CPDACBUF1_54 selected reference voltage * 54/64 54 CPDACBUF1_55 selected reference voltage * 55/64 55 CPDACBUF1_56 selected reference voltage * 56/64 56 CPDACBUF1_57 selected reference voltage * 57/64 57 CPDACBUF1_58 selected reference voltage * 58/64 58 CPDACBUF1_59 selected reference voltage * 59/64 59 CPDACBUF1_60 selected reference voltage * 60/64 60 CPDACBUF1_61 selected reference voltage * 61/64 61 CPDACBUF1_62 selected reference voltage * 62/64 62 CPDACBUF1_63 selected reference voltage * 63/64 63 CPDACBUF2 2nd 6-bit DAC buffer Data 8 6 read-write CPDACBUF2_0 0v 0 CPDACBUF2_1 selected reference voltage * 1/64 1 CPDACBUF2_2 selected reference voltage * 2/64 2 CPDACBUF2_3 selected reference voltage * 3/64 3 CPDACBUF2_4 selected reference voltage * 4/64 4 CPDACBUF2_5 selected reference voltage * 5/64 5 CPDACBUF2_6 selected reference voltage * 6/64 6 CPDACBUF2_7 selected reference voltage * 7/64 7 CPDACBUF2_8 selected reference voltage * 8/64 8 CPDACBUF2_9 selected reference voltage * 9/64 9 CPDACBUF2_10 selected reference voltage * 10/64 10 CPDACBUF2_11 selected reference voltage * 11/64 11 CPDACBUF2_12 selected reference voltage * 12/64 12 CPDACBUF2_13 selected reference voltage * 13/64 13 CPDACBUF2_14 selected reference voltage * 14/64 14 CPDACBUF2_15 selected reference voltage * 15/64 15 CPDACBUF2_16 selected reference voltage * 16/64 16 CPDACBUF2_17 selected reference voltage * 17/64 17 CPDACBUF2_18 selected reference voltage * 18/64 18 CPDACBUF2_19 selected reference voltage * 19/64 19 CPDACBUF2_20 selected reference voltage * 20/64 20 CPDACBUF2_21 selected reference voltage * 21/64 21 CPDACBUF2_22 selected reference voltage * 22/64 22 CPDACBUF2_23 selected reference voltage * 23/64 23 CPDACBUF2_24 selected reference voltage * 24/64 24 CPDACBUF2_25 selected reference voltage * 25/64 25 CPDACBUF2_26 selected reference voltage * 26/64 26 CPDACBUF2_27 selected reference voltage * 27/64 27 CPDACBUF2_28 selected reference voltage * 28/64 28 CPDACBUF2_29 selected reference voltage * 29/64 29 CPDACBUF2_30 selected reference voltage * 30/64 30 CPDACBUF2_31 selected reference voltage * 31/64 31 CPDACBUF2_32 selected reference voltage * 32/64 32 CPDACBUF2_33 selected reference voltage * 33/64 33 CPDACBUF2_34 selected reference voltage * 34/64 34 CPDACBUF2_35 selected reference voltage * 35/64 35 CPDACBUF2_36 selected reference voltage * 36/64 36 CPDACBUF2_37 selected reference voltage * 37/64 37 CPDACBUF2_38 selected reference voltage * 38/64 38 CPDACBUF2_39 selected reference voltage * 39/64 39 CPDACBUF2_40 selected reference voltage * 40/64 40 CPDACBUF2_41 selected reference voltage * 41/64 41 CPDACBUF2_42 selected reference voltage * 42/64 42 CPDACBUF2_43 selected reference voltage * 43/64 43 CPDACBUF2_44 selected reference voltage * 44/64 44 CPDACBUF2_45 selected reference voltage * 45/64 45 CPDACBUF2_46 selected reference voltage * 46/64 46 CPDACBUF2_47 selected reference voltage * 47/64 47 CPDACBUF2_48 selected reference voltage * 48/64 48 CPDACBUF2_49 selected reference voltage * 49/64 49 CPDACBUF2_50 selected reference voltage * 50/64 50 CPDACBUF2_51 selected reference voltage * 51/64 51 CPDACBUF2_52 selected reference voltage * 52/64 52 CPDACBUF2_53 selected reference voltage * 53/64 53 CPDACBUF2_54 selected reference voltage * 54/64 54 CPDACBUF2_55 selected reference voltage * 55/64 55 CPDACBUF2_56 selected reference voltage * 56/64 56 CPDACBUF2_57 selected reference voltage * 57/64 57 CPDACBUF2_58 selected reference voltage * 58/64 58 CPDACBUF2_59 selected reference voltage * 59/64 59 CPDACBUF2_60 selected reference voltage * 60/64 60 CPDACBUF2_61 selected reference voltage * 61/64 61 CPDACBUF2_62 selected reference voltage * 62/64 62 CPDACBUF2_63 selected reference voltage * 63/64 63 SAC0 SAC0 3200 SAC0OA SAC OA Control Register 0 16 65535 PSEL SAC OA Positive input source selection 0 2 read-write PSEL_0 External source selected 0 PSEL_1 12-bit reference DAC source selected 1 PSEL_2 Pair OA source selected 2 PMUXEN SAC Positive input MUX control. 3 1 read-write PMUXEN_0 All positive input sources are disconnected to OA positive port 0 PMUXEN_1 All positive input sources are connected to OA positive port 1 NSEL SAC OA Negative input source selection 4 2 read-write NSEL_0 External source selected 0 NSEL_1 PGA source selected 1 NSEL_2 Device Specific 2 NMUXEN SAC Negative input MUX controL 7 1 read-write NMUXEN_0 All negative input sources are disconnected to OA negative port 0 NMUXEN_1 All negative input sources are connected to OA negative port 1 OAEN SAC OA Enable selection 8 1 read-write OAEN_0 SAC OA is disabled, then the SAC OA output high impedance 0 OAEN_1 SAC OA is enabled, normal mode 1 OAPM SAC OA power mode selection 9 1 read-write OAPM_0 High speed and high power 0 OAPM_1 Llow speed and low power 1 SACEN SAC Enable selection 10 1 read-write SACEN_0 SAC all modules are disabled, then the SAC output high impedance 0 SACEN_1 SAC all modules are enabled, normal mode 1 SAC0PGA SAC PGA Control Register 2 16 65535 MSEL SAC PGA Mode Selection 0 2 read-write MSEL_0 Inverting PGA mode (external pad IN- is selected) 0 MSEL_1 Buffer mode (floating is selected ) 1 MSEL_2 Non-inverting mode 2 MSEL_3 Cascade OA Inverting mode 3 GAIN SAC PGA Gain configuration 4 3 read-write SAC0DAC SAC DAC Control Register 4 16 65535 DACEN SAC DAC enable 0 1 read-write DACEN_0 Disabled 0 DACEN_1 Enabled 1 DACIE SAC DAC interrupt enable 1 1 read-write DACIE_0 Disabled 0 DACIE_1 Enabled 1 DACDMAE SAC DAC DMA request enable 2 1 read-write DACDMAE_0 DMA request disabled 0 DACDMAE_1 DMA request enabled 1 DACLSEL SAC DAC load select. Selects the load trigger for the DAC latch. 8 2 read-write DACLSEL_0 DAC latch loads when DACDAT written 0 DACLSEL_2 Device specific 0. DAC always loads data from DACDAT at the positive edge of this signal 2 DACLSEL_3 Device specific 1. DAC always loads data from DACDAT at the positive edge of this signal 3 DACSREF SAC DAC select reference voltage 12 1 read-write DACSREF_0 AVCC 0 DACSREF_1 Alternative reference 1 SAC0DAT SAC DAC Data Register 6 16 65535 DACData SAC DAC data in unsigned format. 0 12 read-write SAC0DACSTS SAC DAC Status Register 8 16 65535 DACIFG SAC DAC data update flag 0 1 read-write SAC0IV SAC Interrupt Vector Register 10 16 65535 SACIV0 SAC Interrupt Vector Register 0 16 read-only SACIV_0 No interrupt pending 0 SACIV_2 S&H completed interrupt flag (Highest priority) 2 SACIV_4 DAC channel update interrupt flag 4 SAC1 SAC1 3216 SAC1OA SAC OA Control Register 0 16 65535 PSEL SAC OA Positive input source selection 0 2 read-write PSEL_0 External source selected 0 PSEL_1 12-bit reference DAC source selected 1 PSEL_2 Pair OA source selected 2 PMUXEN SAC Positive input MUX control. 3 1 read-write PMUXEN_0 All positive input sources are disconnected to OA positive port 0 PMUXEN_1 All positive input sources are connected to OA positive port 1 NSEL SAC OA Negative input source selection 4 2 read-write NSEL_0 External source selected 0 NSEL_1 PGA source selected 1 NSEL_2 Device Specific 2 NMUXEN SAC Negative input MUX controL 7 1 read-write NMUXEN_0 All negative input sources are disconnected to OA negative port 0 NMUXEN_1 All negative input sources are connected to OA negative port 1 OAEN SAC OA Enable selection 8 1 read-write OAEN_0 SAC OA is disabled, then the SAC OA output high impedance 0 OAEN_1 SAC OA is enabled, normal mode 1 OAPM SAC OA power mode selection 9 1 read-write OAPM_0 High speed and high power 0 OAPM_1 Llow speed and low power 1 SACEN SAC Enable selection 10 1 read-write SACEN_0 SAC all modules are disabled, then the SAC output high impedance 0 SACEN_1 SAC all modules are enabled, normal mode 1 SAC1PGA SAC PGA Control Register 2 16 65535 MSEL SAC PGA Mode Selection 0 2 read-write MSEL_0 Inverting PGA mode (external pad IN- is selected) 0 MSEL_1 Buffer mode (floating is selected ) 1 MSEL_2 Non-inverting mode 2 MSEL_3 Cascade OA Inverting mode 3 GAIN SAC PGA Gain configuration 4 3 read-write SAC1DAC SAC DAC Control Register 4 16 65535 DACEN SAC DAC enable 0 1 read-write DACEN_0 Disabled 0 DACEN_1 Enabled 1 DACIE SAC DAC interrupt enable 1 1 read-write DACIE_0 Disabled 0 DACIE_1 Enabled 1 DACDMAE SAC DAC DMA request enable 2 1 read-write DACDMAE_0 DMA request disabled 0 DACDMAE_1 DMA request enabled 1 DACLSEL SAC DAC load select. Selects the load trigger for the DAC latch. 8 2 read-write DACLSEL_0 DAC latch loads when DACDAT written 0 DACLSEL_2 Device specific 0. DAC always loads data from DACDAT at the positive edge of this signal 2 DACLSEL_3 Device specific 1. DAC always loads data from DACDAT at the positive edge of this signal 3 DACSREF SAC DAC select reference voltage 12 1 read-write DACSREF_0 AVCC 0 DACSREF_1 Alternative reference 1 SAC1DAT SAC DAC Data Register 6 16 65535 DACData SAC DAC data in unsigned format. 0 12 read-write SAC1DACSTS SAC DAC Status Register 8 16 65535 DACIFG SAC DAC data update flag 0 1 read-write SAC1IV SAC Interrupt Vector Register 10 16 65535 SACIV1 SAC Interrupt Vector Register 0 16 read-only SACIV_0 No interrupt pending 0 SACIV_2 S&H completed interrupt flag (Highest priority) 2 SACIV_4 DAC channel update interrupt flag 4 SAC2 SAC2 3232 SAC2OA SAC OA Control Register 0 16 65535 PSEL SAC OA Positive input source selection 0 2 read-write PSEL_0 External source selected 0 PSEL_1 12-bit reference DAC source selected 1 PSEL_2 Pair OA source selected 2 PMUXEN SAC Positive input MUX control. 3 1 read-write PMUXEN_0 All positive input sources are disconnected to OA positive port 0 PMUXEN_1 All positive input sources are connected to OA positive port 1 NSEL SAC OA Negative input source selection 4 2 read-write NSEL_0 External source selected 0 NSEL_1 PGA source selected 1 NSEL_2 Device Specific 2 NMUXEN SAC Negative input MUX controL 7 1 read-write NMUXEN_0 All negative input sources are disconnected to OA negative port 0 NMUXEN_1 All negative input sources are connected to OA negative port 1 OAEN SAC OA Enable selection 8 1 read-write OAEN_0 SAC OA is disabled, then the SAC OA output high impedance 0 OAEN_1 SAC OA is enabled, normal mode 1 OAPM SAC OA power mode selection 9 1 read-write OAPM_0 High speed and high power 0 OAPM_1 Llow speed and low power 1 SACEN SAC Enable selection 10 1 read-write SACEN_0 SAC all modules are disabled, then the SAC output high impedance 0 SACEN_1 SAC all modules are enabled, normal mode 1 SAC2PGA SAC PGA Control Register 2 16 65535 MSEL SAC PGA Mode Selection 0 2 read-write MSEL_0 Inverting PGA mode (external pad IN- is selected) 0 MSEL_1 Buffer mode (floating is selected ) 1 MSEL_2 Non-inverting mode 2 MSEL_3 Cascade OA Inverting mode 3 GAIN SAC PGA Gain configuration 4 3 read-write SAC2DAC SAC DAC Control Register 4 16 65535 DACEN SAC DAC enable 0 1 read-write DACEN_0 Disabled 0 DACEN_1 Enabled 1 DACIE SAC DAC interrupt enable 1 1 read-write DACIE_0 Disabled 0 DACIE_1 Enabled 1 DACDMAE SAC DAC DMA request enable 2 1 read-write DACDMAE_0 DMA request disabled 0 DACDMAE_1 DMA request enabled 1 DACLSEL SAC DAC load select. Selects the load trigger for the DAC latch. 8 2 read-write DACLSEL_0 DAC latch loads when DACDAT written 0 DACLSEL_2 Device specific 0. DAC always loads data from DACDAT at the positive edge of this signal 2 DACLSEL_3 Device specific 1. DAC always loads data from DACDAT at the positive edge of this signal 3 DACSREF SAC DAC select reference voltage 12 1 read-write DACSREF_0 AVCC 0 DACSREF_1 Alternative reference 1 SAC2DAT SAC DAC Data Register 6 16 65535 DACData SAC DAC data in unsigned format. 0 12 read-write SAC2DACSTS SAC DAC Status Register 8 16 65535 DACIFG SAC DAC data update flag 0 1 read-write SAC2IV SAC Interrupt Vector Register 10 16 65535 SACIV2 SAC Interrupt Vector Register 0 16 read-only SACIV_0 No interrupt pending 0 SACIV_2 S&H completed interrupt flag (Highest priority) 2 SACIV_4 DAC channel update interrupt flag 4 SAC3 SAC3 3248 SAC3OA SAC OA Control Register 0 16 65535 PSEL SAC OA Positive input source selection 0 2 read-write PSEL_0 External source selected 0 PSEL_1 12-bit reference DAC source selected 1 PSEL_2 Pair OA source selected 2 PMUXEN SAC Positive input MUX control. 3 1 read-write PMUXEN_0 All positive input sources are disconnected to OA positive port 0 PMUXEN_1 All positive input sources are connected to OA positive port 1 NSEL SAC OA Negative input source selection 4 2 read-write NSEL_0 External source selected 0 NSEL_1 PGA source selected 1 NSEL_2 Device Specific 2 NMUXEN SAC Negative input MUX controL 7 1 read-write NMUXEN_0 All negative input sources are disconnected to OA negative port 0 NMUXEN_1 All negative input sources are connected to OA negative port 1 OAEN SAC OA Enable selection 8 1 read-write OAEN_0 SAC OA is disabled, then the SAC OA output high impedance 0 OAEN_1 SAC OA is enabled, normal mode 1 OAPM SAC OA power mode selection 9 1 read-write OAPM_0 High speed and high power 0 OAPM_1 Llow speed and low power 1 SACEN SAC Enable selection 10 1 read-write SACEN_0 SAC all modules are disabled, then the SAC output high impedance 0 SACEN_1 SAC all modules are enabled, normal mode 1 SAC3PGA SAC PGA Control Register 2 16 65535 MSEL SAC PGA Mode Selection 0 2 read-write MSEL_0 Inverting PGA mode (external pad IN- is selected) 0 MSEL_1 Buffer mode (floating is selected ) 1 MSEL_2 Non-inverting mode 2 MSEL_3 Cascade OA Inverting mode 3 GAIN SAC PGA Gain configuration 4 3 read-write SAC3DAC SAC DAC Control Register 4 16 65535 DACEN SAC DAC enable 0 1 read-write DACEN_0 Disabled 0 DACEN_1 Enabled 1 DACIE SAC DAC interrupt enable 1 1 read-write DACIE_0 Disabled 0 DACIE_1 Enabled 1 DACDMAE SAC DAC DMA request enable 2 1 read-write DACDMAE_0 DMA request disabled 0 DACDMAE_1 DMA request enabled 1 DACLSEL SAC DAC load select. Selects the load trigger for the DAC latch. 8 2 read-write DACLSEL_0 DAC latch loads when DACDAT written 0 DACLSEL_2 Device specific 0. DAC always loads data from DACDAT at the positive edge of this signal 2 DACLSEL_3 Device specific 1. DAC always loads data from DACDAT at the positive edge of this signal 3 DACSREF SAC DAC select reference voltage 12 1 read-write DACSREF_0 AVCC 0 DACSREF_1 Alternative reference 1 SAC3DAT SAC DAC Data Register 6 16 65535 DACData SAC DAC data in unsigned format. 0 12 read-write SAC3DACSTS SAC DAC Status Register 8 16 65535 DACIFG SAC DAC data update flag 0 1 read-write SAC3IV SAC Interrupt Vector Register 10 16 65535 SACIV3 SAC Interrupt Vector Register 0 16 read-only SACIV_0 No interrupt pending 0 SACIV_2 S&H completed interrupt flag (Highest priority) 2 SACIV_4 DAC channel update interrupt flag 4 _INTERRUPTS 65408 PORT4 0xFFCE 21 PORT3 0xFFD0 22 PORT2 0xFFD2 23 PORT1 0xFFD4 24 SAC1_SAC3 0xFFD6 25 SAC0_SAC2 0xFFD8 26 ECOMP0_ECOMP1 0xFFDA 27 ADC 0xFFDC 28 EUSCI_B1 0xFFDE 29 EUSCI_B0 0xFFE0 30 EUSCI_A1 0xFFE2 31 EUSCI_A0 0xFFE4 32 WDT 0xFFE6 33 RTC 0xFFE8 34 TIMER3_B1 0xFFEA 35 TIMER3_B0 0xFFEC 36 TIMER2_B1 0xFFEE 37 TIMER2_B0 0xFFF0 38 TIMER1_B1 0xFFF2 39 TIMER1_B0 0xFFF4 40 TIMER0_B1 0xFFF6 41 TIMER0_B0 0xFFF8 42 UNMI 0xFFFA 43 SYSNMI 0xFFFC 44