MSP430FR2433 2 read-write 0 PORT_1_2 Port 1/2 512 P1IN Port 1 Input 0 8 255 0 255 P1IN0 P1IN0 0 1 read-write P1IN1 P1IN1 1 1 read-write P1IN2 P1IN2 2 1 read-write P1IN3 P1IN3 3 1 read-write P1IN4 P1IN4 4 1 read-write P1IN5 P1IN5 5 1 read-write P1IN6 P1IN6 6 1 read-write P1IN7 P1IN7 7 1 read-write P2IN Port 2 Input 1 8 255 0 255 P2IN0 P2IN0 0 1 read-write P2IN1 P2IN1 1 1 read-write P2IN2 P2IN2 2 1 read-write P2IN3 P2IN3 3 1 read-write P2IN4 P2IN4 4 1 read-write P2IN5 P2IN5 5 1 read-write P2IN6 P2IN6 6 1 read-write P2IN7 P2IN7 7 1 read-write P1OUT Port 1 Output 2 8 255 0 255 P1OUT0 P1OUT0 0 1 read-write P1OUT1 P1OUT1 1 1 read-write P1OUT2 P1OUT2 2 1 read-write P1OUT3 P1OUT3 3 1 read-write P1OUT4 P1OUT4 4 1 read-write P1OUT5 P1OUT5 5 1 read-write P1OUT6 P1OUT6 6 1 read-write P1OUT7 P1OUT7 7 1 read-write P2OUT Port 2 Output 3 8 255 0 255 P2OUT0 P2OUT0 0 1 read-write P2OUT1 P2OUT1 1 1 read-write P2OUT2 P2OUT2 2 1 read-write P2OUT3 P2OUT3 3 1 read-write P2OUT4 P2OUT4 4 1 read-write P2OUT5 P2OUT5 5 1 read-write P2OUT6 P2OUT6 6 1 read-write P2OUT7 P2OUT7 7 1 read-write P1DIR Port 1 Direction 4 8 255 0 255 P1DIR0 P1DIR0 0 1 read-write P1DIR1 P1DIR1 1 1 read-write P1DIR2 P1DIR2 2 1 read-write P1DIR3 P1DIR3 3 1 read-write P1DIR4 P1DIR4 4 1 read-write P1DIR5 P1DIR5 5 1 read-write P1DIR6 P1DIR6 6 1 read-write P1DIR7 P1DIR7 7 1 read-write P2DIR Port 2 Direction 5 8 255 0 255 P2DIR0 P2DIR0 0 1 read-write P2DIR1 P2DIR1 1 1 read-write P2DIR2 P2DIR2 2 1 read-write P2DIR3 P2DIR3 3 1 read-write P2DIR4 P2DIR4 4 1 read-write P2DIR5 P2DIR5 5 1 read-write P2DIR6 P2DIR6 6 1 read-write P2DIR7 P2DIR7 7 1 read-write P1REN Port 1 Resistor Enable 6 8 255 0 255 P1REN0 P1REN0 0 1 read-write P1REN1 P1REN1 1 1 read-write P1REN2 P1REN2 2 1 read-write P1REN3 P1REN3 3 1 read-write P1REN4 P1REN4 4 1 read-write P1REN5 P1REN5 5 1 read-write P1REN6 P1REN6 6 1 read-write P1REN7 P1REN7 7 1 read-write P2REN Port 2 Resistor Enable 7 8 255 0 255 P2REN0 P2REN0 0 1 read-write P2REN1 P2REN1 1 1 read-write P2REN2 P2REN2 2 1 read-write P2REN3 P2REN3 3 1 read-write P2REN4 P2REN4 4 1 read-write P2REN5 P2REN5 5 1 read-write P2REN6 P2REN6 6 1 read-write P2REN7 P2REN7 7 1 read-write P1SEL0 Port 1 Selection 0 10 8 255 0 255 P1SEL0_0 P1SEL0_0 0 1 read-write P1SEL0_1 P1SEL0_1 1 1 read-write P1SEL0_2 P1SEL0_2 2 1 read-write P1SEL0_3 P1SEL0_3 3 1 read-write P1SEL0_4 P1SEL0_4 4 1 read-write P1SEL0_5 P1SEL0_5 5 1 read-write P1SEL0_6 P1SEL0_6 6 1 read-write P1SEL0_7 P1SEL0_7 7 1 read-write P2SEL0 Port 2 Selection 0 11 8 255 0 255 P2SEL0_0 P2SEL0_0 0 1 read-write P2SEL0_1 P2SEL0_1 1 1 read-write P2SEL0_2 P2SEL0_2 2 1 read-write P2SEL0_3 P2SEL0_3 3 1 read-write P2SEL0_4 P2SEL0_4 4 1 read-write P2SEL0_5 P2SEL0_5 5 1 read-write P2SEL0_6 P2SEL0_6 6 1 read-write P2SEL0_7 P2SEL0_7 7 1 read-write P1SEL1 Port 1 Selection 1 12 8 255 0 255 P1SEL1_0 P1SEL1_0 0 1 read-write P1SEL1_1 P1SEL1_1 1 1 read-write P1SEL1_2 P1SEL1_2 2 1 read-write P1SEL1_3 P1SEL1_3 3 1 read-write P1SEL1_4 P1SEL1_4 4 1 read-write P1SEL1_5 P1SEL1_5 5 1 read-write P1SEL1_6 P1SEL1_6 6 1 read-write P1SEL1_7 P1SEL1_7 7 1 read-write P2SEL1 Port 2 Selection 1 13 8 255 0 255 P2SEL1_0 P2SEL1_0 0 1 read-write P2SEL1_1 P2SEL1_1 1 1 read-write P2SEL1_2 P2SEL1_2 2 1 read-write P2SEL1_3 P2SEL1_3 3 1 read-write P2SEL1_4 P2SEL1_4 4 1 read-write P2SEL1_5 P2SEL1_5 5 1 read-write P2SEL1_6 P2SEL1_6 6 1 read-write P2SEL1_7 P2SEL1_7 7 1 read-write P1IES Port 1 Interrupt Edge Select 24 8 255 0 255 P1IES0 P1IES0 0 1 read-write P1IES1 P1IES1 1 1 read-write P1IES2 P1IES2 2 1 read-write P1IES3 P1IES3 3 1 read-write P1IES4 P1IES4 4 1 read-write P1IES5 P1IES5 5 1 read-write P1IES6 P1IES6 6 1 read-write P1IES7 P1IES7 7 1 read-write P2IES Port 2 Interrupt Edge Select 25 8 255 0 255 P2IES0 P2IES0 0 1 read-write P2IES1 P2IES1 1 1 read-write P2IES2 P2IES2 2 1 read-write P2IES3 P2IES3 3 1 read-write P2IES4 P2IES4 4 1 read-write P2IES5 P2IES5 5 1 read-write P2IES6 P2IES6 6 1 read-write P2IES7 P2IES7 7 1 read-write P1IE Port 1 Interrupt Enable 26 8 255 0 255 P1IE0 P1IE0 0 1 read-write P1IE1 P1IE1 1 1 read-write P1IE2 P1IE2 2 1 read-write P1IE3 P1IE3 3 1 read-write P1IE4 P1IE4 4 1 read-write P1IE5 P1IE5 5 1 read-write P1IE6 P1IE6 6 1 read-write P1IE7 P1IE7 7 1 read-write P2IE Port 2 Interrupt Enable 27 8 255 0 255 P2IE0 P2IE0 0 1 read-write P2IE1 P2IE1 1 1 read-write P2IE2 P2IE2 2 1 read-write P2IE3 P2IE3 3 1 read-write P2IE4 P2IE4 4 1 read-write P2IE5 P2IE5 5 1 read-write P2IE6 P2IE6 6 1 read-write P2IE7 P2IE7 7 1 read-write P1IFG Port 1 Interrupt Flag 28 8 255 0 255 P1IFG0 P1IFG0 0 1 read-write P1IFG1 P1IFG1 1 1 read-write P1IFG2 P1IFG2 2 1 read-write P1IFG3 P1IFG3 3 1 read-write P1IFG4 P1IFG4 4 1 read-write P1IFG5 P1IFG5 5 1 read-write P1IFG6 P1IFG6 6 1 read-write P1IFG7 P1IFG7 7 1 read-write P2IFG Port 2 Interrupt Flag 29 8 255 0 255 P2IFG0 P2IFG0 0 1 read-write P2IFG1 P2IFG1 1 1 read-write P2IFG2 P2IFG2 2 1 read-write P2IFG3 P2IFG3 3 1 read-write P2IFG4 P2IFG4 4 1 read-write P2IFG5 P2IFG5 5 1 read-write P2IFG6 P2IFG6 6 1 read-write P2IFG7 P2IFG7 7 1 read-write P1IV Port 1 Interrupt Vector Word 14 16 65535 P2IV Port 2 Interrupt Vector Word 30 16 65535 PORT_3 Port 3 544 P3IN Port 3 Input 0 8 255 0 255 P3IN0 P3IN0 0 1 read-write P3IN1 P3IN1 1 1 read-write P3IN2 P3IN2 2 1 read-write P3IN3 P3IN3 3 1 read-write P3IN4 P3IN4 4 1 read-write P3IN5 P3IN5 5 1 read-write P3IN6 P3IN6 6 1 read-write P3IN7 P3IN7 7 1 read-write P3OUT Port 3 Output 2 8 255 0 255 P3OUT0 P3OUT0 0 1 read-write P3OUT1 P3OUT1 1 1 read-write P3OUT2 P3OUT2 2 1 read-write P3OUT3 P3OUT3 3 1 read-write P3OUT4 P3OUT4 4 1 read-write P3OUT5 P3OUT5 5 1 read-write P3OUT6 P3OUT6 6 1 read-write P3OUT7 P3OUT7 7 1 read-write P3DIR Port 3 Direction 4 8 255 0 255 P3DIR0 P3DIR0 0 1 read-write P3DIR1 P3DIR1 1 1 read-write P3DIR2 P3DIR2 2 1 read-write P3DIR3 P3DIR3 3 1 read-write P3DIR4 P3DIR4 4 1 read-write P3DIR5 P3DIR5 5 1 read-write P3DIR6 P3DIR6 6 1 read-write P3DIR7 P3DIR7 7 1 read-write P3REN Port 3 Resistor Enable 6 8 255 0 255 P3REN0 P3REN0 0 1 read-write P3REN1 P3REN1 1 1 read-write P3REN2 P3REN2 2 1 read-write P3REN3 P3REN3 3 1 read-write P3REN4 P3REN4 4 1 read-write P3REN5 P3REN5 5 1 read-write P3REN6 P3REN6 6 1 read-write P3REN7 P3REN7 7 1 read-write P3SEL0 Port 3 Selection0 10 8 255 0 255 P3SEL0_0 P3SEL0_0 0 1 read-write P3SEL0_1 P3SEL0_1 1 1 read-write P3SEL0_2 P3SEL0_2 2 1 read-write P3SEL0_3 P3SEL0_3 3 1 read-write P3SEL0_4 P3SEL0_4 4 1 read-write P3SEL0_5 P3SEL0_5 5 1 read-write P3SEL0_6 P3SEL0_6 6 1 read-write P3SEL0_7 P3SEL0_7 7 1 read-write P3SEL1 Port 3 Selection1 12 8 255 0 255 P3SEL1_0 P3SEL1_0 0 1 read-write P3SEL1_1 P3SEL1_1 1 1 read-write P3SEL1_2 P3SEL1_2 2 1 read-write P3SEL1_3 P3SEL1_3 3 1 read-write P3SEL1_4 P3SEL1_4 4 1 read-write P3SEL1_5 P3SEL1_5 5 1 read-write P3SEL1_6 P3SEL1_6 6 1 read-write P3SEL1_7 P3SEL1_7 7 1 read-write USCI_A0_UART_MODE USCI_A0 UART Mode 1280 UCA0CTL1 USCI A0 Control Register 1 0 8 255 UCA0CTL0 USCI A0 Control Register 0 1 8 255 UCA0BR0 USCI A0 Baud Rate 0 6 8 255 UCA0BR1 USCI A0 Baud Rate 1 7 8 255 UCA0STATW USCI A0 Status Register 10 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0ABCTL USCI A0 LIN Control 16 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM0 Break Sync Delimiter 0 4 1 read-write UCDELIM1 Break Sync Delimiter 1 5 1 read-write UCA0IRTCTL USCI A0 IrDA Transmit Control 18 8 255 UCA0IRRCTL USCI A0 IrDA Receive Control 19 8 255 UCA0CTLW1 USCI A0 Control Word Register 1 2 16 65535 UCGLIT USCI Deglitch Time Bit 1 0 2 read-write UCGLIT_0 USCI Deglitch time: 0 0 UCGLIT_1 USCI Deglitch time: 1 1 UCGLIT_2 USCI Deglitch time: 2 2 UCGLIT_3 USCI Deglitch time: 3 3 UCA0MCTLW USCI A0 Modulation Control 8 16 65535 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCBRS0 USCI Second Stage Modulation Select 0 8 1 read-write UCBRS1 USCI Second Stage Modulation Select 1 9 1 read-write UCBRS2 USCI Second Stage Modulation Select 2 10 1 read-write UCBRS3 USCI Second Stage Modulation Select 3 11 1 read-write UCBRS4 USCI Second Stage Modulation Select 4 12 1 read-write UCBRS5 USCI Second Stage Modulation Select 5 13 1 read-write UCBRS6 USCI Second Stage Modulation Select 6 14 1 read-write UCBRS7 USCI Second Stage Modulation Select 7 15 1 read-write UCA0RXBUF USCI A0 Receive Buffer 12 16 65535 UCA0TXBUF USCI A0 Transmit Buffer 14 16 65535 UCA0IV USCI A0 Interrupt Vector Register 30 16 65535 USCI_A0_SPI_MODE USCI_A0 SPI Mode 1280 UCA0CTL1_SPI USCI A0 Control Register 1 0 8 255 UCA0CTL0_SPI USCI A0 Control Register 0 1 8 255 UCA0BR0_SPI USCI A0 Baud Rate 0 6 8 255 UCA0BR1_SPI USCI A0 Baud Rate 1 7 8 255 UCA0STATW_SPI USCI A0 Status Register 10 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0IE_SPI USCI A0 Interrupt Enable Register 26 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCA0IFG_SPI USCI A0 Interrupt Flags Register 28 8 255 UCRXIFG SPI Receive Interrupt Flag 0 1 read-write UCTXIFG SPI Transmit Interrupt Flag 1 1 read-write UCA0RXBUF_SPI USCI A0 Receive Buffer 12 16 65535 UCA0TXBUF_SPI USCI A0 Transmit Buffer 14 16 65535 UCA0IV_SPI USCI A0 Interrupt Vector Register 30 16 65535 USCI_A1_UART_MODE USCI_A1 UART Mode 1312 UCA1CTL1 USCI A1 Control Register 1 0 8 255 UCA1CTL0 USCI A1 Control Register 0 1 8 255 UCA1BR0 USCI A1 Baud Rate 0 6 8 255 UCA1BR1 USCI A1 Baud Rate 1 7 8 255 UCA1STATW USCI A1 Status Register 10 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA1ABCTL USCI A1 LIN Control 16 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM0 Break Sync Delimiter 0 4 1 read-write UCDELIM1 Break Sync Delimiter 1 5 1 read-write UCA1IRTCTL USCI A1 IrDA Transmit Control 18 8 255 UCA1IRRCTL USCI A1 IrDA Receive Control 19 8 255 UCA1CTLW1 USCI A1 Control Word Register 1 2 16 65535 UCGLIT USCI Deglitch Time Bit 1 0 2 read-write UCGLIT_0 USCI Deglitch time: 0 0 UCGLIT_1 USCI Deglitch time: 1 1 UCGLIT_2 USCI Deglitch time: 2 2 UCGLIT_3 USCI Deglitch time: 3 3 UCA1MCTLW USCI A1 Modulation Control 8 16 65535 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCBRS0 USCI Second Stage Modulation Select 0 8 1 read-write UCBRS1 USCI Second Stage Modulation Select 1 9 1 read-write UCBRS2 USCI Second Stage Modulation Select 2 10 1 read-write UCBRS3 USCI Second Stage Modulation Select 3 11 1 read-write UCBRS4 USCI Second Stage Modulation Select 4 12 1 read-write UCBRS5 USCI Second Stage Modulation Select 5 13 1 read-write UCBRS6 USCI Second Stage Modulation Select 6 14 1 read-write UCBRS7 USCI Second Stage Modulation Select 7 15 1 read-write UCA1RXBUF USCI A1 Receive Buffer 12 16 65535 UCA1TXBUF USCI A1 Transmit Buffer 14 16 65535 UCA1IV USCI A1 Interrupt Vector Register 30 16 65535 USCI_A1_SPI_MODE USCI_A1 SPI Mode 1312 UCA1CTL1_SPI USCI A1 Control Register 1 0 8 255 UCA1CTL0_SPI USCI A1 Control Register 0 1 8 255 UCA1BR0_SPI USCI A1 Baud Rate 0 6 8 255 UCA1BR1_SPI USCI A1 Baud Rate 1 7 8 255 UCA1STATW_SPI USCI A1 Status Register 10 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA1IE_SPI USCI A1 Interrupt Enable Register 26 8 255 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCA1IFG_SPI USCI A1 Interrupt Flags Register 28 8 255 UCRXIFG SPI Receive Interrupt Flag 0 1 read-write UCTXIFG SPI Transmit Interrupt Flag 1 1 read-write UCA1RXBUF_SPI USCI A1 Receive Buffer 12 16 65535 UCA1TXBUF_SPI USCI A1 Transmit Buffer 14 16 65535 UCA1IV_SPI USCI A1 Interrupt Vector Register 30 16 65535 USCI_B0_I2C_MODE USCI_B0 I2C Mode 1344 UCB0CTL1 USCI B0 Control Register 1 0 8 255 UCB0CTL0 USCI B0 Control Register 0 1 8 255 UCB0BR0 USCI B0 Baud Rate 0 6 8 255 UCB0BR1 USCI B0 Baud Rate 1 7 8 255 UCB0STAT_I2C USCI B0 Status Register 8 8 255 UCBBUSY Bus Busy Flag 4 1 read-write UCGC General Call address received Flag 5 1 read-write UCSCLLOW SCL low 6 1 read-write UCB0BCNT_I2C USCI B0 Byte Counter Register 9 8 255 0 255 UCBCNT0 USCI Byte Counter Bit 0 0 1 read-write UCBCNT1 USCI Byte Counter Bit 1 1 1 read-write UCBCNT2 USCI Byte Counter Bit 2 2 1 read-write UCBCNT3 USCI Byte Counter Bit 3 3 1 read-write UCBCNT4 USCI Byte Counter Bit 4 4 1 read-write UCBCNT5 USCI Byte Counter Bit 5 5 1 read-write UCBCNT6 USCI Byte Counter Bit 6 6 1 read-write UCBCNT7 USCI Byte Counter Bit 7 7 1 read-write UCB0CTLW1 USCI B0 Control Word Register 1 2 16 65535 UCGLIT USCI Deglitch time Bit: 1 0 2 read-write UCGLIT_0 USCI Deglitch time: 0 0 UCGLIT_1 USCI Deglitch time: 1 1 UCGLIT_2 USCI Deglitch time: 2 2 UCGLIT_3 USCI Deglitch time: 3 3 UCASTP USCI Automatic Stop condition generation Bit: 1 2 2 read-write UCASTP_0 USCI Automatic Stop condition generation: 0 0 UCASTP_1 USCI Automatic Stop condition generation: 1 1 UCASTP_2 USCI Automatic Stop condition generation: 2 2 UCASTP_3 USCI Automatic Stop condition generation: 3 3 UCSWACK USCI Software controlled ACK 4 1 read-write UCSTPNACK USCI Acknowledge Stop last byte 5 1 read-write UCCLTO USCI Clock low timeout Bit: 1 6 2 read-write UCCLTO_0 USCI Clock low timeout: 0 0 UCCLTO_1 USCI Clock low timeout: 1 1 UCCLTO_2 USCI Clock low timeout: 2 2 UCCLTO_3 USCI Clock low timeout: 3 3 UCETXINT USCI Early UCTXIFG0 8 1 read-write UCB0TBCNT USCI B0 Byte Counter Threshold Register 10 16 65535 UCB0RXBUF USCI B0 Receive Buffer 12 16 65535 UCB0TXBUF USCI B0 Transmit Buffer 14 16 65535 UCB0I2COA0 USCI B0 I2C Own Address 0 20 16 65535 UCOA0 I2C Own Address Bit 0 0 1 read-write UCOA1 I2C Own Address Bit 1 1 1 read-write UCOA2 I2C Own Address Bit 2 2 1 read-write UCOA3 I2C Own Address Bit 3 3 1 read-write UCOA4 I2C Own Address Bit 4 4 1 read-write UCOA5 I2C Own Address Bit 5 5 1 read-write UCOA6 I2C Own Address Bit 6 6 1 read-write UCOA7 I2C Own Address Bit 7 7 1 read-write UCOA8 I2C Own Address Bit 8 8 1 read-write UCOA9 I2C Own Address Bit 9 9 1 read-write UCOAEN I2C Own Address enable 10 1 read-write UCGCEN I2C General Call enable 15 1 read-write UCB0I2COA1 USCI B0 I2C Own Address 1 22 16 65535 UCOA0 I2C Own Address Bit 0 0 1 read-write UCOA1 I2C Own Address Bit 1 1 1 read-write UCOA2 I2C Own Address Bit 2 2 1 read-write UCOA3 I2C Own Address Bit 3 3 1 read-write UCOA4 I2C Own Address Bit 4 4 1 read-write UCOA5 I2C Own Address Bit 5 5 1 read-write UCOA6 I2C Own Address Bit 6 6 1 read-write UCOA7 I2C Own Address Bit 7 7 1 read-write UCOA8 I2C Own Address Bit 8 8 1 read-write UCOA9 I2C Own Address Bit 9 9 1 read-write UCOAEN I2C Own Address enable 10 1 read-write UCB0I2COA2 USCI B0 I2C Own Address 2 24 16 65535 UCOA0 I2C Own Address Bit 0 0 1 read-write UCOA1 I2C Own Address Bit 1 1 1 read-write UCOA2 I2C Own Address Bit 2 2 1 read-write UCOA3 I2C Own Address Bit 3 3 1 read-write UCOA4 I2C Own Address Bit 4 4 1 read-write UCOA5 I2C Own Address Bit 5 5 1 read-write UCOA6 I2C Own Address Bit 6 6 1 read-write UCOA7 I2C Own Address Bit 7 7 1 read-write UCOA8 I2C Own Address Bit 8 8 1 read-write UCOA9 I2C Own Address Bit 9 9 1 read-write UCOAEN I2C Own Address enable 10 1 read-write UCB0I2COA3 USCI B0 I2C Own Address 3 26 16 65535 UCOA0 I2C Own Address Bit 0 0 1 read-write UCOA1 I2C Own Address Bit 1 1 1 read-write UCOA2 I2C Own Address Bit 2 2 1 read-write UCOA3 I2C Own Address Bit 3 3 1 read-write UCOA4 I2C Own Address Bit 4 4 1 read-write UCOA5 I2C Own Address Bit 5 5 1 read-write UCOA6 I2C Own Address Bit 6 6 1 read-write UCOA7 I2C Own Address Bit 7 7 1 read-write UCOA8 I2C Own Address Bit 8 8 1 read-write UCOA9 I2C Own Address Bit 9 9 1 read-write UCOAEN I2C Own Address enable 10 1 read-write UCB0ADDRX USCI B0 Received Address Register 28 16 65535 UCADDRX0 I2C Receive Address Bit 0 0 1 read-write UCADDRX1 I2C Receive Address Bit 1 1 1 read-write UCADDRX2 I2C Receive Address Bit 2 2 1 read-write UCADDRX3 I2C Receive Address Bit 3 3 1 read-write UCADDRX4 I2C Receive Address Bit 4 4 1 read-write UCADDRX5 I2C Receive Address Bit 5 5 1 read-write UCADDRX6 I2C Receive Address Bit 6 6 1 read-write UCADDRX7 I2C Receive Address Bit 7 7 1 read-write UCADDRX8 I2C Receive Address Bit 8 8 1 read-write UCADDRX9 I2C Receive Address Bit 9 9 1 read-write UCB0ADDMASK USCI B0 Address Mask Register 30 16 65535 UCADDMASK0 I2C Address Mask Bit 0 0 1 read-write UCADDMASK1 I2C Address Mask Bit 1 1 1 read-write UCADDMASK2 I2C Address Mask Bit 2 2 1 read-write UCADDMASK3 I2C Address Mask Bit 3 3 1 read-write UCADDMASK4 I2C Address Mask Bit 4 4 1 read-write UCADDMASK5 I2C Address Mask Bit 5 5 1 read-write UCADDMASK6 I2C Address Mask Bit 6 6 1 read-write UCADDMASK7 I2C Address Mask Bit 7 7 1 read-write UCADDMASK8 I2C Address Mask Bit 8 8 1 read-write UCADDMASK9 I2C Address Mask Bit 9 9 1 read-write UCB0I2CSA USCI B0 I2C Slave Address 32 16 65535 UCSA0 I2C Slave Address Bit 0 0 1 read-write UCSA1 I2C Slave Address Bit 1 1 1 read-write UCSA2 I2C Slave Address Bit 2 2 1 read-write UCSA3 I2C Slave Address Bit 3 3 1 read-write UCSA4 I2C Slave Address Bit 4 4 1 read-write UCSA5 I2C Slave Address Bit 5 5 1 read-write UCSA6 I2C Slave Address Bit 6 6 1 read-write UCSA7 I2C Slave Address Bit 7 7 1 read-write UCSA8 I2C Slave Address Bit 8 8 1 read-write UCSA9 I2C Slave Address Bit 9 9 1 read-write UCB0IE USCI B0 Interrupt Enable Register 42 16 65535 UCB0IE_I2C USCI B0 Interrupt Enable Register UCB0IE 42 16 65535 UCRXIE0 I2C Receive Interrupt Enable 0 0 1 read-write UCTXIE0 I2C Transmit Interrupt Enable 0 1 1 read-write UCSTTIE I2C START Condition interrupt enable 2 1 read-write UCSTPIE I2C STOP Condition interrupt enable 3 1 read-write UCALIE I2C Arbitration Lost interrupt enable 4 1 read-write UCNACKIE I2C NACK Condition interrupt enable 5 1 read-write UCBCNTIE I2C Automatic stop assertion interrupt enable 6 1 read-write UCCLTOIE I2C Clock Low Timeout interrupt enable 7 1 read-write UCRXIE1 I2C Receive Interrupt Enable 1 8 1 read-write UCTXIE1 I2C Transmit Interrupt Enable 1 9 1 read-write UCRXIE2 I2C Receive Interrupt Enable 2 10 1 read-write UCTXIE2 I2C Transmit Interrupt Enable 2 11 1 read-write UCRXIE3 I2C Receive Interrupt Enable 3 12 1 read-write UCTXIE3 I2C Transmit Interrupt Enable 3 13 1 read-write UCBIT9IE I2C Bit 9 Position Interrupt Enable 3 14 1 read-write UCB0IFG USCI B0 Interrupt Flags Register 44 16 65535 UCB0IFG_I2C USCI B0 Interrupt Flags Register UCB0IFG 44 16 65535 UCRXIFG0 I2C Receive Interrupt Flag 0 0 1 read-write UCTXIFG0 I2C Transmit Interrupt Flag 0 1 1 read-write UCSTTIFG I2C START Condition interrupt Flag 2 1 read-write UCSTPIFG I2C STOP Condition interrupt Flag 3 1 read-write UCALIFG I2C Arbitration Lost interrupt Flag 4 1 read-write UCNACKIFG I2C NACK Condition interrupt Flag 5 1 read-write UCBCNTIFG I2C Byte counter interrupt flag 6 1 read-write UCCLTOIFG I2C Clock low Timeout interrupt Flag 7 1 read-write UCRXIFG1 I2C Receive Interrupt Flag 1 8 1 read-write UCTXIFG1 I2C Transmit Interrupt Flag 1 9 1 read-write UCRXIFG2 I2C Receive Interrupt Flag 2 10 1 read-write UCTXIFG2 I2C Transmit Interrupt Flag 2 11 1 read-write UCRXIFG3 I2C Receive Interrupt Flag 3 12 1 read-write UCTXIFG3 I2C Transmit Interrupt Flag 3 13 1 read-write UCBIT9IFG I2C Bit 9 Possition Interrupt Flag 3 14 1 read-write UCB0IV USCI B0 Interrupt Vector Register 46 16 65535 USCI_B0_SPI_MODE USCI_B0 SPI Mode 1344 UCB0CTL1_SPI USCI B0 Control Register 1 0 8 255 UCB0CTL0_SPI USCI B0 Control Register 0 1 8 255 UCB0BR0_SPI USCI B0 Baud Rate 0 6 8 255 UCB0BR1_SPI USCI B0 Baud Rate 1 7 8 255 UCB0RXBUF_SPI USCI B0 Receive Buffer 12 16 65535 UCB0TXBUF_SPI USCI B0 Transmit Buffer 14 16 65535 UCB0IE_SPI USCI B0 Interrupt Enable Register 42 16 65535 UCRXIE USCI Receive Interrupt Enable 0 1 read-write UCTXIE USCI Transmit Interrupt Enable 1 1 read-write UCB0IFG_SPI USCI B0 Interrupt Flags Register 44 16 65535 UCRXIFG SPI Receive Interrupt Flag 0 1 read-write UCTXIFG SPI Transmit Interrupt Flag 1 1 read-write UCB0IV_SPI USCI B0 Interrupt Vector Register 46 16 65535 SFR SFR Special Function Registers 256 SFRIE1 Interrupt Enable 1 0 16 65535 WDTIE WDT Interrupt Enable 0 1 read-write OFIE Osc Fault Enable 1 1 read-write VMAIE Vacant Memory Interrupt Enable 3 1 read-write NMIIE NMI Interrupt Enable 4 1 read-write JMBINIE JTAG Mail Box input Interrupt Enable 6 1 read-write JMBOUTIE JTAG Mail Box output Interrupt Enable 7 1 read-write SFRIFG1 Interrupt Flag 1 2 16 65535 WDTIFG WDT Interrupt Flag 0 1 read-write OFIFG Osc Fault Flag 1 1 read-write VMAIFG Vacant Memory Interrupt Flag 3 1 read-write NMIIFG NMI Interrupt Flag 4 1 read-write JMBINIFG JTAG Mail Box input Interrupt Flag 6 1 read-write JMBOUTIFG JTAG Mail Box output Interrupt Flag 7 1 read-write SFRRPCR RESET Pin Control Register 4 16 65535 SYSNMI NMI select 0 1 read-write SYSNMIIES NMI edge select 1 1 read-write SYSRSTUP RESET Pin pull down/up select 2 1 read-write SYSRSTRE RESET Pin Resistor enable 3 1 read-write PMM PMM Power Management System 288 PMMCTL0 PMM Control 0 0 16 65535 PMMSWBOR PMM Software BOR 2 1 read-write PMMSWPOR PMM Software POR 3 1 read-write PMMREGOFF PMM Turn Regulator off 4 1 read-write SVSHE SVS high side enable 6 1 read-write PMMPWPMM Password88read-writePMMPWRreadPASSWORDValues always reads from the PMMCTL0 register150 PMMPWWwritePASSWORDValues which must be written to the PMMCTL0 register165 PMMCTL1 PMM Control 1 2 16 65535 PMMCTL2 PMM Control 2 4 16 65535 INTREFEN Internal Reference Enable 0 1 read-write EXTREFEN External Reference output Enable 1 1 read-write TSENSOREN Temperature Sensor Enable 3 1 read-write REFGENACT REF Reference generator active 8 1 read-write REFBGACT REF Reference bandgap active 9 1 read-write BGMODE REF Bandgap mode 11 1 read-write REFGENRDY REF Reference generator ready 12 1 read-write REFBGRDY REF Reference bandgap ready 13 1 read-write REFGENReference generator trigger. If written with a 1, the generation of the variable reference voltage is started. When the reference voltage request is set, this bit is cleared by hardware or writing 0.61read-write REFBGENBandgap and bandgap buffer trigger. If written with a 1, the generation of the buffered bandgap voltage is started. When the bandgap buffer voltage request is set, this bit is cleared by hardware or writing 0.71read-write REFVSELInternal reference voltage level select. 00b = 1.5V, 01b = 2.0V, 10b = 2.5V42read-writeREFVSELread-writeREFVSEL_000b = 1.5V0REFVSEL_101b = 2.0V1REFVSEL_210b = 2.5V2REFVSEL_311b = Reserved3 PMMIFG PMM Interrupt Flag 10 16 65535 PMMBORIFG PMM Software BOR interrupt flag 8 1 read-write PMMRSTIFG PMM RESET pin interrupt flag 9 1 read-write PMMPORIFG PMM Software POR interrupt flag 10 1 read-write SVSHIFG SVS low side interrupt flag 13 1 read-write PMMLPM5IFG LPM5 indication Flag 15 1 read-write PMMIE PMM Interrupt Enable 14 16 65535 PM5CTL0 PMM Power Mode 5 Control Register 0 16 16 65535 LOCKLPM5 Lock I/O pin configuration upon entry/exit to/from LPM5 0 1 read-write LPM5SW LPMx.5 switch dis/connected 4 1 read-write LPM5SM Manual mode for LPM3.5 switch 5 1 read-write SYS SYS System Module 320 SYSCTL System control 0 16 65535 SYSRIVECT SYS - RAM based interrupt vectors 0 1 read-write SYSPMMPE SYS - PMM access protect 2 1 read-write SYSBSLIND SYS - TCK/RST indication detected 4 1 read-write SYSJTAGPIN SYS - Dedicated JTAG pins enabled 5 1 read-write SYSBSLC Boot strap configuration area 2 16 65535 SYSBSLR SYS - RAM assigned to BSL 2 1 read-write SYSBSLOFF SYS - BSL Memory disabled 14 1 read-write SYSBSLPE SYS - BSL Memory protection enabled 15 1 read-write SYSJMBC JTAG mailbox control 6 16 65535 JMBIN0FG SYS - Incoming JTAG Mailbox 0 Flag 0 1 read-write JMBIN1FG SYS - Incoming JTAG Mailbox 1 Flag 1 1 read-write JMBOUT0FG SYS - Outgoing JTAG Mailbox 0 Flag 2 1 read-write JMBOUT1FG SYS - Outgoing JTAG Mailbox 1 Flag 3 1 read-write JMBMODE SYS - JMB 16/32 Bit Mode 4 1 read-write JMBCLR0OFF SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe 6 1 read-write JMBCLR1OFF SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe 7 1 read-write SYSJMBI0 JTAG mailbox input 0 8 16 65535 SYSJMBI1 JTAG mailbox input 1 10 16 65535 SYSJMBO0 JTAG mailbox output 0 12 16 65535 SYSJMBO1 JTAG mailbox output 1 14 16 65535 SYSBERRIV Bus Error vector generator 24 16 65535 SYSUNIV User NMI vector generator 26 16 65535 SYSSNIV System NMI vector generator 28 16 65535 SYSRSTIV Reset vector generator 30 16 65535 SYSCFG0 System Configuration 0 32 16 65535 PFWP Program FRAM Write Protection 0 1 read-write DFWP Data FRAM Write Protection 1 1 read-write SYSCFG1 System Configuration 1 34 16 65535 IREN Infrared enable 0 1 read-write IRPSEL Infrared polarity select 1 1 read-write IRMSEL Infrared mode select 2 1 read-write IRDSSEL Infrared data source select 3 1 read-write IRDATA Infrared enable 4 1 read-write SYSCFG2 System Configuration 2 36 16 65535 ADCPCTL0 ADC input A0 pin select 0 1 read-write ADCPCTL1 ADC input A1 pin select 1 1 read-write ADCPCTL2 ADC input A2 pin select 2 1 read-write ADCPCTL3 ADC input A3 pin select 3 1 read-write ADCPCTL4 ADC input A4 pin select 4 1 read-write ADCPCTL5 ADC input A5 pin select 5 1 read-write ADCPCTL6 ADC input A6 pin select 6 1 read-write ADCPCTL7 ADC input A7 pin select 7 1 read-write CS CS Clock System 384 CSCTL0 CS Control Register 0 0 16 65535 DCO0 DCO TAP Bit : 0 0 1 read-write DCO1 DCO TAP Bit : 1 1 1 read-write DCO2 DCO TAP Bit : 2 2 1 read-write DCO3 DCO TAP Bit : 3 3 1 read-write DCO4 DCO TAP Bit : 4 4 1 read-write DCO5 DCO TAP Bit : 5 5 1 read-write DCO6 DCO TAP Bit : 6 6 1 read-write DCO7 DCO TAP Bit : 7 7 1 read-write DCO8 DCO TAP Bit : 8 8 1 read-write MOD0 Modulation Bit Counter Bit : 0 9 1 read-write MOD1 Modulation Bit Counter Bit : 1 10 1 read-write MOD2 Modulation Bit Counter Bit : 2 11 1 read-write MOD3 Modulation Bit Counter Bit : 3 12 1 read-write MOD4 Modulation Bit Counter Bit : 4 13 1 read-write CSCTL1 CS Control Register 1 2 16 65535 DISMOD Disable Modulation 0 1 read-write DCORSEL DCO frequency range select Bit: 0 1 3 read-write DCORSEL_0 DCO frequency range select: 0 0 DCORSEL_1 DCO frequency range select: 1 1 DCORSEL_2 DCO frequency range select: 2 2 DCORSEL_3 DCO frequency range select: 3 3 DCORSEL_4 DCO frequency range select: 4 4 DCORSEL_5 DCO frequency range select: 5 5 DCORSEL_6 DCO frequency range select: 6 6 DCORSEL_7 DCO frequency range select: 7 7 DCOFTRIM DCO frequency trim. Bit: 0 4 3 read-write DCOFTRIM_0 DCO frequency trim: 0 0 DCOFTRIM_1 DCO frequency trim: 1 1 DCOFTRIM_2 DCO frequency trim: 2 2 DCOFTRIM_3 DCO frequency trim: 3 3 DCOFTRIM_4 DCO frequency trim: 4 4 DCOFTRIM_5 DCO frequency trim: 5 5 DCOFTRIM_6 DCO frequency trim: 6 6 DCOFTRIM_7 DCO frequency trim: 7 7 DCOFTRIMEN DCO frequency trim enable 7 1 read-write CSCTL2 CS Control Register 2 4 16 65535 FLLN0 FLL Multipier Bit : 0 0 1 read-write FLLN1 FLL Multipier Bit : 1 1 1 read-write FLLN2 FLL Multipier Bit : 2 2 1 read-write FLLN3 FLL Multipier Bit : 3 3 1 read-write FLLN4 FLL Multipier Bit : 4 4 1 read-write FLLN5 FLL Multipier Bit : 5 5 1 read-write FLLN6 FLL Multipier Bit : 6 6 1 read-write FLLN7 FLL Multipier Bit : 7 7 1 read-write FLLN8 FLL Multipier Bit : 8 8 1 read-write FLLN9 FLL Multipier Bit : 9 9 1 read-write FLLD Loop Divider Bit : 0 12 3 read-write FLLD_0 Multiply Selected Loop Freq. By 1 0 FLLD_1 Multiply Selected Loop Freq. By 2 1 FLLD_2 Multiply Selected Loop Freq. By 4 2 FLLD_3 Multiply Selected Loop Freq. By 8 3 FLLD_4 Multiply Selected Loop Freq. By 16 4 FLLD_5 Multiply Selected Loop Freq. By 32 5 FLLD_6 Reserved 6 FLLD_7 Reserved 7 CSCTL3 CS Control Register 3 6 16 65535 FLLREFDIV Reference Divider Bit : 0 0 3 read-write FLLREFDIV_0 Reference Divider: f(LFCLK)/1 0 FLLREFDIV_1 Reference Divider: f(LFCLK)/2 1 FLLREFDIV_2 Reference Divider: f(LFCLK)/4 2 FLLREFDIV_3 Reference Divider: f(LFCLK)/8 3 FLLREFDIV_4 Reference Divider: f(LFCLK)/12 4 FLLREFDIV_5 Reference Divider: f(LFCLK)/16 5 FLLREFDIV_6 Reference Divider: f(LFCLK)/16 6 FLLREFDIV_7 Reference Divider: f(LFCLK)/16 7 SELREF FLL Reference Clock Select Bit : 0 4 2 read-write SELREF_0 FLL Reference Clock Select 0 0 SELREF_1 FLL Reference Clock Select 1 1 SELREF_2 FLL Reference Clock Select 2 2 SELREF_3 FLL Reference Clock Select 3 3 CSCTL4 CS Control Register 4 8 16 65535 SELMS MCLK and SMCLK Source Select Bit: 0 0 3 read-write SELMS_0 MCLK and SMCLK Source Select 0 0 SELMS_1 MCLK and SMCLK Source Select 1 1 SELMS_2 MCLK and SMCLK Source Select 2 2 SELMS_3 MCLK and SMCLK Source Select 3 3 SELMS_4 MCLK and SMCLK Source Select 4 4 SELMS_5 MCLK and SMCLK Source Select 5 5 SELMS_6 MCLK and SMCLK Source Select 6 6 SELMS_7 MCLK and SMCLK Source Select 7 7 SELA ACLK Source Select Bit: 0 8 1 read-write CSCTL5 CS Control Register 5 10 16 65535 DIVM MCLK Divider Bit: 0 0 3 read-write DIVM_0 MCLK Source Divider 0 0 DIVM_1 MCLK Source Divider 1 1 DIVM_2 MCLK Source Divider 2 2 DIVM_3 MCLK Source Divider 3 3 DIVM_4 MCLK Source Divider 4 4 DIVM_5 MCLK Source Divider 5 5 DIVM_6 MCLK Source Divider 6 6 DIVM_7 MCLK Source Divider 7 7 DIVS SMCLK Divider Bit: 0 4 2 read-write DIVS_0 SMCLK Source Divider 0 0 DIVS_1 SMCLK Source Divider 1 1 DIVS_2 SMCLK Source Divider 2 2 DIVS_3 SMCLK Source Divider 3 3 SMCLKOFF SMCLK off 8 1 read-write VLOAUTOOFF VLO automatic off enable 12 1 read-write CSCTL6 CS Control Register 6 12 16 65535 XT1AUTOOFF XT1 automatic off enable 0 1 read-write XT1AGCOFF XT1 Automatic Gain Control (AGC) disable 1 1 read-write XT1BYPASS XT1 bypass mode : 0: internal 1:sourced from external pin 4 1 read-write XTS 1: Selects high-freq. oscillator 5 1 read-write XT1DRIVE XT1 Drive Level mode Bit 0 6 2 read-write XT1DRIVE_0 XT1 Drive Level mode: 0 0 XT1DRIVE_1 XT1 Drive Level mode: 1 1 XT1DRIVE_2 XT1 Drive Level mode: 2 2 XT1DRIVE_3 XT1 Drive Level mode: 3 3 CSCTL7 CS Control Register 7 14 16 65535 DCOFFG DCO fault flag 0 1 read-write XT1OFFG XT1 Low Frequency Oscillator Fault Flag 1 1 read-write FLLULIFG FLL unlock interrupt flag 4 1 read-write ENSTFCNT1 Enable start counter for XT1 6 1 read-write FLLUNLOCK FLL unlock condition Bit: 0 8 2 read-write FLLUNLOCK_0 FLL unlock condition: 0 0 FLLUNLOCK_1 FLL unlock condition: 1 1 FLLUNLOCK_2 FLL unlock condition: 2 2 FLLUNLOCK_3 FLL unlock condition: 3 3 FLLUNLOCKHIS Unlock history Bit: 0 10 2 read-write FLLUNLOCKHIS_0 Unlock history: 0 0 FLLUNLOCKHIS_1 Unlock history: 1 1 FLLUNLOCKHIS_2 Unlock history: 2 2 FLLUNLOCKHIS_3 Unlock history: 3 3 FLLULPUC FLL unlock PUC enable 12 1 read-write FLLWARNEN Warning enable 13 1 read-write CSCTL8 CS Control Register 8 16 16 65535 ACLKREQEN ACLK Clock Request Enable 0 1 read-write MCLKREQEN MCLK Clock Request Enable 1 1 read-write SMCLKREQEN SMCLK Clock Request Enable 2 1 read-write MODOSCREQEN MODOSC Clock Request Enable 3 1 read-write FRAM FRAM 416 FRCTL0 FRAM Controller Control 0 0 16 65535 NWAITS FRAM Wait state control Bit: 0 4 3 read-write NWAITS_0 FRAM Wait state control: 0 0 NWAITS_1 FRAM Wait state control: 1 1 NWAITS_2 FRAM Wait state control: 2 2 NWAITS_3 FRAM Wait state control: 3 3 NWAITS_4 FRAM Wait state control: 4 4 NWAITS_5 FRAM Wait state control: 5 5 NWAITS_6 FRAM Wait state control: 6 6 NWAITS_7 FRAM Wait state control: 7 7 FRCTLPWFRCTLPW Password88FRCTLPWRreadPASSWORDValue always reads from the FRCTL0 register150 FRCTLPWWwritePASSWORDValue which must be written to the FRCTL0 register165 GCCTL0 General Control 0 4 16 65535 FRLPMPWR FRAM Enable FRAM auto power up after LPM 1 1 read-write FRPWR FRAM Power Control 2 1 read-write ACCTEIE RESERVED 3 1 read-write CBDIE Enable NMI event if correctable bit error detected 5 1 read-write UBDIE Enable NMI event if uncorrectable bit error detected 6 1 read-write UBDRSTEN Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected 7 1 read-write GCCTL1 General Control 1 6 16 65535 CBDIFG FRAM correctable bit error flag 1 1 read-write UBDIFG FRAM uncorrectable bit error flag 2 1 read-write ACCTEIFG Access time error flag 3 1 read-write CRC16 CRC16 448 CRCDI CRC Data In Register 0 16 65535 CRCDIRB CRC data in reverse byte Register 2 16 65535 CRCINIRES CRC Initialisation Register and Result Register 4 16 65535 CRCRESR CRC reverse result Register 6 16 65535 WATCHDOG_TIMER Watchdog Timer 460 WDTCTL Watchdog Timer Control 0 16 65535 WDTCNTCL WDT - Timer Clear 3 1 read-write WDTTMSEL WDT - Timer Mode Select 4 1 read-write WDTSSEL WDT - Timer Clock Source Select 0 5 2 read-write WDTSSEL_0 WDT - Timer Clock Source Select: SMCLK 0 WDTSSEL_1 WDT - Timer Clock Source Select: ACLK 1 WDTSSEL_2 WDT - Timer Clock Source Select: VLO_CLK 2 WDTSSEL_3 WDT - Timer Clock Source Select: reserved 3 WDTHOLD WDT - Timer hold 7 1 read-write WDTPWWatchdog Timer Password88WDTPWRreadPASSWORDValue always read from the Watchdog Password register105 WDTPWWwritePASSWORDValue which must be written to the Watchdog Password register90 WDTISWDT - Timer Interval Select 00303 REAL_TIME_CLOCK Real-Time Clock 768 RTCCTL RTC control Register 0 16 65535 RTCIF Low-Power-Counter Interrupt Flag 0 1 read-write RTCIE Low-Power-Counter Interrupt Enable 1 1 read-write RTCSR Low-Power-Counter Software Reset 6 1 read-write RTCPS Low-Power-Counter Clock Pre-divider Select Bit: 0 8 3 read-write RTCPS_0 Low-Power-Counter Clock Pre-divider Select: 0 0 RTCPS_1 Low-Power-Counter Clock Pre-divider Select: 1 1 RTCPS_2 Low-Power-Counter Clock Pre-divider Select: 2 2 RTCPS_3 Low-Power-Counter Clock Pre-divider Select: 3 3 RTCPS_4 Low-Power-Counter Clock Pre-divider Select: 4 4 RTCPS_5 Low-Power-Counter Clock Pre-divider Select: 5 5 RTCPS_6 Low-Power-Counter Clock Pre-divider Select: 6 6 RTCPS_7 Low-Power-Counter Clock Pre-divider Select: 7 7 RTCSS Low-Power-Counter Clock Source Select Bit: 0 12 2 read-write RTCSS_0 Low-Power-Counter Clock Source Select: 0 0 RTCSS_1 Low-Power-Counter Clock Source Select: 1 1 RTCSS_2 Low-Power-Counter Clock Source Select: 2 2 RTCSS_3 Low-Power-Counter Clock Source Select: 3 3 RTCIV RTC interrupt vector 4 16 65535 RTCMOD RTC moduloRegister 8 16 65535 RTCCNT RTC counter Register 12 16 65535 TIMER_0_A3 Timer0_A3 896 TA0CTL Timer0_A3 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA0CCTL0 Timer0_A3 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0CCTL1 Timer0_A3 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0CCTL2 Timer0_A3 Capture/Compare Control 2 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA0R Timer0_A3 16 16 65535 TA0CCR0 Timer0_A3 Capture/Compare 0 18 16 65535 TA0CCR1 Timer0_A3 Capture/Compare 1 20 16 65535 TA0CCR2 Timer0_A3 Capture/Compare 2 22 16 65535 TA0EX0 Timer0_A3 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA0IV Timer0_A3 Interrupt Vector Word 46 16 65535 TIMER_1_A3 Timer1_A3 960 TA1CTL Timer1_A3 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA1CCTL0 Timer1_A3 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA1CCTL1 Timer1_A3 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA1CCTL2 Timer1_A3 Capture/Compare Control 2 6 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA1R Timer1_A3 16 16 65535 TA1CCR0 Timer1_A3 Capture/Compare 0 18 16 65535 TA1CCR1 Timer1_A3 Capture/Compare 1 20 16 65535 TA1CCR2 Timer1_A3 Capture/Compare 2 22 16 65535 TA1EX0 Timer1_A3 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA1IV Timer1_A3 Interrupt Vector Word 46 16 65535 TIMER_2_A2 Timer2_A2 1024 TA2CTL Timer2_A2 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA2CCTL0 Timer2_A2 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA2CCTL1 Timer2_A2 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA2R Timer2_A2 16 16 65535 TA2CCR0 Timer2_A2 Capture/Compare 0 18 16 65535 TA2CCR1 Timer2_A2 Capture/Compare 1 20 16 65535 TA2EX0 Timer2_A2 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA2IV Timer2_A2 Interrupt Vector Word 46 16 65535 TIMER_3_A2 Timer3_A2 1088 TA3CTL Timer3_A2 Control 0 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continuous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TA3CCTL0 Timer3_A2 Capture/Compare Control 0 2 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA3CCTL1 Timer3_A2 Capture/Compare Control 1 4 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TA3R Timer3_A2 16 16 65535 TA3CCR0 Timer3_A2 Capture/Compare 0 18 16 65535 TA3CCR1 Timer3_A2 Capture/Compare 1 20 16 65535 TA3EX0 Timer3_A2 Expansion Register 0 32 16 65535 TAIDEX Timer A Input divider expansion Bit: 0 0 3 read-write TAIDEX_0 Timer A Input divider expansion : /1 0 TAIDEX_1 Timer A Input divider expansion : /2 1 TAIDEX_2 Timer A Input divider expansion : /3 2 TAIDEX_3 Timer A Input divider expansion : /4 3 TAIDEX_4 Timer A Input divider expansion : /5 4 TAIDEX_5 Timer A Input divider expansion : /6 5 TAIDEX_6 Timer A Input divider expansion : /7 6 TAIDEX_7 Timer A Input divider expansion : /8 7 TA3IV Timer3_A2 Interrupt Vector Word 46 16 65535 MPY_16 MPY 16 Multiplier 16 Bit Mode 1216 MPY Multiply Unsigned/Operand 1 0 16 65535 MPYS Multiply Signed/Operand 1 2 16 65535 MAC Multiply Unsigned and Accumulate/Operand 1 4 16 65535 MACS Multiply Signed and Accumulate/Operand 1 6 16 65535 OP2 Operand 2 8 16 65535 RESLO Result Low Word 10 16 65535 RESHI Result High Word 12 16 65535 SUMEXT Sum Extend 14 16 65535 MPY32CTL0 MPY32 Control Register 0 44 16 65535 MPYC Carry of the multiplier 0 1 read-write MPYFRAC Fractional mode 2 1 read-write MPYSAT Saturation mode 3 1 read-write MPYM Multiplier mode Bit:0 4 2 read-write MPYM_0 Multiplier mode: MPY 0 MPYM_1 Multiplier mode: MPYS 1 MPYM_2 Multiplier mode: MAC 2 MPYM_3 Multiplier mode: MACS 3 OP1_32 Bit-width of operand 1 0:16Bit / 1:32Bit 6 1 read-write OP2_32 Bit-width of operand 2 0:16Bit / 1:32Bit 7 1 read-write MPYDLYWRTEN Delayed write enable 8 1 read-write MPYDLY32 Delayed write mode 9 1 read-write MPY_32 MPY 32 Multiplier 32 Bit Mode 1232 MPY32L 32-bit operand 1 - multiply - low word 0 16 65535 MPY32H 32-bit operand 1 - multiply - high word 2 16 65535 MPYS32L 32-bit operand 1 - signed multiply - low word 4 16 65535 MPYS32H 32-bit operand 1 - signed multiply - high word 6 16 65535 MAC32L 32-bit operand 1 - multiply accumulate - low word 8 16 65535 MAC32H 32-bit operand 1 - multiply accumulate - high word 10 16 65535 MACS32L 32-bit operand 1 - signed multiply accumulate - low word 12 16 65535 MACS32H 32-bit operand 1 - signed multiply accumulate - high word 14 16 65535 OP2L 32-bit operand 2 - low word 16 16 65535 OP2H 32-bit operand 2 - high word 18 16 65535 RES0 32x32-bit result 0 - least significant word 20 16 65535 RES1 32x32-bit result 1 22 16 65535 RES2 32x32-bit result 2 24 16 65535 RES3 32x32-bit result 3 - most significant word 26 16 65535 BACKUP_MEMORY Backup Memory 1632 BAKMEM0 Battery Backup Memory 0 0 16 65535 BAKMEM1 Battery Backup Memory 1 2 16 65535 BAKMEM2 Battery Backup Memory 2 4 16 65535 BAKMEM3 Battery Backup Memory 3 6 16 65535 BAKMEM4 Battery Backup Memory 4 8 16 65535 BAKMEM5 Battery Backup Memory 5 10 16 65535 BAKMEM6 Battery Backup Memory 6 12 16 65535 BAKMEM7 Battery Backup Memory 7 14 16 65535 BAKMEM8 Battery Backup Memory 8 16 16 65535 BAKMEM9 Battery Backup Memory 9 18 16 65535 BAKMEM10 Battery Backup Memory 10 20 16 65535 BAKMEM11 Battery Backup Memory 11 22 16 65535 BAKMEM12 Battery Backup Memory 12 24 16 65535 BAKMEM13 Battery Backup Memory 13 26 16 65535 BAKMEM14 Battery Backup Memory 14 28 16 65535 BAKMEM15 Battery Backup Memory 15 30 16 65535 ADC ADC 1792 ADCCTL0 ADC Control 0 0 16 65535 ADCSC ADC Start Conversion 0 1 read-write ADCENC ADC Enable Conversion 1 1 read-write ADCON ADC On/enable 4 1 read-write ADCMSC ADC Multiple SampleConversion 7 1 read-write ADCSHT ADC Sample Hold Select Bit: 0 8 4 read-write ADCSHT_0 ADC Sample Hold Select 0 0 ADCSHT_1 ADC Sample Hold Select 1 1 ADCSHT_2 ADC Sample Hold Select 2 2 ADCSHT_3 ADC Sample Hold Select 3 3 ADCSHT_4 ADC Sample Hold Select 4 4 ADCSHT_5 ADC Sample Hold Select 5 5 ADCSHT_6 ADC Sample Hold Select 6 6 ADCSHT_7 ADC Sample Hold Select 7 7 ADCSHT_8 ADC Sample Hold Select 8 8 ADCSHT_9 ADC Sample Hold Select 9 9 ADCSHT_10 ADC Sample Hold Select 10 10 ADCSHT_11 ADC Sample Hold Select 11 11 ADCSHT_12 ADC Sample Hold Select 12 12 ADCSHT_13 ADC Sample Hold Select 13 13 ADCSHT_14 ADC Sample Hold Select 14 14 ADCSHT_15 ADC Sample Hold Select 15 15 ADCCTL1 ADC Control 1 2 16 65535 ADCBUSY ADC Busy 0 1 read-write ADCCONSEQ ADC Conversion Sequence Select 0 1 2 read-write ADCCONSEQ_0 ADC Conversion Sequence Select: 0 0 ADCCONSEQ_1 ADC Conversion Sequence Select: 1 1 ADCCONSEQ_2 ADC Conversion Sequence Select: 2 2 ADCCONSEQ_3 ADC Conversion Sequence Select: 3 3 ADCSSEL ADC Clock Source Select 0 3 2 read-write ADCSSEL_0 ADC Clock Source Select: 0 0 ADCSSEL_1 ADC Clock Source Select: 1 1 ADCSSEL_2 ADC Clock Source Select: 2 2 ADCSSEL_3 ADC Clock Source Select: 3 3 ADCDIV ADC Clock Divider Select 0 5 3 read-write ADCDIV_0 ADC Clock Divider Select: 0 0 ADCDIV_1 ADC Clock Divider Select: 1 1 ADCDIV_2 ADC Clock Divider Select: 2 2 ADCDIV_3 ADC Clock Divider Select: 3 3 ADCDIV_4 ADC Clock Divider Select: 4 4 ADCDIV_5 ADC Clock Divider Select: 5 5 ADCDIV_6 ADC Clock Divider Select: 6 6 ADCDIV_7 ADC Clock Divider Select: 7 7 ADCISSH ADC Invert Sample Hold Signal 8 1 read-write ADCSHP ADC Sample/Hold Pulse Mode 9 1 read-write ADCSHS ADC Sample/Hold Source 0 10 2 read-write ADCSHS_0 ADC Sample/Hold Source: 0 0 ADCSHS_1 ADC Sample/Hold Source: 1 1 ADCSHS_2 ADC Sample/Hold Source: 2 2 ADCSHS_3 ADC Sample/Hold Source: 3 3 ADCCTL2 ADC Control 2 4 16 65535 ADCSR ADC Sampling Rate 2 1 read-write ADCDF ADC Data Format 3 1 read-write ADCRES ADC Resolution 4 2 read-write ADCRES_0 8 bit 0 ADCRES_1 10 bit 1 ADCRES_2 Reserved 2 ADCRES_3 Reserved 3 ADCPDIV ADC predivider Bit: 0 8 2 read-write ADCPDIV_0 ADC predivider /1 0 ADCPDIV_1 ADC predivider /2 1 ADCPDIV_2 ADC predivider /64 2 ADCPDIV_3 ADC predivider reserved 3 ADCLO ADC Window Comparator High Threshold 6 16 65535 ADCHI ADC Window Comparator High Threshold 8 16 65535 ADCMCTL0 ADC Memory Control 0 10 16 65535 ADCINCH ADC Input Channel Select Bit 0 0 4 read-write ADCINCH_0 ADC Input Channel 0 0 ADCINCH_1 ADC Input Channel 1 1 ADCINCH_2 ADC Input Channel 2 2 ADCINCH_3 ADC Input Channel 3 3 ADCINCH_4 ADC Input Channel 4 4 ADCINCH_5 ADC Input Channel 5 5 ADCINCH_6 ADC Input Channel 6 6 ADCINCH_7 ADC Input Channel 7 7 ADCINCH_8 ADC Input Channel 8 8 ADCINCH_9 ADC Input Channel 9 9 ADCINCH_10 ADC Input Channel 10 10 ADCINCH_11 ADC Input Channel 11 11 ADCINCH_12 ADC Input Channel 12 12 ADCINCH_13 ADC Input Channel 13 13 ADCINCH_14 ADC Input Channel 14 14 ADCINCH_15 ADC Input Channel 15 15 ADCSREF ADC Select Reference Bit 0 4 3 read-write ADCSREF_0 ADC Select Reference 0 0 ADCSREF_1 ADC Select Reference 1 1 ADCSREF_2 ADC Select Reference 2 2 ADCSREF_3 ADC Select Reference 3 3 ADCSREF_4 ADC Select Reference 4 4 ADCSREF_5 ADC Select Reference 5 5 ADCSREF_6 ADC Select Reference 6 6 ADCSREF_7 ADC Select Reference 7 7 ADCMEM0 ADC Conversion Memory 0 18 16 65535 ADCIE ADC Interrupt Enable 26 16 65535 ADCIE0 ADC Interrupt enable 0 1 read-write ADCINIE ADC Interrupt enable for the inside of window of the Window comparator 1 1 read-write ADCLOIE ADC Interrupt enable for lower threshold of the Window comparator 2 1 read-write ADCHIIE ADC Interrupt enable for upper threshold of the Window comparator 3 1 read-write ADCOVIE ADC ADCMEM overflow Interrupt enable 4 1 read-write ADCTOVIE ADC conversion-time-overflow Interrupt enable 5 1 read-write ADCIFG ADC Interrupt Flag 28 16 65535 ADCIFG0 ADC Interrupt Flag 0 1 read-write ADCINIFG ADC Interrupt Flag for the inside of window of the Window comparator 1 1 read-write ADCLOIFG ADC Interrupt Flag for lower threshold of the Window comparator 2 1 read-write ADCHIIFG ADC Interrupt Flag for upper threshold of the Window comparator 3 1 read-write ADCOVIFG ADC ADCMEM overflow Interrupt Flag 4 1 read-write ADCTOVIFG ADC conversion-time-overflow Interrupt Flag 5 1 read-write ADCIV ADC Interrupt Vector Word 30 16 65535 _INTERRUPTS 65408 PORT2 0xFFDA Port 2 41 PORT1 0xFFDC Port 1 42 ADC 0xFFDE ADC 43 USCI_B0 0xFFE0 USCI B0 Receive/Transmit 44 USCI_A1 0xFFE2 USCI A1 Receive/Transmit 45 USCI_A0 0xFFE4 USCI A0 Receive/Transmit 46 WDT 0xFFE6 Watchdog Timer 47 RTC 0xFFE8 RTC 48 TIMER3_A1 0xFFEA Timer3_A2 CC1, TA 49 TIMER3_A0 0xFFEC Timer3_A2 CC0 50 TIMER2_A1 0xFFEE Timer2_A2 CC1, TA 51 TIMER2_A0 0xFFF0 Timer2_A2 CC0 52 TIMER1_A1 0xFFF2 Timer1_A3 CC1-2, TA 53 TIMER1_A0 0xFFF4 Timer1_A3 CC0 54 TIMER0_A1 0xFFF6 Timer0_A3 CC1-2, TA 55 TIMER0_A0 0xFFE8 Timer0_A3 CC0 56 UNMI 0xFFFA User Non-maskable 57 SYSNMI 0xFFFC System Non-maskable 58 0.3.0 69d35ad