MSP430FR5962 2.1 Texas Instruments MSP430FR59xx Ultra-low power MCU MSP430FR5962 r2p1 little true false 3 false 8 16 16 read-write 0x00000000 0xFFFFFFFF ADC12_B 0x0800 0 10 registers ADC12CTL0 0x0 16 ADC12_B Control 0 ADC12SC [0:0] start conversion 1 0 ADC12SC_0 0x0 No sample-and-conversion-start ADC12SC_1 0x1 Start sample-and-conversion ADC12ENC [1:1] enable conversion 1 1 ADC12ENC_0 0x0 ADC12_B disabled ADC12ENC_1 0x1 ADC12_B enabled ADC12ON [4:4] ADC on 1 4 ADC12ON_0 0x0 ADC12_B off ADC12ON_1 0x1 ADC12_B on ADC12MSC [7:7] sample-and-hold time. 1 7 ADC12MSC_0 0x0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert. ADC12MSC_1 0x1 The incidence of a positive(or for devices first rising edge of the) SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed. ADC12SHT0 [11:8] sample-and-hold time. 4 8 ADC12SHT0_0 0x0 4 ADC12CLK cycles ADC12SHT0_1 0x1 8 ADC12CLK cycles ADC12SHT0_2 0x2 16 ADC12CLK cycles ADC12SHT0_3 0x3 32 ADC12CLK cycles ADC12SHT0_4 0x4 64 ADC12CLK cycles ADC12SHT0_5 0x5 96 ADC12CLK cycles ADC12SHT0_6 0x6 128 ADC12CLK cycles ADC12SHT0_7 0x7 192 ADC12CLK cycles ADC12SHT0_8 0x8 256 ADC12CLK cycles ADC12SHT0_9 0x9 384 ADC12CLK cycles ADC12SHT0_10 0xA 512 ADC12CLK cycles ADC12SHT0_11 0xB Reserved ADC12SHT0_12 0xC Reserved ADC12SHT0_13 0xD Reserved ADC12SHT0_14 0xE Reserved ADC12SHT0_15 0xF Reserved ADC12SHT1 [15:12] sample-and-hold time. 4 12 ADC12SHT1_0 0x0 4 ADC12CLK cycles ADC12SHT1_1 0x1 8 ADC12CLK cycles ADC12SHT1_2 0x2 16 ADC12CLK cycles ADC12SHT1_3 0x3 32 ADC12CLK cycles ADC12SHT1_4 0x4 64 ADC12CLK cycles ADC12SHT1_5 0x5 96 ADC12CLK cycles ADC12SHT1_6 0x6 128 ADC12CLK cycles ADC12SHT1_7 0x7 192 ADC12CLK cycles ADC12SHT1_8 0x8 256 ADC12CLK cycles ADC12SHT1_9 0x9 384 ADC12CLK cycles ADC12SHT1_10 0xA 512 ADC12CLK cycles ADC12SHT1_11 0xB Reserved ADC12SHT1_12 0xC Reserved ADC12SHT1_13 0xD Reserved ADC12SHT1_14 0xE Reserved ADC12SHT1_15 0xF Reserved 0 ADC12CTL1 0x2 16 ADC12_B Control 1 ADC12BUSY [0:0] ADC busy 1 0 ADC12BUSY_0 0x0 No operation is active. ADC12BUSY_1 0x1 A sequence, sample, or conversion is active. ADC12CONSEQ [2:1] conversion sequence mode select 2 1 ADC12CONSEQ_0 0x0 Single-channel, single-conversion ADC12CONSEQ_1 0x1 Sequence-of-channels ADC12CONSEQ_2 0x2 Repeat-single-channel ADC12CONSEQ_3 0x3 Repeat-sequence-of-channels ADC12SSEL [4:3] clock source select 2 3 ADC12SSEL_0 0x0 ADC12OSC (MODOSC) ADC12SSEL_1 0x1 ACLK ADC12SSEL_2 0x2 MCLK ADC12SSEL_3 0x3 SMCLK ADC12DIV [7:5] clock divider 3 5 ADC12DIV_0 0x0 /1 ADC12DIV_1 0x1 /2 ADC12DIV_2 0x2 /3 ADC12DIV_3 0x3 /4 ADC12DIV_4 0x4 /5 ADC12DIV_5 0x5 /6 ADC12DIV_6 0x6 /7 ADC12DIV_7 0x7 /8 ADC12ISSH [8:8] invert signal sample-and-hold 1 8 ADC12ISSH_0 0x0 The sample-input signal is not inverted. ADC12ISSH_1 0x1 The sample-input signal is inverted. ADC12SHP [9:9] sample-and-hold pulse-mode select 1 9 ADC12SHP_0 0x0 SAMPCON signal is sourced from the sample-input signal. ADC12SHP_1 0x1 SAMPCON signal is sourced from the sampling timer. ADC12SHS [12:10] sample-and-hold source select 3 10 ADC12SHS_0 0x0 ADC12SC bit ADC12SHS_1 0x1 see the device-specific data sheet for source ADC12SHS_2 0x2 see the device-specific data sheet for source ADC12SHS_3 0x3 see the device-specific data sheet for source ADC12SHS_4 0x4 see the device-specific data sheet for source ADC12SHS_5 0x5 see the device-specific data sheet for source ADC12SHS_6 0x6 see the device-specific data sheet for source ADC12SHS_7 0x7 see the device-specific data sheet for source ADC12PDIV [14:13] predivider 2 13 1 0x0 Predivide by 1 4 0x1 Predivide by 4 32 0x2 Predivide by 32 64 0x3 Predivide by 64 0 ADC12CTL2 0x4 16 ADC12_B Control 2 ADC12PWRMD [0:0] low-power mode 1 0 ADC12PWRMD_0 0x0 Regular power mode where sample rate is not restricted ADC12PWRMD_1 0x1 Low power mode enable, ADC12CLK can not be greater than 1/4 the device-specific data sheet specified maximum for ADC12PWRMD = 0 ADC12DF [3:3] data read-back format 1 3 ADC12DF_0 0x0 Binary unsigned. Theoretically for ADC12DIF = 0 and 12-bit mode the analog input voltage VREF results in 0000h, the analog input voltage + VREF results in 0FFFh. ADC12DF_1 0x1 Signed binary (2s complement), left aligned. Theoretically, for ADC12DIF = 0 and 12-bit mode, the analog input voltage VREF results in 8000h, the analog input voltage + VREF results in 7FF0h. ADC12RES [5:4] resolution 2 4 8BIT 0x0 8 bit (10 clock cycle conversion time) 10BIT 0x1 10 bit (12 clock cycle conversion time) 12BIT 0x2 12 bit (14 clock cycle conversion time) ADC12RES_3 0x3 Reserved 0 ADC12CTL3 0x6 16 ADC12_B Control 3 ADC12CSTARTADD [4:0] conversion start address 5 0 ADC12MEM0 0x0 Conversion start address ADC12MEM0 ADC12MEM1 0x1 Conversion start address ADC12MEM1 ADC12MEM2 0x2 Conversion start address ADC12MEM2 ADC12MEM3 0x3 Conversion start address ADC12MEM3 ADC12MEM4 0x4 Conversion start address ADC12MEM4 ADC12MEM5 0x5 Conversion start address ADC12MEM5 ADC12MEM6 0x6 Conversion start address ADC12MEM6 ADC12MEM7 0x7 Conversion start address ADC12MEM7 ADC12MEM8 0x8 Conversion start address ADC12MEM8 ADC12MEM9 0x9 Conversion start address ADC12MEM9 ADC12MEM10 0xA Conversion start address ADC12MEM10 ADC12MEM11 0xB Conversion start address ADC12MEM10 ADC12MEM12 0xC Conversion start address ADC12MEM12 ADC12MEM13 0xD Conversion start address ADC12MEM13 ADC12MEM14 0xE Conversion start address ADC12MEM14 ADC12MEM15 0xF Conversion start address ADC12MEM15 ADC12MEM16 0x10 Conversion start address ADC12MEM16 ADC12MEM17 0x11 Conversion start address ADC12MEM17 ADC12MEM18 0x12 Conversion start address ADC12MEM18 ADC12MEM19 0x13 Conversion start address ADC12MEM19 ADC12MEM20 0x14 Conversion start address ADC12MEM20 ADC12MEM21 0x15 Conversion start address ADC12MEM21 ADC12MEM22 0x16 Conversion start address ADC12MEM22 ADC12MEM23 0x17 Conversion start address ADC12MEM23 ADC12MEM24 0x18 Conversion start address ADC12MEM24 ADC12MEM25 0x19 Conversion start address ADC12MEM25 ADC12MEM26 0x1A Conversion start address ADC12MEM26 ADC12MEM27 0x1B Conversion start address ADC12MEM27 ADC12MEM28 0x1C Conversion start address ADC12MEM28 ADC12MEM29 0x1D Conversion start address ADC12MEM29 ADC12MEM30 0x1E Conversion start address ADC12MEM30 ADC12MEM31 0x1F Conversion start address ADC12MEM31 ADC12BATMAP [6:6] 1/2 AVCC ADC input channel selection 1 6 ADC12BATMAP_0 0x0 external pin is selected for ADC input channel A31 ADC12BATMAP_1 0x1 ADC internal 1/2 x AVCC channel is selected for ADC input channel A31 ADC12TCMAP [7:7] temperature sensor ADC input channel selection 1 7 ADC12TCMAP_0 0x0 external pin is selected for ADC input channel A30 ADC12TCMAP_1 0x1 ADC internal temperature sensor channel is selected for ADC input channel A30 ADC12ICH0MAP [8:8] int ch 0 sel to ADC in ch A29 1 8 ADC12ICH0MAP_0 0x0 external pin is selected for ADC input channel A29 ADC12ICH0MAP_1 0x1 ADC input channel internal 0 is selected for ADC input channel A29, see device-specific data sheet for availability ADC12ICH1MAP [9:9] int ch 1 sel to ADC in ch A28 1 9 ADC12ICH1MAP_0 0x0 external pin is selected for ADC input channel A28 ADC12ICH1MAP_1 0x1 ADC input channel internal 1 is selected for ADC input channel A28, see device-specific data sheet for availability ADC12ICH2MAP [10:10] int ch 2 sel to ADC in ch A27 1 10 ADC12ICH2MAP_0 0x0 external pin is selected for ADC input channel A27 ADC12ICH2MAP_1 0x1 ADC input channel internal 2 is selected for ADC input channel A27, see device-specific data sheet for availability ADC12ICH3MAP [11:11] int ch 3 sel to ADC in ch A26 1 11 ADC12ICH3MAP_0 0x0 external pin is selected for ADC input channel A26 ADC12ICH3MAP_1 0x1 ADC input channel internal 3 is selected for ADC input channel A26, see device-specific data sheet for availability 0 ADC12LO 0x8 16 ADC12_B Window Comparator Low Threshold Register 0 ADC12HI 0xA 16 ADC12_B Window Comparator High Threshold Register 0 ADC12IFGR0 0xC 16 ADC12_B Interrupt Flag 0 ADC12IFG0 [0:0] ADC12MEM0 interrupt flag 1 0 ADC12IFG0_0 0x0 No interrupt pending ADC12IFG0_1 0x1 Interrupt pending ADC12IFG1 [1:1] ADC12MEM1 interrupt flag 1 1 ADC12IFG1_0 0x0 No interrupt pending ADC12IFG1_1 0x1 Interrupt pending ADC12IFG2 [2:2] ADC12MEM2 interrupt flag 1 2 ADC12IFG2_0 0x0 No interrupt pending ADC12IFG2_1 0x1 Interrupt pending ADC12IFG3 [3:3] ADC12MEM3 interrupt flag 1 3 ADC12IFG3_0 0x0 No interrupt pending ADC12IFG3_1 0x1 Interrupt pending ADC12IFG4 [4:4] ADC12MEM4 interrupt flag 1 4 ADC12IFG4_0 0x0 No interrupt pending ADC12IFG4_1 0x1 Interrupt pending ADC12IFG5 [5:5] ADC12MEM5 interrupt flag 1 5 ADC12IFG5_0 0x0 No interrupt pending ADC12IFG5_1 0x1 Interrupt pending ADC12IFG6 [6:6] ADC12MEM6 interrupt flag 1 6 ADC12IFG6_0 0x0 No interrupt pending ADC12IFG6_1 0x1 Interrupt pending ADC12IFG7 [7:7] ADC12MEM7 interrupt flag 1 7 ADC12IFG7_0 0x0 No interrupt pending ADC12IFG7_1 0x1 Interrupt pending ADC12IFG8 [8:8] ADC12MEM8 interrupt flag 1 8 ADC12IFG8_0 0x0 No interrupt pending ADC12IFG8_1 0x1 Interrupt pending ADC12IFG9 [9:9] ADC12MEM9 interrupt flag 1 9 ADC12IFG9_0 0x0 No interrupt pending ADC12IFG9_1 0x1 Interrupt pending ADC12IFG10 [10:10] ADC12MEM10 interrupt flag 1 10 ADC12IFG10_0 0x0 No interrupt pending ADC12IFG10_1 0x1 Interrupt pending ADC12IFG11 [11:11] ADC12MEM11 interrupt flag 1 11 ADC12IFG11_0 0x0 No interrupt pending ADC12IFG11_1 0x1 Interrupt pending ADC12IFG12 [12:12] ADC12MEM12 interrupt flag 1 12 ADC12IFG12_0 0x0 No interrupt pending ADC12IFG12_1 0x1 Interrupt pending ADC12IFG13 [13:13] ADC12MEM13 interrupt flag 1 13 ADC12IFG13_0 0x0 No interrupt pending ADC12IFG13_1 0x1 Interrupt pending ADC12IFG14 [14:14] ADC12MEM14 interrupt flag 1 14 ADC12IFG14_0 0x0 No interrupt pending ADC12IFG14_1 0x1 Interrupt pending ADC12IFG15 [15:15] ADC12MEM15 interrupt flag 1 15 ADC12IFG15_0 0x0 No interrupt pending ADC12IFG15_1 0x1 Interrupt pending 0 ADC12IFGR1 0xE 16 ADC12_B Interrupt Flag 1 ADC12IFG16 [0:0] ADC12MEM16 interrupt flag 1 0 ADC12IFG16_0 0x0 No interrupt pending ADC12IFG16_1 0x1 Interrupt pending ADC12IFG17 [1:1] ADC12MEM17 interrupt flag 1 1 ADC12IFG17_0 0x0 No interrupt pending ADC12IFG17_1 0x1 Interrupt pending ADC12IFG18 [2:2] ADC12MEM18 interrupt flag 1 2 ADC12IFG18_0 0x0 No interrupt pending ADC12IFG18_1 0x1 Interrupt pending ADC12IFG19 [3:3] ADC12MEM19 interrupt flag 1 3 ADC12IFG19_0 0x0 No interrupt pending ADC12IFG19_1 0x1 Interrupt pending ADC12IFG20 [4:4] ADC12MEM20 interrupt flag 1 4 ADC12IFG20_0 0x0 No interrupt pending ADC12IFG20_1 0x1 Interrupt pending ADC12IFG21 [5:5] ADC12MEM21 interrupt flag 1 5 ADC12IFG21_0 0x0 No interrupt pending ADC12IFG21_1 0x1 Interrupt pending ADC12IFG22 [6:6] ADC12MEM22 interrupt flag 1 6 ADC12IFG22_0 0x0 No interrupt pending ADC12IFG22_1 0x1 Interrupt pending ADC12IFG23 [7:7] ADC12MEM23 interrupt flag 1 7 ADC12IFG23_0 0x0 No interrupt pending ADC12IFG23_1 0x1 Interrupt pending ADC12IFG24 [8:8] ADC12MEM24 interrupt flag 1 8 ADC12IFG24_0 0x0 No interrupt pending ADC12IFG24_1 0x1 Interrupt pending ADC12IFG25 [9:9] ADC12MEM25 interrupt flag 1 9 ADC12IFG25_0 0x0 No interrupt pending ADC12IFG25_1 0x1 Interrupt pending ADC12IFG26 [10:10] ADC12MEM26 interrupt flag 1 10 ADC12IFG26_0 0x0 No interrupt pending ADC12IFG26_1 0x1 Interrupt pending ADC12IFG27 [11:11] ADC12MEM27 interrupt flag 1 11 ADC12IFG27_0 0x0 No interrupt pending ADC12IFG27_1 0x1 Interrupt pending ADC12IFG28 [12:12] ADC12MEM28 interrupt flag 1 12 ADC12IFG28_0 0x0 No interrupt pending ADC12IFG28_1 0x1 Interrupt pending ADC12IFG29 [13:13] ADC12MEM29 interrupt flag 1 13 ADC12IFG29_0 0x0 No interrupt pending ADC12IFG29_1 0x1 Interrupt pending ADC12IFG30 [14:14] ADC12MEM30 interrupt flag 1 14 ADC12IFG30_0 0x0 No interrupt pending ADC12IFG30_1 0x1 Interrupt pending ADC12IFG31 [15:15] ADC12MEM31 interrupt flag 1 15 ADC12IFG31_0 0x0 No interrupt pending ADC12IFG31_1 0x1 Interrupt pending 0 ADC12IFGR2 0x10 16 ADC12_B Interrupt Flag 2 ADC12INIFG [1:1] Interrupt flag for ADC12MEMx between ADC12HI and ADC12LO 1 1 ADC12INIFG_0 0x0 No interrupt pending ADC12INIFG_1 0x1 Interrupt pending ADC12LOIFG [2:2] Interrupt flag for ADC12MEMx ADC12LO 1 2 ADC12LOIFG_0 0x0 No interrupt pending ADC12LOIFG_1 0x1 Interrupt pending ADC12HIIFG [3:3] Interrupt flag for ADC12MEMx ADC12HI 1 3 ADC12HIIFG_0 0x0 No interrupt pending ADC12HIIFG_1 0x1 Interrupt pending ADC12OVIFG [4:4] ADC12MEMx overflow-interrupt flag. 1 4 ADC12OVIFG_0 0x0 No interrupt pending ADC12OVIFG_1 0x1 Interrupt pending ADC12TOVIFG [5:5] conversion-time-overflow interrupt flag 1 5 ADC12TOVIFG_0 0x0 No interrupt pending ADC12TOVIFG_1 0x1 Interrupt pending ADC12RDYIFG [6:6] reference buffer ready interrupt flag 1 6 ADC12RDYIFG_0 0x0 No interrupt pending ADC12RDYIFG_1 0x1 Interrupt pending 0 ADC12IER0 0x12 16 ADC12_B Interrupt Enable 0 ADC12IE0 [0:0] Interrupt enable 0 1 0 ADC12IE0_0 0x0 Interrupt disabled ADC12IE0_1 0x1 Interrupt enabled ADC12IE1 [1:1] interrupt enable 1 1 1 ADC12IE1_0 0x0 Interrupt disabled ADC12IE1_1 0x1 Interrupt enabled ADC12IE2 [2:2] interrupt enable 2 1 2 ADC12IE2_0 0x0 Interrupt disabled ADC12IE2_1 0x1 Interrupt enabled ADC12IE3 [3:3] interrupt enable 3 1 3 ADC12IE3_0 0x0 Interrupt disabled ADC12IE3_1 0x1 Interrupt enabled ADC12IE4 [4:4] interrupt enable 4 1 4 ADC12IE4_0 0x0 Interrupt disabled ADC12IE4_1 0x1 Interrupt enabled ADC12IE5 [5:5] interrupt enable 5 1 5 ADC12IE5_0 0x0 Interrupt disabled ADC12IE5_1 0x1 Interrupt enabled ADC12IE6 [6:6] interrupt enable 6 1 6 ADC12IE6_0 0x0 Interrupt disabled ADC12IE6_1 0x1 Interrupt enabled ADC12IE7 [7:7] interrupt enable 7 1 7 ADC12IE7_0 0x0 Interrupt disabled ADC12IE7_1 0x1 Interrupt enabled ADC12IE8 [8:8] interrupt enable 8 1 8 ADC12IE8_0 0x0 Interrupt disabled ADC12IE8_1 0x1 Interrupt enabled ADC12IE9 [9:9] interrupt enable 9 1 9 ADC12IE9_0 0x0 Interrupt disabled ADC12IE9_1 0x1 Interrupt enabled ADC12IE10 [10:10] interrupt enable 10 1 10 ADC12IE10_0 0x0 Interrupt disabled ADC12IE10_1 0x1 Interrupt enabled ADC12IE11 [11:11] interrupt enable 11 1 11 ADC12IE11_0 0x0 Interrupt disabled ADC12IE11_1 0x1 Interrupt enabled ADC12IE12 [12:12] interrupt enable 12 1 12 ADC12IE12_0 0x0 Interrupt disabled ADC12IE12_1 0x1 Interrupt enabled ADC12IE13 [13:13] interrupt enable 13 1 13 ADC12IE13_0 0x0 Interrupt disabled ADC12IE13_1 0x1 Interrupt enabled ADC12IE14 [14:14] interrupt enable 14 1 14 ADC12IE14_0 0x0 Interrupt disabled ADC12IE14_1 0x1 Interrupt enabled ADC12IE15 [15:15] interrupt enable 15 1 15 ADC12IE15_0 0x0 Interrupt disabled ADC12IE15_1 0x1 Interrupt enabled 0 ADC12IER1 0x14 16 ADC12_B Interrupt Enable 1 ADC12IE16 [0:0] interrupt enable 16 1 0 ADC12IE16_0 0x0 Interrupt disabled ADC12IE16_1 0x1 Interrupt enabled ADC12IE17 [1:1] interrupt enable 17 1 1 ADC12IE17_0 0x0 Interrupt disabled ADC12IE17_1 0x1 Interrupt enabled ADC12IE18 [2:2] interrupt enable 18 1 2 ADC12IE18_0 0x0 Interrupt disabled ADC12IE18_1 0x1 Interrupt enabled ADC12IE19 [3:3] interrupt enable 19 1 3 ADC12IE19_0 0x0 Interrupt disabled ADC12IE19_1 0x1 Interrupt enabled ADC12IE20 [4:4] interrupt enable 19 1 4 ADC12IE20_0 0x0 Interrupt disabled ADC12IE20_1 0x1 Interrupt enabled ADC12IE21 [5:5] interrupt enable 21 1 5 ADC12IE21_0 0x0 Interrupt disabled ADC12IE21_1 0x1 Interrupt enabled ADC12IE22 [6:6] interrupt enable 22 1 6 ADC12IE22_0 0x0 Interrupt disabled ADC12IE22_1 0x1 Interrupt enabled ADC12IE23 [7:7] interrupt enable 23 1 7 ADC12IE23_0 0x0 Interrupt disabled ADC12IE23_1 0x1 Interrupt enabled ADC12IE24 [8:8] interrupt enable 24 1 8 ADC12IE24_0 0x0 Interrupt disabled ADC12IE24_1 0x1 Interrupt enabled ADC12IE25 [9:9] interrupt enable 25 1 9 ADC12IE25_0 0x0 Interrupt disabled ADC12IE25_1 0x1 Interrupt enabled ADC12IE26 [10:10] interrupt enable 26 1 10 ADC12IE26_0 0x0 Interrupt disabled ADC12IE26_1 0x1 Interrupt enabled ADC12IE27 [11:11] interrupt enable 27 1 11 ADC12IE27_0 0x0 Interrupt disabled ADC12IE27_1 0x1 Interrupt enabled ADC12IE28 [12:12] interrupt enable 28 1 12 ADC12IE28_0 0x0 Interrupt disabled ADC12IE28_1 0x1 Interrupt enabled ADC12IE29 [13:13] interrupt enable 29 1 13 ADC12IE29_0 0x0 Interrupt disabled ADC12IE29_1 0x1 Interrupt enabled ADC12IE30 [14:14] interrupt enable 30 1 14 ADC12IE30_0 0x0 Interrupt disabled ADC12IE30_1 0x1 Interrupt enabled ADC12IE31 [15:15] interrupt enable 30 1 15 ADC12IE31_0 0x0 Interrupt disabled ADC12IE31_1 0x1 Interrupt enabled 0 ADC12IER2 0x16 16 ADC12_B Interrupt Enable 2 ADC12INIE [1:1] interrupt enable MEMx between ADC12HI and LO 1 1 ADC12INIE_0 0x0 Interrupt disabled ADC12INIE_1 0x1 Interrupt enabled ADC12LOIE [2:2] interrupt enable MEMx ADC12LO 1 2 ADC12LOIE_0 0x0 Interrupt disabled ADC12LOIE_1 0x1 Interrupt enabled ADC12HIIE [3:3] interrupt enable MEMx ADC12HI 1 3 ADC12HIIE_0 0x0 Interrupt disabled ADC12HIIE_1 0x1 Interrupt enabled ADC12OVIE [4:4] ADC12MEMx overflow-interrupt enable 1 4 ADC12OVIE_0 0x0 Interrupt disabled ADC12OVIE_1 0x1 Interrupt enabled ADC12TOVIE [5:5] conversion-time-overflow interrupt enable 1 5 ADC12TOVIE_0 0x0 Interrupt disabled ADC12TOVIE_1 0x1 Interrupt enabled ADC12RDYIE [6:6] interrupt enable ADC ref buffer ready 1 6 ADC12RDYIE_0 0x0 Interrupt disabled ADC12RDYIE_1 0x1 Interrupt enabled 0 ADC12IV 0x18 16 ADC12_B Interrupt Vector ADC12IV [15:0] interrupt vector value 16 0 NONE 0x0 Interrupt Source: No interrupt pending, Interrupt Flag: None ADC12OVIFG 0x2 Interrupt Source: ADC12MEMx overflow, Interrupt Flag: ADC12OVIFG, Interrupt Priority: Highest ADC12TOVIFG 0x4 Interrupt Source: Conversion time overflow, Interrupt Flag: ADC12TOVIFG ADC12HIIFG 0x6 Interrupt Source: ADC12 window high interrupt flag, Interrupt Flag: ADC12HIIFG ADC12LOIFG 0x8 Interrupt Source: ADC12 window low interrupt flag, Interrupt Flag: ADC12LOIFG ADC12INIFG 0xA Interrupt Source: ADC12 in-window interrupt flag, Interrupt Flag: ADC12INIFG ADC12IFG0 0xC Interrupt Source: ADC12MEM0 interrupt flag, Interrupt Flag: ADC12IFG0 ADC12IFG1 0xE Interrupt Source: ADC12MEM1 interrupt flag, Interrupt Flag: ADC12IFG1 ADC12IFG2 0x10 Interrupt Source: ADC12MEM2 interrupt flag, Interrupt Flag: ADC12IFG2 ADC12IFG3 0x12 Interrupt Source: ADC12MEM3 interrupt flag, Interrupt Flag: ADC12IFG3 ADC12IFG4 0x14 Interrupt Source: ADC12MEM4 interrupt flag, Interrupt Flag: ADC12IFG4 ADC12IFG5 0x16 Interrupt Source: ADC12MEM5 interrupt flag, Interrupt Flag: ADC12IFG5 ADC12IFG6 0x18 Interrupt Source: ADC12MEM6 interrupt flag, Interrupt Flag: ADC12IFG6 ADC12IFG7 0x1A Interrupt Source: ADC12MEM7 interrupt flag, Interrupt Flag: ADC12IFG7 ADC12IFG8 0x1C Interrupt Source: ADC12MEM8 interrupt flag, Interrupt Flag: ADC12IFG8 ADC12IFG9 0x1E Interrupt Source: ADC12MEM9 interrupt flag, Interrupt Flag: ADC12IFG9 ADC12IFG10 0x20 Interrupt Source: ADC12MEM10 interrupt flag, Interrupt Flag: ADC12IFG10 ADC12IFG11 0x22 Interrupt Source: ADC12MEM11 interrupt flag, Interrupt Flag: ADC12IFG11 ADC12IFG12 0x24 Interrupt Source: ADC12MEM12 interrupt flag, Interrupt Flag: ADC12IFG12 ADC12IFG13 0x26 Interrupt Source: ADC12MEM13 interrupt flag, Interrupt Flag: ADC12IFG13 ADC12IFG14 0x28 Interrupt Source: ADC12MEM14 interrupt flag, Interrupt Flag: ADC12IFG14 ADC12IFG15 0x2A Interrupt Source: ADC12MEM15 interrupt flag, Interrupt Flag: ADC12IFG15 ADC12IFG16 0x2C Interrupt Source: ADC12MEM16 interrupt flag, Interrupt Flag: ADC12IFG16 ADC12IFG17 0x2E Interrupt Source: ADC12MEM17 interrupt flag, Interrupt Flag: ADC12IFG17 ADC12IFG18 0x30 Interrupt Source: ADC12MEM18 interrupt flag, Interrupt Flag: ADC12IFG18 ADC12IFG19 0x32 Interrupt Source: ADC12MEM19 interrupt flag, Interrupt Flag: ADC12IFG19 ADC12IFG20 0x34 Interrupt Source: ADC12MEM20 interrupt flag, Interrupt Flag: ADC12IFG20 ADC12IFG21 0x36 Interrupt Source: ADC12MEM21 interrupt flag, Interrupt Flag: ADC12IFG21 ADC12IFG22 0x38 Interrupt Source: ADC12MEM22 interrupt flag, Interrupt Flag: ADC12IFG22 ADC12IFG23 0x3A Interrupt Source: ADC12MEM23 interrupt flag, Interrupt Flag: ADC12IFG23 ADC12IFG24 0x3C Interrupt Source: ADC12MEM24 interrupt flag, Interrupt Flag: ADC12IFG24 ADC12IFG25 0x3E Interrupt Source: ADC12MEM25 interrupt flag, Interrupt Flag: ADC12IFG25 ADC12IFG26 0x40 Interrupt Source: ADC12MEM26 interrupt flag, Interrupt Flag: ADC12IFG26 ADC12IFG27 0x42 Interrupt Source: ADC12MEM27 interrupt flag, Interrupt Flag: ADC12IFG27 ADC12IFG28 0x44 Interrupt Source: ADC12MEM28 interrupt flag, Interrupt Flag: ADC12IFG28 ADC12IFG29 0x46 Interrupt Source: ADC12MEM29 interrupt flag, Interrupt Flag: ADC12IFG29 ADC12IFG30 0x48 Interrupt Source: ADC12MEM30 interrupt flag, Interrupt Flag: ADC12IFG30 ADC12IFG31 0x4A Interrupt Source: ADC12MEM31 interrupt flag, Interrupt Flag: ADC12IFG31 ADC12RDYIFG 0x4C Interrupt Source: ADC12RDYIFG interrupt flag, Interrupt Flag: ADC12RDYIFG 0 ADC12MCTL0 0x20 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL1 0x22 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL2 0x24 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL3 0x26 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL4 0x28 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL5 0x2A 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL6 0x2C 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL7 0x2E 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL8 0x30 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL9 0x32 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL10 0x34 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL11 0x36 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL12 0x38 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL13 0x3A 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL14 0x3C 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL15 0x3E 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL16 0x40 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL17 0x42 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL18 0x44 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL19 0x46 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL20 0x48 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL21 0x4A 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL22 0x4C 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL23 0x4E 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL24 0x50 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL25 0x52 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL26 0x54 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL27 0x56 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL28 0x58 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL29 0x5A 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL30 0x5C 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MCTL31 0x5E 16 ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register ADC12INCH [4:0] Input channel select 5 0 ADC12INCH_0 0x0 If ADC12DIF = 0: A0; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_1 0x1 If ADC12DIF = 0: A1; If ADC12DIF = 1: Ain+ = A0, Ain- = A1 ADC12INCH_2 0x2 If ADC12DIF = 0: A2; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_3 0x3 If ADC12DIF = 0: A3; If ADC12DIF = 1: Ain+ = A2, Ain- = A3 ADC12INCH_4 0x4 If ADC12DIF = 0: A4; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_5 0x5 If ADC12DIF = 0: A5; If ADC12DIF = 1: Ain+ = A4, Ain- = A5 ADC12INCH_6 0x6 If ADC12DIF = 0: A6; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_7 0x7 If ADC12DIF = 0: A7; If ADC12DIF = 1: Ain+ = A6, Ain- = A7 ADC12INCH_8 0x8 If ADC12DIF = 0: A8; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_9 0x9 If ADC12DIF = 0: A9; If ADC12DIF = 1: Ain+ = A8, Ain- = A9 ADC12INCH_10 0xA If ADC12DIF = 0: A10; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_11 0xB If ADC12DIF = 0: A11; If ADC12DIF = 1: Ain+ = A10, Ain- = A11 ADC12INCH_12 0xC If ADC12DIF = 0: A12; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_13 0xD If ADC12DIF = 0: A13; If ADC12DIF = 1: Ain+ = A12, Ain- = A13 ADC12INCH_14 0xE If ADC12DIF = 0: A14; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_15 0xF If ADC12DIF = 0: A15; If ADC12DIF = 1: Ain+ = A14, Ain- = A15 ADC12INCH_16 0x10 If ADC12DIF = 0: A16; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_17 0x11 If ADC12DIF = 0: A17; If ADC12DIF = 1: Ain+ = A16, Ain- = A17 ADC12INCH_18 0x12 If ADC12DIF = 0: A18; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_19 0x13 If ADC12DIF = 0: A19; If ADC12DIF = 1: Ain+ = A18, Ain- = A19 ADC12INCH_20 0x14 If ADC12DIF = 0: A20; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_21 0x15 If ADC12DIF = 0: A21; If ADC12DIF = 1: Ain+ = A20, Ain- = A21 ADC12INCH_22 0x16 If ADC12DIF = 0: A22; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_23 0x17 If ADC12DIF = 0: A23; If ADC12DIF = 1: Ain+ = A22, Ain- = A23 ADC12INCH_24 0x18 If ADC12DIF = 0: A24; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_25 0x19 If ADC12DIF = 0: A25; If ADC12DIF = 1: Ain+ = A24, Ain- = A25 ADC12INCH_26 0x1A If ADC12DIF = 0: A26; If ADC12DIF = 1: Ain+ = A26, Ain- =A27 ADC12INCH_27 0x1B If ADC12DIF = 0: A27; If ADC12DIF = 1: Ain+ = A26, Ain- = A27 ADC12INCH_28 0x1C If ADC12DIF = 0: A28; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_29 0x1D If ADC12DIF = 0: A29; If ADC12DIF = 1: Ain+ = A28, Ain- = A29 ADC12INCH_30 0x1E If ADC12DIF = 0: A30; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12INCH_31 0x1F If ADC12DIF = 0: A31; If ADC12DIF = 1: Ain+ = A30, Ain- = A31 ADC12EOS [7:7] End of sequence 1 7 ADC12EOS_0 0x0 Not end of sequence ADC12EOS_1 0x1 End of sequence ADC12VRSEL [11:8] reference selection 4 8 ADC12VRSEL_0 0x0 VR+ = AVCC, VR- = AVSS ADC12VRSEL_1 0x1 VR+ = VREF buffered, VR- = AVSS ADC12VRSEL_2 0x2 VR+ = VeREF-, VR- = AVSS ADC12VRSEL_3 0x3 VR+ = VeREF+ buffered, VR- = AVSS ADC12VRSEL_4 0x4 VR+ = VeREF+, VR- = AVSS ADC12VRSEL_5 0x5 VR+ = AVCC, VR- = VeREF+ buffered ADC12VRSEL_6 0x6 VR+ = AVCC, VR- = VeREF+ ADC12VRSEL_7 0x7 VR+ = VREF buffered, VR- = VeREF+ ADC12VRSEL_8 0x8 Reserved ADC12VRSEL_9 0x9 VR+ = AVCC, VR- = VREF buffered ADC12VRSEL_10 0xA Reserved ADC12VRSEL_11 0xB VR+ = VeREF+, VR- = VREF buffered ADC12VRSEL_12 0xC VR+ = AVCC, VR- = VeREF- ADC12VRSEL_13 0xD VR+ = VREF buffered, VR- = VeREF- ADC12VRSEL_14 0xE VR+ = VeREF+, VR- = VeREF- ADC12VRSEL_15 0xF VR+ = VeREF+ buffered, VR- = VeREF- ADC12DIF [13:13] Differential mode. 1 13 ADC12DIF_0 0x0 Single-ended mode enabled ADC12DIF_1 0x1 Differential mode enabled ADC12WINC [14:14] Comparator window enable 1 14 ADC12WINC_0 0x0 Comparator window disabled ADC12WINC_1 0x1 Comparator window enabled 0 ADC12MEM0 0x60 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM1 0x62 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM2 0x64 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM3 0x66 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM4 0x68 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM5 0x6A 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM6 0x6C 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM7 0x6E 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM8 0x70 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM9 0x72 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM10 0x74 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM11 0x76 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM12 0x78 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM13 0x7A 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM14 0x7C 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM15 0x7E 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM16 0x80 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM17 0x82 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM18 0x84 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM19 0x86 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM20 0x88 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM21 0x8A 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM22 0x8C 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM23 0x8E 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM24 0x90 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM25 0x92 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM26 0x94 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM27 0x96 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM28 0x98 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM29 0x9A 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM30 0x9C 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 ADC12MEM31 0x9E 16 ADC12_B Memory 0 Register to ADC12_B Memory 31 Register 0 AES256 0x09C0 0 10 registers AESACTL0 0x0 16 AES Accelerator Control Register 0 AESOP [1:0] AES operation 2 0 AESOP_0 0x0 Encryption AESOP_1 0x1 Decryption. The provided key is the same key used for encryption AESOP_2 0x2 Generate first round key required for decryption AESOP_3 0x3 Decryption. The provided key is the first round key required for decryption AESKL [3:2] AES key length 2 2 128 0x0 AES128. The key size is 128 bit 192 0x1 AES192. The key size is 192 bit. 256 0x2 AES256. The key size is 256 bit AESCM [6:5] AES cipher mode select 2 5 ECB 0x0 ECB CBC 0x1 CBC OFB 0x2 OFB CFB 0x3 CFB AESSWRST [7:7] AES software reset 1 7 AESSWRST_0 0x0 No reset RESET 0x1 Reset AES accelerator module AESRDYIFG [8:8] AES ready interrupt flag 1 8 AESRDYIFG_0 0x0 No interrupt pending AESRDYIFG_1 0x1 Interrupt pending AESERRFG [11:11] AES error flag 1 11 AESERRFG_0 0x0 No error AESERRFG_1 0x1 Error occurred AESRDYIE [12:12] AES ready interrupt enable 1 12 DISABLE 0x0 Interrupt disabled ENABLE 0x1 Interrupt enabled AESCMEN [15:15] AES cipher mode enable 1 15 DISABLE 0x0 No DMA triggers are generated ENABLE 0x1 DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated 0 AESACTL1 0x2 16 AES Accelerator Control Register 1 AESBLKCNT [7:0] Cipher Block Counter 8 0 0 AESASTAT 0x4 16 AES Accelerator Status Register AESBUSY [0:0] AES accelerator module busy 1 0 IDLE 0x0 Not busy BUSY 0x1 Busy AESKEYWR [1:1] All 16 bytes written to AESAKEY 1 1 AESKEYWR_0 0x0 Not all bytes written AESKEYWR_1 0x1 All bytes written AESDINWR [2:2] All 16 bytes written to AESADIN, AESAXDIN or AESAXIN 1 2 AESDINWR_0 0x0 Not all bytes written AESDINWR_1 0x1 All bytes written AESDOUTRD [3:3] All 16 bytes read from AESADOUT 1 3 AESDOUTRD_0 0x0 Not all bytes read AESDOUTRD_1 0x1 All bytes read AESKEYCNT [7:4] Bytes written via AESAKEY for AESKL=00, half-words written via AESAKEY 4 4 AESDINCNT [11:8] Bytes written via AESADIN, AESAXDIN or AESAXIN 4 8 AESDOUTCNT [15:12] Bytes read via AESADOUT 4 12 0 AESAKEY 0x6 16 AES Accelerator Key Register AESKEY0 [7:0] AES key byte n when AESAKEY is written as half-word 8 0 AESKEY1 [15:8] AES key byte n+1 when AESAKEY is written as half-word 8 8 0 AESADIN 0x8 16 AES Accelerator Data In Register AESDIN0 [7:0] AES data in byte n when AESADIN is written as half-word 8 0 AESDIN1 [15:8] AES data in byte n+1 when AESADIN is written as half-word 8 8 0 AESADOUT 0xA 16 AES Accelerator Data Out Register AESDOUT0 [7:0] AES data out byte n when AESADOUT is read as half-word 8 0 AESDOUT1 [15:8] AES data out byte n+1 when AESADOUT is read as half-word 8 8 0 AESAXDIN 0xC 16 AES Accelerator XORed Data In Register AESXDIN0 [7:0] AES data in byte n when AESAXDIN is written as half-word 8 0 AESXDIN1 [15:8] AES data in byte n+1 when AESAXDIN is written as half-word 8 8 0 AESAXIN 0xE 16 AES Accelerator XORed Data In Register AESXIN0 [7:0] AES data in byte n when AESAXIN is written as half-word 8 0 AESXIN1 [15:8] AES data in byte n+1 when AESAXIN is written as half-word 8 8 0 CAPTIO0 0x0430 0 10 registers CAPTIO0CTL 0xE 16 Capacitive Touch IO 0 Control Register CAPTIOPISEL0 [3:1] Capacitive Touch IO pin select 3 1 CAPTIOPISEL_0 0x0 Px.0 CAPTIOPISEL_1 0x1 Px.1 CAPTIOPISEL_2 0x2 Px.2 CAPTIOPISEL_3 0x3 Px.3 CAPTIOPISEL_4 0x4 Px.4 CAPTIOPISEL_5 0x5 Px.5 CAPTIOPISEL_6 0x6 Px.6 CAPTIOPISEL_7 0x7 Px.7 CAPTIOPOSEL0 [7:4] Capacitive Touch IO port select 4 4 PJ 0x0 Px = PJ P1 0x1 Px = P1 P2 0x2 Px = P2 P3 0x3 Px = P3 P4 0x4 Px = P4 P5 0x5 Px = P5 P6 0x6 Px = P6 P7 0x7 Px = P7 P8 0x8 Px = P8 P9 0x9 Px = P9 P10 0xA Px = P10 P11 0xB Px = P11 P12 0xC Px = P12 P13 0xD Px = P13 P14 0xE Px = P14 P15 0xF Px = P15 CAPTIOEN [8:8] Capacitive Touch IO enable 1 8 OFF 0x0 All Capacitive Touch IOs are disabled. Signal towards timers is 0. ON 0x1 Selected Capacitive Touch IO is enabled CAPTIO [9:9] Capacitive Touch IO state 1 9 CAPTIO_0 0x0 Curent state 0 or Capacitive Touch IO is disabled CAPTIO_1 0x1 Current state 1 0 CAPTIO1 0x0470 0 10 registers CAPTIO1CTL 0xE 16 Capacitive Touch IO 0 Control Register CAPTIOPISEL1 [3:1] Capacitive Touch IO pin select 3 1 CAPTIOPISEL_0 0x0 Px.0 CAPTIOPISEL_1 0x1 Px.1 CAPTIOPISEL_2 0x2 Px.2 CAPTIOPISEL_3 0x3 Px.3 CAPTIOPISEL_4 0x4 Px.4 CAPTIOPISEL_5 0x5 Px.5 CAPTIOPISEL_6 0x6 Px.6 CAPTIOPISEL_7 0x7 Px.7 CAPTIOPOSEL1 [7:4] Capacitive Touch IO port select 4 4 PJ 0x0 Px = PJ P1 0x1 Px = P1 P2 0x2 Px = P2 P3 0x3 Px = P3 P4 0x4 Px = P4 P5 0x5 Px = P5 P6 0x6 Px = P6 P7 0x7 Px = P7 P8 0x8 Px = P8 P9 0x9 Px = P9 P10 0xA Px = P10 P11 0xB Px = P11 P12 0xC Px = P12 P13 0xD Px = P13 P14 0xE Px = P14 P15 0xF Px = P15 CAPTIOEN [8:8] Capacitive Touch IO enable 1 8 OFF 0x0 All Capacitive Touch IOs are disabled. Signal towards timers is 0. ON 0x1 Selected Capacitive Touch IO is enabled CAPTIO [9:9] Capacitive Touch IO state 1 9 CAPTIO_0 0x0 Curent state 0 or Capacitive Touch IO is disabled CAPTIO_1 0x1 Current state 1 0 COMP_E 0x08C0 0 10 registers CECTL0 0x0 16 Comparator Control Register 0 CEIPSEL [3:0] Channel input selected for the V+ terminal 4 0 CEIPSEL_0 0x0 Channel 0 selected CEIPSEL_1 0x1 Channel 1 selected CEIPSEL_2 0x2 Channel 2 selected CEIPSEL_3 0x3 Channel 3 selected CEIPSEL_4 0x4 Channel 4 selected CEIPSEL_5 0x5 Channel 5 selected CEIPSEL_6 0x6 Channel 6 selected CEIPSEL_7 0x7 Channel 7 selected CEIPSEL_8 0x8 Channel 8 selected CEIPSEL_9 0x9 Channel 9 selected CEIPSEL_10 0xA Channel 10 selected CEIPSEL_11 0xB Channel 11 selected CEIPSEL_12 0xC Channel 12 selected CEIPSEL_13 0xD Channel 13 selected CEIPSEL_14 0xE Channel 14 selected CEIPSEL_15 0xF Channel 15 selected CEIPEN [7:7] Channel input enable for the V+ terminal 1 7 DISABLE 0x0 Selected analog input channel for V+ terminal is disabled ENABLE 0x1 Selected analog input channel for V+ terminal is enabled CEIMSEL [11:8] Channel input selected for the - terminal 4 8 CEIMSEL_0 0x0 Channel 0 selected CEIMSEL_1 0x1 Channel 1 selected CEIMSEL_2 0x2 Channel 2 selected CEIMSEL_3 0x3 Channel 3 selected CEIMSEL_4 0x4 Channel 4 selected CEIMSEL_5 0x5 Channel 5 selected CEIMSEL_6 0x6 Channel 6 selected CEIMSEL_7 0x7 Channel 7 selected CEIMSEL_8 0x8 Channel 8 selected CEIMSEL_9 0x9 Channel 9 selected CEIMSEL_10 0xA Channel 10 selected CEIMSEL_11 0xB Channel 11 selected CEIMSEL_12 0xC Channel 12 selected CEIMSEL_13 0xD Channel 13 selected CEIMSEL_14 0xE Channel 14 selected CEIMSEL_15 0xF Channel 15 selected CEIMEN [15:15] Channel input enable for the - terminal 1 15 DISABLE 0x0 Selected analog input channel for V- terminal is disabled ENABLE 0x1 Selected analog input channel for V- terminal is enabled 0 CECTL1 0x2 16 Comparator Control Register 1 CEOUT [0:0] Comparator output value 1 0 CEOUTPOL [1:1] Comparator output polarity 1 1 CEOUTPOL_0 0x0 Noninverted CEOUTPOL_1 0x1 Inverted CEF [2:2] Comparator output filter 1 2 CEF_0 0x0 Comparator output is not filtered CEF_1 0x1 Comparator output is filtered CEIES [3:3] Interrupt edge select for CEIIFG and CEIFG 1 3 CEIES_0 0x0 Rising edge for CEIFG, falling edge for CEIIFG CEIES_1 0x1 Falling edge for CEIFG, rising edge for CEIIFG CESHORT [4:4] Input short 1 4 CESHORT_0 0x0 Inputs not shorted CESHORT_1 0x1 Inputs shorted CEEX [5:5] Exchange 1 5 CEFDLY [7:6] Filter delay 2 6 CEFDLY_0 0x0 Typical filter delay of TBD (450) ns CEFDLY_1 0x1 Typical filter delay of TBD (900) ns CEFDLY_2 0x2 Typical filter delay of TBD (1800) ns CEFDLY_3 0x3 Typical filter delay of TBD (3600) ns CEPWRMD [9:8] Power Mode 2 8 CEPWRMD_0 0x0 High-speed mode CEPWRMD_1 0x1 Normal mode CEPWRMD_2 0x2 Ultra-low power mode CEON [10:10] Comparator On 1 10 OFF 0x0 Off ON 0x1 On CEMRVL [11:11] This bit is valid of CEMRVS is set to 1 1 11 VREF0 0x0 VREF0 is selected if CERS = 00, 01, or 10 VREF1 0x1 VREF1 is selected if CERS = 00, 01, or 10 CEMRVS [12:12] This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10. 1 12 CEMRVS_0 0x0 Comparator output state selects between VREF0 or VREF1 CEMRVS_1 0x1 CEMRVL selects between VREF0 or VREF1 0 CECTL2 0x4 16 Comparator Control Register 2 CEREF0 [4:0] Reference resistor tap 0 5 0 CERSEL [5:5] Reference select 1 5 CERSEL_0 0x0 When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal CERSEL_1 0x1 When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal CERS [7:6] Reference source 2 6 CERS_0 0x0 No current is drawn by the reference circuitry CERS_1 0x1 VCC applied to the resistor ladder CERS_2 0x2 Shared reference voltage applied to the resistor ladder CERS_3 0x3 Shared reference voltage supplied to V(CREF). Resistor ladder is off CEREF1 [12:8] Reference resistor tap 1 5 8 CEREFL [14:13] Reference voltage level 2 13 OFF 0x0 Reference amplifier is disabled. No reference voltage is requested 1P2V 0x1 1.2 V is selected as shared reference voltage input 2P0V 0x2 2.0 V is selected as shared reference voltage input 2P5V 0x3 2.5 V is selected as shared reference voltage input CEREFACC [15:15] Reference accuracy 1 15 STATIC 0x0 Static mode CLOCKED 0x1 Clocked (low power, low accuracy) mode 0 CECTL3 0x6 16 Comparator Control Register 3 CEPD0 [0:0] Port disable 1 0 CEPD0_0 0x0 The input buffer is enabled CEPD0_1 0x1 The input buffer is disabled CEPD1 [1:1] Port disable 1 1 CEPD1_0 0x0 The input buffer is enabled CEPD1_1 0x1 The input buffer is disabled CEPD2 [2:2] Port disable 1 2 CEPD2_0 0x0 The input buffer is enabled CEPD2_1 0x1 The input buffer is disabled CEPD3 [3:3] Port disable 1 3 CEPD3_0 0x0 The input buffer is enabled CEPD3_1 0x1 The input buffer is disabled CEPD4 [4:4] Port disable 1 4 CEPD4_0 0x0 The input buffer is enabled CEPD4_1 0x1 The input buffer is disabled CEPD5 [5:5] Port disable 1 5 CEPD5_0 0x0 The input buffer is enabled CEPD5_1 0x1 The input buffer is disabled CEPD6 [6:6] Port disable 1 6 CEPD6_0 0x0 The input buffer is enabled CEPD6_1 0x1 The input buffer is disabled CEPD7 [7:7] Port disable 1 7 CEPD7_0 0x0 The input buffer is enabled CEPD7_1 0x1 The input buffer is disabled CEPD8 [8:8] Port disable 1 8 CEPD8_0 0x0 The input buffer is enabled CEPD8_1 0x1 The input buffer is disabled CEPD9 [9:9] Port disable 1 9 CEPD9_0 0x0 The input buffer is enabled CEPD9_1 0x1 The input buffer is disabled CEPD10 [10:10] Port disable 1 10 CEPD10_0 0x0 The input buffer is enabled CEPD10_1 0x1 The input buffer is disabled CEPD11 [11:11] Port disable 1 11 CEPD11_0 0x0 The input buffer is enabled CEPD11_1 0x1 The input buffer is disabled CEPD12 [12:12] Port disable 1 12 CEPD12_0 0x0 The input buffer is enabled CEPD12_1 0x1 The input buffer is disabled CEPD13 [13:13] Port disable 1 13 CEPD13_0 0x0 The input buffer is enabled CEPD13_1 0x1 The input buffer is disabled CEPD14 [14:14] Port disable 1 14 CEPD14_0 0x0 The input buffer is enabled CEPD14_1 0x1 The input buffer is disabled CEPD15 [15:15] Port disable 1 15 CEPD15_0 0x0 The input buffer is enabled CEPD15_1 0x1 The input buffer is disabled 0 CEINT 0xC 16 Comparator Interrupt Control Register CEIFG [0:0] Comparator output interrupt flag 1 0 CEIFG_0 0x0 No interrupt pending CEIFG_1 0x1 Interrupt pending CEIIFG [1:1] Comparator output inverted interrupt flag 1 1 CEIIFG_0 0x0 No interrupt pending CEIIFG_1 0x1 Interrupt pending CERDYIFG [4:4] Comparator ready interrupt flag 1 4 CERDYIFG_0 0x0 No interrupt pending CERDYIFG_1 0x1 Interrupt pending CEIE [8:8] Comparator output interrupt enable 1 8 DISABLE 0x0 Interrupt disabled ENABLE 0x1 Interrupt enabled CEIIE [9:9] Comparator output interrupt enable inverted polarity 1 9 DISABLE 0x0 Interrupt disabled ENABLE 0x1 Interrupt enabled CERDYIE [12:12] Comparator ready interrupt enable 1 12 DISABLE 0x0 Interrupt disabled ENABLE 0x1 Interrupt enabled 0 CEIV 0xE 16 Comparator Interrupt Vector Word Register CEIV [15:0] Comparator interrupt vector word register 16 0 NONE 0x0 No interrupt pending CEIFG 0x2 Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest CEIIFG 0x4 Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG CERDYIFG 0xA Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest 0 CRC 0x0150 0 10 registers CRCDI 0x0 16 CRC Data In 0 CRCDIRB 0x2 16 CRC Data In Reverse Byte 0 CRCINIRES 0x4 16 CRC Initialization and Result 0 CRCRESR 0x6 16 CRC Result Reverse 0 CRC32 0x0980 0 10 registers CRC32DIW0 0x0 16 CRC32 Data Input Word 0 0 CRC32DIW1 0x2 16 CRC32 Data Input Word 1 0 CRC32DIRBW1 0x4 16 CRC32 Data In Reverse Word 1 0 CRC32DIRBW0 0x6 16 CRC32 Data In Reverse Word 0 0 CRC32INIRESW0 0x8 16 CRC32 Initialization and Result Word 0 0 CRC32INIRESW1 0xA 16 CRC32 Initialization and Result Word 1 0 CRC32RESRW1 0xC 16 CRC32 Result Reverse Word 1 0 CRC32RESRW0 0xE 16 CRC32 Result Reverse Word 0 0 CRC16DIW0 0x10 16 CRC16 Data Input 0 CRC16DIRBW0 0x16 16 CRC16 Data In Reverse 0 CRC16INIRESW0 0x18 16 CRC16 Init and Result 0 CRC16RESRW0 0x1E 16 CRC16 Result Reverse 0 CS 0x0160 0 10 registers CSCTL0 0x0 16 Clock System Control 0 CSKEY [15:8] CSKEY password 8 8 0 CSCTL1 0x2 16 Clock System Control 1 DCOFSEL [3:1] DCO frequency select 3 1 DCOFSEL_0 0x0 If DCORSEL = 0: 1 MHz; If DCORSEL = 1: 1 MHz DCOFSEL_1 0x1 If DCORSEL = 0: 2.67 MHz; If DCORSEL = 1: 5.33 MHz DCOFSEL_2 0x2 If DCORSEL = 0: 3.33 MHz; If DCORSEL = 1: 6.67 MHz DCOFSEL_3 0x3 If DCORSEL = 0: 4 MHz; If DCORSEL = 1: 8 MHz DCOFSEL_4 0x4 If DCORSEL = 0: 5.33 MHz; If DCORSEL = 1: 16 MHz DCOFSEL_5 0x5 If DCORSEL = 0: 6.67 MHz; If DCORSEL = 1: 21 MHz DCOFSEL_6 0x6 If DCORSEL = 0: 8 MHz; If DCORSEL = 1: 24 MHz DCOFSEL_7 0x7 If DCORSEL = 0: Reserved. Defaults to 8. It is not recommended to use this setting; If DCORSEL = 1: Reserved. Defaults to 24. It is not recommended to use this setting DCORSEL [6:6] DCO range select 1 6 0 CSCTL2 0x4 16 Clock System Control 2 SELM [2:0] Selects the MCLK source 3 0 LFXTCLK 0x0 LFXTCLK when LFXT available, otherwise VLOCLK VLOCLK 0x1 VLOCLK LFMODCLK 0x2 LFMODCLK DCOCLK 0x3 DCOCLK MODCLK 0x4 MODCLK HFXTCLK 0x5 HFXTCLK when HFXT available, otherwise DCOCLK SELS [6:4] Selects the SMCLK source 3 4 LFXTCLK 0x0 LFXTCLK when LFXT available, otherwise VLOCLK. VLOCLK 0x1 VLOCLK LFMODCLK 0x2 LFMODCLK DCOCLK 0x3 DCOCLK MODCLK 0x4 MODCLK HFXTCLK 0x5 HFXTCLK when HFXT available, otherwise DCOCLK. SELA [10:8] Selects the ACLK source 3 8 LFXTCLK 0x0 LFXTCLK when LFXT available, otherwise VLOCLK. VLOCLK 0x1 VLOCLK LFMODCLK 0x2 LFMODCLK 0 CSCTL3 0x6 16 Clock System Control 3 DIVM [2:0] MCLK source divider 3 0 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 16 0x4 /16 32 0x5 /32 DIVS [6:4] SMCLK source divider 3 4 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 16 0x4 /16 32 0x5 /32 DIVA [10:8] ACLK source divider 3 8 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 16 0x4 /16 32 0x5 /32 0 CSCTL4 0x8 16 Clock System Control 4 LFXTOFF [0:0] LFXT off 1 0 LFXTOFF_0 0x0 LFXT is on if LFXT is selected via the port selection and LFXT is not in bypass mode of operation LFXTOFF_1 0x1 LFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK SMCLKOFF [1:1] SMCLK off 1 1 SMCLKOFF_0 0x0 SMCLK on SMCLKOFF_1 0x1 SMCLK off VLOOFF [3:3] VLO off 1 3 VLOOFF_0 0x0 VLO is on VLOOFF_1 0x1 VLO is off if it is not used as a source for ACLK, MCLK, or SMCLK or if not used as a source for the RTC in LPM3.5 LFXTBYPASS [4:4] LFXT bypass select 1 4 LFXTBYPASS_0 0x0 LFXT sourced from external crystal LFXTBYPASS_1 0x1 LFXT sourced from external clock signal LFXTDRIVE [7:6] LFXT oscillator current 2 6 LFXTDRIVE_0 0x0 Lowest drive strength and current consumption LFXT oscillator LFXTDRIVE_1 0x1 Increased drive strength LFXT oscillator LFXTDRIVE_2 0x2 Increased drive strength LFXT oscillator LFXTDRIVE_3 0x3 Maximum drive strength and maximum current consumption LFXT oscillator HFXTOFF [8:8] Turns off the HFXT oscillator 1 8 HFXTOFF_0 0x0 HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation HFXTOFF_1 0x1 HFXT is off if it is not used as a source for ACLK, MCLK, or SMCLK HFFREQ [11:10] HFXT frequency selection 2 10 HFFREQ_0 0x0 0 to 4 MHz HFFREQ_1 0x1 Greater than 4 MHz to 8 MHz HFFREQ_2 0x2 Greater than 8 MHz to 16 MHz HFFREQ_3 0x3 Greater than 16 MHz to 24 MHz HFXTBYPASS [12:12] HFXT bypass select 1 12 HFXTBYPASS_0 0x0 HFXT sourced from external crystal HFXTBYPASS_1 0x1 HFXT sourced from external clock signal HFXTDRIVE [15:14] HFXT oscillator current 2 14 HFXTDRIVE_0 0x0 Lowest current consumption HFXTDRIVE_1 0x1 Increased drive strength HFXT oscillator HFXTDRIVE_2 0x2 Increased drive strength HFXT oscillator HFXTDRIVE_3 0x3 Maximum drive strength HFXT oscillator 0 CSCTL5 0xA 16 Clock System Control 5 LFXTOFFG [0:0] LFXT oscillator fault flag 1 0 LFXTOFFG_0 0x0 No fault condition occurred after the last reset LFXTOFFG_1 0x1 LFXT fault; an LFXT fault occurred after the last reset HFXTOFFG [1:1] HFXT oscillator fault flag 1 1 HFXTOFFG_0 0x0 No fault condition occurred after the last reset HFXTOFFG_1 0x1 HFXT fault; an HFXT fault occurred after the last reset ENSTFCNT1 [6:6] Enable start counter for LFXT 1 6 DISABLE 0x0 Startup fault counter disabled. Counter is cleared. ENABLE 0x1 Startup fault counter enabled ENSTFCNT2 [7:7] Enable start counter for HFXT 1 7 DISABLE 0x0 Startup fault counter disabled. Counter is cleared. ENABLE 0x1 Startup fault counter enabled 0 CSCTL6 0xC 16 Clock System Control 6 ACLKREQEN [0:0] ACLK clock request enable 1 0 DISABLE 0x0 ACLK conditional requests are disabled ENABLE 0x1 ACLK conditional requests are enabled MCLKREQEN [1:1] MCLK clock request enable 1 1 DISABLE 0x0 MCLK conditional requests are disabled ENABLE 0x1 MCLK conditional requests are enabled SMCLKREQEN [2:2] SMCLK clock request enable 1 2 DISABLE 0x0 SMCLK conditional requests are disabled ENABLE 0x1 SMCLK conditional requests are enabled MODCLKREQEN [3:3] MODCLK clock request enable 1 3 DISABLE 0x0 MODCLK conditional requests are disabled ENABLE 0x1 MODCLK conditional requests are enabled 0 PA 0x0200 0 10 registers PAIN 0x0 16 Port A Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PAOUT 0x2 16 Port A Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PADIR 0x4 16 Port A Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PAREN 0x6 16 Port A Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PASEL0 0xA 16 Port A Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PASEL1 0xC 16 Port A Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PASELC 0x16 16 Port A Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PAIES 0x18 16 Port A Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PAIE 0x1A 16 Port A Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PAIFG 0x1C 16 Port A Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write P1 0x0200 0 10 registers P1IV 0xE 16 Port 1 Interrupt Vector Register P1IV [4:0] Port 1 interrupt vector value 5 0 NONE 0x0 No interrupt pending P1IFG0 0x2 Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest P1IFG1 0x4 Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 P1IFG2 0x6 Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 P1IFG3 0x8 Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 P1IFG4 0xA Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 P1IFG5 0xC Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 P1IFG6 0xE Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 P1IFG7 0x10 Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest 0 P1IN 0x0 8 Port 1 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1OUT 0x2 8 Port 1 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1DIR 0x4 8 Port 1 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1REN 0x6 8 Port 1 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SEL0 0xA 8 Port 1 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SEL1 0xC 8 Port 1 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SELC 0x16 8 Port 1 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IES 0x18 8 Port 1 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IE 0x1A 8 Port 1 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IFG 0x1C 8 Port 1 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2 0x0200 0 10 registers P2IV 0x1E 16 Port 2 Interrupt Vector Register P2IV [4:0] Port 2 interrupt vector value 5 0 NONE 0x0 No interrupt pending P2IFG0 0x2 Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest P2IFG1 0x4 Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 P2IFG2 0x6 Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 P2IFG3 0x8 Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 P2IFG4 0xA Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 P2IFG5 0xC Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 P2IFG6 0xE Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 P2IFG7 0x10 Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest 0 P2IN 0x1 8 Port 2 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2OUT 0x3 8 Port 2 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2DIR 0x5 8 Port 2 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2REN 0x7 8 Port 2 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SEL0 0xB 8 Port 2 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SEL1 0xD 8 Port 2 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SELC 0x17 8 Port 2 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IES 0x19 8 Port 2 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IE 0x1B 8 Port 2 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IFG 0x1D 8 Port 2 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PB 0x0200 0 10 registers PBIN 0x20 16 Port B Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBOUT 0x22 16 Port B Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBDIR 0x24 16 Port B Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBREN 0x26 16 Port B Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBSEL0 0x2A 16 Port B Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBSEL1 0x2C 16 Port B Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBSELC 0x36 16 Port B Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBIES 0x38 16 Port B Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBIE 0x3A 16 Port B Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PBIFG 0x3C 16 Port B Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write P3 0x0200 0 10 registers P3IV 0x2E 16 Port 3 Interrupt Vector Register P3IV [4:0] Port 3 interrupt vector value 5 0 NONE 0x0 No interrupt pending P3IFG0 0x2 Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest P3IFG1 0x4 Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 P3IFG2 0x6 Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 P3IFG3 0x8 Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 P3IFG4 0xA Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 P3IFG5 0xC Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 P3IFG6 0xE Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 P3IFG7 0x10 Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest 0 P3IN 0x20 8 Port 3 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3OUT 0x22 8 Port 3 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3DIR 0x24 8 Port 3 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3REN 0x26 8 Port 3 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3SEL0 0x2A 8 Port 3 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3SEL1 0x2C 8 Port 3 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3SELC 0x36 8 Port 3 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3IES 0x38 8 Port 3 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3IE 0x3A 8 Port 3 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3IFG 0x3C 8 Port 3 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4 0x0200 0 10 registers P4IV 0x3E 16 Port 4 Interrupt Vector Register P4IV [4:0] Port 4 interrupt vector value 5 0 NONE 0x0 No interrupt pending P4IFG0 0x2 Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest P4IFG1 0x4 Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 P4IFG2 0x6 Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 P4IFG3 0x8 Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 P4IFG4 0xA Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 P4IFG5 0xC Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 P4IFG6 0xE Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 P4IFG7 0x10 Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest 0 P4IN 0x21 8 Port 4 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4OUT 0x23 8 Port 4 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4DIR 0x25 8 Port 4 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4REN 0x27 8 Port 4 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4SEL0 0x2B 8 Port 4 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4SEL1 0x2D 8 Port 4 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4SELC 0x37 8 Port 4 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4IES 0x39 8 Port 4 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4IE 0x3B 8 Port 4 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P4IFG 0x3D 8 Port 4 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PC 0x0200 0 10 registers PCIN 0x40 16 Port C Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCOUT 0x42 16 Port C Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCDIR 0x44 16 Port C Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCREN 0x46 16 Port C Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCSEL0 0x4A 16 Port C Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCSEL1 0x4C 16 Port C Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCSELC 0x56 16 Port C Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCIES 0x58 16 Port C Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCIE 0x5A 16 Port C Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PCIFG 0x5C 16 Port C Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write P5 0x0200 0 10 registers P5IV 0x4E 16 Port 5 Interrupt Vector Register P5IV [4:0] Port 5 interrupt vector value 5 0 NONE 0x0 No interrupt pending P5IFG0 0x2 Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest P5IFG1 0x4 Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 P5IFG2 0x6 Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 P5IFG3 0x8 Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 P5IFG4 0xA Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 P5IFG5 0xC Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 P5IFG6 0xE Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 P5IFG7 0x10 Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest 0 P5IN 0x40 8 Port 5 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5OUT 0x42 8 Port 5 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5DIR 0x44 8 Port 5 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5REN 0x46 8 Port 5 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5SEL0 0x4A 8 Port 5 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5SEL1 0x4C 8 Port 5 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5SELC 0x56 8 Port 5 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5IES 0x58 8 Port 5 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5IE 0x5A 8 Port 5 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P5IFG 0x5C 8 Port 5 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6 0x0200 0 10 registers P6IV 0x5E 16 Port 6 Interrupt Vector Register P6IV [4:0] Port 6 interrupt vector value 5 0 NONE 0x0 No interrupt pending P6IFG0 0x2 Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest P6IFG1 0x4 Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 P6IFG2 0x6 Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 P6IFG3 0x8 Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 P6IFG4 0xA Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 P6IFG5 0xC Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 P6IFG6 0xE Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 P6IFG7 0x10 Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest 0 P6IN 0x41 8 Port 6 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6OUT 0x43 8 Port 6 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6DIR 0x45 8 Port 6 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6REN 0x47 8 Port 6 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6SEL0 0x4B 8 Port 6 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6SEL1 0x4D 8 Port 6 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6SELC 0x57 8 Port 6 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6IES 0x59 8 Port 6 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6IE 0x5B 8 Port 6 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P6IFG 0x5D 8 Port 6 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PD 0x0200 0 10 registers PDIN 0x60 16 Port D Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDOUT 0x62 16 Port D Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDDIR 0x64 16 Port D Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDREN 0x66 16 Port D Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDSEL0 0x6A 16 Port D Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDSEL1 0x6C 16 Port D Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDSELC 0x76 16 Port D Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDIES 0x78 16 Port D Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDIE 0x7A 16 Port D Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PDIFG 0x7C 16 Port D Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write P7 0x0200 0 10 registers P7IV 0x6E 16 Port 7 Interrupt Vector Register P7IV [4:0] Port 7 interrupt vector value 5 0 NONE 0x0 No interrupt pending P7IFG0 0x2 Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest P7IFG1 0x4 Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 P7IFG2 0x6 Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 P7IFG3 0x8 Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 P7IFG4 0xA Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 P7IFG5 0xC Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 P7IFG6 0xE Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 P7IFG7 0x10 Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest 0 P7IN 0x60 8 Port 7 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7OUT 0x62 8 Port 7 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7DIR 0x64 8 Port 7 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7REN 0x66 8 Port 7 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7SEL0 0x6A 8 Port 7 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7SEL1 0x6C 8 Port 7 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7SELC 0x76 8 Port 7 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7IES 0x78 8 Port 7 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7IE 0x7A 8 Port 7 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P7IFG 0x7C 8 Port 7 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 0x0200 0 10 registers P8IV 0x7E 16 Port 8 Interrupt Vector Register P8IV [4:0] Port 8 interrupt vector value 5 0 NONE 0x0 No interrupt pending P8IFG0 0x2 Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest P8IFG1 0x4 Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 P8IFG2 0x6 Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 P8IFG3 0x8 Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 P8IFG4 0xA Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 P8IFG5 0xC Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 P8IFG6 0xE Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 P8IFG7 0x10 Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest 0 P8IN 0x61 8 Port 8 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8OUT 0x63 8 Port 8 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8DIR 0x65 8 Port 8 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8REN 0x67 8 Port 8 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8SEL0 0x6B 8 Port 8 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8SEL1 0x6D 8 Port 8 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8SELC 0x77 8 Port 8 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8IES 0x79 8 Port 8 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8IE 0x7B 8 Port 8 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8IFG 0x7D 8 Port 8 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PE 0x0200 0 10 registers PEIN 0x80 16 Port E Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PEOUT 0x82 16 Port E Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PEDIR 0x84 16 Port E Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PEREN 0x86 16 Port E Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PESEL0 0x8A 16 Port E Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PESEL1 0x8C 16 Port E Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PESELC 0x96 16 Port E Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PEIES 0x98 16 Port E Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PEIE 0x9A 16 Port E Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PEIFG 0x9C 16 Port E Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write P9 0x0200 0 10 registers P9IV 0x8E 16 Port 9 Interrupt Vector Register P9IV [4:0] Port 9 interrupt vector value 5 0 NONE 0x0 No interrupt pending P9IFG0 0x2 Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest P9IFG1 0x4 Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 P9IFG2 0x6 Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 P9IFG3 0x8 Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 P9IFG4 0xA Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 P9IFG5 0xC Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 P9IFG6 0xE Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 P9IFG7 0x10 Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest 0 P9IN 0x80 8 Port 9 Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9OUT 0x82 8 Port 9 Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9DIR 0x84 8 Port 9 Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9REN 0x86 8 Port 9 Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9SEL0 0x8A 8 Port 9 Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9SEL1 0x8C 8 Port 9 Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9SELC 0x96 8 Port 9 Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9IES 0x98 8 Port 9 Interrupt Edge Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9IE 0x9A 8 Port 9 Interrupt Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P9IFG 0x9C 8 Port 9 Interrupt Flag 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write PJ 0x0200 0 10 registers PJIN 0x120 16 Port J Input 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PJOUT 0x122 16 Port J Output 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PJDIR 0x124 16 Port J Direction 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PJREN 0x126 16 Port J Resistor Enable 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PJSEL0 0x12A 16 Port J Select 0 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PJSEL1 0x12C 16 Port J Select 1 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write PJSELC 0x136 16 Port J Complement Select 0 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P8 P8 8 1 read-write P9 P9 9 1 read-write P10 P10 10 1 read-write P11 P11 11 1 read-write P12 P12 12 1 read-write P13 P13 13 1 read-write P14 P14 14 1 read-write P15 P15 15 1 read-write DMA 0x0500 0 10 registers DMACTL0 0x0 16 DMA Control 0 DMA0TSEL [4:0] DMA trigger select 5 0 DMA0TRIG0 0x0 DMA0TRIG0 DMA0TRIG1 0x1 DMA0TRIG1 DMA0TRIG2 0x2 DMA0TRIG2 DMA0TRIG3 0x3 DMA0TRIG3 DMA0TRIG4 0x4 DMA0TRIG4 DMA0TRIG5 0x5 DMA0TRIG5 DMA0TRIG6 0x6 DMA0TRIG6 DMA0TRIG7 0x7 DMA0TRIG7 DMA0TRIG8 0x8 DMA0TRIG8 DMA0TRIG9 0x9 DMA0TRIG9 DMA0TRIG10 0xA DMA0TRIG10 DMA0TRIG11 0xB DMA0TRIG11 DMA0TRIG12 0xC DMA0TRIG12 DMA0TRIG13 0xD DMA0TRIG13 DMA0TRIG14 0xE DMA0TRIG14 DMA0TRIG15 0xF DMA0TRIG15 DMA0TRIG16 0x10 DMA0TRIG16 DMA0TRIG17 0x11 DMA0TRIG17 DMA0TRIG18 0x12 DMA0TRIG18 DMA0TRIG19 0x13 DMA0TRIG19 DMA0TRIG20 0x14 DMA0TRIG20 DMA0TRIG21 0x15 DMA0TRIG21 DMA0TRIG22 0x16 DMA0TRIG22 DMA0TRIG23 0x17 DMA0TRIG23 DMA0TRIG24 0x18 DMA0TRIG24 DMA0TRIG25 0x19 DMA0TRIG25 DMA0TRIG26 0x1A DMA0TRIG26 DMA0TRIG27 0x1B DMA0TRIG27 DMA0TRIG28 0x1C DMA0TRIG28 DMA0TRIG29 0x1D DMA0TRIG29 DMA0TRIG30 0x1E DMA0TRIG30 DMA0TRIG31 0x1F DMA0TRIG31 DMA1TSEL [12:8] DMA trigger select 5 8 DMA1TRIG0 0x0 DMA1TRIG0 DMA1TRIG1 0x1 DMA1TRIG1 DMA1TRIG2 0x2 DMA1TRIG2 DMA1TRIG3 0x3 DMA1TRIG3 DMA1TRIG4 0x4 DMA1TRIG4 DMA1TRIG5 0x5 DMA1TRIG5 DMA1TRIG6 0x6 DMA1TRIG6 DMA1TRIG7 0x7 DMA1TRIG7 DMA1TRIG8 0x8 DMA1TRIG8 DMA1TRIG9 0x9 DMA1TRIG9 DMA1TRIG10 0xA DMA1TRIG10 DMA1TRIG11 0xB DMA1TRIG11 DMA1TRIG12 0xC DMA1TRIG12 DMA1TRIG13 0xD DMA1TRIG13 DMA1TRIG14 0xE DMA1TRIG14 DMA1TRIG15 0xF DMA1TRIG15 DMA1TRIG16 0x10 DMA1TRIG16 DMA1TRIG17 0x11 DMA1TRIG17 DMA1TRIG18 0x12 DMA1TRIG18 DMA1TRIG19 0x13 DMA1TRIG19 DMA1TRIG20 0x14 DMA1TRIG20 DMA1TRIG21 0x15 DMA1TRIG21 DMA1TRIG22 0x16 DMA1TRIG22 DMA1TRIG23 0x17 DMA1TRIG23 DMA1TRIG24 0x18 DMA1TRIG24 DMA1TRIG25 0x19 DMA1TRIG25 DMA1TRIG26 0x1A DMA1TRIG26 DMA1TRIG27 0x1B DMA1TRIG27 DMA1TRIG28 0x1C DMA1TRIG28 DMA1TRIG29 0x1D DMA1TRIG29 DMA1TRIG30 0x1E DMA1TRIG30 DMA1TRIG31 0x1F DMA1TRIG31 0 DMACTL1 0x2 16 DMA Control 1 DMA2TSEL [4:0] DMA trigger select 5 0 DMA2TRIG0 0x0 DMA2TRIG0 DMA2TRIG1 0x1 DMA2TRIG1 DMA2TRIG2 0x2 DMA2TRIG2 DMA2TRIG3 0x3 DMA2TRIG3 DMA2TRIG4 0x4 DMA2TRIG4 DMA2TRIG5 0x5 DMA2TRIG5 DMA2TRIG6 0x6 DMA2TRIG6 DMA2TRIG7 0x7 DMA2TRIG7 DMA2TRIG8 0x8 DMA2TRIG8 DMA2TRIG9 0x9 DMA2TRIG9 DMA2TRIG10 0xA DMA2TRIG10 DMA2TRIG11 0xB DMA2TRIG11 DMA2TRIG12 0xC DMA2TRIG12 DMA2TRIG13 0xD DMA2TRIG13 DMA2TRIG14 0xE DMA2TRIG14 DMA2TRIG15 0xF DMA2TRIG15 DMA2TRIG16 0x10 DMA2TRIG16 DMA2TRIG17 0x11 DMA2TRIG17 DMA2TRIG18 0x12 DMA2TRIG18 DMA2TRIG19 0x13 DMA2TRIG19 DMA2TRIG20 0x14 DMA2TRIG20 DMA2TRIG21 0x15 DMA2TRIG21 DMA2TRIG22 0x16 DMA2TRIG22 DMA2TRIG23 0x17 DMA2TRIG23 DMA2TRIG24 0x18 DMA2TRIG24 DMA2TRIG25 0x19 DMA2TRIG25 DMA2TRIG26 0x1A DMA2TRIG26 DMA2TRIG27 0x1B DMA2TRIG27 DMA2TRIG28 0x1C DMA2TRIG28 DMA2TRIG29 0x1D DMA2TRIG29 DMA2TRIG30 0x1E DMA2TRIG30 DMA2TRIG31 0x1F DMA2TRIG31 DMA3TSEL [12:8] DMA trigger select 5 8 DMA3TRIG0 0x0 DMA3TRIG0 DMA3TRIG1 0x1 DMA3TRIG1 DMA3TRIG2 0x2 DMA3TRIG2 DMA3TRIG3 0x3 DMA3TRIG3 DMA3TRIG4 0x4 DMA3TRIG4 DMA3TRIG5 0x5 DMA3TRIG5 DMA3TRIG6 0x6 DMA3TRIG6 DMA3TRIG7 0x7 DMA3TRIG7 DMA3TRIG8 0x8 DMA3TRIG8 DMA3TRIG9 0x9 DMA3TRIG9 DMA3TRIG10 0xA DMA3TRIG10 DMA3TRIG11 0xB DMA3TRIG11 DMA3TRIG12 0xC DMA3TRIG12 DMA3TRIG13 0xD DMA3TRIG13 DMA3TRIG14 0xE DMA3TRIG14 DMA3TRIG15 0xF DMA3TRIG15 DMA3TRIG16 0x10 DMA3TRIG16 DMA3TRIG17 0x11 DMA3TRIG17 DMA3TRIG18 0x12 DMA3TRIG18 DMA3TRIG19 0x13 DMA3TRIG19 DMA3TRIG20 0x14 DMA3TRIG20 DMA3TRIG21 0x15 DMA3TRIG21 DMA3TRIG22 0x16 DMA3TRIG22 DMA3TRIG23 0x17 DMA3TRIG23 DMA3TRIG24 0x18 DMA3TRIG24 DMA3TRIG25 0x19 DMA3TRIG25 DMA3TRIG26 0x1A DMA3TRIG26 DMA3TRIG27 0x1B DMA3TRIG27 DMA3TRIG28 0x1C DMA3TRIG28 DMA3TRIG29 0x1D DMA3TRIG29 DMA3TRIG30 0x1E DMA3TRIG30 DMA3TRIG31 0x1F DMA3TRIG31 0 DMACTL2 0x4 16 DMA Control 2 DMA4TSEL [4:0] DMA trigger select 5 0 DMA4TRIG0 0x0 DMA4TRIG0 DMA4TRIG1 0x1 DMA4TRIG1 DMA4TRIG2 0x2 DMA4TRIG2 DMA4TRIG3 0x3 DMA4TRIG3 DMA4TRIG4 0x4 DMA4TRIG4 DMA4TRIG5 0x5 DMA4TRIG5 DMA4TRIG6 0x6 DMA4TRIG6 DMA4TRIG7 0x7 DMA4TRIG7 DMA4TRIG8 0x8 DMA4TRIG8 DMA4TRIG9 0x9 DMA4TRIG9 DMA4TRIG10 0xA DMA4TRIG10 DMA4TRIG11 0xB DMA4TRIG11 DMA4TRIG12 0xC DMA4TRIG12 DMA4TRIG13 0xD DMA4TRIG13 DMA4TRIG14 0xE DMA4TRIG14 DMA4TRIG15 0xF DMA4TRIG15 DMA4TRIG16 0x10 DMA4TRIG16 DMA4TRIG17 0x11 DMA4TRIG17 DMA4TRIG18 0x12 DMA4TRIG18 DMA4TRIG19 0x13 DMA4TRIG19 DMA4TRIG20 0x14 DMA4TRIG20 DMA4TRIG21 0x15 DMA4TRIG21 DMA4TRIG22 0x16 DMA4TRIG22 DMA4TRIG23 0x17 DMA4TRIG23 DMA4TRIG24 0x18 DMA4TRIG24 DMA4TRIG25 0x19 DMA4TRIG25 DMA4TRIG26 0x1A DMA4TRIG26 DMA4TRIG27 0x1B DMA4TRIG27 DMA4TRIG28 0x1C DMA4TRIG28 DMA4TRIG29 0x1D DMA4TRIG29 DMA4TRIG30 0x1E DMA4TRIG30 DMA4TRIG31 0x1F DMA4TRIG31 DMA5TSEL [12:8] DMA trigger select 5 8 DMA5TRIG0 0x0 DMA5TRIG0 DMA5TRIG1 0x1 DMA5TRIG1 DMA5TRIG2 0x2 DMA5TRIG2 DMA5TRIG3 0x3 DMA5TRIG3 DMA5TRIG4 0x4 DMA5TRIG4 DMA5TRIG5 0x5 DMA5TRIG5 DMA5TRIG6 0x6 DMA5TRIG6 DMA5TRIG7 0x7 DMA5TRIG7 DMA5TRIG8 0x8 DMA5TRIG8 DMA5TRIG9 0x9 DMA5TRIG9 DMA5TRIG10 0xA DMA5TRIG10 DMA5TRIG11 0xB DMA5TRIG11 DMA5TRIG12 0xC DMA5TRIG12 DMA5TRIG13 0xD DMA5TRIG13 DMA5TRIG14 0xE DMA5TRIG14 DMA5TRIG15 0xF DMA5TRIG15 DMA5TRIG16 0x10 DMA5TRIG16 DMA5TRIG17 0x11 DMA5TRIG17 DMA5TRIG18 0x12 DMA5TRIG18 DMA5TRIG19 0x13 DMA5TRIG19 DMA5TRIG20 0x14 DMA5TRIG20 DMA5TRIG21 0x15 DMA5TRIG21 DMA5TRIG22 0x16 DMA5TRIG22 DMA5TRIG23 0x17 DMA5TRIG23 DMA5TRIG24 0x18 DMA5TRIG24 DMA5TRIG25 0x19 DMA5TRIG25 DMA5TRIG26 0x1A DMA5TRIG26 DMA5TRIG27 0x1B DMA5TRIG27 DMA5TRIG28 0x1C DMA5TRIG28 DMA5TRIG29 0x1D DMA5TRIG29 DMA5TRIG30 0x1E DMA5TRIG30 DMA5TRIG31 0x1F DMA5TRIG31 0 DMACTL4 0x8 16 DMA Control 4 ENNMI [0:0] Enable NMI 1 0 ENNMI_0 0x0 NMI does not interrupt DMA transfer ENNMI_1 0x1 NMI interrupts a DMA transfer ROUNDROBIN [1:1] Round robin 1 1 ROUNDROBIN_0 0x0 DMA channel priority is DMA0-DMA1-DMA2 - ... - DMA7 ROUNDROBIN_1 0x1 DMA channel priority changes with each transfer DMARMWDIS [2:2] Read-modify-write disable 1 2 DMARMWDIS_0 0x0 DMA transfers can occur during read-modify-write CPU operations DMARMWDIS_1 0x1 DMA transfers inhibited during read-modify-write CPU operations 0 DMAIV 0xE 16 DMA Interrupt Vector DMAIV [15:0] DMA interrupt vector value 16 0 NONE 0x0 No interrupt pending DMA0IFG 0x2 Interrupt Source: DMA channel 0; Interrupt Flag: DMA0IFG; Interrupt Priority: Highest DMA1IFG 0x4 Interrupt Source: DMA channel 1; Interrupt Flag: DMA1IFG DMA2IFG 0x6 Interrupt Source: DMA channel 2; Interrupt Flag: DMA2IFG DMA3IFG 0x8 Interrupt Source: DMA channel 3; Interrupt Flag: DMA3IFG DMA4IFG 0xA Interrupt Source: DMA channel 4; Interrupt Flag: DMA4IFG DMA5IFG 0xC Interrupt Source: DMA channel 5; Interrupt Flag: DMA5IFG DMA6IFG 0xE Interrupt Source: DMA channel 6; Interrupt Flag: DMA6IFG DMA7IFG 0x10 Interrupt Source: DMA channel 7; Interrupt Flag: DMA7IFG; Interrupt Priority: Lowest 0 DMA0CTL 0x10 16 DMA Channel 0 Control DMAREQ [0:0] DMA request 1 0 DMAREQ_0 0x0 No DMA start DMAREQ_1 0x1 Start DMA DMAABORT [1:1] DMA abort 1 1 DMAABORT_0 0x0 DMA transfer not interrupted DMAABORT_1 0x1 DMA transfer interrupted by NMI DMAIE [2:2] DMA interrupt enable 1 2 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMAIFG [3:3] DMA interrupt flag 1 3 DMAIFG_0 0x0 No interrupt pending DMAIFG_1 0x1 Interrupt pending DMAEN [4:4] DMA enable 1 4 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMALEVEL [5:5] DMA level 1 5 EDGE 0x0 Edge sensitive (rising edge) LEVEL 0x1 Level sensitive (high level) DMASRCBYTE [6:6] DMA source byte 1 6 WORD 0x0 Word BYTE 0x1 Byte DMADSTBYTE [7:7] DMA destination byte 1 7 WORD 0x0 Word BYTE 0x1 Byte DMASRCINCR [9:8] DMA source increment 2 8 DMASRCINCR_0 0x0 Source address is unchanged DMASRCINCR_1 0x1 Source address is unchanged DMASRCINCR_2 0x2 Source address is decremented DMASRCINCR_3 0x3 Source address is incremented DMADSTINCR [11:10] DMA destination increment 2 10 DMADSTINCR_0 0x0 Destination address is unchanged DMADSTINCR_1 0x1 Destination address is unchanged DMADSTINCR_2 0x2 Destination address is decremented DMADSTINCR_3 0x3 Destination address is incremented DMADT [14:12] DMA transfer mode 3 12 DMADT_0 0x0 Single transfer DMADT_1 0x1 Block transfer DMADT_2 0x2 Burst-block transfer DMADT_3 0x3 Burst-block transfer DMADT_4 0x4 Repeated single transfer DMADT_5 0x5 Repeated block transfer DMADT_6 0x6 Repeated burst-block transfer DMADT_7 0x7 Repeated burst-block transfer 0 DMA0SA 0x12 20 DMA Channel 0 Source Address 0 DMA0DA 0x16 20 DMA Channel 0 Destination Address 0 DMA0SZ 0x1A 16 DMA Channel 0 Transfer Size 0 DMA1CTL 0x20 16 DMA Channel 1 Control DMAREQ [0:0] DMA request 1 0 DMAREQ_0 0x0 No DMA start DMAREQ_1 0x1 Start DMA DMAABORT [1:1] DMA abort 1 1 DMAABORT_0 0x0 DMA transfer not interrupted DMAABORT_1 0x1 DMA transfer interrupted by NMI DMAIE [2:2] DMA interrupt enable 1 2 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMAIFG [3:3] DMA interrupt flag 1 3 DMAIFG_0 0x0 No interrupt pending DMAIFG_1 0x1 Interrupt pending DMAEN [4:4] DMA enable 1 4 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMALEVEL [5:5] DMA level 1 5 EDGE 0x0 Edge sensitive (rising edge) LEVEL 0x1 Level sensitive (high level) DMASRCBYTE [6:6] DMA source byte 1 6 WORD 0x0 Word BYTE 0x1 Byte DMADSTBYTE [7:7] DMA destination byte 1 7 WORD 0x0 Word BYTE 0x1 Byte DMASRCINCR [9:8] DMA source increment 2 8 DMASRCINCR_0 0x0 Source address is unchanged DMASRCINCR_1 0x1 Source address is unchanged DMASRCINCR_2 0x2 Source address is decremented DMASRCINCR_3 0x3 Source address is incremented DMADSTINCR [11:10] DMA destination increment 2 10 DMADSTINCR_0 0x0 Destination address is unchanged DMADSTINCR_1 0x1 Destination address is unchanged DMADSTINCR_2 0x2 Destination address is decremented DMADSTINCR_3 0x3 Destination address is incremented DMADT [14:12] DMA transfer mode 3 12 DMADT_0 0x0 Single transfer DMADT_1 0x1 Block transfer DMADT_2 0x2 Burst-block transfer DMADT_3 0x3 Burst-block transfer DMADT_4 0x4 Repeated single transfer DMADT_5 0x5 Repeated block transfer DMADT_6 0x6 Repeated burst-block transfer DMADT_7 0x7 Repeated burst-block transfer 0 DMA1SA 0x22 20 DMA Channel 1 Source Address 0 DMA1DA 0x26 20 DMA Channel 1 Destination Address 0 DMA1SZ 0x2A 16 DMA Channel 1 Transfer Size 0 DMA2CTL 0x30 16 DMA Channel 2 Control DMAREQ [0:0] DMA request 1 0 DMAREQ_0 0x0 No DMA start DMAREQ_1 0x1 Start DMA DMAABORT [1:1] DMA abort 1 1 DMAABORT_0 0x0 DMA transfer not interrupted DMAABORT_1 0x1 DMA transfer interrupted by NMI DMAIE [2:2] DMA interrupt enable 1 2 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMAIFG [3:3] DMA interrupt flag 1 3 DMAIFG_0 0x0 No interrupt pending DMAIFG_1 0x1 Interrupt pending DMAEN [4:4] DMA enable 1 4 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMALEVEL [5:5] DMA level 1 5 EDGE 0x0 Edge sensitive (rising edge) LEVEL 0x1 Level sensitive (high level) DMASRCBYTE [6:6] DMA source byte 1 6 WORD 0x0 Word BYTE 0x1 Byte DMADSTBYTE [7:7] DMA destination byte 1 7 WORD 0x0 Word BYTE 0x1 Byte DMASRCINCR [9:8] DMA source increment 2 8 DMASRCINCR_0 0x0 Source address is unchanged DMASRCINCR_1 0x1 Source address is unchanged DMASRCINCR_2 0x2 Source address is decremented DMASRCINCR_3 0x3 Source address is incremented DMADSTINCR [11:10] DMA destination increment 2 10 DMADSTINCR_0 0x0 Destination address is unchanged DMADSTINCR_1 0x1 Destination address is unchanged DMADSTINCR_2 0x2 Destination address is decremented DMADSTINCR_3 0x3 Destination address is incremented DMADT [14:12] DMA transfer mode 3 12 DMADT_0 0x0 Single transfer DMADT_1 0x1 Block transfer DMADT_2 0x2 Burst-block transfer DMADT_3 0x3 Burst-block transfer DMADT_4 0x4 Repeated single transfer DMADT_5 0x5 Repeated block transfer DMADT_6 0x6 Repeated burst-block transfer DMADT_7 0x7 Repeated burst-block transfer 0 DMA2SA 0x32 20 DMA Channel 2 Source Address 0 DMA2DA 0x36 20 DMA Channel 2 Destination Address 0 DMA2SZ 0x3A 16 DMA Channel 2 Transfer Size 0 DMA3CTL 0x40 16 DMA Channel 3 Control DMAREQ [0:0] DMA request 1 0 DMAREQ_0 0x0 No DMA start DMAREQ_1 0x1 Start DMA DMAABORT [1:1] DMA abort 1 1 DMAABORT_0 0x0 DMA transfer not interrupted DMAABORT_1 0x1 DMA transfer interrupted by NMI DMAIE [2:2] DMA interrupt enable 1 2 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMAIFG [3:3] DMA interrupt flag 1 3 DMAIFG_0 0x0 No interrupt pending DMAIFG_1 0x1 Interrupt pending DMAEN [4:4] DMA enable 1 4 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMALEVEL [5:5] DMA level 1 5 EDGE 0x0 Edge sensitive (rising edge) LEVEL 0x1 Level sensitive (high level) DMASRCBYTE [6:6] DMA source byte 1 6 WORD 0x0 Word BYTE 0x1 Byte DMADSTBYTE [7:7] DMA destination byte 1 7 WORD 0x0 Word BYTE 0x1 Byte DMASRCINCR [9:8] DMA source increment 2 8 DMASRCINCR_0 0x0 Source address is unchanged DMASRCINCR_1 0x1 Source address is unchanged DMASRCINCR_2 0x2 Source address is decremented DMASRCINCR_3 0x3 Source address is incremented DMADSTINCR [11:10] DMA destination increment 2 10 DMADSTINCR_0 0x0 Destination address is unchanged DMADSTINCR_1 0x1 Destination address is unchanged DMADSTINCR_2 0x2 Destination address is decremented DMADSTINCR_3 0x3 Destination address is incremented DMADT [14:12] DMA transfer mode 3 12 DMADT_0 0x0 Single transfer DMADT_1 0x1 Block transfer DMADT_2 0x2 Burst-block transfer DMADT_3 0x3 Burst-block transfer DMADT_4 0x4 Repeated single transfer DMADT_5 0x5 Repeated block transfer DMADT_6 0x6 Repeated burst-block transfer DMADT_7 0x7 Repeated burst-block transfer 0 DMA3SA 0x42 20 DMA Channel 3 Source Address 0 DMA3DA 0x46 20 DMA Channel 3 Destination Address 0 DMA3SZ 0x4A 16 DMA Channel 3 Transfer Size 0 DMA4CTL 0x50 16 DMA Channel 4 Control DMAREQ [0:0] DMA request 1 0 DMAREQ_0 0x0 No DMA start DMAREQ_1 0x1 Start DMA DMAABORT [1:1] DMA abort 1 1 DMAABORT_0 0x0 DMA transfer not interrupted DMAABORT_1 0x1 DMA transfer interrupted by NMI DMAIE [2:2] DMA interrupt enable 1 2 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMAIFG [3:3] DMA interrupt flag 1 3 DMAIFG_0 0x0 No interrupt pending DMAIFG_1 0x1 Interrupt pending DMAEN [4:4] DMA enable 1 4 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMALEVEL [5:5] DMA level 1 5 EDGE 0x0 Edge sensitive (rising edge) LEVEL 0x1 Level sensitive (high level) DMASRCBYTE [6:6] DMA source byte 1 6 WORD 0x0 Word BYTE 0x1 Byte DMADSTBYTE [7:7] DMA destination byte 1 7 WORD 0x0 Word BYTE 0x1 Byte DMASRCINCR [9:8] DMA source increment 2 8 DMASRCINCR_0 0x0 Source address is unchanged DMASRCINCR_1 0x1 Source address is unchanged DMASRCINCR_2 0x2 Source address is decremented DMASRCINCR_3 0x3 Source address is incremented DMADSTINCR [11:10] DMA destination increment 2 10 DMADSTINCR_0 0x0 Destination address is unchanged DMADSTINCR_1 0x1 Destination address is unchanged DMADSTINCR_2 0x2 Destination address is decremented DMADSTINCR_3 0x3 Destination address is incremented DMADT [14:12] DMA transfer mode 3 12 DMADT_0 0x0 Single transfer DMADT_1 0x1 Block transfer DMADT_2 0x2 Burst-block transfer DMADT_3 0x3 Burst-block transfer DMADT_4 0x4 Repeated single transfer DMADT_5 0x5 Repeated block transfer DMADT_6 0x6 Repeated burst-block transfer DMADT_7 0x7 Repeated burst-block transfer 0 DMA4SA 0x52 20 DMA Channel 4 Source Address 0 DMA4DA 0x56 20 DMA Channel 4 Destination Address 0 DMA4SZ 0x5A 16 DMA Channel 4 Transfer Size 0 DMA5CTL 0x60 16 DMA Channel 5 Control DMAREQ [0:0] DMA request 1 0 DMAREQ_0 0x0 No DMA start DMAREQ_1 0x1 Start DMA DMAABORT [1:1] DMA abort 1 1 DMAABORT_0 0x0 DMA transfer not interrupted DMAABORT_1 0x1 DMA transfer interrupted by NMI DMAIE [2:2] DMA interrupt enable 1 2 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMAIFG [3:3] DMA interrupt flag 1 3 DMAIFG_0 0x0 No interrupt pending DMAIFG_1 0x1 Interrupt pending DMAEN [4:4] DMA enable 1 4 DISABLE 0x0 Disabled ENABLE 0x1 Enabled DMALEVEL [5:5] DMA level 1 5 EDGE 0x0 Edge sensitive (rising edge) LEVEL 0x1 Level sensitive (high level) DMASRCBYTE [6:6] DMA source byte 1 6 WORD 0x0 Word BYTE 0x1 Byte DMADSTBYTE [7:7] DMA destination byte 1 7 WORD 0x0 Word BYTE 0x1 Byte DMASRCINCR [9:8] DMA source increment 2 8 DMASRCINCR_0 0x0 Source address is unchanged DMASRCINCR_1 0x1 Source address is unchanged DMASRCINCR_2 0x2 Source address is decremented DMASRCINCR_3 0x3 Source address is incremented DMADSTINCR [11:10] DMA destination increment 2 10 DMADSTINCR_0 0x0 Destination address is unchanged DMADSTINCR_1 0x1 Destination address is unchanged DMADSTINCR_2 0x2 Destination address is decremented DMADSTINCR_3 0x3 Destination address is incremented DMADT [14:12] DMA transfer mode 3 12 DMADT_0 0x0 Single transfer DMADT_1 0x1 Block transfer DMADT_2 0x2 Burst-block transfer DMADT_3 0x3 Burst-block transfer DMADT_4 0x4 Repeated single transfer DMADT_5 0x5 Repeated block transfer DMADT_6 0x6 Repeated burst-block transfer DMADT_7 0x7 Repeated burst-block transfer 0 DMA5SA 0x62 20 DMA Channel 5 Source Address 0 DMA5DA 0x66 20 DMA Channel 5 Destination Address 0 DMA5SZ 0x6A 16 DMA Channel 5 Transfer Size 0 FRCTL_A 0x0140 0 10 registers FRCTL0 0x0 16 FRAM Controller A Control Register 0 NWAITS [7:4] Wait state numbers 4 4 NWAITS_0 0x0 FRAM wait states: 0 NWAITS_1 0x1 FRAM wait states: 1 NWAITS_2 0x2 FRAM wait states: 2 NWAITS_3 0x3 FRAM wait states: 3 NWAITS_4 0x4 FRAM wait states: 4 NWAITS_5 0x5 FRAM wait states: 5 NWAITS_6 0x6 FRAM wait states: 6 NWAITS_7 0x7 FRAM wait states: 7 NWAITS_8 0x8 FRAM wait states: 8 NWAITS_9 0x9 FRAM wait states: 9 NWAITS_10 0xA FRAM wait states: 10 NWAITS_11 0xB FRAM wait states: 11 NWAITS_12 0xC FRAM wait states: 12 NWAITS_13 0xD FRAM wait states: 13 NWAITS_14 0xE FRAM wait states: 14 NWAITS_15 0xF FRAM wait states: 15 FRCTLPW [15:8] FRCTLPW password 8 8 AUTO [3:3] Enable automatic Wait State Mode 1 3 AUTO_0 0x0 User Wait State Mode. The NWAITS[3:0] is used for the FRAM wait state. AUTO_1 0x1 Auto mode. The NWAITS[3:0] is ignored. Wait states are generated automatically by the internal FRAM controller state machine. WPROT [0:0] Write Protection Enable 1 0 WPROT_0 0x0 Disable Write Protection. Write to FRAM memory is allowed. WPROT_1 0x1 Enable Write Protection. Write to FRAM memory is not allowed. In case a write access is attempted, the WPIFG (Write Protection Flag) bit will be set. 0 GCCTL0 0x4 16 General Control Register 0 UBDRSTEN [7:7] Enable Power Up Clear (PUC) reset for the uncorrectable bit error detection flag (UBDIFG) 1 7 UBDRSTEN_0 0x0 PUC not initiated on uncorrectable bit error detection flag. UBDRSTEN_1 0x1 PUC initiated on uncorrectable bit error detection flag. Generates vector in SYSRSTIV. Clear the UBDIE bit. UBDIE [6:6] Enable NMI event for the uncorrectable bit error detection flag (UBDIFG) 1 6 UBDIE_0 0x0 Disable NMI for the uncorrectable bit error detection flag (UBDIFG). UBDIE_1 0x1 Enable NMI for the uncorrectable bit error detection flag (UBDIFG). Generates vector in SYSSNIV. Clear the UBDRSTEN bit. CBDIE [5:5] Enable NMI event for the correctable bit error detection flag (CBDIFG) 1 5 CBDIE_0 0x0 Disable NMI for the correctable bit error detection flag (CBDIFG). CBDIE_1 0x1 Disable NMI for the correctable bit error detection flag (CBDIFG). Generates vector in SYSSNIV. WPIE [4:4] Enable NMI event for the Write Protection Detection flag (WPIFG) 1 4 WPIE_0 0x0 Disable NMI for the Write Protection Detection flag (WPIFG). WPIE_1 0x1 Enable NMI for the Write Protection Detection flag (WPIFG). Generates vector in SYSSNIV. ACCTEIE [3:3] Enable NMI event for the Access time error flag (ACCTEIFG) 1 3 ACCTEIE_0 0x0 Disable NMI for the Access time error flag (ACCTEIFG). ACCTEIE_1 0x1 Enable NMI for the Access time error flag (ACCTEIFG). Generates vector in SYSSNIV. FRPWR [2:2] FRAM Memory Power Control Request 1 2 FRPWR_0 0x0 Enable INACTIVE mode. FRPWR_1 0x1 Enable ACTIVE mode. 0 GCCTL1 0x6 16 General Control Register 1 WPIFG [4:4] Write Protection Detection flag 1 4 WPIFG_0 0x0 No interrupt pending. WPIFG_1 0x1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV when it is the highest pending interrupt. ACCTEIFG [3:3] Access time error flag 1 3 ACCTEIFG_0 0x0 No interrupt pending. ACCTEIFG_1 0x1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV when it is the highest pending interrupt. UBDIFG [2:2] FRAM uncorrectable bit error detection flag 1 2 UBDIFG_0 0x0 No interrupt pending. UBDIFG_1 0x1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV when it is the highest pending interrupt. CBDIFG [1:1] FRAM correctable bit error detection flag 1 1 CBDIFG_0 0x0 No interrupt is pending CBDIFG_1 0x1 Interrupt pending. Can be cleared by writing '0' or by reading SYSSNIV if it is the highest pending interrupt. 0 MPU 0x05A0 0 10 registers MPUCTL0 0x0 16 Memory Protection Unit Control 0 MPUENA [0:0] MPU Enable 1 0 DISABLE 0x0 Disabled ENABLE 0x1 Enabled MPULOCK [1:1] MPU Lock 1 1 OPEN 0x0 Open LOCK 0x1 Locked MPUSEGIE [4:4] Enable NMI Event if a Segment violation 1 4 DISABLE 0x0 Segment violation interrupt disabled ENABLE 0x1 Segment violation interrupt enabled MPUPW [15:8] MPU Password 8 8 0 MPUCTL1 0x2 16 Memory Protection Unit Control 1 MPUSEG1IFG [0:0] Main Memory Segment 1 Violation Interrupt Flag 1 0 MPUSEG1IFG_0 0x0 No interrupt pending MPUSEG1IFG_1 0x1 Interrupt pending MPUSEG2IFG [1:1] Main Memory Segment 2 Violation Interrupt Flag 1 1 MPUSEG2IFG_0 0x0 No interrupt pending MPUSEG2IFG_1 0x1 Interrupt pending MPUSEG3IFG [2:2] Main Memory Segment 3 Violation Interrupt Flag 1 2 MPUSEG1IFG_0 0x0 No interrupt pending MPUSEG1IFG_1 0x1 Interrupt pending MPUSEGIIFG [3:3] User Information Memory Violation Interrupt Flag 1 3 MPUSEGIIFG_0 0x0 No interrupt pending MPUSEGIIFG_1 0x1 Interrupt pending MPUSEGIPIFG [4:4] IP Encapsulation Access Violation Interrupt Flag 1 4 MPUSEG1IFG_0 0x0 No interrupt pending MPUSEG1IFG_1 0x1 Interrupt pending 0 MPUSEGB2 0x4 16 Memory Protection Unit Segmentation Border 2 Register 0 MPUSEGB1 0x6 16 Memory Protection Unit Segmentation Border 1 Register 0 MPUSAM 0x8 16 Memory Protection Unit Segmentation Access Management Register MPUSEG1RE [0:0] MPU Main Memory Segment 1 Read Enable 1 0 DISABLE 0x0 Read on Main Memory Segment 1 causes a violation if MPUSEG1WE = MPUSEG1XE = 0 ENABLE 0x1 Read on Main Memory Segment 1 is allowed MPUSEG1WE [1:1] MPU Main Memory Segment 1 Write Enable 1 1 DISABLE 0x0 Write on Main Memory Segment 1 causes a violation ENABLE 0x1 Write on Main Memory Segment 1 is allowed MPUSEG1XE [2:2] MPU Main Memory Segment 1 Execute Enable 1 2 DISABLE 0x0 Execute code on Main Memory Segment 1 causes a violation ENABLE 0x1 Execute code on Main Memory Segment 1 is allowed MPUSEG1VS [3:3] MPU Main Memory Segment 1 Violation Select 1 3 MPUSEG1VS_0 0x0 Violation in Main Memory Segment 1 asserts the MPUSEG1IFG bit and executes a SNMI if enabled by MPUSEGIE = 1 MPUSEG1VS_1 0x1 Violation in Main Memory Segment 1 asserts the MPUSEG1IFG bit and executes a PUC MPUSEG2RE [4:4] MPU Main Memory Segment 2 Read Enable 1 4 DISABLE 0x0 Read on Main Memory Segment 2 causes a violation if MPUSEG2WE = MPUSEG2XE = 0 ENABLE 0x1 Read on Main Memory Segment 2 is allowed MPUSEG2WE [5:5] MPU Main Memory Segment 2 Write Enable 1 5 DISABLE 0x0 Write on Main Memory Segment 2 causes a violation ENABLE 0x1 Write on Main Memory Segment 2 is allowed MPUSEG2XE [6:6] MPU Main Memory Segment 2 Execute Enable 1 6 DISABLE 0x0 Execute code on Main Memory Segment 2 causes a violation ENABLE 0x1 Execute code on Main Memory Segment 2 is allowed MPUSEG2VS [7:7] MPU Main Memory Segment 2 Violation Select 1 7 MPUSEG2VS_0 0x0 Violation in Main Memory Segment 2 asserts the MPUSEG2IFG bit and executes a SNMI if enabled by MPUSEGIE = 1 MPUSEG2VS_1 0x1 Violation in Main Memory Segment 2 asserts the MPUSEG2IFG bit and executes a PUC MPUSEG3RE [8:8] MPU Main Memory Segment 3 Read Enable 1 8 DISABLE 0x0 Read on Main Memory Segment 3 causes a violation if MPUSEG3WE = MPUSEG3XE = 0 ENABLE 0x1 Read on Main Memory Segment 3 is allowed MPUSEG3WE [9:9] MPU Main Memory Segment 3 Write Enable 1 9 DISABLE 0x0 Write on Main Memory Segment 3 causes a violation ENABLE 0x1 Write on Main Memory Segment 3 is allowed MPUSEG3XE [10:10] MPU Main Memory Segment 3 Execute Enable 1 10 DISABLE 0x0 Execute code on Main Memory Segment 3 causes a violation ENABLE 0x1 Execute code on Main Memory Segment 3 is allowed MPUSEG3VS [11:11] MPU Main Memory Segment 3 Violation Select 1 11 MPUSEG3VS_0 0x0 Violation in Main Memory Segment 3 asserts the MPUSEG3IFG bit and executes a SNMI if enabled by MPUSEGIE = 1 MPUSEG3VS_1 0x1 Violation in Main Memory Segment 3 asserts the MPUSEG3IFG bit and executes a PUC MPUSEGIRE [12:12] MPU User Information Memory Segment Read Enable 1 12 DISABLE 0x0 Read on User Information Memory causes a violation if MPUSEGIWE=MPUSEGIXE=0 ENABLE 0x1 Read on User Information Memory is allowed MPUSEGIWE [13:13] MPU User Information Memory Segment Write Enable. 1 13 DISABLE 0x0 Write on User Information Memory causes a violation ENABLE 0x1 Write on User Information Memory is allowed MPUSEGIXE [14:14] MPU User Information Memory Segment Execute Enable 1 14 DISABLE 0x0 Execute code on User Information Memory causes a violation ENABLE 0x1 Execute code on User Information Memory is allowed MPUSEGIVS [15:15] MPU User Information Memory Segment Violation Select 1 15 MPUSEGIVS_0 0x0 Violation in User Information Memory asserts the MPUSEGIIFG bit and executes a SNMI if enabled by MPUSEGIE =1 MPUSEGIVS_1 0x1 Violation in User Information Memory asserts the MPUSEGIIFG bit and executes a PUC 0 MPUIPC0 0xA 16 Memory Protection Unit IP Control 0 Register MPUIPVS [5:5] MPU IP Encapsulation segment Violation Select 1 5 MPUIPVS_0 0x0 Violation in Main Memory Segment 1 asserts the MPUSEGPIFG bit and executes a SNMI if enabled by MPUSEGIE = 1 MPUIPVS_1 0x1 Violation in Main Memory Segment 1 asserts the MPUSEGPIFG bit and executes a PUC MPUIPENA [6:6] MPU IP Encapsulation Enable 1 6 DISABLE 0x0 Disabled ENABLE 0x1 Enabled MPUIPLOCK [7:7] MPU IP Encapsulation Lock 1 7 OPEN 0x0 Open LOCK 0x1 Locked 0 MPUIPSEGB2 0xC 16 Memory Protection Unit IP Encapsulation Segment Border 2 Register 0 MPUIPSEGB1 0xE 16 Memory Protection Unit IP Encapsulation Segment Border 1 Register 0 MPY32 0x04C0 0 10 registers MPY 0x0 16 16-bit operand one multiply 0 MPYS 0x2 16 16-bit operand one signed multiply 0 MAC 0x4 16 16-bit operand one multiply accumulate 0 MACS 0x6 16 16-bit operand one signed multiply accumulate 0 OP2 0x8 16 16-bit operand two 0 RESLO 0xA 16 16x16-bit result low word 0 RESHI 0xC 16 16x16-bit result high word 0 SUMEXT 0xE 16 16x16-bit sum extension register 0 MPY32L 0x10 16 32-bit operand 1 multiply low word 0 MPY32H 0x12 16 32-bit operand 1 multiply high word 0 MPYS32L 0x14 16 32-bit operand 1 signed multiply low word 0 MPYS32H 0x16 16 32-bit operand 1 signed multiply high word 0 MAC32L 0x18 16 32-bit operand 1 multiply accumulate low word 0 MAC32H 0x1A 16 32-bit operand 1 multiply accumulate high word 0 MACS32L 0x1C 16 32-bit operand 1 signed multiply accumulate low word 0 MACS32H 0x1E 16 32-bit operand 1 signed multiply accumulate high word MACS32H [15:8] 32-bit operand 1 signed multiply accumulate high word 8 8 0 OP2L 0x20 16 32-bit operand 2 low word 0 OP2H 0x22 16 32-bit operand 2 high word 0 RES0 0x24 16 32x32-bit result 0 least significant word 0 RES1 0x26 16 32x32-bit result 1 0 RES2 0x28 16 32x32-bit result 2 0 RES3 0x2A 16 32x32-bit result 3 most significant word 0 MPY32CTL0 0x2C 16 MPY32 control register 0 MPYDLY32 [9:9] Delayed write mode. 1 9 MPYDLY32_0 0x0 Writes are delayed until 64-bit result (RES0 to RES3) is available. MPYDLY32_1 0x1 Writes are delayed until 32-bit result (RES0 to RES1) is available. 8 MPYDLYWRTEN MPYDLYWRTEN [8:8] Delayed write enable. 1 8 MPYDLYWRTEN_0 0x0 Writes are not delayed. MPYDLYWRTEN_1 0x1 Writes are delayed. MPYOP2_32 [7:7] Multiplier bit width of operand 2 1 7 16 0x0 16 bits. 32 0x1 32 bits. MPYOP1_32 [6:6] Multiplier bit width of operand 1 1 6 16 0x0 16 bits. 32 0x1 32 bits. MPYM [5:4] Multiplier mode 2 4 MPY 0x0 MPY Multiply MPYS 0x1 MPYS Signed multiply MAC 0x2 MAC Multiply accumulate MACS 0x3 MACS Signed multiply accumulate MPYSAT [3:3] Saturation mode 1 3 DISABLE 0x0 Saturation mode disabled. ENABLE 0x1 Saturation mode enabled. MPYFRAC [2:2] Fractional mode. 1 2 DISABLE 0x0 Fractional mode disabled. ENABLE 0x1 Fractional mode enabled. MPYC [0:0] Carry of the multiplier 1 0 MPYC_0 0x0 No carry for result. MPYC_1 0x1 Result has a carry. 0 PMM 0x0120 0 10 registers PMMCTL0 0x0 16 PMM control register 0 PMMSWBOR [2:2] Software brownout reset. 1 2 PMMSWBOR_0 0x0 Normal operation PMMSWBOR_1 0x1 Set to 1 to trigger a BOR PMMSWPOR [3:3] Software POR. 1 3 PMMSWPOR_0 0x0 Normal operation PMMSWPOR_1 0x1 Set to 1 to trigger a POR PMMREGOFF [4:4] Regulator off 1 4 PMMREGOFF_0 0x0 Regulator remains on when going into LPM3 or LPM4 PMMREGOFF_1 0x1 Regulator is turned off when going to LPM3 or LPM4. System enters LPM3.5 or LPM4.5, respectively. SVSHE [6:6] High-side SVS enable. 1 6 SVSHE_0 0x0 High-side SVS (SVSH) is disabled in LPM2, LPM3, LPM4, LPM3.5, and LPM4.5. SVSH is always enabled in active mode, LPM0, and LPM1. SVSHE_1 0x1 SVSH is always enabled. PMMPW [15:8] PMM password. 8 8 0 PMMIFG 0xA 16 PMM interrupt flag register PMMBORIFG [8:8] PMM software brownout reset interrupt flag. 1 8 PMMBORIFG_0 0x0 Reset not due to PMMSWBOR PMMBORIFG_1 0x1 Reset due to PMMSWBOR PMMRSTIFG [9:9] PMM reset pin interrupt flag. 1 9 PMMBORIFG_0 0x0 Reset not due to reset pin PMMBORIFG_1 0x1 Reset due to reset pin PMMPORIFG [10:10] PMM software POR interrupt flag. 1 10 PMMBORIFG_0 0x0 Reset not due to PMMSWPOR PMMBORIFG_1 0x1 Reset due to PMMSWPOR SVSHIFG [13:13] High-side SVS interrupt flag. 1 13 SVSHIFG_0 0x0 Reset not due to SVSH SVSHIFG_1 0x1 Reset due to SVSH PMMLPM5IFG [15:15] LPMx.5 flag. 1 15 PMMLPM5IFG_0 0x0 Reset not due to wake-up from LPMx.5 PMMLPM5IFG_1 0x1 Reset due to wake-up from LPMx.5 0 PM5CTL0 0x10 16 Power mode 5 control register 0 LOCKLPM5 [0:0] LPMx.5 Lock Bit 1 0 LOCKLPM5_0 0x0 LPMx.5 configuration is not locked and defaults to its reset condition. LOCKLPM5_1 0x1 LPMx.5 configuration remains locked. Pin state is held during LPMx.5 entry and exit. 0 RAMCTL 0x0158 0 10 registers RCCTL0 0x0 16 RAM Controller Control 0 RCRS0OFF [1:0] RAM controller RAM sector 0 off 2 0 RCRS0OFF_0 0x0 Contents of this RAM sector are retained in LPM3 and LPM4. RCRS0OFF_1 0x1 Turns off this RAM sector in LPM3 and LPM4, re-activates it on wake-up. All data of this RAM sector is lost after wakeup from LPM3 and LPM4. See the device-specific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCRS0OFF_2 0x2 Turns off this RAM sector entering LPM3 and LPM4, the RAM sector remains off after wake-up. All data of this RAM sector is lost. See the devicespecific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCKEY [15:8] RAM controller key. Always reads as 69h. Must be written as 5Ah; any other write is is ignored. 8 8 RCRS1OFF [3:2] RAM controller RAM sector 0 off 2 2 RCRS0OFF_0 0x0 Contents of this RAM sector are retained in LPM3 and LPM4. RCRS0OFF_1 0x1 Turns off this RAM sector in LPM3 and LPM4, re-activates it on wake-up. All data of this RAM sector is lost after wakeup from LPM3 and LPM4. See the device-specific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCRS0OFF_2 0x2 Turns off this RAM sector entering LPM3 and LPM4, the RAM sector remains off after wake-up. All data of this RAM sector is lost. See the devicespecific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCRS3OFF [7:6] RAM controller RAM sector 3 off 2 6 RCRS0OFF_0 0x0 Contents of this RAM sector are retained in LPM3 and LPM4. RCRS0OFF_1 0x1 Turns off this RAM sector in LPM3 and LPM4, re-activates it on wake-up. All data of this RAM sector is lost after wakeup from LPM3 and LPM4. See the device-specific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCRS0OFF_2 0x2 Turns off this RAM sector entering LPM3 and LPM4, the RAM sector remains off after wake-up. All data of this RAM sector is lost. See the devicespecific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCRS2OFF [5:4] RAM controller RAM sector 0 off 2 4 RCRS0OFF_0 0x0 Contents of this RAM sector are retained in LPM3 and LPM4. RCRS0OFF_1 0x1 Turns off this RAM sector in LPM3 and LPM4, re-activates it on wake-up. All data of this RAM sector is lost after wakeup from LPM3 and LPM4. See the device-specific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. RCRS0OFF_2 0x2 Turns off this RAM sector entering LPM3 and LPM4, the RAM sector remains off after wake-up. All data of this RAM sector is lost. See the devicespecific data sheet to find the number of available sectors, the address range, and the size of each RAM sector. 0 REF_A 0x01B0 0 10 registers REFCTL0 0x0 16 REF Control Register 0 REFON [0:0] Reference enable 1 0 REFON_0 0x0 Disables reference if no other reference requests are pending REFON_1 0x1 Enables reference in static mode REFOUT [1:1] Reference output buffer 1 1 REFOUT_0 0x0 Reference output not available externally REFOUT_1 0x1 Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion. REFTCOFF [3:3] Temperature sensor disabled 1 3 REFTCOFF_0 0x0 Temperature sensor enabled REFTCOFF_1 0x1 Temperature sensor disabled to save power REFVSEL [5:4] Reference voltage level select 2 4 REFVSEL_0 0x0 1.2 V available when reference requested or REFON = 1 REFVSEL_1 0x1 2.0 V available when reference requested or REFON = 1 REFVSEL_2 0x2 2.5 V available when reference requested or REFON = 1 REFVSEL_3 0x3 2.5 V available when reference requested or REFON = 1 REFGENOT [6:6] Reference generator one-time trigger 1 6 REFGENOT_0 0x0 No trigger REFGENOT_1 0x1 Generation of the reference voltage is started by writing 1 or by a hardware trigger REFBGOT [7:7] Bandgap and bandgap buffer one-time trigger 1 7 REFBGOT_0 0x0 No trigger REFBGOT_1 0x1 Generation of the bandgap voltage is started by writing 1 or by a hardware trigger REFGENACT [8:8] Reference generator active 1 8 REFGENACT_0 0x0 Reference generator not active REFGENACT_1 0x1 Reference generator active REFBGACT [9:9] Reference bandgap active 1 9 REFBGACT_0 0x0 Reference bandgap buffer not active REFBGACT_1 0x1 Reference bandgap buffer active REFGENBUSY [10:10] Reference generator busy 1 10 REFGENBUSY_0 0x0 Reference generator not busy REFGENBUSY_1 0x1 Reference generator busy BGMODE [11:11] Bandgap mode 1 11 BGMODE_0 0x0 Static mode BGMODE_1 0x1 Sampled mode REFGENRDY [12:12] Variable reference voltage ready status 1 12 REFGENRDY_0 0x0 Reference voltage output is not ready to be used REFGENRDY_1 0x1 Reference voltage output is ready to be used REFBGRDY [13:13] Buffered bandgap voltage ready status 1 13 REFBGRDY_0 0x0 Buffered bandgap voltage is not ready to be used REFBGRDY_1 0x1 Buffered bandgap voltage is ready to be used 0 RTC_C 0x04A0 0 10 registers RTCCTL0 0x0 16 RTCCTL0 Register RTCRDYIFG [0:0] Real-time clock ready interrupt flag 1 0 RTCAIFG [1:1] Real-time clock alarm interrupt flag 1 1 RTCTEVIFG [2:2] Real-time clock time event interrupt flag 1 2 RTCOFIFG [3:3] 32-kHz crystal oscillator fault interrupt flag 1 3 RTCRDYIE [4:4] Real-time clock ready interrupt enable 1 4 RTCAIE [5:5] Real-time clock alarm interrupt enable 1 5 RTCTEVIE [6:6] Real-time clock time event interrupt enable 1 6 RTCOFIE [7:7] 32-kHz crystal oscillator fault interrupt enable 1 7 RTCKEY [15:8] Real-time clock key 8 8 0 RTCCTL13 0x2 16 RTCCTL13 Register RTCTEV [1:0] Real-time clock time event 2 0 MIN 0x0 Minute changed HOUR 0x1 Hour changed 0000 0x2 Every day at midnight (00:00) 1200 0x3 Every day at noon (12:00) RTCSSEL [3:2] Real-time clock source select 2 2 LFXT 0x0 32-kHz crystal oscillator clock LFXT_ 0x1 32-kHz crystal oscillator clock RT1PS 0x2 Output from RT1PS RT1PS_ 0x3 Output from RT1PS RTCRDY [4:4] Real-time clock ready 1 4 RTCRDY_0 0x0 RTC time values in transition RTCRDY_1 0x1 RTC time values safe for reading. This bit indicates when the real-time clock time values are safe for reading. RTCMODE 1 5 RTCMODE_1 0x1 Calendar mode. Always reads a value of 1. RTCHOLD [6:6] Real-time clock hold 1 6 RTCHOLD_0 0x0 Real-time clock is operational RTCHOLD_1 0x1 When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care RTCBCD [7:7] Real-time clock BCD select 1 7 HEX 0x0 Binary (hexadecimal) code selected BCD 0x1 Binary coded decimal (BCD) code selected RTCCALF [9:8] Real-time clock calibration frequency 2 8 NONE 0x0 No frequency output to RTCCLK pin 512 0x1 512 Hz 256 0x2 256 Hz 1 0x3 1 Hz 0 RTCOCAL 0x4 16 RTCOCAL Register RTCOCAL [7:0] Real-time clock offset error calibration 8 0 RTCOCALS [15:15] Real-time clock offset error calibration sign 1 15 DOWN 0x0 Down calibration. Frequency adjusted down. UP 0x1 Up calibration. Frequency adjusted up. 0 RTCTCMP 0x6 16 RTCTCMP Register RTCTCMP [7:0] Real-time clock temperature compensation 8 0 RTCTCOK [13:13] Real-time clock temperature compensation write OK 1 13 RTCTCOK_0 0x0 Write to RTCTCMPx is unsuccessful RTCTCOK_1 0x1 Write to RTCTCMPx is successful RTCTCRDY [14:14] Real-time clock temperature compensation ready 1 14 RTCTCMPS [15:15] Real-time clock temperature compensation sign 1 15 DOWN 0x0 Down calibration. Frequency adjusted down UP 0x1 Up calibration. Frequency adjusted up 0 RTCPS0CTL 0x8 16 Real-Time Clock Prescale Timer 0 Control Register RT0PSIFG [0:0] Prescale timer 0 interrupt flag 1 0 RT0PSIFG_0 0x0 No time event occurred RT0PSIFG_1 0x1 Time event occurred RT0PSIE [1:1] Prescale timer 0 interrupt enable 1 1 DISABLE 0x0 Interrupt not enabled ENABLE 0x1 Interrupt enabled RT0IP [4:2] Prescale timer 0 interrupt interval 3 2 2 0x0 Divide by 2 4 0x1 Divide by 4 8 0x2 Divide by 8 16 0x3 Divide by 16 32 0x4 Divide by 32 64 0x5 Divide by 64 128 0x6 Divide by 128 256 0x7 Divide by 256 RT0PSHOLD [8:8] Prescale timer 0 hold 1 8 RT0PSHOLD_0 0x0 RT0PS is operational RT0PSHOLD_1 0x1 RT0PS is held RT0PSDIV [13:11] Prescale timer 0 clock divide 3 11 2 0x0 Divide by 2 4 0x1 Divide by 4 8 0x2 Divide by 8 16 0x3 Divide by 16 32 0x4 Divide by 32 64 0x5 Divide by 64 128 0x6 Divide by 128 256 0x7 Divide by 256 0 RTCPS1CTL 0xA 16 Real-Time Clock Prescale Timer 1 Control Register RT1PSIFG [0:0] Prescale timer 1 interrupt flag 1 0 RT1PSIFG_0 0x0 No time event occurred RT1PSIFG_1 0x1 Time event occurred RT1PSIE [1:1] Prescale timer 1 interrupt enable 1 1 DISABLE 0x0 Interrupt not enabled ENABLE 0x1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) RT1IP [4:2] Prescale timer 1 interrupt interval 3 2 2 0x0 Divide by 2 4 0x1 Divide by 4 8 0x2 Divide by 8 16 0x3 Divide by 16 32 0x4 Divide by 32 64 0x5 Divide by 64 128 0x6 Divide by 128 256 0x7 Divide by 256 RT1PSHOLD [8:8] Prescale timer 1 hold 1 8 RT1PSHOLD_0 0x0 RT1PS is operational RT1PSHOLD_1 0x1 RT1PS is held RT1PSDIV [13:11] Prescale timer 1 clock divide 3 11 2 0x0 Divide by 2 4 0x1 Divide by 4 8 0x2 Divide by 8 16 0x3 Divide by 16 32 0x4 Divide by 32 64 0x5 Divide by 64 128 0x6 Divide by 128 256 0x7 Divide by 256 RT1SSEL [15:14] Prescale timer 1 clock source select 2 14 RT1SSEL_0 0x0 32-kHz crystal oscillator clock RT1SSEL_1 0x1 32-kHz crystal oscillator clock RT0PS 0x2 Output from RT0PS RT0PS_ 0x3 Output from RT0PS 0 RTCPS 0xC 16 Real-Time Clock Prescale Timer Counter Register 0 RTCIV 0xE 16 Real-Time Clock Interrupt Vector Register RTCIV [15:0] Real-time clock interrupt vector value 16 0 NONE 0x0 No interrupt pending RTCOFIFG 0x2 Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG; Interrupt Priority: Highest RTCRDYIFG 0x4 Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG RTCTEVIFG 0x6 Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG RTCAIFG 0x8 Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG RT0PSIFG 0xA Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG RT1PSIFG 0xC Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 0 RTCTIM0 0x10 16 RTCTIM0 Register Hexadecimal Format SECONDS [5:0] Seconds (0 to 59) 6 0 MINUTES [13:8] Minutes (0 to 59) 6 8 0 RTCTIM0_BCD 0x10 16 Real-Time Clock Seconds, Minutes Register - BCD Format SECONDSLOWDIGIT [3:0] Seconds low digit (0 to 9) 4 0 SECONDSHIGHDIGIT [6:4] Seconds high digit (0 to 5) 3 4 MINUTESLOWDIGIT [11:8] Minutes low digit (0 to 9) 4 8 MINUTESHIGHDIGIT [14:12] Minutes high digit (0 to 5) 3 12 0 RTCCNT12 0x10 16 Real-Time Clock Counter 1 and 2 Register Counter Mode 0 RTCTIM1 0x12 16 Real-Time Clock Hour, Day of Week HOURS [4:0] Hours (0 to 23) 5 0 DAYOFWEEK [10:8] Day of week (0 to 6) 3 8 0 RTCTIM1_BCD 0x12 16 Real-Time Clock Hour, Day of Week - BCD Format HOURSLOWDIGIT [3:0] Hours low digit (0 to 9) 4 0 HOURSHIGHDIGIT [5:4] Hours high digit (0 to 2) 2 4 DAYOFWEEK [10:8] Day of week (0 to 6) 3 8 0 RTCCNT34 0x12 16 Real-Time Clock Counter 3 and 4 Register Counter Mode 0 RTCDATE 0x14 16 RTCDATE - Hexadecimal Format DAY [4:0] Day of month (1 to 28, 29, 30, 31) 5 0 MONTH [11:8] Month (1 to 12) 4 8 0 RTCDATE_BCD 0x14 16 Real-Time Clock Date - BCD Format DAYLOWDIGIT [3:0] Day of month low digit (0 to 9) 4 0 DAYHIGHDIGIT [5:4] Day of month high digit (0 to 3) 2 4 MONTHLOWDIGIT [11:8] Month low digit (0 to 9) 4 8 MONTHHIGHDIGIT [12:12] Month high digit (0 or 1) 1 12 0 RTCYEAR 0x16 16 RTCYEAR Register Hexadecimal Format YEARLOWBYTE [7:0] Year low byte. Valid values for Year are 0 to 4095. 8 0 YEARHIGHBYTE [11:8] Year high byte. Valid values for Year are 0 to 4095. 4 8 0 RTCYEAR_BCD 0x16 16 Real-Time Clock Year Register - BCD Format YEAR [3:0] Year lowest digit (0 to 9) 4 0 DECADE [7:4] Decade (0 to 9) 4 4 CENTURYLOWDIGIT [11:8] Century low digit (0 to 9) 4 8 CENTURYHIGHDIGIT [14:12] Century high digit (0 to 4) 3 12 0 RTCAMINHR 0x18 16 RTCMINHR - Hexadecimal Format MIN [5:0] Minutes (0 to 59) 6 0 MINAE [7:7] Alarm enable 1 7 HOUR [12:8] Hours (0 to 23) 5 8 HOURAE [15:15] Alarm enable 1 15 0 RTCAMINHR_BCD 0x18 16 Real-Time Clock Minutes, Hour Alarm - BCD Format MINUTESLOWDIGIT [3:0] Minutes low digit (0 to 9) 4 0 MINUTESHIGHDIGIT [6:4] Minutes high digit (0 to 5) 3 4 MINAE [7:7] Alarm enable 1 7 HOURSLOWDIGIT [11:8] Hours low digit (0 to 9) 4 8 HOURSHIGHDIGIT [13:12] Hours high digit (0 to 2) 2 12 HOURAE [15:15] Alarm enable 1 15 0 RTCADOWDAY 0x1A 16 RTCADOWDAY - Hexadecimal Format DOW [2:0] Day of week (0 to 6) 3 0 DOWAE [7:7] Alarm enable 1 7 DAY [12:8] Day of month (1 to 28, 29, 30, 31) 5 8 DAYAE [15:15] Alarm enable 1 15 0 RTCADOWDAY_BCD 0x1A 16 Real-Time Clock Day of Week, Day of Month Alarm - BCD Format DOW [2:0] Day of week (0 to 6) 3 0 DOWAE [7:7] Alarm enable 1 7 DAY_LD [11:8] Day of month low digit (0 to 9) 4 8 DAY_HD [13:12] Day of month high digit (0 to 3) 2 12 DAYAE [15:15] Alarm enable 1 15 0 BIN2BCD 0x1C 16 Binary-to-BCD Conversion Register 0 BCD2BIN 0x1E 16 BCD-to-Binary Conversion Register 0 RT0PS 0xC 8 Prescale timer 0 counter value 0 RT1PS 0xD 8 Prescale timer 1 counter value 0 RTCCNT1 0x10 8 The RTCCNT1 register is the count of RTCCNT1 0 RTCCNT2 0x11 8 The RTCCNT2 register is the count of RTCCNT2 0 RTCCNT3 0x12 8 The RTCCNT3 register is the count of RTCCNT3 0 RTCCNT4 0x13 8 The RTCCNT4 register is the count of RTCCNT4 0 SFR 0x0100 0 10 registers SFRIE1 0x0 16 Interrupt Enable WDTIE [0:0] Watchdog timer interrupt enable 1 0 DISABLE 0x0 Interrupts disabled ENABLE 0x1 Interrupts enabled OFIE [1:1] Oscillator fault interrupt enable 1 1 DISABLE 0x0 Interrupts disabled ENABLE 0x1 Interrupts enabled VMAIE [3:3] Vacant memory access interrupt enable 1 3 DISABLE 0x0 Interrupts disabled ENABLE 0x1 Interrupts enabled NMIIE [4:4] NMI pin interrupt enable 1 4 DISABLE 0x0 Interrupts disabled ENABLE 0x1 Interrupts enabled JMBINIE [6:6] JTAG mailbox input interrupt enable 1 6 DISABLE 0x0 Interrupts disabled ENABLE 0x1 Interrupts enabled JMBOUTIE [7:7] JTAG mailbox output interrupt enable 1 7 DISABLE 0x0 Interrupts disabled ENABLE 0x1 Interrupts enabled 0 SFRIFG1 0x2 16 Interrupt Flag OFIFG [1:1] Oscillator fault interrupt flag 1 1 OFIFG_0 0x0 No interrupt pending OFIFG_1 0x1 Interrupt pending VMAIFG [3:3] Vacant memory access interrupt flag 1 3 VMAIFG_0 0x0 No interrupt pending VMAIFG_1 0x1 Interrupt pending NMIIFG [4:4] NMI pin interrupt flag 1 4 NMIIFG_0 0x0 No interrupt pending NMIIFG_1 0x1 Interrupt pending WDTIFG [0:0] Watchdog timer interrupt flag 1 0 WDTIFG_0 0x0 No interrupt pending WDTIFG_1 0x1 Interrupt pending JMBINIFG [6:6] JTAG mailbox input interrupt flag 1 6 JMBINIFG_0 0x0 No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically when JMBI0 is read by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared automatically when both JMBI0 and JMBI1 have been read by the CPU. This bit is also cleared when the associated vector in SYSUNIV has been read JMBINIFG_1 0x1 Interrupt pending. A message is waiting in the JMBIN registers. In 16-bit mode (JMBMODE = 0) when JMBI0 has been written by the JTAG module. In 32-bit mode (JMBMODE = 1) when JMBI0 and JMBI1 have been written by the JTAG module. JMBOUTIFG [7:7] JTAG mailbox output interrupt flag 1 7 JMBOUTIFG_0 0x0 No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically when JMBO0 has been written with a new message to the JTAG module by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared automatically when both JMBO0 and JMBO1 have been written with new messages to the JTAG module by the CPU. This bit is also cleared when the associated vector in SYSUNIV has been read. JMBOUTIFG_1 0x1 Interrupt pending. JMBO registers are ready for new messages. In 16-bit mode (JMBMODE = 0), JMBO0 has been received by the JTAG module and is ready for a new message from the CPU. In 32-bit mode (JMBMODE = 1), JMBO0 and JMBO1 have been received by the JTAG module and are ready for new messages from the CPU. 0 SFRRPCR 0x4 16 Reset Pin Control SYSNMI [0:0] NMI select 1 0 RESET 0x0 Reset function NMI 0x1 NMI function SYSNMIIES [1:1] NMI edge select 1 1 RISING 0x0 NMI on rising edge FALLING 0x1 NMI on falling edge SYSRSTUP [2:2] Reset resistor pin pullup or pulldown 1 2 PULLDOWN 0x0 Pulldown is selected PULLUP 0x1 Pullup is selected SYSRSTRE [3:3] Reset pin resistor enable 1 3 DISABLE 0x0 Pullup or pulldown resistor at the RST/NMI pin is disabled ENABLE 0x1 Pullup or pulldown resistor at the RST/NMI pin is enabled 0 SYS 0x0180 0 10 registers SYSCTL 0x0 16 System Control SYSRIVECT [0:0] RAM-based interrupt vectors 1 0 FRAM 0x0 Interrupt vectors generated with end address TOP of lower 64K FRAM FFFFh RAM 0x1 Interrupt vectors generated with end address TOP of RAM, when RAM available SYSPMMPE [2:2] PMM access protect 1 2 SYSPMMPE_0 0x0 Access from anywhere in memory SYSPMMPE_1 0x1 Access only from the BSL segments SYSBSLIND [4:4] BSL entry indication 1 4 SYSBSLIND_0 0x0 No BSL entry sequence detected SYSBSLIND_1 0x1 BSL entry sequence detected SYSJTAGPIN [5:5] Dedicated JTAG pins enable 1 5 SHARED 0x0 Shared JTAG pins (JTAG mode selectable using SBW sequence) DEDICATED 0x1 Dedicated JTAG pins (explicit 4-wire JTAG mode selection) 0 SYSJMBC 0x6 16 JTAG Mailbox Control JMBIN0FG [0:0] Incoming JTAG Mailbox 0 flag 1 0 JMBIN0FG_0 0x0 JMBI0 has no new data JMBIN0FG_1 0x1 JMBI0 has new data available JMBIN1FG [1:1] Incoming JTAG Mailbox 1 flag 1 1 JMBIN1FG_0 0x0 JMBI1 has no new data JMBIN1FG_1 0x1 JMBI1 has new data available JMBOUT0FG [2:2] Outgoing JTAG Mailbox 0 flag 1 2 JMBOUT0FG_0 0x0 JMBO0 is not ready to receive new data JMBOUT0FG_1 0x1 JMBO0 is ready to receive new data JMBOUT1FG [3:3] Outgoing JTAG Mailbox 1 flag 1 3 JMBOUT1FG_0 0x0 JMBO1 is not ready to receive new data JMBOUT1FG_1 0x1 JMBO1 is ready to receive new data JMBMODE [4:4] Operation mode of JMB 1 4 16BIT 0x0 16-bit transfers using JMBO0 and JMBI0 only 32BIT 0x1 32-bit transfers using JMBO0 with JMBO1 and JMBI0 with JMBI1 JMBCLR0OFF [6:6] Incoming JTAG Mailbox 0 flag auto-clear disable 1 6 JMBCLR0OFF_0 0x0 JMBIN0FG cleared on read of JMB0IN register JMBCLR0OFF_1 0x1 JMBIN0FG cleared by software JMBCLR1OFF [7:7] Incoming JTAG Mailbox 1 flag auto-clear disable 1 7 JMBCLR1OFF_0 0x0 JMBIN1FG cleared on read of JMB1IN register JMBCLR1OFF_1 0x1 JMBIN1FG cleared by software 0 SYSJMBI0 0x8 16 JTAG Mailbox Input MSGLO [7:0] JTAG mailbox incoming message low byte 8 0 MSGHI [15:8] JTAG mailbox incoming message high byte 8 8 0 SYSJMBI1 0xA 16 JTAG Mailbox Input MSGLO [7:0] JTAG mailbox incoming message low byte 8 0 MSGHI [15:8] JTAG mailbox incoming message high byte 8 8 0 SYSJMBO0 0xC 16 JTAG Mailbox Output MSGLO [7:0] JTAG mailbox outgoing message low byte 8 0 MSGHI [15:8] JTAG mailbox outgoing message high byte 8 8 0 SYSJMBO1 0xE 16 JTAG Mailbox Output MSGLO [7:0] JTAG mailbox outgoing message low byte 8 0 MSGHI [15:8] JTAG mailbox outgoing message high byte 8 8 0 SYSUNIV 0x1A 16 User NMI Vector Generator SYSUNIV [15:0] User NMI vector 16 0 NONE 0x0 No interrupt pending NMIIFG 0x2 NMIIFG NMI pin OFIFG 0x4 OFIFG oscillator fault 0 SYSSNIV 0x1C 16 System NMI Vector Generator SYSSNIV [15:0] System NMI vector 16 0 NONE 0x0 No interrupt pending SYSSNIV_2 0x2 Reserved UBDIFG 0x4 Uncorrectable FRAM bit error detection ACCTEIFG 0x6 FRAM Access Time Error MPUSEGPIFG 0x8 MPUSEGPIFG encapsulated IP memory segment violation MPUSEGIIFG 0xA MPUSEGIIFG information memory segment violation MPUSEG1IFG 0xC MPUSEG1IFG segment 1 memory violation MPUSEG2IFG 0xE MPUSEG2IFG segment 2 memory violation MPUSEG3IFG 0x10 MPUSEG3IFG segment 3 memory violation VMAIFG 0x12 VMAIFG Vacant memory access JMBINIFG 0x14 JMBINIFG JTAG mailbox input JMBOUTIFG 0x16 JMBOUTIFG JTAG mailbox output CBDIFG 0x18 Correctable FRAM bit error detection WPROT 0x1A FRAM write protection detection LEATO 0x1C LEA time-out fault LEACMD 0x1E LEA command fault 0 SYSRSTIV 0x1E 16 Reset Vector Generator SYSRSTIV [15:0] Reset interrupt vector 16 0 NONE 0x0 No interrupt pending BOR 0x2 Brownout RSTNMI 0x4 RSTIFG RST/NMI PMMSWBOR 0x6 PMMSWBOR software BOR LPM5WU 0x8 LPMx.5 wakeup SECYV 0xA Security violation SYSRSTIV_12 0xC Reserved SVSHIFG 0xE SVSHIFG SVSH event SYSRSTIV_16 0x10 Reserved SYSRSTIV_18 0x12 Reserved PMMSWPOR 0x14 PMMSWPOR software POR WDTIFG 0x16 WDTIFG watchdog timeout WDTPW 0x18 WDTPW watchdog password violation FRCTLPW 0x1A FRCTLPW password violation UBDIFG 0x1C Uncorrectable FRAM bit error detection PERF 0x1E Peripheral area fetch PMMPW 0x20 PMM password violation MPUPW 0x22 MPU password violation CSPW 0x24 CS password violation MPUSEGPIFG 0x26 MPUSEGPIFG encapsulated IP memory segment violation MPUSEGIIFG 0x28 MPUSEGIIFG information memory segment violation MPUSEG1IFG 0x2A MPUSEG1IFG segment 1 memory violation MPUSEG2IFG 0x2C MPUSEG2IFG segment 2 memory violation MPUSEG3IFG 0x2E MPUSEG3IFG segment 3 memory violation 0 TA0 0x0340 0 10 registers TA0CTL 0x0 16 TimerAx Control Register TAIFG [0:0] TimerA interrupt flag 1 0 TAIFG_0 0x0 No interrupt pending TAIFG_1 0x1 Interrupt pending TAIE [1:1] TimerA interrupt enable 1 1 TAIE_0 0x0 Interrupt disabled TAIE_1 0x1 Interrupt enabled TACLR [2:2] TimerA clear 1 2 MC [5:4] Mode control 2 4 STOP 0x0 Stop mode: Timer is halted UP 0x1 Up mode: Timer counts up to TAxCCR0 CONTINUOUS 0x2 Continuous mode: Timer counts up to 0FFFFh UPDOWN 0x3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h ID [7:6] Input divider 2 6 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 TASSEL [9:8] TimerA clock source select 2 8 TACLK 0x0 TAxCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK INCLK 0x3 INCLK 0 TA0CCTL0 0x2 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA0CCTL1 0x4 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA0CCTL2 0x6 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA0R 0x10 16 TimerA register 0 TA0CCR0 0x12 16 Timer_A Capture/Compare Register 0 TA0CCR1 0x14 16 Timer_A Capture/Compare Register 0 TA0CCR2 0x16 16 Timer_A Capture/Compare Register 0 TA0EX0 0x20 16 TimerAx Expansion 0 Register TAIDEX [2:0] Input divider expansion 3 0 1 0x0 Divide by 1 2 0x1 Divide by 2 3 0x2 Divide by 3 4 0x3 Divide by 4 5 0x4 Divide by 5 6 0x5 Divide by 6 7 0x6 Divide by 7 8 0x7 Divide by 8 0 TA0IV 0x2E 16 TimerAx Interrupt Vector Register TAIV [15:0] TimerA interrupt vector value 16 0 NONE 0x0 No interrupt pending TACCR1 0x2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest TACCR2 0x4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG TACCR3 0x6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG TACCR4 0x8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG TACCR5 0xA Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG TACCR6 0xC Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG TAIFG 0xE Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 0 TA1 0x0380 0 10 registers TA1CTL 0x0 16 TimerAx Control Register TAIFG [0:0] TimerA interrupt flag 1 0 TAIFG_0 0x0 No interrupt pending TAIFG_1 0x1 Interrupt pending TAIE [1:1] TimerA interrupt enable 1 1 TAIE_0 0x0 Interrupt disabled TAIE_1 0x1 Interrupt enabled TACLR [2:2] TimerA clear 1 2 MC [5:4] Mode control 2 4 STOP 0x0 Stop mode: Timer is halted UP 0x1 Up mode: Timer counts up to TAxCCR0 CONTINUOUS 0x2 Continuous mode: Timer counts up to 0FFFFh UPDOWN 0x3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h ID [7:6] Input divider 2 6 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 TASSEL [9:8] TimerA clock source select 2 8 TACLK 0x0 TAxCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK INCLK 0x3 INCLK 0 TA1CCTL0 0x2 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA1CCTL1 0x4 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA1CCTL2 0x6 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA1R 0x10 16 TimerA register 0 TA1CCR0 0x12 16 Timer_A Capture/Compare Register 0 TA1CCR1 0x14 16 Timer_A Capture/Compare Register 0 TA1CCR2 0x16 16 Timer_A Capture/Compare Register 0 TA1EX0 0x20 16 TimerAx Expansion 0 Register TAIDEX [2:0] Input divider expansion 3 0 1 0x0 Divide by 1 2 0x1 Divide by 2 3 0x2 Divide by 3 4 0x3 Divide by 4 5 0x4 Divide by 5 6 0x5 Divide by 6 7 0x6 Divide by 7 8 0x7 Divide by 8 0 TA1IV 0x2E 16 TimerAx Interrupt Vector Register TAIV [15:0] TimerA interrupt vector value 16 0 NONE 0x0 No interrupt pending TACCR1 0x2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest TACCR2 0x4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG TACCR3 0x6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG TACCR4 0x8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG TACCR5 0xA Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG TACCR6 0xC Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG TAIFG 0xE Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 0 TA2 0x0400 0 10 registers TA2CTL 0x0 16 TimerAx Control Register TAIFG [0:0] TimerA interrupt flag 1 0 TAIFG_0 0x0 No interrupt pending TAIFG_1 0x1 Interrupt pending TAIE [1:1] TimerA interrupt enable 1 1 TAIE_0 0x0 Interrupt disabled TAIE_1 0x1 Interrupt enabled TACLR [2:2] TimerA clear 1 2 MC [5:4] Mode control 2 4 STOP 0x0 Stop mode: Timer is halted UP 0x1 Up mode: Timer counts up to TAxCCR0 CONTINUOUS 0x2 Continuous mode: Timer counts up to 0FFFFh UPDOWN 0x3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h ID [7:6] Input divider 2 6 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 TASSEL [9:8] TimerA clock source select 2 8 TACLK 0x0 TAxCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK INCLK 0x3 INCLK 0 TA2CCTL0 0x2 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA2CCTL1 0x4 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA2R 0x10 16 TimerA register 0 TA2CCR0 0x12 16 Timer_A Capture/Compare Register 0 TA2CCR1 0x14 16 Timer_A Capture/Compare Register 0 TA2EX0 0x20 16 TimerAx Expansion 0 Register TAIDEX [2:0] Input divider expansion 3 0 1 0x0 Divide by 1 2 0x1 Divide by 2 3 0x2 Divide by 3 4 0x3 Divide by 4 5 0x4 Divide by 5 6 0x5 Divide by 6 7 0x6 Divide by 7 8 0x7 Divide by 8 0 TA2IV 0x2E 16 TimerAx Interrupt Vector Register TAIV [15:0] TimerA interrupt vector value 16 0 NONE 0x0 No interrupt pending TACCR1 0x2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest TACCR2 0x4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG TACCR3 0x6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG TACCR4 0x8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG TACCR5 0xA Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG TACCR6 0xC Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG TAIFG 0xE Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 0 TA3 0x0440 0 10 registers TA3CTL 0x0 16 TimerAx Control Register TAIFG [0:0] TimerA interrupt flag 1 0 TAIFG_0 0x0 No interrupt pending TAIFG_1 0x1 Interrupt pending TAIE [1:1] TimerA interrupt enable 1 1 TAIE_0 0x0 Interrupt disabled TAIE_1 0x1 Interrupt enabled TACLR [2:2] TimerA clear 1 2 MC [5:4] Mode control 2 4 STOP 0x0 Stop mode: Timer is halted UP 0x1 Up mode: Timer counts up to TAxCCR0 CONTINUOUS 0x2 Continuous mode: Timer counts up to 0FFFFh UPDOWN 0x3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h ID [7:6] Input divider 2 6 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 TASSEL [9:8] TimerA clock source select 2 8 TACLK 0x0 TAxCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK INCLK 0x3 INCLK 0 TA3CCTL0 0x2 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA3CCTL1 0x4 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA3R 0x10 16 TimerA register 0 TA3CCR0 0x12 16 Timer_A Capture/Compare Register 0 TA3CCR1 0x14 16 Timer_A Capture/Compare Register 0 TA3EX0 0x20 16 TimerAx Expansion 0 Register TAIDEX [2:0] Input divider expansion 3 0 1 0x0 Divide by 1 2 0x1 Divide by 2 3 0x2 Divide by 3 4 0x3 Divide by 4 5 0x4 Divide by 5 6 0x5 Divide by 6 7 0x6 Divide by 7 8 0x7 Divide by 8 0 TA3IV 0x2E 16 TimerAx Interrupt Vector Register TAIV [15:0] TimerA interrupt vector value 16 0 NONE 0x0 No interrupt pending TACCR1 0x2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest TACCR2 0x4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG TACCR3 0x6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG TACCR4 0x8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG TACCR5 0xA Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG TACCR6 0xC Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG TAIFG 0xE Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 0 TA4 0x07C0 0 10 registers TA4CTL 0x0 16 TimerAx Control Register TAIFG [0:0] TimerA interrupt flag 1 0 TAIFG_0 0x0 No interrupt pending TAIFG_1 0x1 Interrupt pending TAIE [1:1] TimerA interrupt enable 1 1 TAIE_0 0x0 Interrupt disabled TAIE_1 0x1 Interrupt enabled TACLR [2:2] TimerA clear 1 2 MC [5:4] Mode control 2 4 STOP 0x0 Stop mode: Timer is halted UP 0x1 Up mode: Timer counts up to TAxCCR0 CONTINUOUS 0x2 Continuous mode: Timer counts up to 0FFFFh UPDOWN 0x3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h ID [7:6] Input divider 2 6 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 TASSEL [9:8] TimerA clock source select 2 8 TACLK 0x0 TAxCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK INCLK 0x3 INCLK 0 TA4CCTL0 0x2 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA4CCTL1 0x4 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA4CCTL2 0x6 16 Timer_A Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode SCCI [10:10] Synchronized capture/compare input 1 10 SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TA4R 0x10 16 TimerA register 0 TA4CCR0 0x12 16 Timer_A Capture/Compare Register 0 TA4CCR1 0x14 16 Timer_A Capture/Compare Register 0 TA4CCR2 0x16 16 Timer_A Capture/Compare Register 0 TA4EX0 0x20 16 TimerAx Expansion 0 Register TAIDEX [2:0] Input divider expansion 3 0 1 0x0 Divide by 1 2 0x1 Divide by 2 3 0x2 Divide by 3 4 0x3 Divide by 4 5 0x4 Divide by 5 6 0x5 Divide by 6 7 0x6 Divide by 7 8 0x7 Divide by 8 0 TA4IV 0x2E 16 TimerAx Interrupt Vector Register TAIV [15:0] TimerA interrupt vector value 16 0 NONE 0x0 No interrupt pending TACCR1 0x2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest TACCR2 0x4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG TACCR3 0x6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG TACCR4 0x8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG TACCR5 0xA Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG TACCR6 0xC Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG TAIFG 0xE Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 0 TB0 0x03C0 0 10 registers TB0CTL 0x0 16 Timer_B Control Register TBIFG [0:0] TimerB interrupt flag 1 0 TBIFG_0 0x0 No interrupt pending TBIFG_1 0x1 Interrupt pending TBIE [1:1] TimerB interrupt enable 1 1 TBIE_0 0x0 Interrupt disabled TBIE_1 0x1 Interrupt enabled TBCLR [2:2] TimerB clear 1 2 MC [5:4] Mode control 2 4 STOP 0x0 Stop mode: Timer is halted UP 0x1 Up mode: Timer counts up to TBxCL0 CONTINUOUS 0x2 Continuous mode: Timer counts up to the value set by CNTL UPDOWN 0x3 Up/down mode: Timer counts up to TBxCL0 then down to 0000h ID [7:6] Input divider 2 6 1 0x0 /1 2 0x1 /2 4 0x2 /4 8 0x3 /8 TBSSEL [9:8] TimerB clock source select 2 8 TBCLK 0x0 TBxCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK INCLK 0x3 INCLK CNTL [12:11] Counter length 2 11 16 0x0 16-bit, TBxR(max) = 0FFFFh 12 0x1 12-bit, TBxR(max) = 0FFFh 10 0x2 10-bit, TBxR(max) = 03FFh 8 0x3 8-bit, TBxR(max) = 0FFh TBCLGRP [14:13] TBxCLn group 2 13 TBCLGRP_0 0x0 Each TBxCLn latch loads independently TBCLGRP_1 0x1 TBxCL1+TBxCL2 (TBxCCR1 CLLD bits control the update); TBxCL3+TBxCL4 (TBxCCR3 CLLD bits control the update); TBxCL5+TBxCL6 (TBxCCR5 CLLD bits control the update); TBxCL0 independent TBCLGRP_2 0x2 TBxCL1+TBxCL2+TBxCL3 (TBxCCR1 CLLD bits control the update); TBxCL4+TBxCL5+TBxCL6 (TBxCCR4 CLLD bits control the update); TBxCL0 independent TBCLGRP_3 0x3 TBxCL0+TBxCL1+TBxCL2+TBxCL3+TBxCL4+TBxCL5+TBxCL6 (TBxCCR1 CLLD bits control the update) 0 TB0CCTL0 0x2 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0CCTL1 0x4 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0CCTL2 0x6 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0CCTL3 0x8 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0CCTL4 0xA 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0CCTL5 0xC 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0CCTL6 0xE 16 Timer_B Capture/Compare Control Register CCIFG [0:0] Capture/compare interrupt flag 1 0 CCIFG_0 0x0 No interrupt pending CCIFG_1 0x1 Interrupt pending COV [1:1] Capture overflow 1 1 COV_0 0x0 No capture overflow occurred COV_1 0x1 Capture overflow occurred OUT [2:2] Output 1 2 LOW 0x0 Output low HIGH 0x1 Output high CCI [3:3] Capture/compare input 1 3 CCIE [4:4] Capture/compare interrupt enable 1 4 CCIE_0 0x0 Interrupt disabled CCIE_1 0x1 Interrupt enabled OUTMOD [7:5] Output mode 3 5 OUTMOD_0 0x0 OUT bit value OUTMOD_1 0x1 Set OUTMOD_2 0x2 Toggle/reset OUTMOD_3 0x3 Set/reset OUTMOD_4 0x4 Toggle OUTMOD_5 0x5 Reset OUTMOD_6 0x6 Toggle/set OUTMOD_7 0x7 Reset/set CAP [8:8] Capture mode 1 8 COMPARE 0x0 Compare mode CAPTURE 0x1 Capture mode CLLD [10:9] Compare latch load 2 9 CLLD_0 0x0 TBxCLn loads on write to TBxCCRn CLLD_1 0x1 TBxCLn loads when TBxR counts to 0 CLLD_2 0x2 TBxCLn loads when TBxR counts to 0 (up or continuous mode). TBxCLn loads when TBxR counts to TBxCL0 or to 0 (up/down mode). CLLD_3 0x3 TBxCLn loads when TBxR counts to TBxCLn SCS [11:11] Synchronize capture source 1 11 ASYNC 0x0 Asynchronous capture SYNC 0x1 Synchronous capture CCIS [13:12] Capture/compare input select 2 12 CCIA 0x0 CCIxA CCIB 0x1 CCIxB GND 0x2 GND VCC 0x3 VCC CM [15:14] Capture mode 2 14 NONE 0x0 No capture RISING 0x1 Capture on rising edge FALLING 0x2 Capture on falling edge BOTH 0x3 Capture on both rising and falling edges 0 TB0R 0x10 16 Timer_B count register 0 TB0CCR0 0x12 16 Timer_B Capture/Compare Register 0 TB0CCR1 0x14 16 Timer_B Capture/Compare Register 0 TB0CCR2 0x16 16 Timer_B Capture/Compare Register 0 TB0CCR3 0x18 16 Timer_B Capture/Compare Register 0 TB0CCR4 0x1A 16 Timer_B Capture/Compare Register 0 TB0CCR5 0x1C 16 Timer_B Capture/Compare Register 0 TB0CCR6 0x1E 16 Timer_B Capture/Compare Register 0 TB0EX0 0x20 16 Timer_Bx Expansion Register 0 TBIDEX [2:0] Input divider expansion 3 0 1 0x0 Divide by 1 2 0x1 Divide by 2 3 0x2 Divide by 3 4 0x3 Divide by 4 5 0x4 Divide by 5 6 0x5 Divide by 6 7 0x6 Divide by 7 8 0x7 Divide by 8 0 TB0IV 0x2E 16 Timer_Bx Interrupt Vector Register TBIV [15:0] Timer_B interrupt vector value 16 0 NONE 0x0 No interrupt pending TBCCR1 0x2 Interrupt Source: Capture/compare 1; Interrupt Flag: TBxCCR1 CCIFG; Interrupt Priority: Highest TBCCR2 0x4 Interrupt Source: Capture/compare 2; Interrupt Flag: TBxCCR2 CCIFG TBCCR3 0x6 Interrupt Source: Capture/compare 3; Interrupt Flag: TBxCCR3 CCIFG TBCCR4 0x8 Interrupt Source: Capture/compare 4; Interrupt Flag: TBxCCR4 CCIFG TBCCR5 0xA Interrupt Source: Capture/compare 5; Interrupt Flag: TBxCCR5 CCIFG TBCCR6 0xC Interrupt Source: Capture/compare 6; Interrupt Flag: TBxCCR6 CCIFG TBIFG 0xE Interrupt Source: Timer overflow; Interrupt Flag: TBxCTL TBIFG; Interrupt Priority: Lowest 0 WDT_A 0x015C 0 10 registers WDTCTL 0x0 16 Watchdog Timer Control Register WDTIS [2:0] Watchdog timer interval select 3 0 2G 0x0 Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) 128M 0x1 Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) 8192K 0x2 Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) 512K 0x3 Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) 32K 0x4 Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) 8192 0x5 Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) 512 0x6 Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) 64 0x7 Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) WDTCNTCL [3:3] Watchdog timer counter clear 1 3 WDTCNTCL_0 0x0 No action WDTCNTCL_1 0x1 WDTCNT = 0000h WDTTMSEL [4:4] Watchdog timer mode select 1 4 WDTTMSEL_0 0x0 Watchdog mode WDTTMSEL_1 0x1 Interval timer mode WDTSSEL [6:5] Watchdog timer clock source select 2 5 SMCLK 0x0 SMCLK ACLK 0x1 ACLK VLOCLK 0x2 VLOCLK BCLK 0x3 BCLK WDTHOLD [7:7] Watchdog timer hold 1 7 UNHOLD 0x0 Watchdog timer is not stopped HOLD 0x1 Watchdog timer is stopped WDTPW [15:8] Watchdog timer password 8 8 0 eUSCI_A0 0x05C0 0 10 registers UCA0CTLW0 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCTXBRK [1:1] Transmit break 1 1 UCTXBRK_0 0x0 Next frame transmitted is not a break UCTXBRK_1 0x1 Next frame transmitted is a break or a break/synch UCTXADDR [2:2] Transmit address 1 2 UCTXADDR_0 0x0 Next frame transmitted is data UCTXADDR_1 0x1 Next frame transmitted is an address UCDORM [3:3] Dormant 1 3 UCDORM_0 0x0 Not dormant. All received characters set UCRXIFG. UCDORM_1 0x1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. UCBRKIE [4:4] Receive break character interrupt enable 1 4 UCBRKIE_0 0x0 Received break characters do not set UCRXIFG UCBRKIE_1 0x1 Received break characters set UCRXIFG UCRXEIE [5:5] Receive erroneous-character interrupt enable 1 5 UCRXEIE_0 0x0 Erroneous characters rejected and UCRXIFG is not set UCRXEIE_1 0x1 Erroneous characters received set UCRXIFG UCSSEL [7:6] eUSCI_A clock source select 2 6 UCLK 0x0 UCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_A mode 2 9 UCMODE_0 0x0 UART mode UCMODE_1 0x1 Idle-line multiprocessor mode UCMODE_2 0x2 Address-bit multiprocessor mode UCMODE_3 0x3 UART mode with automatic baud-rate detection UCSPB [11:11] Stop bit select 1 11 UCSPB_0 0x0 One stop bit UCSPB_1 0x1 Two stop bits UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCPAR [14:14] Parity select 1 14 ODD 0x0 Odd parity EVEN 0x1 Even parity UCPEN [15:15] Parity enable 1 15 UCPEN_0 0x0 Parity disabled UCPEN_1 0x1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 0 UCA0CTLW0_SPI 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_A clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCA0CTLW1 0x2 16 eUSCI_Ax Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 Approximately 2 ns (equivalent of 1 delay element) UCGLIT_1 0x1 Approximately 50 ns UCGLIT_2 0x2 Approximately 100 ns UCGLIT_3 0x3 Approximately 200 ns 0 UCA0BRW 0x6 16 eUSCI_Ax Baud Rate Control Word Register 0 UCA0BRW_SPI 0x6 16 eUSCI_Ax Bit Rate Control Register 1 0 UCA0MCTLW 0x8 16 eUSCI_Ax Modulation Control Word Register UCOS16 [0:0] Oversampling mode enabled 1 0 UCOS16_0 0x0 Disabled UCOS16_1 0x1 Enabled UCBRF [7:4] First modulation stage select 4 4 UCBRS [15:8] Second modulation stage select 8 8 0 UCA0STATW 0xA 16 eUSCI_Ax Status Register UCBUSY [0:0] eUSCI_A busy 1 0 IDLE 0x0 eUSCI_A inactive BUSY 0x1 eUSCI_A transmitting or receiving UCADDR_UCIDLE [1:1] Address received / Idle line detected 1 1 UCRXERR [2:2] Receive error flag 1 2 UCRXERR_0 0x0 No receive errors detected UCRXERR_1 0x1 Receive error detected UCBRK [3:3] Break detect flag 1 3 UCBRK_0 0x0 No break condition UCBRK_1 0x1 Break condition occurred UCPE [4:4] Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 1 4 UCPE_0 0x0 No error UCPE_1 0x1 Character received with parity error UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Character received with low stop bit UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA0STATW_SPI 0xA 16 UCA0STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA0RXBUF 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA0RXBUF_SPI 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA0TXBUF 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA0TXBUF_SPI 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA0ABCTL 0x10 16 eUSCI_Ax Auto Baud Rate Control Register UCABDEN [0:0] Automatic baud-rate detect enable 1 0 UCABDEN_0 0x0 Baud-rate detection disabled. Length of break and synch field is not measured. UCABDEN_1 0x1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. UCBTOE [2:2] Break time out error 1 2 UCBTOE_0 0x0 No error UCBTOE_1 0x1 Length of break field exceeded 22 bit times UCSTOE [3:3] Synch field time out error 1 3 UCSTOE_0 0x0 No error UCSTOE_1 0x1 Length of synch field exceeded measurable time UCDELIM [5:4] Break/synch delimiter length 2 4 UCDELIM_0 0x0 1 bit time UCDELIM_1 0x1 2 bit times UCDELIM_2 0x2 3 bit times UCDELIM_3 0x3 4 bit times 0 UCA0IRCTL 0x12 16 eUSCI_Ax IrDA Control Word Register UCIREN [0:0] IrDA encoder/decoder enable 1 0 UCIREN_0 0x0 IrDA encoder/decoder disabled UCIREN_1 0x1 IrDA encoder/decoder enabled UCIRTXCLK [1:1] IrDA transmit pulse clock select 1 1 UCIRTXCLK_0 0x0 BRCLK UCIRTXCLK_1 0x1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. UCIRTXPL [7:2] Transmit pulse length 6 2 UCIRRXFE [8:8] IrDA receive filter enabled 1 8 UCIRRXFE_0 0x0 Receive filter disabled UCIRRXFE_1 0x1 Receive filter enabled UCIRRXPL [9:9] IrDA receive input UCAxRXD polarity 1 9 HIGH 0x0 IrDA transceiver delivers a high pulse when a light pulse is seen LOW 0x1 IrDA transceiver delivers a low pulse when a light pulse is seen UCIRRXFL [15:10] Receive filter length 6 10 0 UCA0IE 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled UCSTTIE [2:2] Start bit interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCTXCPTIE [3:3] Transmit complete interrupt enable 1 3 UCTXCPTIE_0 0x0 Interrupt disabled UCTXCPTIE_1 0x1 Interrupt enabled 0 UCA0IE_SPI 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCA0IFG 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending UCSTTIFG [2:2] Start bit interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCTXCPTIFG [3:3] Transmit ready interrupt enable 1 3 UCTXCPTIFG_0 0x0 No interrupt pending UCTXCPTIFG_1 0x1 Interrupt pending 0 UCA0IFG_SPI 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCA0IV 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG UCSTTIFG 0x6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG UCTXCPTIFG 0x8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 0 UCA0IV_SPI 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_A1 0x05E0 0 10 registers UCA1CTLW0 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCTXBRK [1:1] Transmit break 1 1 UCTXBRK_0 0x0 Next frame transmitted is not a break UCTXBRK_1 0x1 Next frame transmitted is a break or a break/synch UCTXADDR [2:2] Transmit address 1 2 UCTXADDR_0 0x0 Next frame transmitted is data UCTXADDR_1 0x1 Next frame transmitted is an address UCDORM [3:3] Dormant 1 3 UCDORM_0 0x0 Not dormant. All received characters set UCRXIFG. UCDORM_1 0x1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. UCBRKIE [4:4] Receive break character interrupt enable 1 4 UCBRKIE_0 0x0 Received break characters do not set UCRXIFG UCBRKIE_1 0x1 Received break characters set UCRXIFG UCRXEIE [5:5] Receive erroneous-character interrupt enable 1 5 UCRXEIE_0 0x0 Erroneous characters rejected and UCRXIFG is not set UCRXEIE_1 0x1 Erroneous characters received set UCRXIFG UCSSEL [7:6] eUSCI_A clock source select 2 6 UCLK 0x0 UCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_A mode 2 9 UCMODE_0 0x0 UART mode UCMODE_1 0x1 Idle-line multiprocessor mode UCMODE_2 0x2 Address-bit multiprocessor mode UCMODE_3 0x3 UART mode with automatic baud-rate detection UCSPB [11:11] Stop bit select 1 11 UCSPB_0 0x0 One stop bit UCSPB_1 0x1 Two stop bits UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCPAR [14:14] Parity select 1 14 ODD 0x0 Odd parity EVEN 0x1 Even parity UCPEN [15:15] Parity enable 1 15 UCPEN_0 0x0 Parity disabled UCPEN_1 0x1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 0 UCA1CTLW0_SPI 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_A clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCA1CTLW1 0x2 16 eUSCI_Ax Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 Approximately 2 ns (equivalent of 1 delay element) UCGLIT_1 0x1 Approximately 50 ns UCGLIT_2 0x2 Approximately 100 ns UCGLIT_3 0x3 Approximately 200 ns 0 UCA1BRW 0x6 16 eUSCI_Ax Baud Rate Control Word Register 0 UCA1BRW_SPI 0x6 16 eUSCI_Ax Bit Rate Control Register 1 0 UCA1MCTLW 0x8 16 eUSCI_Ax Modulation Control Word Register UCOS16 [0:0] Oversampling mode enabled 1 0 UCOS16_0 0x0 Disabled UCOS16_1 0x1 Enabled UCBRF [7:4] First modulation stage select 4 4 UCBRS [15:8] Second modulation stage select 8 8 0 UCA1STATW 0xA 16 eUSCI_Ax Status Register UCBUSY [0:0] eUSCI_A busy 1 0 IDLE 0x0 eUSCI_A inactive BUSY 0x1 eUSCI_A transmitting or receiving UCADDR_UCIDLE [1:1] Address received / Idle line detected 1 1 UCRXERR [2:2] Receive error flag 1 2 UCRXERR_0 0x0 No receive errors detected UCRXERR_1 0x1 Receive error detected UCBRK [3:3] Break detect flag 1 3 UCBRK_0 0x0 No break condition UCBRK_1 0x1 Break condition occurred UCPE [4:4] Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 1 4 UCPE_0 0x0 No error UCPE_1 0x1 Character received with parity error UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Character received with low stop bit UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA1STATW_SPI 0xA 16 UCA1STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA1RXBUF 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA1RXBUF_SPI 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA1TXBUF 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA1TXBUF_SPI 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA1ABCTL 0x10 16 eUSCI_Ax Auto Baud Rate Control Register UCABDEN [0:0] Automatic baud-rate detect enable 1 0 UCABDEN_0 0x0 Baud-rate detection disabled. Length of break and synch field is not measured. UCABDEN_1 0x1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. UCBTOE [2:2] Break time out error 1 2 UCBTOE_0 0x0 No error UCBTOE_1 0x1 Length of break field exceeded 22 bit times UCSTOE [3:3] Synch field time out error 1 3 UCSTOE_0 0x0 No error UCSTOE_1 0x1 Length of synch field exceeded measurable time UCDELIM [5:4] Break/synch delimiter length 2 4 UCDELIM_0 0x0 1 bit time UCDELIM_1 0x1 2 bit times UCDELIM_2 0x2 3 bit times UCDELIM_3 0x3 4 bit times 0 UCA1IRCTL 0x12 16 eUSCI_Ax IrDA Control Word Register UCIREN [0:0] IrDA encoder/decoder enable 1 0 UCIREN_0 0x0 IrDA encoder/decoder disabled UCIREN_1 0x1 IrDA encoder/decoder enabled UCIRTXCLK [1:1] IrDA transmit pulse clock select 1 1 UCIRTXCLK_0 0x0 BRCLK UCIRTXCLK_1 0x1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. UCIRTXPL [7:2] Transmit pulse length 6 2 UCIRRXFE [8:8] IrDA receive filter enabled 1 8 UCIRRXFE_0 0x0 Receive filter disabled UCIRRXFE_1 0x1 Receive filter enabled UCIRRXPL [9:9] IrDA receive input UCAxRXD polarity 1 9 HIGH 0x0 IrDA transceiver delivers a high pulse when a light pulse is seen LOW 0x1 IrDA transceiver delivers a low pulse when a light pulse is seen UCIRRXFL [15:10] Receive filter length 6 10 0 UCA1IE 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled UCSTTIE [2:2] Start bit interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCTXCPTIE [3:3] Transmit complete interrupt enable 1 3 UCTXCPTIE_0 0x0 Interrupt disabled UCTXCPTIE_1 0x1 Interrupt enabled 0 UCA1IE_SPI 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCA1IFG 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending UCSTTIFG [2:2] Start bit interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCTXCPTIFG [3:3] Transmit ready interrupt enable 1 3 UCTXCPTIFG_0 0x0 No interrupt pending UCTXCPTIFG_1 0x1 Interrupt pending 0 UCA1IFG_SPI 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCA1IV 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG UCSTTIFG 0x6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG UCTXCPTIFG 0x8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 0 UCA1IV_SPI 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_A2 0x0600 0 10 registers UCA2CTLW0 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCTXBRK [1:1] Transmit break 1 1 UCTXBRK_0 0x0 Next frame transmitted is not a break UCTXBRK_1 0x1 Next frame transmitted is a break or a break/synch UCTXADDR [2:2] Transmit address 1 2 UCTXADDR_0 0x0 Next frame transmitted is data UCTXADDR_1 0x1 Next frame transmitted is an address UCDORM [3:3] Dormant 1 3 UCDORM_0 0x0 Not dormant. All received characters set UCRXIFG. UCDORM_1 0x1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. UCBRKIE [4:4] Receive break character interrupt enable 1 4 UCBRKIE_0 0x0 Received break characters do not set UCRXIFG UCBRKIE_1 0x1 Received break characters set UCRXIFG UCRXEIE [5:5] Receive erroneous-character interrupt enable 1 5 UCRXEIE_0 0x0 Erroneous characters rejected and UCRXIFG is not set UCRXEIE_1 0x1 Erroneous characters received set UCRXIFG UCSSEL [7:6] eUSCI_A clock source select 2 6 UCLK 0x0 UCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_A mode 2 9 UCMODE_0 0x0 UART mode UCMODE_1 0x1 Idle-line multiprocessor mode UCMODE_2 0x2 Address-bit multiprocessor mode UCMODE_3 0x3 UART mode with automatic baud-rate detection UCSPB [11:11] Stop bit select 1 11 UCSPB_0 0x0 One stop bit UCSPB_1 0x1 Two stop bits UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCPAR [14:14] Parity select 1 14 ODD 0x0 Odd parity EVEN 0x1 Even parity UCPEN [15:15] Parity enable 1 15 UCPEN_0 0x0 Parity disabled UCPEN_1 0x1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 0 UCA2CTLW0_SPI 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_A clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCA2CTLW1 0x2 16 eUSCI_Ax Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 Approximately 2 ns (equivalent of 1 delay element) UCGLIT_1 0x1 Approximately 50 ns UCGLIT_2 0x2 Approximately 100 ns UCGLIT_3 0x3 Approximately 200 ns 0 UCA2BRW 0x6 16 eUSCI_Ax Baud Rate Control Word Register 0 UCA2BRW_SPI 0x6 16 eUSCI_Ax Bit Rate Control Register 1 0 UCA2MCTLW 0x8 16 eUSCI_Ax Modulation Control Word Register UCOS16 [0:0] Oversampling mode enabled 1 0 UCOS16_0 0x0 Disabled UCOS16_1 0x1 Enabled UCBRF [7:4] First modulation stage select 4 4 UCBRS [15:8] Second modulation stage select 8 8 0 UCA2STATW 0xA 16 eUSCI_Ax Status Register UCBUSY [0:0] eUSCI_A busy 1 0 IDLE 0x0 eUSCI_A inactive BUSY 0x1 eUSCI_A transmitting or receiving UCADDR_UCIDLE [1:1] Address received / Idle line detected 1 1 UCRXERR [2:2] Receive error flag 1 2 UCRXERR_0 0x0 No receive errors detected UCRXERR_1 0x1 Receive error detected UCBRK [3:3] Break detect flag 1 3 UCBRK_0 0x0 No break condition UCBRK_1 0x1 Break condition occurred UCPE [4:4] Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 1 4 UCPE_0 0x0 No error UCPE_1 0x1 Character received with parity error UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Character received with low stop bit UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA2STATW_SPI 0xA 16 UCA2STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA2RXBUF 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA2RXBUF_SPI 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA2TXBUF 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA2TXBUF_SPI 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA2ABCTL 0x10 16 eUSCI_Ax Auto Baud Rate Control Register UCABDEN [0:0] Automatic baud-rate detect enable 1 0 UCABDEN_0 0x0 Baud-rate detection disabled. Length of break and synch field is not measured. UCABDEN_1 0x1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. UCBTOE [2:2] Break time out error 1 2 UCBTOE_0 0x0 No error UCBTOE_1 0x1 Length of break field exceeded 22 bit times UCSTOE [3:3] Synch field time out error 1 3 UCSTOE_0 0x0 No error UCSTOE_1 0x1 Length of synch field exceeded measurable time UCDELIM [5:4] Break/synch delimiter length 2 4 UCDELIM_0 0x0 1 bit time UCDELIM_1 0x1 2 bit times UCDELIM_2 0x2 3 bit times UCDELIM_3 0x3 4 bit times 0 UCA2IRCTL 0x12 16 eUSCI_Ax IrDA Control Word Register UCIREN [0:0] IrDA encoder/decoder enable 1 0 UCIREN_0 0x0 IrDA encoder/decoder disabled UCIREN_1 0x1 IrDA encoder/decoder enabled UCIRTXCLK [1:1] IrDA transmit pulse clock select 1 1 UCIRTXCLK_0 0x0 BRCLK UCIRTXCLK_1 0x1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. UCIRTXPL [7:2] Transmit pulse length 6 2 UCIRRXFE [8:8] IrDA receive filter enabled 1 8 UCIRRXFE_0 0x0 Receive filter disabled UCIRRXFE_1 0x1 Receive filter enabled UCIRRXPL [9:9] IrDA receive input UCAxRXD polarity 1 9 HIGH 0x0 IrDA transceiver delivers a high pulse when a light pulse is seen LOW 0x1 IrDA transceiver delivers a low pulse when a light pulse is seen UCIRRXFL [15:10] Receive filter length 6 10 0 UCA2IE 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled UCSTTIE [2:2] Start bit interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCTXCPTIE [3:3] Transmit complete interrupt enable 1 3 UCTXCPTIE_0 0x0 Interrupt disabled UCTXCPTIE_1 0x1 Interrupt enabled 0 UCA2IE_SPI 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCA2IFG 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending UCSTTIFG [2:2] Start bit interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCTXCPTIFG [3:3] Transmit ready interrupt enable 1 3 UCTXCPTIFG_0 0x0 No interrupt pending UCTXCPTIFG_1 0x1 Interrupt pending 0 UCA2IFG_SPI 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCA2IV 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG UCSTTIFG 0x6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG UCTXCPTIFG 0x8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 0 UCA2IV_SPI 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_A3 0x0620 0 10 registers UCA3CTLW0 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCTXBRK [1:1] Transmit break 1 1 UCTXBRK_0 0x0 Next frame transmitted is not a break UCTXBRK_1 0x1 Next frame transmitted is a break or a break/synch UCTXADDR [2:2] Transmit address 1 2 UCTXADDR_0 0x0 Next frame transmitted is data UCTXADDR_1 0x1 Next frame transmitted is an address UCDORM [3:3] Dormant 1 3 UCDORM_0 0x0 Not dormant. All received characters set UCRXIFG. UCDORM_1 0x1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. UCBRKIE [4:4] Receive break character interrupt enable 1 4 UCBRKIE_0 0x0 Received break characters do not set UCRXIFG UCBRKIE_1 0x1 Received break characters set UCRXIFG UCRXEIE [5:5] Receive erroneous-character interrupt enable 1 5 UCRXEIE_0 0x0 Erroneous characters rejected and UCRXIFG is not set UCRXEIE_1 0x1 Erroneous characters received set UCRXIFG UCSSEL [7:6] eUSCI_A clock source select 2 6 UCLK 0x0 UCLK ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_A mode 2 9 UCMODE_0 0x0 UART mode UCMODE_1 0x1 Idle-line multiprocessor mode UCMODE_2 0x2 Address-bit multiprocessor mode UCMODE_3 0x3 UART mode with automatic baud-rate detection UCSPB [11:11] Stop bit select 1 11 UCSPB_0 0x0 One stop bit UCSPB_1 0x1 Two stop bits UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCPAR [14:14] Parity select 1 14 ODD 0x0 Odd parity EVEN 0x1 Even parity UCPEN [15:15] Parity enable 1 15 UCPEN_0 0x0 Parity disabled UCPEN_1 0x1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 0 UCA3CTLW0_SPI 0x0 16 eUSCI_Ax Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_A reset released for operation ENABLE 0x1 Enabled. eUSCI_A logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_A clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCA3CTLW1 0x2 16 eUSCI_Ax Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 Approximately 2 ns (equivalent of 1 delay element) UCGLIT_1 0x1 Approximately 50 ns UCGLIT_2 0x2 Approximately 100 ns UCGLIT_3 0x3 Approximately 200 ns 0 UCA3BRW 0x6 16 eUSCI_Ax Baud Rate Control Word Register 0 UCA3BRW_SPI 0x6 16 eUSCI_Ax Bit Rate Control Register 1 0 UCA3MCTLW 0x8 16 eUSCI_Ax Modulation Control Word Register UCOS16 [0:0] Oversampling mode enabled 1 0 UCOS16_0 0x0 Disabled UCOS16_1 0x1 Enabled UCBRF [7:4] First modulation stage select 4 4 UCBRS [15:8] Second modulation stage select 8 8 0 UCA3STATW 0xA 16 eUSCI_Ax Status Register UCBUSY [0:0] eUSCI_A busy 1 0 IDLE 0x0 eUSCI_A inactive BUSY 0x1 eUSCI_A transmitting or receiving UCADDR_UCIDLE [1:1] Address received / Idle line detected 1 1 UCRXERR [2:2] Receive error flag 1 2 UCRXERR_0 0x0 No receive errors detected UCRXERR_1 0x1 Receive error detected UCBRK [3:3] Break detect flag 1 3 UCBRK_0 0x0 No break condition UCBRK_1 0x1 Break condition occurred UCPE [4:4] Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 1 4 UCPE_0 0x0 No error UCPE_1 0x1 Character received with parity error UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Character received with low stop bit UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA3STATW_SPI 0xA 16 UCA3STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCAxTXD is internally fed back to the receiver 0 UCA3RXBUF 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA3RXBUF_SPI 0xC 16 eUSCI_Ax Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCA3TXBUF 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA3TXBUF_SPI 0xE 16 eUSCI_Ax Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCA3ABCTL 0x10 16 eUSCI_Ax Auto Baud Rate Control Register UCABDEN [0:0] Automatic baud-rate detect enable 1 0 UCABDEN_0 0x0 Baud-rate detection disabled. Length of break and synch field is not measured. UCABDEN_1 0x1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. UCBTOE [2:2] Break time out error 1 2 UCBTOE_0 0x0 No error UCBTOE_1 0x1 Length of break field exceeded 22 bit times UCSTOE [3:3] Synch field time out error 1 3 UCSTOE_0 0x0 No error UCSTOE_1 0x1 Length of synch field exceeded measurable time UCDELIM [5:4] Break/synch delimiter length 2 4 UCDELIM_0 0x0 1 bit time UCDELIM_1 0x1 2 bit times UCDELIM_2 0x2 3 bit times UCDELIM_3 0x3 4 bit times 0 UCA3IRCTL 0x12 16 eUSCI_Ax IrDA Control Word Register UCIREN [0:0] IrDA encoder/decoder enable 1 0 UCIREN_0 0x0 IrDA encoder/decoder disabled UCIREN_1 0x1 IrDA encoder/decoder enabled UCIRTXCLK [1:1] IrDA transmit pulse clock select 1 1 UCIRTXCLK_0 0x0 BRCLK UCIRTXCLK_1 0x1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. UCIRTXPL [7:2] Transmit pulse length 6 2 UCIRRXFE [8:8] IrDA receive filter enabled 1 8 UCIRRXFE_0 0x0 Receive filter disabled UCIRRXFE_1 0x1 Receive filter enabled UCIRRXPL [9:9] IrDA receive input UCAxRXD polarity 1 9 HIGH 0x0 IrDA transceiver delivers a high pulse when a light pulse is seen LOW 0x1 IrDA transceiver delivers a low pulse when a light pulse is seen UCIRRXFL [15:10] Receive filter length 6 10 0 UCA3IE 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled UCSTTIE [2:2] Start bit interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCTXCPTIE [3:3] Transmit complete interrupt enable 1 3 UCTXCPTIE_0 0x0 Interrupt disabled UCTXCPTIE_1 0x1 Interrupt enabled 0 UCA3IE_SPI 0x1A 16 eUSCI_Ax Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCA3IFG 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending UCSTTIFG [2:2] Start bit interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCTXCPTIFG [3:3] Transmit ready interrupt enable 1 3 UCTXCPTIFG_0 0x0 No interrupt pending UCTXCPTIFG_1 0x1 Interrupt pending 0 UCA3IFG_SPI 0x1C 16 eUSCI_Ax Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCA3IV 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG UCSTTIFG 0x6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG UCTXCPTIFG 0x8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 0 UCA3IV_SPI 0x1E 16 eUSCI_Ax Interrupt Vector Register UCIV [15:0] eUSCI_A interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_B0 0x0640 0 10 registers UCB0CTLW0 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCTXSTT [1:1] Transmit START condition in master mode 1 1 UCTXSTT_0 0x0 Do not generate START condition UCTXSTT_1 0x1 Generate START condition UCTXSTP [2:2] Transmit STOP condition in master mode 1 2 UCTXSTP_0 0x0 No STOP generated UCTXSTP_1 0x1 Generate STOP UCTXNACK [3:3] Transmit a NACK 1 3 UCTXNACK_0 0x0 Acknowledge normally UCTXNACK_1 0x1 Generate NACK UCTR [4:4] Transmitter/receiver 1 4 RX 0x0 Receiver TX 0x1 Transmitter UCTXACK [5:5] Transmit ACK condition in slave mode 1 5 UCTXACK_0 0x0 Do not acknowledge the slave address UCTXACK_1 0x1 Acknowledge the slave address UCSSEL [7:6] eUSCI_B clock source select 2 6 UCLKI 0x0 UCLKI ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_B mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI (master or slave enabled if STE = 1) UCMODE_2 0x2 4-pin SPI (master or slave enabled if STE = 0) UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UCMM [13:13] Multi-master environment select 1 13 SINGLE 0x0 Single master environment. There is no other master in the system. The address compare unit is disabled. MULTI 0x1 Multi-master environment UCSLA10 [14:14] Slave addressing mode select 1 14 7BIT 0x0 Address slave with 7-bit address 10BIT 0x1 Address slave with 10-bit address UCA10 [15:15] Own addressing mode select 1 15 UCA10_0 0x0 Own address is a 7-bit address UCA10_1 0x1 Own address is a 10-bit address 0 UCB0CTLW0_SPI 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_B clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCB0CTLW1 0x2 16 eUSCI_Bx Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 50 ns UCGLIT_1 0x1 25 ns UCGLIT_2 0x2 12.5 ns UCGLIT_3 0x3 6.25 ns UCASTP [3:2] Automatic STOP condition generation 2 2 UCASTP_0 0x0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. UCASTP_1 0x1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT UCASTP_2 0x2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold UCSWACK [4:4] SW or HW ACK control 1 4 UCSWACK_0 0x0 The address acknowledge of the slave is controlled by the eUSCI_B module UCSWACK_1 0x1 The user needs to trigger the sending of the address ACK by issuing UCTXACK UCSTPNACK [5:5] ACK all master bytes 1 5 UCSTPNACK_0 0x0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) UCSTPNACK_1 0x1 All bytes are acknowledged by the eUSCI_B when configured as master receiver UCCLTO [7:6] Clock low timeout select 2 6 UCCLTO_0 0x0 Disable clock low timeout counter UCCLTO_1 0x1 135 000 SYSCLK cycles (approximately 28 ms) UCCLTO_2 0x2 150 000 SYSCLK cycles (approximately 31 ms) UCCLTO_3 0x3 165 000 SYSCLK cycles (approximately 34 ms) UCETXINT [8:8] Early UCTXIFG0 1 8 UCETXINT_0 0x0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit UCETXINT_1 0x1 UCTXIFG0 is set for each START condition 0 UCB0BRW 0x6 16 eUSCI_Bx Baud Rate Control Word Register 0 UCB0BRW_SPI 0x6 16 eUSCI_Bx Bit Rate Control Register 1 0 UCB0STATW 0x8 16 eUSCI_Bx Status Register UCBBUSY [4:4] Bus busy 1 4 IDLE 0x0 Bus inactive BUSY 0x1 Bus busy UCGC [5:5] General call address received 1 5 UCGC_0 0x0 No general call address received UCGC_1 0x1 General call address received UCSCLLOW [6:6] SCL low 1 6 UCSCLLOW_0 0x0 SCL is not held low UCSCLLOW_1 0x1 SCL is held low UCBCNT [15:8] Hardware byte counter value 8 8 0 UCB0STATW_SPI 0x8 16 UCB0STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCBxTXD is internally fed back to the receiver 0 UCB0TBCNT 0xA 16 eUSCI_Bx Byte Counter Threshold Register UCTBCNT [7:0] Byte counter threshold value 8 0 0 UCB0RXBUF 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB0RXBUF_SPI 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB0TXBUF 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB0TXBUF_SPI 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB0I2COA0 0x14 16 eUSCI_Bx I2C Own Address 0 Register I2COA0 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA0 is disabled ENABLE 0x1 The slave address defined in I2COA0 is enabled UCGCEN [15:15] General call response enable 1 15 UCGCEN_0 0x0 Do not respond to a general call UCGCEN_1 0x1 Respond to a general call 0 UCB0I2COA1 0x16 16 eUSCI_Bx I2C Own Address 1 Register I2COA1 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA1 is disabled ENABLE 0x1 The slave address defined in I2COA1 is enabled 0 UCB0I2COA2 0x18 16 eUSCI_Bx I2C Own Address 2 Register I2COA2 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA2 is disabled ENABLE 0x1 The slave address defined in I2COA2 is enabled 0 UCB0I2COA3 0x1A 16 eUSCI_Bx I2C Own Address 3 Register I2COA3 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA3 is disabled ENABLE 0x1 The slave address defined in I2COA3 is enabled 0 UCB0ADDRX 0x1C 16 eUSCI_Bx I2C Received Address Register ADDRX [9:0] Received Address Register 10 0 0 UCB0ADDMASK 0x1E 16 eUSCI_Bx I2C Address Mask Register ADDMASK [9:0] Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 10 0 0 UCB0I2CSA 0x20 16 eUSCI_Bx I2C Slave Address Register I2CSA [9:0] I2C slave address 10 0 0 UCB0IE 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE0 [0:0] Receive interrupt enable 0 1 0 UCRXIE0_0 0x0 Interrupt disabled UCRXIE0_1 0x1 Interrupt enabled UCTXIE0 [1:1] Transmit interrupt enable 0 1 1 UCTXIE0_0 0x0 Interrupt disabled UCTXIE0_1 0x1 Interrupt enabled UCSTTIE [2:2] START condition interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCSTPIE [3:3] STOP condition interrupt enable 1 3 UCSTPIE_0 0x0 Interrupt disabled UCSTPIE_1 0x1 Interrupt enabled UCALIE [4:4] Arbitration lost interrupt enable 1 4 UCALIE_0 0x0 Interrupt disabled UCALIE_1 0x1 Interrupt enabled UCNACKIE [5:5] Not-acknowledge interrupt enable 1 5 UCNACKIE_0 0x0 Interrupt disabled UCNACKIE_1 0x1 Interrupt enabled UCBCNTIE [6:6] Byte counter interrupt enable 1 6 UCBCNTIE_0 0x0 Interrupt disabled UCBCNTIE_1 0x1 Interrupt enabled UCCLTOIE [7:7] Clock low timeout interrupt enable 1 7 UCCLTOIE_0 0x0 Interrupt disabled UCCLTOIE_1 0x1 Interrupt enabled UCRXIE1 [8:8] Receive interrupt enable 1 1 8 UCRXIE1_0 0x0 Interrupt disabled UCRXIE1_1 0x1 Interrupt enabled UCTXIE1 [9:9] Transmit interrupt enable 1 1 9 UCTXIE1_0 0x0 Interrupt disabled UCTXIE1_1 0x1 Interrupt enabled UCRXIE2 [10:10] Receive interrupt enable 2 1 10 UCRXIE2_0 0x0 Interrupt disabled UCRXIE2_1 0x1 Interrupt enabled UCTXIE2 [11:11] Transmit interrupt enable 2 1 11 UCTXIE2_0 0x0 Interrupt disabled UCTXIE2_1 0x1 Interrupt enabled UCRXIE3 [12:12] Receive interrupt enable 3 1 12 UCRXIE3_0 0x0 Interrupt disabled UCRXIE3_1 0x1 Interrupt enabled UCTXIE3 [13:13] Transmit interrupt enable 3 1 13 UCTXIE3_0 0x0 Interrupt disabled UCTXIE3_1 0x1 Interrupt enabled UCBIT9IE [14:14] Bit position 9 interrupt enable 1 14 UCBIT9IE_0 0x0 Interrupt disabled UCBIT9IE_1 0x1 Interrupt enabled 0 UCB0IE_SPI 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCB0IFG 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG0 [0:0] eUSCI_B receive interrupt flag 0 1 0 UCRXIFG0_0 0x0 No interrupt pending UCRXIFG0_1 0x1 Interrupt pending UCTXIFG0 [1:1] eUSCI_B transmit interrupt flag 0 1 1 UCTXIFG0_0 0x0 No interrupt pending UCTXIFG0_1 0x1 Interrupt pending UCSTTIFG [2:2] START condition interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCSTPIFG [3:3] STOP condition interrupt flag 1 3 UCSTPIFG_0 0x0 No interrupt pending UCSTPIFG_1 0x1 Interrupt pending UCALIFG [4:4] Arbitration lost interrupt flag 1 4 UCALIFG_0 0x0 No interrupt pending UCALIFG_1 0x1 Interrupt pending UCNACKIFG [5:5] Not-acknowledge received interrupt flag 1 5 UCNACKIFG_0 0x0 No interrupt pending UCNACKIFG_1 0x1 Interrupt pending UCBCNTIFG [6:6] Byte counter interrupt flag 1 6 UCBCNTIFG_0 0x0 No interrupt pending UCBCNTIFG_1 0x1 Interrupt pending UCCLTOIFG [7:7] Clock low timeout interrupt flag 1 7 UCCLTOIFG_0 0x0 No interrupt pending UCCLTOIFG_1 0x1 Interrupt pending UCRXIFG1 [8:8] eUSCI_B receive interrupt flag 1 1 8 UCRXIFG1_0 0x0 No interrupt pending UCRXIFG1_1 0x1 Interrupt pending UCTXIFG1 [9:9] eUSCI_B transmit interrupt flag 1 1 9 UCTXIFG1_0 0x0 No interrupt pending UCTXIFG1_1 0x1 Interrupt pending UCRXIFG2 [10:10] eUSCI_B receive interrupt flag 2 1 10 UCRXIFG2_0 0x0 No interrupt pending UCRXIFG2_1 0x1 Interrupt pending UCTXIFG2 [11:11] eUSCI_B transmit interrupt flag 2 1 11 UCTXIFG2_0 0x0 No interrupt pending UCTXIFG2_1 0x1 Interrupt pending UCRXIFG3 [12:12] eUSCI_B receive interrupt flag 3 1 12 UCRXIFG3_0 0x0 No interrupt pending UCRXIFG3_1 0x1 Interrupt pending UCTXIFG3 [13:13] eUSCI_B transmit interrupt flag 3 1 13 UCTXIFG3_0 0x0 No interrupt pending UCTXIFG3_1 0x1 Interrupt pending UCBIT9IFG [14:14] Bit position 9 interrupt flag 1 14 UCBIT9IFG_0 0x0 No interrupt pending UCBIT9IFG_1 0x1 Interrupt pending 0 UCB0IFG_SPI 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCB0IV 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCALIFG 0x2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest UCNACKIFG 0x4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG UCSTTIFG 0x6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG UCSTPIFG 0x8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG UCRXIFG3 0xA Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 UCTXIFG3 0xC Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 UCRXIFG2 0xE Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 UCTXIFG2 0x10 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 UCRXIFG1 0x12 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 UCTXIFG1 0x14 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 UCRXIFG0 0x16 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 UCTXIFG0 0x18 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 UCBCNTIFG 0x1A Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG UCCLTOIFG 0x1C Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG UCBIT9IFG 0x1E Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 0 UCB0IV_SPI 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_B1 0x0680 0 10 registers UCB1CTLW0 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCTXSTT [1:1] Transmit START condition in master mode 1 1 UCTXSTT_0 0x0 Do not generate START condition UCTXSTT_1 0x1 Generate START condition UCTXSTP [2:2] Transmit STOP condition in master mode 1 2 UCTXSTP_0 0x0 No STOP generated UCTXSTP_1 0x1 Generate STOP UCTXNACK [3:3] Transmit a NACK 1 3 UCTXNACK_0 0x0 Acknowledge normally UCTXNACK_1 0x1 Generate NACK UCTR [4:4] Transmitter/receiver 1 4 RX 0x0 Receiver TX 0x1 Transmitter UCTXACK [5:5] Transmit ACK condition in slave mode 1 5 UCTXACK_0 0x0 Do not acknowledge the slave address UCTXACK_1 0x1 Acknowledge the slave address UCSSEL [7:6] eUSCI_B clock source select 2 6 UCLKI 0x0 UCLKI ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_B mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI (master or slave enabled if STE = 1) UCMODE_2 0x2 4-pin SPI (master or slave enabled if STE = 0) UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UCMM [13:13] Multi-master environment select 1 13 SINGLE 0x0 Single master environment. There is no other master in the system. The address compare unit is disabled. MULTI 0x1 Multi-master environment UCSLA10 [14:14] Slave addressing mode select 1 14 7BIT 0x0 Address slave with 7-bit address 10BIT 0x1 Address slave with 10-bit address UCA10 [15:15] Own addressing mode select 1 15 UCA10_0 0x0 Own address is a 7-bit address UCA10_1 0x1 Own address is a 10-bit address 0 UCB1CTLW0_SPI 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_B clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCB1CTLW1 0x2 16 eUSCI_Bx Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 50 ns UCGLIT_1 0x1 25 ns UCGLIT_2 0x2 12.5 ns UCGLIT_3 0x3 6.25 ns UCASTP [3:2] Automatic STOP condition generation 2 2 UCASTP_0 0x0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. UCASTP_1 0x1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT UCASTP_2 0x2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold UCSWACK [4:4] SW or HW ACK control 1 4 UCSWACK_0 0x0 The address acknowledge of the slave is controlled by the eUSCI_B module UCSWACK_1 0x1 The user needs to trigger the sending of the address ACK by issuing UCTXACK UCSTPNACK [5:5] ACK all master bytes 1 5 UCSTPNACK_0 0x0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) UCSTPNACK_1 0x1 All bytes are acknowledged by the eUSCI_B when configured as master receiver UCCLTO [7:6] Clock low timeout select 2 6 UCCLTO_0 0x0 Disable clock low timeout counter UCCLTO_1 0x1 135 000 SYSCLK cycles (approximately 28 ms) UCCLTO_2 0x2 150 000 SYSCLK cycles (approximately 31 ms) UCCLTO_3 0x3 165 000 SYSCLK cycles (approximately 34 ms) UCETXINT [8:8] Early UCTXIFG0 1 8 UCETXINT_0 0x0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit UCETXINT_1 0x1 UCTXIFG0 is set for each START condition 0 UCB1BRW 0x6 16 eUSCI_Bx Baud Rate Control Word Register 0 UCB1BRW_SPI 0x6 16 eUSCI_Bx Bit Rate Control Register 1 0 UCB1STATW 0x8 16 eUSCI_Bx Status Register UCBBUSY [4:4] Bus busy 1 4 IDLE 0x0 Bus inactive BUSY 0x1 Bus busy UCGC [5:5] General call address received 1 5 UCGC_0 0x0 No general call address received UCGC_1 0x1 General call address received UCSCLLOW [6:6] SCL low 1 6 UCSCLLOW_0 0x0 SCL is not held low UCSCLLOW_1 0x1 SCL is held low UCBCNT [15:8] Hardware byte counter value 8 8 0 UCB1STATW_SPI 0x8 16 UCB1STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCBxTXD is internally fed back to the receiver 0 UCB1TBCNT 0xA 16 eUSCI_Bx Byte Counter Threshold Register UCTBCNT [7:0] Byte counter threshold value 8 0 0 UCB1RXBUF 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB1RXBUF_SPI 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB1TXBUF 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB1TXBUF_SPI 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB1I2COA0 0x14 16 eUSCI_Bx I2C Own Address 0 Register I2COA0 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA0 is disabled ENABLE 0x1 The slave address defined in I2COA0 is enabled UCGCEN [15:15] General call response enable 1 15 UCGCEN_0 0x0 Do not respond to a general call UCGCEN_1 0x1 Respond to a general call 0 UCB1I2COA1 0x16 16 eUSCI_Bx I2C Own Address 1 Register I2COA1 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA1 is disabled ENABLE 0x1 The slave address defined in I2COA1 is enabled 0 UCB1I2COA2 0x18 16 eUSCI_Bx I2C Own Address 2 Register I2COA2 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA2 is disabled ENABLE 0x1 The slave address defined in I2COA2 is enabled 0 UCB1I2COA3 0x1A 16 eUSCI_Bx I2C Own Address 3 Register I2COA3 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA3 is disabled ENABLE 0x1 The slave address defined in I2COA3 is enabled 0 UCB1ADDRX 0x1C 16 eUSCI_Bx I2C Received Address Register ADDRX [9:0] Received Address Register 10 0 0 UCB1ADDMASK 0x1E 16 eUSCI_Bx I2C Address Mask Register ADDMASK [9:0] Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 10 0 0 UCB1I2CSA 0x20 16 eUSCI_Bx I2C Slave Address Register I2CSA [9:0] I2C slave address 10 0 0 UCB1IE 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE0 [0:0] Receive interrupt enable 0 1 0 UCRXIE0_0 0x0 Interrupt disabled UCRXIE0_1 0x1 Interrupt enabled UCTXIE0 [1:1] Transmit interrupt enable 0 1 1 UCTXIE0_0 0x0 Interrupt disabled UCTXIE0_1 0x1 Interrupt enabled UCSTTIE [2:2] START condition interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCSTPIE [3:3] STOP condition interrupt enable 1 3 UCSTPIE_0 0x0 Interrupt disabled UCSTPIE_1 0x1 Interrupt enabled UCALIE [4:4] Arbitration lost interrupt enable 1 4 UCALIE_0 0x0 Interrupt disabled UCALIE_1 0x1 Interrupt enabled UCNACKIE [5:5] Not-acknowledge interrupt enable 1 5 UCNACKIE_0 0x0 Interrupt disabled UCNACKIE_1 0x1 Interrupt enabled UCBCNTIE [6:6] Byte counter interrupt enable 1 6 UCBCNTIE_0 0x0 Interrupt disabled UCBCNTIE_1 0x1 Interrupt enabled UCCLTOIE [7:7] Clock low timeout interrupt enable 1 7 UCCLTOIE_0 0x0 Interrupt disabled UCCLTOIE_1 0x1 Interrupt enabled UCRXIE1 [8:8] Receive interrupt enable 1 1 8 UCRXIE1_0 0x0 Interrupt disabled UCRXIE1_1 0x1 Interrupt enabled UCTXIE1 [9:9] Transmit interrupt enable 1 1 9 UCTXIE1_0 0x0 Interrupt disabled UCTXIE1_1 0x1 Interrupt enabled UCRXIE2 [10:10] Receive interrupt enable 2 1 10 UCRXIE2_0 0x0 Interrupt disabled UCRXIE2_1 0x1 Interrupt enabled UCTXIE2 [11:11] Transmit interrupt enable 2 1 11 UCTXIE2_0 0x0 Interrupt disabled UCTXIE2_1 0x1 Interrupt enabled UCRXIE3 [12:12] Receive interrupt enable 3 1 12 UCRXIE3_0 0x0 Interrupt disabled UCRXIE3_1 0x1 Interrupt enabled UCTXIE3 [13:13] Transmit interrupt enable 3 1 13 UCTXIE3_0 0x0 Interrupt disabled UCTXIE3_1 0x1 Interrupt enabled UCBIT9IE [14:14] Bit position 9 interrupt enable 1 14 UCBIT9IE_0 0x0 Interrupt disabled UCBIT9IE_1 0x1 Interrupt enabled 0 UCB1IE_SPI 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCB1IFG 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG0 [0:0] eUSCI_B receive interrupt flag 0 1 0 UCRXIFG0_0 0x0 No interrupt pending UCRXIFG0_1 0x1 Interrupt pending UCTXIFG0 [1:1] eUSCI_B transmit interrupt flag 0 1 1 UCTXIFG0_0 0x0 No interrupt pending UCTXIFG0_1 0x1 Interrupt pending UCSTTIFG [2:2] START condition interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCSTPIFG [3:3] STOP condition interrupt flag 1 3 UCSTPIFG_0 0x0 No interrupt pending UCSTPIFG_1 0x1 Interrupt pending UCALIFG [4:4] Arbitration lost interrupt flag 1 4 UCALIFG_0 0x0 No interrupt pending UCALIFG_1 0x1 Interrupt pending UCNACKIFG [5:5] Not-acknowledge received interrupt flag 1 5 UCNACKIFG_0 0x0 No interrupt pending UCNACKIFG_1 0x1 Interrupt pending UCBCNTIFG [6:6] Byte counter interrupt flag 1 6 UCBCNTIFG_0 0x0 No interrupt pending UCBCNTIFG_1 0x1 Interrupt pending UCCLTOIFG [7:7] Clock low timeout interrupt flag 1 7 UCCLTOIFG_0 0x0 No interrupt pending UCCLTOIFG_1 0x1 Interrupt pending UCRXIFG1 [8:8] eUSCI_B receive interrupt flag 1 1 8 UCRXIFG1_0 0x0 No interrupt pending UCRXIFG1_1 0x1 Interrupt pending UCTXIFG1 [9:9] eUSCI_B transmit interrupt flag 1 1 9 UCTXIFG1_0 0x0 No interrupt pending UCTXIFG1_1 0x1 Interrupt pending UCRXIFG2 [10:10] eUSCI_B receive interrupt flag 2 1 10 UCRXIFG2_0 0x0 No interrupt pending UCRXIFG2_1 0x1 Interrupt pending UCTXIFG2 [11:11] eUSCI_B transmit interrupt flag 2 1 11 UCTXIFG2_0 0x0 No interrupt pending UCTXIFG2_1 0x1 Interrupt pending UCRXIFG3 [12:12] eUSCI_B receive interrupt flag 3 1 12 UCRXIFG3_0 0x0 No interrupt pending UCRXIFG3_1 0x1 Interrupt pending UCTXIFG3 [13:13] eUSCI_B transmit interrupt flag 3 1 13 UCTXIFG3_0 0x0 No interrupt pending UCTXIFG3_1 0x1 Interrupt pending UCBIT9IFG [14:14] Bit position 9 interrupt flag 1 14 UCBIT9IFG_0 0x0 No interrupt pending UCBIT9IFG_1 0x1 Interrupt pending 0 UCB1IFG_SPI 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCB1IV 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCALIFG 0x2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest UCNACKIFG 0x4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG UCSTTIFG 0x6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG UCSTPIFG 0x8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG UCRXIFG3 0xA Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 UCTXIFG3 0xC Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 UCRXIFG2 0xE Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 UCTXIFG2 0x10 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 UCRXIFG1 0x12 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 UCTXIFG1 0x14 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 UCRXIFG0 0x16 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 UCTXIFG0 0x18 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 UCBCNTIFG 0x1A Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG UCCLTOIFG 0x1C Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG UCBIT9IFG 0x1E Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 0 UCB1IV_SPI 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_B2 0x06C0 0 10 registers UCB2CTLW0 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCTXSTT [1:1] Transmit START condition in master mode 1 1 UCTXSTT_0 0x0 Do not generate START condition UCTXSTT_1 0x1 Generate START condition UCTXSTP [2:2] Transmit STOP condition in master mode 1 2 UCTXSTP_0 0x0 No STOP generated UCTXSTP_1 0x1 Generate STOP UCTXNACK [3:3] Transmit a NACK 1 3 UCTXNACK_0 0x0 Acknowledge normally UCTXNACK_1 0x1 Generate NACK UCTR [4:4] Transmitter/receiver 1 4 RX 0x0 Receiver TX 0x1 Transmitter UCTXACK [5:5] Transmit ACK condition in slave mode 1 5 UCTXACK_0 0x0 Do not acknowledge the slave address UCTXACK_1 0x1 Acknowledge the slave address UCSSEL [7:6] eUSCI_B clock source select 2 6 UCLKI 0x0 UCLKI ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_B mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI (master or slave enabled if STE = 1) UCMODE_2 0x2 4-pin SPI (master or slave enabled if STE = 0) UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UCMM [13:13] Multi-master environment select 1 13 SINGLE 0x0 Single master environment. There is no other master in the system. The address compare unit is disabled. MULTI 0x1 Multi-master environment UCSLA10 [14:14] Slave addressing mode select 1 14 7BIT 0x0 Address slave with 7-bit address 10BIT 0x1 Address slave with 10-bit address UCA10 [15:15] Own addressing mode select 1 15 UCA10_0 0x0 Own address is a 7-bit address UCA10_1 0x1 Own address is a 10-bit address 0 UCB2CTLW0_SPI 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_B clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCB2CTLW1 0x2 16 eUSCI_Bx Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 50 ns UCGLIT_1 0x1 25 ns UCGLIT_2 0x2 12.5 ns UCGLIT_3 0x3 6.25 ns UCASTP [3:2] Automatic STOP condition generation 2 2 UCASTP_0 0x0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. UCASTP_1 0x1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT UCASTP_2 0x2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold UCSWACK [4:4] SW or HW ACK control 1 4 UCSWACK_0 0x0 The address acknowledge of the slave is controlled by the eUSCI_B module UCSWACK_1 0x1 The user needs to trigger the sending of the address ACK by issuing UCTXACK UCSTPNACK [5:5] ACK all master bytes 1 5 UCSTPNACK_0 0x0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) UCSTPNACK_1 0x1 All bytes are acknowledged by the eUSCI_B when configured as master receiver UCCLTO [7:6] Clock low timeout select 2 6 UCCLTO_0 0x0 Disable clock low timeout counter UCCLTO_1 0x1 135 000 SYSCLK cycles (approximately 28 ms) UCCLTO_2 0x2 150 000 SYSCLK cycles (approximately 31 ms) UCCLTO_3 0x3 165 000 SYSCLK cycles (approximately 34 ms) UCETXINT [8:8] Early UCTXIFG0 1 8 UCETXINT_0 0x0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit UCETXINT_1 0x1 UCTXIFG0 is set for each START condition 0 UCB2BRW 0x6 16 eUSCI_Bx Baud Rate Control Word Register 0 UCB2BRW_SPI 0x6 16 eUSCI_Bx Bit Rate Control Register 1 0 UCB2STATW 0x8 16 eUSCI_Bx Status Register UCBBUSY [4:4] Bus busy 1 4 IDLE 0x0 Bus inactive BUSY 0x1 Bus busy UCGC [5:5] General call address received 1 5 UCGC_0 0x0 No general call address received UCGC_1 0x1 General call address received UCSCLLOW [6:6] SCL low 1 6 UCSCLLOW_0 0x0 SCL is not held low UCSCLLOW_1 0x1 SCL is held low UCBCNT [15:8] Hardware byte counter value 8 8 0 UCB2STATW_SPI 0x8 16 UCB2STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCBxTXD is internally fed back to the receiver 0 UCB2TBCNT 0xA 16 eUSCI_Bx Byte Counter Threshold Register UCTBCNT [7:0] Byte counter threshold value 8 0 0 UCB2RXBUF 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB2RXBUF_SPI 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB2TXBUF 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB2TXBUF_SPI 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB2I2COA0 0x14 16 eUSCI_Bx I2C Own Address 0 Register I2COA0 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA0 is disabled ENABLE 0x1 The slave address defined in I2COA0 is enabled UCGCEN [15:15] General call response enable 1 15 UCGCEN_0 0x0 Do not respond to a general call UCGCEN_1 0x1 Respond to a general call 0 UCB2I2COA1 0x16 16 eUSCI_Bx I2C Own Address 1 Register I2COA1 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA1 is disabled ENABLE 0x1 The slave address defined in I2COA1 is enabled 0 UCB2I2COA2 0x18 16 eUSCI_Bx I2C Own Address 2 Register I2COA2 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA2 is disabled ENABLE 0x1 The slave address defined in I2COA2 is enabled 0 UCB2I2COA3 0x1A 16 eUSCI_Bx I2C Own Address 3 Register I2COA3 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA3 is disabled ENABLE 0x1 The slave address defined in I2COA3 is enabled 0 UCB2ADDRX 0x1C 16 eUSCI_Bx I2C Received Address Register ADDRX [9:0] Received Address Register 10 0 0 UCB2ADDMASK 0x1E 16 eUSCI_Bx I2C Address Mask Register ADDMASK [9:0] Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 10 0 0 UCB2I2CSA 0x20 16 eUSCI_Bx I2C Slave Address Register I2CSA [9:0] I2C slave address 10 0 0 UCB2IE 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE0 [0:0] Receive interrupt enable 0 1 0 UCRXIE0_0 0x0 Interrupt disabled UCRXIE0_1 0x1 Interrupt enabled UCTXIE0 [1:1] Transmit interrupt enable 0 1 1 UCTXIE0_0 0x0 Interrupt disabled UCTXIE0_1 0x1 Interrupt enabled UCSTTIE [2:2] START condition interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCSTPIE [3:3] STOP condition interrupt enable 1 3 UCSTPIE_0 0x0 Interrupt disabled UCSTPIE_1 0x1 Interrupt enabled UCALIE [4:4] Arbitration lost interrupt enable 1 4 UCALIE_0 0x0 Interrupt disabled UCALIE_1 0x1 Interrupt enabled UCNACKIE [5:5] Not-acknowledge interrupt enable 1 5 UCNACKIE_0 0x0 Interrupt disabled UCNACKIE_1 0x1 Interrupt enabled UCBCNTIE [6:6] Byte counter interrupt enable 1 6 UCBCNTIE_0 0x0 Interrupt disabled UCBCNTIE_1 0x1 Interrupt enabled UCCLTOIE [7:7] Clock low timeout interrupt enable 1 7 UCCLTOIE_0 0x0 Interrupt disabled UCCLTOIE_1 0x1 Interrupt enabled UCRXIE1 [8:8] Receive interrupt enable 1 1 8 UCRXIE1_0 0x0 Interrupt disabled UCRXIE1_1 0x1 Interrupt enabled UCTXIE1 [9:9] Transmit interrupt enable 1 1 9 UCTXIE1_0 0x0 Interrupt disabled UCTXIE1_1 0x1 Interrupt enabled UCRXIE2 [10:10] Receive interrupt enable 2 1 10 UCRXIE2_0 0x0 Interrupt disabled UCRXIE2_1 0x1 Interrupt enabled UCTXIE2 [11:11] Transmit interrupt enable 2 1 11 UCTXIE2_0 0x0 Interrupt disabled UCTXIE2_1 0x1 Interrupt enabled UCRXIE3 [12:12] Receive interrupt enable 3 1 12 UCRXIE3_0 0x0 Interrupt disabled UCRXIE3_1 0x1 Interrupt enabled UCTXIE3 [13:13] Transmit interrupt enable 3 1 13 UCTXIE3_0 0x0 Interrupt disabled UCTXIE3_1 0x1 Interrupt enabled UCBIT9IE [14:14] Bit position 9 interrupt enable 1 14 UCBIT9IE_0 0x0 Interrupt disabled UCBIT9IE_1 0x1 Interrupt enabled 0 UCB2IE_SPI 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCB2IFG 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG0 [0:0] eUSCI_B receive interrupt flag 0 1 0 UCRXIFG0_0 0x0 No interrupt pending UCRXIFG0_1 0x1 Interrupt pending UCTXIFG0 [1:1] eUSCI_B transmit interrupt flag 0 1 1 UCTXIFG0_0 0x0 No interrupt pending UCTXIFG0_1 0x1 Interrupt pending UCSTTIFG [2:2] START condition interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCSTPIFG [3:3] STOP condition interrupt flag 1 3 UCSTPIFG_0 0x0 No interrupt pending UCSTPIFG_1 0x1 Interrupt pending UCALIFG [4:4] Arbitration lost interrupt flag 1 4 UCALIFG_0 0x0 No interrupt pending UCALIFG_1 0x1 Interrupt pending UCNACKIFG [5:5] Not-acknowledge received interrupt flag 1 5 UCNACKIFG_0 0x0 No interrupt pending UCNACKIFG_1 0x1 Interrupt pending UCBCNTIFG [6:6] Byte counter interrupt flag 1 6 UCBCNTIFG_0 0x0 No interrupt pending UCBCNTIFG_1 0x1 Interrupt pending UCCLTOIFG [7:7] Clock low timeout interrupt flag 1 7 UCCLTOIFG_0 0x0 No interrupt pending UCCLTOIFG_1 0x1 Interrupt pending UCRXIFG1 [8:8] eUSCI_B receive interrupt flag 1 1 8 UCRXIFG1_0 0x0 No interrupt pending UCRXIFG1_1 0x1 Interrupt pending UCTXIFG1 [9:9] eUSCI_B transmit interrupt flag 1 1 9 UCTXIFG1_0 0x0 No interrupt pending UCTXIFG1_1 0x1 Interrupt pending UCRXIFG2 [10:10] eUSCI_B receive interrupt flag 2 1 10 UCRXIFG2_0 0x0 No interrupt pending UCRXIFG2_1 0x1 Interrupt pending UCTXIFG2 [11:11] eUSCI_B transmit interrupt flag 2 1 11 UCTXIFG2_0 0x0 No interrupt pending UCTXIFG2_1 0x1 Interrupt pending UCRXIFG3 [12:12] eUSCI_B receive interrupt flag 3 1 12 UCRXIFG3_0 0x0 No interrupt pending UCRXIFG3_1 0x1 Interrupt pending UCTXIFG3 [13:13] eUSCI_B transmit interrupt flag 3 1 13 UCTXIFG3_0 0x0 No interrupt pending UCTXIFG3_1 0x1 Interrupt pending UCBIT9IFG [14:14] Bit position 9 interrupt flag 1 14 UCBIT9IFG_0 0x0 No interrupt pending UCBIT9IFG_1 0x1 Interrupt pending 0 UCB2IFG_SPI 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCB2IV 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCALIFG 0x2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest UCNACKIFG 0x4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG UCSTTIFG 0x6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG UCSTPIFG 0x8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG UCRXIFG3 0xA Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 UCTXIFG3 0xC Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 UCRXIFG2 0xE Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 UCTXIFG2 0x10 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 UCRXIFG1 0x12 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 UCTXIFG1 0x14 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 UCRXIFG0 0x16 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 UCTXIFG0 0x18 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 UCBCNTIFG 0x1A Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG UCCLTOIFG 0x1C Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG UCBIT9IFG 0x1E Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 0 UCB2IV_SPI 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 eUSCI_B3 0x0700 0 10 registers UCB3CTLW0 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCTXSTT [1:1] Transmit START condition in master mode 1 1 UCTXSTT_0 0x0 Do not generate START condition UCTXSTT_1 0x1 Generate START condition UCTXSTP [2:2] Transmit STOP condition in master mode 1 2 UCTXSTP_0 0x0 No STOP generated UCTXSTP_1 0x1 Generate STOP UCTXNACK [3:3] Transmit a NACK 1 3 UCTXNACK_0 0x0 Acknowledge normally UCTXNACK_1 0x1 Generate NACK UCTR [4:4] Transmitter/receiver 1 4 RX 0x0 Receiver TX 0x1 Transmitter UCTXACK [5:5] Transmit ACK condition in slave mode 1 5 UCTXACK_0 0x0 Do not acknowledge the slave address UCTXACK_1 0x1 Acknowledge the slave address UCSSEL [7:6] eUSCI_B clock source select 2 6 UCLKI 0x0 UCLKI ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI_B mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI (master or slave enabled if STE = 1) UCMODE_2 0x2 4-pin SPI (master or slave enabled if STE = 0) UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UCMM [13:13] Multi-master environment select 1 13 SINGLE 0x0 Single master environment. There is no other master in the system. The address compare unit is disabled. MULTI 0x1 Multi-master environment UCSLA10 [14:14] Slave addressing mode select 1 14 7BIT 0x0 Address slave with 7-bit address 10BIT 0x1 Address slave with 10-bit address UCA10 [15:15] Own addressing mode select 1 15 UCA10_0 0x0 Own address is a 7-bit address UCA10_1 0x1 Own address is a 10-bit address 0 UCB3CTLW0_SPI 0x0 16 eUSCI_Bx Control Word Register 0 UCSWRST [0:0] Software reset enable 1 0 DISABLE 0x0 Disabled. eUSCI_B reset released for operation ENABLE 0x1 Enabled. eUSCI_B logic held in reset state UCSTEM [1:1] STE mode select in master mode. 1 1 UCSTEM_0 0x0 STE pin is used to prevent conflicts with other masters UCSTEM_1 0x1 STE pin is used to generate the enable signal for a 4-wire slave UCSSEL [7:6] eUSCI_B clock source select 2 6 UCSSEL_0 0x0 Reserved ACLK 0x1 ACLK SMCLK 0x2 SMCLK UCSSEL_3 0x3 SMCLK UCSYNC [8:8] Synchronous mode enable 1 8 ASYNC 0x0 Asynchronous mode SYNC 0x1 Synchronous mode UCMODE [10:9] eUSCI mode 2 9 UCMODE_0 0x0 3-pin SPI UCMODE_1 0x1 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 UCMODE_2 0x2 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 UCMODE_3 0x3 I2C mode UCMST [11:11] Master mode select 1 11 SLAVE 0x0 Slave mode MASTER 0x1 Master mode UC7BIT [12:12] Character length 1 12 8BIT 0x0 8-bit data 7BIT 0x1 7-bit data UCMSB [13:13] MSB first select 1 13 UCMSB_0 0x0 LSB first UCMSB_1 0x1 MSB first UCCKPL [14:14] Clock polarity select 1 14 LOW 0x0 The inactive state is low HIGH 0x1 The inactive state is high UCCKPH [15:15] Clock phase select 1 15 UCCKPH_0 0x0 Data is changed on the first UCLK edge and captured on the following edge. UCCKPH_1 0x1 Data is captured on the first UCLK edge and changed on the following edge. 0 UCB3CTLW1 0x2 16 eUSCI_Bx Control Word Register 1 UCGLIT [1:0] Deglitch time 2 0 UCGLIT_0 0x0 50 ns UCGLIT_1 0x1 25 ns UCGLIT_2 0x2 12.5 ns UCGLIT_3 0x3 6.25 ns UCASTP [3:2] Automatic STOP condition generation 2 2 UCASTP_0 0x0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. UCASTP_1 0x1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT UCASTP_2 0x2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold UCSWACK [4:4] SW or HW ACK control 1 4 UCSWACK_0 0x0 The address acknowledge of the slave is controlled by the eUSCI_B module UCSWACK_1 0x1 The user needs to trigger the sending of the address ACK by issuing UCTXACK UCSTPNACK [5:5] ACK all master bytes 1 5 UCSTPNACK_0 0x0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) UCSTPNACK_1 0x1 All bytes are acknowledged by the eUSCI_B when configured as master receiver UCCLTO [7:6] Clock low timeout select 2 6 UCCLTO_0 0x0 Disable clock low timeout counter UCCLTO_1 0x1 135 000 SYSCLK cycles (approximately 28 ms) UCCLTO_2 0x2 150 000 SYSCLK cycles (approximately 31 ms) UCCLTO_3 0x3 165 000 SYSCLK cycles (approximately 34 ms) UCETXINT [8:8] Early UCTXIFG0 1 8 UCETXINT_0 0x0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit UCETXINT_1 0x1 UCTXIFG0 is set for each START condition 0 UCB3BRW 0x6 16 eUSCI_Bx Baud Rate Control Word Register 0 UCB3BRW_SPI 0x6 16 eUSCI_Bx Bit Rate Control Register 1 0 UCB3STATW 0x8 16 eUSCI_Bx Status Register UCBBUSY [4:4] Bus busy 1 4 IDLE 0x0 Bus inactive BUSY 0x1 Bus busy UCGC [5:5] General call address received 1 5 UCGC_0 0x0 No general call address received UCGC_1 0x1 General call address received UCSCLLOW [6:6] SCL low 1 6 UCSCLLOW_0 0x0 SCL is not held low UCSCLLOW_1 0x1 SCL is held low UCBCNT [15:8] Hardware byte counter value 8 8 0 UCB3STATW_SPI 0x8 16 UCB3STATW_SPI UCOE [5:5] Overrun error flag 1 5 UCOE_0 0x0 No error UCOE_1 0x1 Overrun error occurred UCFE [6:6] Framing error flag 1 6 UCFE_0 0x0 No error UCFE_1 0x1 Bus conflict occurred UCLISTEN [7:7] Listen enable 1 7 UCLISTEN_0 0x0 Disabled UCLISTEN_1 0x1 Enabled. UCBxTXD is internally fed back to the receiver 0 UCB3TBCNT 0xA 16 eUSCI_Bx Byte Counter Threshold Register UCTBCNT [7:0] Byte counter threshold value 8 0 0 UCB3RXBUF 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB3RXBUF_SPI 0xC 16 eUSCI_Bx Receive Buffer Register UCRXBUF [7:0] Receive data buffer 8 0 0 UCB3TXBUF 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB3TXBUF_SPI 0xE 16 eUSCI_Bx Transmit Buffer Register UCTXBUF [7:0] Transmit data buffer 8 0 0 UCB3I2COA0 0x14 16 eUSCI_Bx I2C Own Address 0 Register I2COA0 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA0 is disabled ENABLE 0x1 The slave address defined in I2COA0 is enabled UCGCEN [15:15] General call response enable 1 15 UCGCEN_0 0x0 Do not respond to a general call UCGCEN_1 0x1 Respond to a general call 0 UCB3I2COA1 0x16 16 eUSCI_Bx I2C Own Address 1 Register I2COA1 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA1 is disabled ENABLE 0x1 The slave address defined in I2COA1 is enabled 0 UCB3I2COA2 0x18 16 eUSCI_Bx I2C Own Address 2 Register I2COA2 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA2 is disabled ENABLE 0x1 The slave address defined in I2COA2 is enabled 0 UCB3I2COA3 0x1A 16 eUSCI_Bx I2C Own Address 3 Register I2COA3 [9:0] I2C own address 10 0 UCOAEN [10:10] Own Address enable register 1 10 DISABLE 0x0 The slave address defined in I2COA3 is disabled ENABLE 0x1 The slave address defined in I2COA3 is enabled 0 UCB3ADDRX 0x1C 16 eUSCI_Bx I2C Received Address Register ADDRX [9:0] Received Address Register 10 0 0 UCB3ADDMASK 0x1E 16 eUSCI_Bx I2C Address Mask Register ADDMASK [9:0] Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 10 0 0 UCB3I2CSA 0x20 16 eUSCI_Bx I2C Slave Address Register I2CSA [9:0] I2C slave address 10 0 0 UCB3IE 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE0 [0:0] Receive interrupt enable 0 1 0 UCRXIE0_0 0x0 Interrupt disabled UCRXIE0_1 0x1 Interrupt enabled UCTXIE0 [1:1] Transmit interrupt enable 0 1 1 UCTXIE0_0 0x0 Interrupt disabled UCTXIE0_1 0x1 Interrupt enabled UCSTTIE [2:2] START condition interrupt enable 1 2 UCSTTIE_0 0x0 Interrupt disabled UCSTTIE_1 0x1 Interrupt enabled UCSTPIE [3:3] STOP condition interrupt enable 1 3 UCSTPIE_0 0x0 Interrupt disabled UCSTPIE_1 0x1 Interrupt enabled UCALIE [4:4] Arbitration lost interrupt enable 1 4 UCALIE_0 0x0 Interrupt disabled UCALIE_1 0x1 Interrupt enabled UCNACKIE [5:5] Not-acknowledge interrupt enable 1 5 UCNACKIE_0 0x0 Interrupt disabled UCNACKIE_1 0x1 Interrupt enabled UCBCNTIE [6:6] Byte counter interrupt enable 1 6 UCBCNTIE_0 0x0 Interrupt disabled UCBCNTIE_1 0x1 Interrupt enabled UCCLTOIE [7:7] Clock low timeout interrupt enable 1 7 UCCLTOIE_0 0x0 Interrupt disabled UCCLTOIE_1 0x1 Interrupt enabled UCRXIE1 [8:8] Receive interrupt enable 1 1 8 UCRXIE1_0 0x0 Interrupt disabled UCRXIE1_1 0x1 Interrupt enabled UCTXIE1 [9:9] Transmit interrupt enable 1 1 9 UCTXIE1_0 0x0 Interrupt disabled UCTXIE1_1 0x1 Interrupt enabled UCRXIE2 [10:10] Receive interrupt enable 2 1 10 UCRXIE2_0 0x0 Interrupt disabled UCRXIE2_1 0x1 Interrupt enabled UCTXIE2 [11:11] Transmit interrupt enable 2 1 11 UCTXIE2_0 0x0 Interrupt disabled UCTXIE2_1 0x1 Interrupt enabled UCRXIE3 [12:12] Receive interrupt enable 3 1 12 UCRXIE3_0 0x0 Interrupt disabled UCRXIE3_1 0x1 Interrupt enabled UCTXIE3 [13:13] Transmit interrupt enable 3 1 13 UCTXIE3_0 0x0 Interrupt disabled UCTXIE3_1 0x1 Interrupt enabled UCBIT9IE [14:14] Bit position 9 interrupt enable 1 14 UCBIT9IE_0 0x0 Interrupt disabled UCBIT9IE_1 0x1 Interrupt enabled 0 UCB3IE_SPI 0x2A 16 eUSCI_Bx Interrupt Enable Register UCRXIE [0:0] Receive interrupt enable 1 0 UCRXIE_0 0x0 Interrupt disabled UCRXIE_1 0x1 Interrupt enabled UCTXIE [1:1] Transmit interrupt enable 1 1 UCTXIE_0 0x0 Interrupt disabled UCTXIE_1 0x1 Interrupt enabled 0 UCB3IFG 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG0 [0:0] eUSCI_B receive interrupt flag 0 1 0 UCRXIFG0_0 0x0 No interrupt pending UCRXIFG0_1 0x1 Interrupt pending UCTXIFG0 [1:1] eUSCI_B transmit interrupt flag 0 1 1 UCTXIFG0_0 0x0 No interrupt pending UCTXIFG0_1 0x1 Interrupt pending UCSTTIFG [2:2] START condition interrupt flag 1 2 UCSTTIFG_0 0x0 No interrupt pending UCSTTIFG_1 0x1 Interrupt pending UCSTPIFG [3:3] STOP condition interrupt flag 1 3 UCSTPIFG_0 0x0 No interrupt pending UCSTPIFG_1 0x1 Interrupt pending UCALIFG [4:4] Arbitration lost interrupt flag 1 4 UCALIFG_0 0x0 No interrupt pending UCALIFG_1 0x1 Interrupt pending UCNACKIFG [5:5] Not-acknowledge received interrupt flag 1 5 UCNACKIFG_0 0x0 No interrupt pending UCNACKIFG_1 0x1 Interrupt pending UCBCNTIFG [6:6] Byte counter interrupt flag 1 6 UCBCNTIFG_0 0x0 No interrupt pending UCBCNTIFG_1 0x1 Interrupt pending UCCLTOIFG [7:7] Clock low timeout interrupt flag 1 7 UCCLTOIFG_0 0x0 No interrupt pending UCCLTOIFG_1 0x1 Interrupt pending UCRXIFG1 [8:8] eUSCI_B receive interrupt flag 1 1 8 UCRXIFG1_0 0x0 No interrupt pending UCRXIFG1_1 0x1 Interrupt pending UCTXIFG1 [9:9] eUSCI_B transmit interrupt flag 1 1 9 UCTXIFG1_0 0x0 No interrupt pending UCTXIFG1_1 0x1 Interrupt pending UCRXIFG2 [10:10] eUSCI_B receive interrupt flag 2 1 10 UCRXIFG2_0 0x0 No interrupt pending UCRXIFG2_1 0x1 Interrupt pending UCTXIFG2 [11:11] eUSCI_B transmit interrupt flag 2 1 11 UCTXIFG2_0 0x0 No interrupt pending UCTXIFG2_1 0x1 Interrupt pending UCRXIFG3 [12:12] eUSCI_B receive interrupt flag 3 1 12 UCRXIFG3_0 0x0 No interrupt pending UCRXIFG3_1 0x1 Interrupt pending UCTXIFG3 [13:13] eUSCI_B transmit interrupt flag 3 1 13 UCTXIFG3_0 0x0 No interrupt pending UCTXIFG3_1 0x1 Interrupt pending UCBIT9IFG [14:14] Bit position 9 interrupt flag 1 14 UCBIT9IFG_0 0x0 No interrupt pending UCBIT9IFG_1 0x1 Interrupt pending 0 UCB3IFG_SPI 0x2C 16 eUSCI_Bx Interrupt Flag Register UCRXIFG [0:0] Receive interrupt flag 1 0 UCRXIFG_0 0x0 No interrupt pending UCRXIFG_1 0x1 Interrupt pending UCTXIFG [1:1] Transmit interrupt flag 1 1 UCTXIFG_0 0x0 No interrupt pending UCTXIFG_1 0x1 Interrupt pending 0 UCB3IV 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCALIFG 0x2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest UCNACKIFG 0x4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG UCSTTIFG 0x6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG UCSTPIFG 0x8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG UCRXIFG3 0xA Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 UCTXIFG3 0xC Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 UCRXIFG2 0xE Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 UCTXIFG2 0x10 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 UCRXIFG1 0x12 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 UCTXIFG1 0x14 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 UCRXIFG0 0x16 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 UCTXIFG0 0x18 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 UCBCNTIFG 0x1A Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG UCCLTOIFG 0x1C Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG UCBIT9IFG 0x1E Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 0 UCB3IV_SPI 0x2E 16 eUSCI_Bx Interrupt Vector Register UCIV [15:0] eUSCI_B interrupt vector value 16 0 NONE 0x0 No interrupt pending UCRXIFG 0x2 Interrupt Source: Data received; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest UCTXIFG 0x4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest 0 _INTERRUPTS 65424 PORT8 0xFFB6 19 PORT7 0xFFB8 20 EUSCI_B3 0xFFBA 21 EUSCI_B2 0xFFBC 22 EUSCI_B1 0xFFBE 23 EUSCI_A3 0xFFC0 24 EUSCI_A2 0xFFC2 25 PORT6 0xFFC4 26 PORT5 0xFFC6 27 TIMER4_A1 0xFFC8 28 TIMER4_A0 0xFFCA 29 AES256 0xFFCC 30 RTC_C 0xFFCE 31 PORT4 0xFFD0 32 PORT3 0xFFD2 33 TIMER3_A1 0xFFD4 34 TIMER3_A0 0xFFD6 35 PORT2 0xFFD8 36 TIMER2_A1 0xFFDA 37 TIMER2_A0 0xFFDC 38 PORT1 0xFFDE 39 TIMER1_A1 0xFFE0 40 TIMER1_A0 0xFFE2 41 DMA 0xFFE4 42 EUSCI_A1 0xFFE6 43 TIMER0_A1 0xFFE8 44 TIMER0_A0 0xFFEA 45 ADC12_B 0xFFEC 46 EUSCI_B0 0xFFEE 47 EUSCI_A0 0xFFF0 48 WDT 0xFFF2 49 TIMER0_B1 0xFFF4 50 TIMER0_B0 0xFFF6 51 COMP_E 0xFFF8 52 UNMI 0xFFFA 53 SYSNMI 0xFFFC 54