msp430gen MSP430G2231 v0.4.0 8 16 16 read-write 0 SPECIAL_FUNCTION Special Function 0 IE1 Interrupt Enable 1 0 8 255 WDTIE Watchdog Interrupt Enable 0 1 read-write OFIE Osc. Fault Interrupt Enable 1 1 read-write NMIIE NMI Interrupt Enable 4 1 read-write ACCVIE Flash Access Violation Interrupt Enable 5 1 read-write IFG1 Interrupt Flag 1 2 8 255 WDTIFG Watchdog Interrupt Flag 0 1 read-write OFIFG Osc. Fault Interrupt Flag 1 1 read-write PORIFG Power On Interrupt Flag 2 1 read-write RSTIFG Reset Interrupt Flag 3 1 read-write NMIIFG NMI Interrupt Flag 4 1 read-write PORT_1_2 Port 1/2 32 P1IN Port 1 Input 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IN Port 1 Input register 0 8 0 255 P1OUT Port 1 Output 1 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1OUT Port 1 Output register 0 8 0 255 P1DIR Port 1 Direction 2 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1DIR Port 1 Direction register 0 8 0 255 P1IFG Port 1 Interrupt Flag 3 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IFG Port 1 Interrupt Flag register 0 8 0 255 P1IES Port 1 Interrupt Edge Select 4 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IES Port 1 Interrupt Edge Select register 0 8 0 255 P1IE Port 1 Interrupt Enable 5 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IE Port 1 Interrupt Enable register 0 8 0 255 P1SEL Port 1 Selection 6 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SEL Port 1 Selection register 0 8 0 255 P1REN Port 1 Resistor Enable 7 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1REN Port 1 Resistor Enable register 0 8 0 255 P2IN Port 2 Input 8 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IN Port 2 Input register 0 8 0 255 P2OUT Port 2 Output 9 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2OUT Port 2 Output register 0 8 0 255 P2DIR Port 2 Direction 10 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2DIR Port 2 Direction register 0 8 0 255 P2IFG Port 2 Interrupt Flag 11 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IFG Port 2 Interrupt Flag register 0 8 0 255 P2IES Port 2 Interrupt Edge Select 12 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IES Port 2 Interrupt Edge Select register 0 8 0 255 P2IE Port 2 Interrupt Enable 13 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IE Port 2 Interrupt Enable register 0 8 0 255 P2SEL Port 2 Selection 14 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SEL Port 2 Selection register 0 8 0 255 P2REN Port 2 Resistor Enable 15 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2REN Port 2 Resistor Enable register 0 8 0 255 ADC10 ADC10 72 ADC10DTC0 ADC10 Data Transfer Control 0 0 8 255 ADC10FETCH This bit should normally be reset 0 1 read-write ADC10B1 ADC10 block one 1 1 read-write ADC10CT ADC10 continuous transfer 2 1 read-write ADC10TB ADC10 two-block mode 3 1 read-write ADC10DTC1 ADC10 Data Transfer Control 1 1 8 255 ADC10DTC1 ADC10 Data Transfer Control 1 register 0 8 0 255 ADC10AE0 ADC10 Analog Enable 0 2 8 255 ADC10AE0 ADC10 Analog Enable 0 register 0 8 0 255 ADC10CTL0 ADC10 Control 0 360 16 65535 ADC10SC ADC10 Start Conversion 0 1 read-write ENC ADC10 Enable Conversion 1 1 read-write ADC10IFG ADC10 Interrupt Flag 2 1 read-write ADC10IE ADC10 Interrupt Enalbe 3 1 read-write ADC10ON ADC10 On/Enable 4 1 read-write REFON ADC10 Reference on 5 1 read-write REF2_5V ADC10 Ref 0:1.5V / 1:2.5V 6 1 read-write MSC ADC10 Multiple SampleConversion 7 1 read-write REFBURST ADC10 Reference Burst Mode 8 1 read-write REFOUT ADC10 Enalbe output of Ref. 9 1 read-write ADC10SR ADC10 Sampling Rate 0:200ksps / 1:50ksps 10 1 read-write ADC10SHT ADC10 Sample Hold Select Bit: 0 11 2 read-write ADC10SHT_0 4 x ADC10CLKs 0 ADC10SHT_1 8 x ADC10CLKs 1 ADC10SHT_2 16 x ADC10CLKs 2 ADC10SHT_3 64 x ADC10CLKs 3 SREF ADC10 Reference Select Bit: 0 13 3 read-write SREF_0 VR+ = AVCC and VR- = AVSS 0 SREF_1 VR+ = VREF+ and VR- = AVSS 1 SREF_2 VR+ = VEREF+ and VR- = AVSS 2 SREF_3 VR+ = VEREF+ and VR- = AVSS 3 SREF_4 VR+ = AVCC and VR- = VREF-/VEREF- 4 SREF_5 VR+ = VREF+ and VR- = VREF-/VEREF- 5 SREF_6 VR+ = VEREF+ and VR- = VREF-/VEREF- 6 SREF_7 VR+ = VEREF+ and VR- = VREF-/VEREF- 7 ADC10CTL1 ADC10 Control 1 362 16 65535 ADC10BUSY ADC10 BUSY 0 1 read-write CONSEQ ADC10 Conversion Sequence Select 0 1 2 read-write CONSEQ_0 Single channel single conversion 0 CONSEQ_1 Sequence of channels 1 CONSEQ_2 Repeat single channel 2 CONSEQ_3 Repeat sequence of channels 3 ADC10SSEL ADC10 Clock Source Select Bit: 0 3 2 read-write ADC10SSEL_0 ADC10OSC 0 ADC10SSEL_1 ACLK 1 ADC10SSEL_2 MCLK 2 ADC10SSEL_3 SMCLK 3 ADC10DIV ADC10 Clock Divider Select Bit: 0 5 3 read-write ADC10DIV_0 ADC10 Clock Divider Select 0 0 ADC10DIV_1 ADC10 Clock Divider Select 1 1 ADC10DIV_2 ADC10 Clock Divider Select 2 2 ADC10DIV_3 ADC10 Clock Divider Select 3 3 ADC10DIV_4 ADC10 Clock Divider Select 4 4 ADC10DIV_5 ADC10 Clock Divider Select 5 5 ADC10DIV_6 ADC10 Clock Divider Select 6 6 ADC10DIV_7 ADC10 Clock Divider Select 7 7 ISSH ADC10 Invert Sample Hold Signal 8 1 read-write ADC10DF ADC10 Data Format 0:binary 1:2's complement 9 1 read-write SHS ADC10 Sample/Hold Source Bit: 0 10 2 read-write SHS_0 ADC10SC 0 SHS_1 TA3 OUT1 1 SHS_2 TA3 OUT0 2 SHS_3 TA3 OUT2 3 INCH ADC10 Input Channel Select Bit: 0 12 4 read-write INCH_0 Selects Channel 0 0 INCH_1 Selects Channel 1 1 INCH_2 Selects Channel 2 2 INCH_3 Selects Channel 3 3 INCH_4 Selects Channel 4 4 INCH_5 Selects Channel 5 5 INCH_6 Selects Channel 6 6 INCH_7 Selects Channel 7 7 INCH_8 Selects Channel 8 8 INCH_9 Selects Channel 9 9 INCH_10 Selects Channel 10 10 INCH_11 Selects Channel 11 11 INCH_12 Selects Channel 12 12 INCH_13 Selects Channel 13 13 INCH_14 Selects Channel 14 14 INCH_15 Selects Channel 15 15 ADC10MEM ADC10 Memory 364 16 65535 ADC10MEM ADC10 Memory register 0 16 0 65535 ADC10SA ADC10 Data Transfer Start Address 372 16 65535 ADC10SA ADC10 Data Transfer Start Address register 0 16 0 65535 SYSTEM_CLOCK System Clock 82 BCSCTL3 Basic Clock System Control 3 1 8 255 LFXT1OF Low/high Frequency Oscillator Fault Flag 0 1 read-write XT2OF High frequency oscillator 2 fault flag 1 1 read-write XCAP XIN/XOUT Cap 0 2 2 read-write XCAP_0 XIN/XOUT Cap : 0 pF 0 XCAP_1 XIN/XOUT Cap : 6 pF 1 XCAP_2 XIN/XOUT Cap : 10 pF 2 XCAP_3 XIN/XOUT Cap : 12.5 pF 3 LFXT1S Mode 0 for LFXT1 (XTS = 0) 4 2 read-write LFXT1S_0 Mode 0 for LFXT1 : Normal operation 0 LFXT1S_1 Mode 1 for LFXT1 : Reserved 1 LFXT1S_2 Mode 2 for LFXT1 : VLO 2 LFXT1S_3 Mode 3 for LFXT1 : Digital input signal 3 XT2S Mode 0 for XT2 6 2 read-write XT2S_0 Mode 0 for XT2 : 0.4 - 1 MHz 0 XT2S_1 Mode 1 for XT2 : 1 - 4 MHz 1 XT2S_2 Mode 2 for XT2 : 2 - 16 MHz 2 XT2S_3 Mode 3 for XT2 : Digital input signal 3 DCOCTL DCO Clock Frequency Control 4 8 255 0 255 DCOCTL DCO Clock Frequency Control register 0 8 0 255 DCO DCO Select Bit 0 5 3 0 7 MOD Modulation Bit 0 0 5 0 31 BCSCTL1 Basic Clock System Control 1 5 8 255 DIVA ACLK Divider 0 4 2 read-write DIVA_0 ACLK Divider 0: /1 0 DIVA_1 ACLK Divider 1: /2 1 DIVA_2 ACLK Divider 2: /4 2 DIVA_3 ACLK Divider 3: /8 3 XTS LFXTCLK 0:Low Freq. / 1: High Freq. 6 1 read-write XT2OFF Enable XT2CLK 7 1 read-write BCSCTL1 Basic Clock System Control 1 register 0 8 0 255 RSEL Range Select Bit 0 0 4 0 15 BCSCTL2 Basic Clock System Control 2 6 8 255 DIVS SMCLK Divider 0 1 2 read-write DIVS_0 SMCLK Divider 0: /1 0 DIVS_1 SMCLK Divider 1: /2 1 DIVS_2 SMCLK Divider 2: /4 2 DIVS_3 SMCLK Divider 3: /8 3 SELS SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK 3 1 read-write DIVM MCLK Divider 0 4 2 read-write DIVM_0 MCLK Divider 0: /1 0 DIVM_1 MCLK Divider 1: /2 1 DIVM_2 MCLK Divider 2: /4 2 DIVM_3 MCLK Divider 3: /8 3 SELM MCLK Source Select 0 6 2 read-write SELM_0 MCLK Source Select 0: DCOCLK 0 SELM_1 MCLK Source Select 1: DCOCLK 1 SELM_2 MCLK Source Select 2: XT2CLK/LFXTCLK 2 SELM_3 MCLK Source Select 3: LFXTCLK 3 USI USI 120 USICTL0 USI Control Register 0 0 8 255 0 255 USISWRST USI Software Reset 0 1 read-write USIOE USI Output Enable 1 1 read-write USIGE USI General Output Enable Latch 2 1 read-write USIMST USI Master Select 0:Slave / 1:Master 3 1 read-write USILSB USI LSB first 1:LSB / 0:MSB 4 1 read-write USIPE5 USI Port Enable Px.5 5 1 read-write USIPE6 USI Port Enable Px.6 6 1 read-write USIPE7 USI Port Enable Px.7 7 1 read-write USICTL1 USI Control Register 1 1 8 255 0 255 USIIFG USI Counter Interrupt Flag 0 1 read-write USISTTIFG USI START Condition interrupt Flag 1 1 read-write USISTP USI STOP Condition received 2 1 read-write USIAL USI Arbitration Lost 3 1 read-write USIIE USI Counter Interrupt enable 4 1 read-write USISTTIE USI START Condition interrupt enable 5 1 read-write USII2C USI I2C Mode 6 1 read-write USICKPH USI Sync. Mode: Clock Phase 7 1 read-write USICKCTL USI Clock Control Register 2 8 255 USISWCLK USI Software Clock 0 1 read-write USICKPL USI Clock Polarity 0:Inactive=Low / 1:Inactive=High 1 1 read-write USISSEL USI Clock Source Select 2 2 3 read-write USISSEL_0 USI Clock Source: 0 0 USISSEL_1 USI Clock Source: 1 1 USISSEL_2 USI Clock Source: 2 2 USISSEL_3 USI Clock Source: 3 3 USISSEL_4 USI Clock Source: 4 4 USISSEL_5 USI Clock Source: 5 5 USISSEL_6 USI Clock Source: 6 6 USISSEL_7 USI Clock Source: 7 7 USIDIV USI Clock Divider 2 5 3 read-write USIDIV_0 USI Clock Divider: 0 0 USIDIV_1 USI Clock Divider: 1 1 USIDIV_2 USI Clock Divider: 2 2 USIDIV_3 USI Clock Divider: 3 3 USIDIV_4 USI Clock Divider: 4 4 USIDIV_5 USI Clock Divider: 5 5 USIDIV_6 USI Clock Divider: 6 6 USIDIV_7 USI Clock Divider: 7 7 USICNT USI Bit Counter Register 3 8 255 0 255 USICNT0 USI Bit Count 0 0 1 read-write USICNT1 USI Bit Count 1 1 1 read-write USICNT2 USI Bit Count 2 2 1 read-write USICNT3 USI Bit Count 3 3 1 read-write USICNT4 USI Bit Count 4 4 1 read-write USIIFGCC USI Interrupt Flag Clear Control 5 1 read-write USI16B USI 16 Bit Shift Register Enable 6 1 read-write USISCLREL USI SCL Released 7 1 read-write USISRL USI Low Byte Shift Register 4 8 255 USISRH USI High Byte Shift Register 5 8 255 CALIBRATION_DATA Calibration Data 4350 CALDCO_1MHZ DCOCTL Calibration Data for 1MHz 0 8 255 CALDCO_1MHZ DCOCTL Calibration Data register 0 8 CALBC1_1MHZ BCSCTL1 Calibration Data for 1MHz 1 8 255 CALBC1_1MHZ BCSCTL1 Calibration Data register 0 8 WATCHDOG_TIMER Watchdog Timer 288 WDTCTL Watchdog Timer Control 0 16 65535 WDTSSEL WDTSSEL 2 1 read-write WDTCNTCL WDTCNTCL 3 1 read-write WDTTMSEL WDTTMSEL 4 1 read-write WDTNMI WDTNMI 5 1 read-write WDTNMIES WDTNMIES 6 1 read-write WDTHOLD WDTHOLD 7 1 read-write WDTPW Watchdog Timer Password 8 8 WDTPWR read PASSWORD Value always read from the Watchdog Password register 105 WDTPWW write PASSWORD Value which must be written to the Watchdog Password register 90 WDTIS WDTIS0 0 2 0 3 FLASH Flash 296 FCTL1 FLASH Control 1 0 16 65535 ERASE Enable bit for Flash segment erase 1 1 read-write MERAS Enable bit for Flash mass erase 2 1 read-write WRT Enable bit for Flash write 6 1 read-write BLKWRT Enable bit for Flash segment write 7 1 read-write FWKEY FCTL1 Password 8 8 FWKEYR read PASSWORD Value always read from the FCTL1 Password register 150 FWKEYW write PASSWORD Value which must be written to the FCTL1 Password register 165 FCTL2 FLASH Control 2 2 16 65535 FSSEL Flash clock select 0 */ /* to distinguish from USART SSELx 6 2 read-write FSSEL_0 Flash clock select: 0 - ACLK 0 FSSEL_1 Flash clock select: 1 - MCLK 1 FSSEL_2 Flash clock select: 2 - SMCLK 2 FSSEL_3 Flash clock select: 3 - SMCLK 3 FWKEY FCTL2 Password 8 8 FWKEYR read PASSWORD Value always read from the FCTL2 Password register 150 FWKEYW write PASSWORD Value which must be written to the FCTL2 Password register 165 FN Divide Flash clock by 1 to 64 using FN0 to FN5 according to: 0 6 0 63 FCTL3 FLASH Control 3 4 16 65535 BUSY Flash busy: 1 0 1 read-write KEYV Flash Key violation flag 1 1 read-write ACCVIFG Flash Access violation flag 2 1 read-write WAIT Wait flag for segment write 3 1 read-write LOCK Lock bit: 1 - Flash is locked (read only) 4 1 read-write EMEX Flash Emergency Exit 5 1 read-write LOCKA Segment A Lock bit: read = 1 - Segment is locked (read only) 6 1 read-write FAIL Last Program or Erase failed 7 1 read-write FWKEY FCTL3 Password 8 8 FWKEYR read PASSWORD Value always read from the FCTL3 Password register 150 FWKEYW write PASSWORD Value which must be written to the FCTL3 Password register 165 TIMER_A2 Timer A2 302 TAIV Timer A Interrupt Vector Word 0 16 65535 TAIV Timer A Interrupt Vector value 0 4 TAIV read-write NONE No interrupt pending 0 TACCR1 Capture/Compare 1 2 TAIFG Timer overflow 10 TACTL Timer A Control 50 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TACCTL0 Timer A Capture/Compare Control 0 52 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TACCTL1 Timer A Capture/Compare Control 1 54 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TAR Timer A Counter Register 66 16 65535 TAR Timer A Counter Register 0 16 0 65535 TACCR0 Timer A Capture/Compare 0 68 16 65535 TACCR0 Timer A Capture/Compare register 0 0 16 0 65535 TACCR1 Timer A Capture/Compare 1 70 16 65535 TACCR1 Timer A Capture/Compare register 1 0 16 0 65535 _INTERRUPTS 65504 PORT1 0xFFE4 Port 1 2 PORT2 0xFFE6 Port 2 3 USI 0xFFE8 USI 4 ADC10 0xFFEA ADC10 5 TIMERA1 0xFFF0 Timer A CC1, TA 8 TIMERA0 0xFFF2 Timer A CC0 9 WDT 0xFFF4 Watchdog Timer 10 NMI 0xFFFC Non-maskable 14