msp430gen MSP430G2553 v0.4.0 8 16 16 read-write 0 SPECIAL_FUNCTION Special Function 0 IE1 Interrupt Enable 1 0 8 255 WDTIE Watchdog Interrupt Enable 0 1 read-write OFIE Osc. Fault Interrupt Enable 1 1 read-write NMIIE NMI Interrupt Enable 4 1 read-write ACCVIE Flash Access Violation Interrupt Enable 5 1 read-write IE2 Interrupt Enable 2 1 8 255 UCA0RXIE UCA0RXIE 0 1 read-write UCA0TXIE UCA0TXIE 1 1 read-write UCB0RXIE UCB0RXIE 2 1 read-write UCB0TXIE UCB0TXIE 3 1 read-write IFG1 Interrupt Flag 1 2 8 255 WDTIFG Watchdog Interrupt Flag 0 1 read-write OFIFG Osc. Fault Interrupt Flag 1 1 read-write PORIFG Power On Interrupt Flag 2 1 read-write RSTIFG Reset Interrupt Flag 3 1 read-write NMIIFG NMI Interrupt Flag 4 1 read-write IFG2 Interrupt Flag 2 3 8 255 UCA0RXIFG UCA0RXIFG 0 1 read-write UCA0TXIFG UCA0TXIFG 1 1 read-write UCB0RXIFG UCB0RXIFG 2 1 read-write UCB0TXIFG UCB0TXIFG 3 1 read-write PORT_3_4 Port 3/4 16 P3REN Port 3 Resistor Enable 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3REN Port 3 Resistor Enable register 0 8 0 255 P3IN Port 3 Input 8 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3IN Port 3 Input register 0 8 0 255 P3OUT Port 3 Output 9 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3OUT Port 3 Output register 0 8 0 255 P3DIR Port 3 Direction 10 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3DIR Port 3 Direction register 0 8 0 255 P3SEL Port 3 Selection 11 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3SEL Port 3 Selection register 0 8 0 255 P3SEL2 Port 3 Selection 2 51 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P3SEL2 Port 3 Selection register 2 0 8 0 255 PORT_1_2 Port 1/2 32 P1IN Port 1 Input 0 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IN Port 1 Input register 0 8 0 255 P1OUT Port 1 Output 1 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1OUT Port 1 Output register 0 8 0 255 P1DIR Port 1 Direction 2 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1DIR Port 1 Direction register 0 8 0 255 P1IFG Port 1 Interrupt Flag 3 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IFG Port 1 Interrupt Flag register 0 8 0 255 P1IES Port 1 Interrupt Edge Select 4 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IES Port 1 Interrupt Edge Select register 0 8 0 255 P1IE Port 1 Interrupt Enable 5 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1IE Port 1 Interrupt Enable register 0 8 0 255 P1SEL Port 1 Selection 6 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SEL Port 1 Selection register 0 8 0 255 P1REN Port 1 Resistor Enable 7 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1REN Port 1 Resistor Enable register 0 8 0 255 P2IN Port 2 Input 8 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IN Port 2 Input register 0 8 0 255 P2OUT Port 2 Output 9 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2OUT Port 2 Output register 0 8 0 255 P2DIR Port 2 Direction 10 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2DIR Port 2 Direction register 0 8 0 255 P2IFG Port 2 Interrupt Flag 11 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IFG Port 2 Interrupt Flag register 0 8 0 255 P2IES Port 2 Interrupt Edge Select 12 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IES Port 2 Interrupt Edge Select register 0 8 0 255 P2IE Port 2 Interrupt Enable 13 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2IE Port 2 Interrupt Enable register 0 8 0 255 P2SEL Port 2 Selection 14 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SEL Port 2 Selection register 0 8 0 255 P2REN Port 2 Resistor Enable 15 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2REN Port 2 Resistor Enable register 0 8 0 255 P1SEL2 Port 1 Selection 2 33 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P1SEL2 Port 1 Selection register 2 0 8 0 255 P2SEL2 Port 2 Selection 2 34 8 255 0 255 P0 P0 0 1 read-write P1 P1 1 1 read-write P2 P2 2 1 read-write P3 P3 3 1 read-write P4 P4 4 1 read-write P5 P5 5 1 read-write P6 P6 6 1 read-write P7 P7 7 1 read-write P2SEL2 Port 2 Selection register 2 0 8 0 255 ADC10 ADC10 72 ADC10DTC0 ADC10 Data Transfer Control 0 0 8 255 ADC10FETCH This bit should normally be reset 0 1 read-write ADC10B1 ADC10 block one 1 1 read-write ADC10CT ADC10 continuous transfer 2 1 read-write ADC10TB ADC10 two-block mode 3 1 read-write ADC10DTC1 ADC10 Data Transfer Control 1 1 8 255 ADC10DTC1 ADC10 Data Transfer Control 1 register 0 8 0 255 ADC10AE0 ADC10 Analog Enable 0 2 8 255 ADC10AE0 ADC10 Analog Enable 0 register 0 8 0 255 ADC10CTL0 ADC10 Control 0 360 16 65535 ADC10SC ADC10 Start Conversion 0 1 read-write ENC ADC10 Enable Conversion 1 1 read-write ADC10IFG ADC10 Interrupt Flag 2 1 read-write ADC10IE ADC10 Interrupt Enalbe 3 1 read-write ADC10ON ADC10 On/Enable 4 1 read-write REFON ADC10 Reference on 5 1 read-write REF2_5V ADC10 Ref 0:1.5V / 1:2.5V 6 1 read-write MSC ADC10 Multiple SampleConversion 7 1 read-write REFBURST ADC10 Reference Burst Mode 8 1 read-write REFOUT ADC10 Enalbe output of Ref. 9 1 read-write ADC10SR ADC10 Sampling Rate 0:200ksps / 1:50ksps 10 1 read-write ADC10SHT ADC10 Sample Hold Select Bit: 0 11 2 read-write ADC10SHT_0 4 x ADC10CLKs 0 ADC10SHT_1 8 x ADC10CLKs 1 ADC10SHT_2 16 x ADC10CLKs 2 ADC10SHT_3 64 x ADC10CLKs 3 SREF ADC10 Reference Select Bit: 0 13 3 read-write SREF_0 VR+ = AVCC and VR- = AVSS 0 SREF_1 VR+ = VREF+ and VR- = AVSS 1 SREF_2 VR+ = VEREF+ and VR- = AVSS 2 SREF_3 VR+ = VEREF+ and VR- = AVSS 3 SREF_4 VR+ = AVCC and VR- = VREF-/VEREF- 4 SREF_5 VR+ = VREF+ and VR- = VREF-/VEREF- 5 SREF_6 VR+ = VEREF+ and VR- = VREF-/VEREF- 6 SREF_7 VR+ = VEREF+ and VR- = VREF-/VEREF- 7 ADC10CTL1 ADC10 Control 1 362 16 65535 ADC10BUSY ADC10 BUSY 0 1 read-write CONSEQ ADC10 Conversion Sequence Select 0 1 2 read-write CONSEQ_0 Single channel single conversion 0 CONSEQ_1 Sequence of channels 1 CONSEQ_2 Repeat single channel 2 CONSEQ_3 Repeat sequence of channels 3 ADC10SSEL ADC10 Clock Source Select Bit: 0 3 2 read-write ADC10SSEL_0 ADC10OSC 0 ADC10SSEL_1 ACLK 1 ADC10SSEL_2 MCLK 2 ADC10SSEL_3 SMCLK 3 ADC10DIV ADC10 Clock Divider Select Bit: 0 5 3 read-write ADC10DIV_0 ADC10 Clock Divider Select 0 0 ADC10DIV_1 ADC10 Clock Divider Select 1 1 ADC10DIV_2 ADC10 Clock Divider Select 2 2 ADC10DIV_3 ADC10 Clock Divider Select 3 3 ADC10DIV_4 ADC10 Clock Divider Select 4 4 ADC10DIV_5 ADC10 Clock Divider Select 5 5 ADC10DIV_6 ADC10 Clock Divider Select 6 6 ADC10DIV_7 ADC10 Clock Divider Select 7 7 ISSH ADC10 Invert Sample Hold Signal 8 1 read-write ADC10DF ADC10 Data Format 0:binary 1:2's complement 9 1 read-write SHS ADC10 Sample/Hold Source Bit: 0 10 2 read-write SHS_0 ADC10SC 0 SHS_1 TA3 OUT1 1 SHS_2 TA3 OUT0 2 SHS_3 TA3 OUT2 3 INCH ADC10 Input Channel Select Bit: 0 12 4 read-write INCH_0 Selects Channel 0 0 INCH_1 Selects Channel 1 1 INCH_2 Selects Channel 2 2 INCH_3 Selects Channel 3 3 INCH_4 Selects Channel 4 4 INCH_5 Selects Channel 5 5 INCH_6 Selects Channel 6 6 INCH_7 Selects Channel 7 7 INCH_8 Selects Channel 8 8 INCH_9 Selects Channel 9 9 INCH_10 Selects Channel 10 10 INCH_11 Selects Channel 11 11 INCH_12 Selects Channel 12 12 INCH_13 Selects Channel 13 13 INCH_14 Selects Channel 14 14 INCH_15 Selects Channel 15 15 ADC10MEM ADC10 Memory 364 16 65535 ADC10MEM ADC10 Memory register 0 16 0 65535 ADC10SA ADC10 Data Transfer Start Address 372 16 65535 ADC10SA ADC10 Data Transfer Start Address register 0 16 0 65535 SYSTEM_CLOCK System Clock 82 BCSCTL3 Basic Clock System Control 3 1 8 255 LFXT1OF Low/high Frequency Oscillator Fault Flag 0 1 read-write XT2OF High frequency oscillator 2 fault flag 1 1 read-write XCAP XIN/XOUT Cap 0 2 2 read-write XCAP_0 XIN/XOUT Cap : 0 pF 0 XCAP_1 XIN/XOUT Cap : 6 pF 1 XCAP_2 XIN/XOUT Cap : 10 pF 2 XCAP_3 XIN/XOUT Cap : 12.5 pF 3 LFXT1S Mode 0 for LFXT1 (XTS = 0) 4 2 read-write LFXT1S_0 Mode 0 for LFXT1 : Normal operation 0 LFXT1S_1 Mode 1 for LFXT1 : Reserved 1 LFXT1S_2 Mode 2 for LFXT1 : VLO 2 LFXT1S_3 Mode 3 for LFXT1 : Digital input signal 3 XT2S Mode 0 for XT2 6 2 read-write XT2S_0 Mode 0 for XT2 : 0.4 - 1 MHz 0 XT2S_1 Mode 1 for XT2 : 1 - 4 MHz 1 XT2S_2 Mode 2 for XT2 : 2 - 16 MHz 2 XT2S_3 Mode 3 for XT2 : Digital input signal 3 DCOCTL DCO Clock Frequency Control 4 8 255 0 255 DCOCTL DCO Clock Frequency Control register 0 8 0 255 DCO DCO Select Bit 0 5 3 0 7 MOD Modulation Bit 0 0 5 0 31 BCSCTL1 Basic Clock System Control 1 5 8 255 DIVA ACLK Divider 0 4 2 read-write DIVA_0 ACLK Divider 0: /1 0 DIVA_1 ACLK Divider 1: /2 1 DIVA_2 ACLK Divider 2: /4 2 DIVA_3 ACLK Divider 3: /8 3 XTS LFXTCLK 0:Low Freq. / 1: High Freq. 6 1 read-write XT2OFF Enable XT2CLK 7 1 read-write BCSCTL1 Basic Clock System Control 1 register 0 8 0 255 RSEL Range Select Bit 0 0 4 0 15 BCSCTL2 Basic Clock System Control 2 6 8 255 DIVS SMCLK Divider 0 1 2 read-write DIVS_0 SMCLK Divider 0: /1 0 DIVS_1 SMCLK Divider 1: /2 1 DIVS_2 SMCLK Divider 2: /4 2 DIVS_3 SMCLK Divider 3: /8 3 SELS SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK 3 1 read-write DIVM MCLK Divider 0 4 2 read-write DIVM_0 MCLK Divider 0: /1 0 DIVM_1 MCLK Divider 1: /2 1 DIVM_2 MCLK Divider 2: /4 2 DIVM_3 MCLK Divider 3: /8 3 SELM MCLK Source Select 0 6 2 read-write SELM_0 MCLK Source Select 0: DCOCLK 0 SELM_1 MCLK Source Select 1: DCOCLK 1 SELM_2 MCLK Source Select 2: XT2CLK/LFXTCLK 2 SELM_3 MCLK Source Select 3: LFXTCLK 3 COMPARATOR_A Comparator A 88 CACTL1 Comparator A Control 1 1 8 255 CAIFG Comp. A Interrupt Flag 0 1 read-write CAIE Comp. A Interrupt Enable 1 1 read-write CAIES Comp. A Int. Edge Select: 0:rising / 1:falling 2 1 read-write CAON Comp. A enable 3 1 read-write CAREF Comp. A Internal Reference Select 0 4 2 read-write CAREF_0 Comp. A Int. Ref. Select 0 : Off 0 CAREF_1 Comp. A Int. Ref. Select 1 : 0.25*Vcc 1 CAREF_2 Comp. A Int. Ref. Select 2 : 0.5*Vcc 2 CAREF_3 Comp. A Int. Ref. Select 3 : Vt 3 CARSEL Comp. A Internal Reference Enable 6 1 read-write CAEX Comp. A Exchange Inputs 7 1 read-write CACTL2 Comparator A Control 2 2 8 255 0 255 CAOUT Comp. A Output 0 1 read-write CAF Comp. A Enable Output Filter 1 1 read-write CASHORT Comp. A Short + and - Terminals 7 1 read-write P2CA Comp. A +Terminal Multiplexer 2 5 P2CA read-write NONE_NONE No + or - connection 0 NONE_CA1 No connection to +, connect - to CA1 2 NONE_CA2 No connection to +, connect - to CA2 4 NONE_CA3 No connection to +, connect - to CA3 6 NONE_CA4 No connection to +, connect - to CA4 8 NONE_CA5 No connection to +, connect - to CA5 10 NONE_CA6 No connection to +, connect - to CA6 12 NONE_CA7 No connection to +, connect - to CA7 14 CA0_NONE Connect + to CA0, no connection to - 1 CA0_CA1 Connect + to CA0, connect - to CA1 3 CA0_CA2 Connect + to CA0, connect - to CA2 5 CA0_CA3 Connect + to CA0, connect - to CA3 7 CA0_CA4 Connect + to CA0, connect - to CA4 9 CA0_CA5 Connect + to CA0, connect - to CA5 11 CA0_CA6 Connect + to CA0, connect - to CA6 13 CA0_CA7 Connect + to CA0, connect - to CA7 15 CA1_NONE Connect + to CA1, no connection to - 16 CA1_CA1 Connect + to CA1, connect - to CA1 18 CA1_CA2 Connect + to CA1, connect - to CA2 20 CA1_CA3 Connect + to CA1, connect - to CA3 22 CA1_CA4 Connect + to CA1, connect - to CA4 24 CA1_CA5 Connect + to CA1, connect - to CA5 26 CA1_CA6 Connect + to CA1, connect - to CA6 28 CA1_CA7 Connect + to CA1, connect - to CA7 30 CA2_NONE Connect + to CA2, no connection to - 17 CA2_CA1 Connect + to CA2, connect - to CA1 19 CA2_CA2 Connect + to CA2, connect - to CA2 21 CA2_CA3 Connect + to CA2, connect - to CA3 23 CA2_CA4 Connect + to CA2, connect - to CA4 25 CA2_CA5 Connect + to CA2, connect - to CA5 27 CA2_CA6 Connect + to CA2, connect - to CA6 29 CA2_CA7 Connect + to CA2, connect - to CA7 31 CAPD Comparator A Port Disable 3 8 255 0 255 CAPD0 Comp. A Disable Input Buffer of Port Register .0 0 1 read-write CAPD1 Comp. A Disable Input Buffer of Port Register .1 1 1 read-write CAPD2 Comp. A Disable Input Buffer of Port Register .2 2 1 read-write CAPD3 Comp. A Disable Input Buffer of Port Register .3 3 1 read-write CAPD4 Comp. A Disable Input Buffer of Port Register .4 4 1 read-write CAPD5 Comp. A Disable Input Buffer of Port Register .5 5 1 read-write CAPD6 Comp. A Disable Input Buffer of Port Register .6 6 1 read-write CAPD7 Comp. A Disable Input Buffer of Port Register .7 7 1 read-write CAPD Comparator A Port Disable register 0 8 0 255 USCI_A0_UART_MODE USCI_A0 UART Mode 92 UCA0ABCTL USCI A0 LIN Control 1 8 255 UCABDEN Auto Baud Rate detect enable 0 1 read-write UCBTOE Break Timeout error 2 1 read-write UCSTOE Sync-Field Timeout error 3 1 read-write UCDELIM Break Sync Delimiter 0 4 2 0 3 UCA0IRTCTL USCI A0 IrDA Transmit Control 2 8 255 0 255 UCIREN IRDA Encoder/Decoder enable 0 1 read-write UCIRTXCLK IRDA Transmit Pulse Clock Select 1 1 read-write UCIRTXPL IRDA Transmit Pulse Length 0 2 6 0 63 UCA0IRRCTL USCI A0 IrDA Receive Control 3 8 255 0 255 UCIRRXFE IRDA Receive Filter enable 0 1 read-write UCIRRXPL IRDA Receive Input Polarity 1 1 read-write UCIRRXFL IRDA Receive Filter Length 0 2 6 0 63 UCA0CTL0 USCI A0 Control Register 0 4 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Async. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCSPB Async. Mode: Stop Bits 0:one / 1: two 3 1 read-write UC7BIT Async. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Async. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCPAR Async. Mode: Parity 0:odd / 1:even 6 1 read-write UCPEN Async. Mode: Parity enable 7 1 read-write UCA0CTL1 USCI A0 Control Register 1 5 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXBRK Send next Data as Break 1 1 read-write UCTXADDR Send next Data as Address 2 1 read-write UCDORM Dormant (Sleep) Mode 3 1 read-write UCBRKIE Break interrupt enable 4 1 read-write UCRXEIE RX Error interrupt enable 5 1 read-write UCSSEL USCI 0 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA0BR0 USCI A0 Baud Rate 0 6 8 255 UCA0BR0 USCI A0 Baud Rate 0 register 0 8 0 255 UCA0BR1 USCI A0 Baud Rate 1 7 8 255 UCA0BR1 USCI A0 Baud Rate 1 register 0 8 0 255 UCA0MCTL USCI A0 Modulation Control 8 8 255 UCOS16 USCI 16-times Oversampling enable 0 1 read-write UCBRS USCI Second Stage Modulation Select 2 1 3 read-write UCBRS_0 USCI Second Stage Modulation: 0 0 UCBRS_1 USCI Second Stage Modulation: 1 1 UCBRS_2 USCI Second Stage Modulation: 2 2 UCBRS_3 USCI Second Stage Modulation: 3 3 UCBRS_4 USCI Second Stage Modulation: 4 4 UCBRS_5 USCI Second Stage Modulation: 5 5 UCBRS_6 USCI Second Stage Modulation: 6 6 UCBRS_7 USCI Second Stage Modulation: 7 7 UCBRF USCI First Stage Modulation Select 3 4 4 read-write UCBRF_0 USCI First Stage Modulation: 0 0 UCBRF_1 USCI First Stage Modulation: 1 1 UCBRF_2 USCI First Stage Modulation: 2 2 UCBRF_3 USCI First Stage Modulation: 3 3 UCBRF_4 USCI First Stage Modulation: 4 4 UCBRF_5 USCI First Stage Modulation: 5 5 UCBRF_6 USCI First Stage Modulation: 6 6 UCBRF_7 USCI First Stage Modulation: 7 7 UCBRF_8 USCI First Stage Modulation: 8 8 UCBRF_9 USCI First Stage Modulation: 9 9 UCBRF_10 USCI First Stage Modulation: A 10 UCBRF_11 USCI First Stage Modulation: B 11 UCBRF_12 USCI First Stage Modulation: C 12 UCBRF_13 USCI First Stage Modulation: D 13 UCBRF_14 USCI First Stage Modulation: E 14 UCBRF_15 USCI First Stage Modulation: F 15 UCA0STAT USCI A0 Status Register 9 8 255 0 255 UCBUSY USCI Busy Flag 0 1 read-write UCADDR USCI Address received Flag 1 1 read-write UCRXERR USCI RX Error Flag 2 1 read-write UCBRK USCI Break received 3 1 read-write UCPE USCI Parity Error Flag 4 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCIDLE Idle line detected 1 1 UCA0RXBUF USCI A0 Receive Buffer 10 8 255 UCA0RXBUF USCI A0 Receive Buffer register 0 8 0 255 UCA0TXBUF USCI A0 Transmit Buffer 11 8 255 UCA0TXBUF USCI A0 Transmit Buffer register 0 8 0 255 USCI_A0_SPI_MODE USCI_A0 SPI Mode 96 UCA0CTL0 USCI A0 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCA0CTL1 USCI A0 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCA0BR0 USCI A0 Baud Rate 0 2 8 255 UCA0BR0 USCI A0 Baud Rate 0 register 0 8 0 255 UCA0BR1 USCI A0 Baud Rate 1 3 8 255 UCA0BR1 USCI A0 Baud Rate 1 register 0 8 0 255 UCA0STAT USCI A0 Status Register 5 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCA0RXBUF USCI A0 Receive Buffer 6 8 255 UCA0RXBUF USCI A0 Receive Buffer register 0 8 0 255 UCA0TXBUF USCI A0 Transmit Buffer 7 8 255 UCA0TXBUF USCI A0 Transmit Buffer register 0 8 0 255 USCI_B0_I2C_MODE USCI_B0 I2C Mode 104 UCB0CTL0 USCI B0 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UCMM Multi-Master Environment 5 1 read-write UCSLA10 10-bit Slave Address Mode 6 1 read-write UCA10 10-bit Address Mode 7 1 read-write UCB0CTL1 USCI B0 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCTXSTT Transmit START 1 1 read-write UCTXSTP Transmit STOP 2 1 read-write UCTXNACK Transmit NACK 3 1 read-write UCTR Transmit/Receive Select/Flag 4 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB0BR0 USCI B0 Baud Rate 0 2 8 255 UCB0BR0 USCI B0 Baud Rate 0 register 0 8 0 255 UCB0BR1 USCI B0 Baud Rate 1 3 8 255 UCB0BR1 USCI B0 Baud Rate 1 register 0 8 0 255 UCB0I2CIE USCI B0 I2C Interrupt Enable Register 4 8 255 UCALIE Arbitration Lost interrupt enable 0 1 read-write UCSTTIE START Condition interrupt enable 1 1 read-write UCSTPIE STOP Condition interrupt enable 2 1 read-write UCNACKIE NACK Condition interrupt enable 3 1 read-write UCB0STAT USCI B0 Status Register 5 8 255 0 255 UCALIFG Arbitration Lost interrupt Flag 0 1 read-write UCSTTIFG START Condition interrupt Flag 1 1 read-write UCSTPIFG STOP Condition interrupt Flag 2 1 read-write UCNACKIFG NAK Condition interrupt Flag 3 1 read-write UCBBUSY Bus Busy Flag 4 1 read-write UCGC General Call address received Flag 5 1 read-write UCSCLLOW SCL low 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB0RXBUF USCI B0 Receive Buffer 6 8 255 UCB0RXBUF USCI B0 Receive Buffer register 0 8 0 255 UCB0TXBUF USCI B0 Transmit Buffer 7 8 255 UCB0TXBUF USCI B0 Transmit Buffer register 0 8 0 255 UCB0I2COA USCI B0 I2C Own Address 176 16 65535 UCGCEN I2C General Call enable 15 1 read-write UCOA I2C Own Address 0 0 10 0 1023 UCB0I2CSA USCI B0 I2C Slave Address 178 16 65535 UCSA I2C Slave Address 0 0 10 0 1023 USCI_B0_SPI_MODE USCI_B0 SPI Mode 104 UCB0CTL0 USCI B0 Control Register 0 0 8 255 UCSYNC Sync-Mode 0:UART-Mode / 1:SPI-Mode 0 1 read-write UCMODE Sync. Mode: USCI Mode 1 1 2 read-write UCMODE_0 Sync. Mode: USCI Mode: 0 0 UCMODE_1 Sync. Mode: USCI Mode: 1 1 UCMODE_2 Sync. Mode: USCI Mode: 2 2 UCMODE_3 Sync. Mode: USCI Mode: 3 3 UCMST Sync. Mode: Master Select 3 1 read-write UC7BIT Sync. Mode: Data Bits 0:8-bits / 1:7-bits 4 1 read-write UCMSB Sync. Mode: MSB first 0:LSB / 1:MSB 5 1 read-write UCCKPL Sync. Mode: Clock Polarity 6 1 read-write UCCKPH Sync. Mode: Clock Phase 7 1 read-write UCB0CTL1 USCI B0 Control Register 1 1 8 255 UCSWRST USCI Software Reset 0 1 read-write UCSSEL USCI 1 Clock Source Select 1 6 2 read-write UCSSEL_0 USCI 0 Clock Source: 0 0 UCSSEL_1 USCI 0 Clock Source: 1 1 UCSSEL_2 USCI 0 Clock Source: 2 2 UCSSEL_3 USCI 0 Clock Source: 3 3 UCB0BR0 USCI B0 Baud Rate 0 2 8 255 UCB0BR0 USCI B0 Baud Rate 0 register 0 8 0 255 UCB0BR1 USCI B0 Baud Rate 1 3 8 255 UCB0BR1 USCI B0 Baud Rate 1 register 0 8 0 255 UCB0STAT USCI B0 Status Register 5 8 255 UCBUSY USCI Busy Flag 0 1 read-write UCOE USCI Overrun Error Flag 5 1 read-write UCFE USCI Frame Error Flag 6 1 read-write UCLISTEN USCI Listen mode 7 1 read-write UCB0RXBUF USCI B0 Receive Buffer 6 8 255 UCB0RXBUF USCI B0 Receive Buffer register 0 8 0 255 UCB0TXBUF USCI B0 Transmit Buffer 7 8 255 UCB0TXBUF USCI B0 Transmit Buffer register 0 8 0 255 TLV_CALIBRATION_DATA TLV Calibration Data 4288 TLV_ADC10_1_TAG TLV ADC10_1 TAG 26 8 255 TLV_ADC10_1_TAG TLV ADC10_1 TAG register 0 8 0 255 TLV_ADC10_1_LEN TLV ADC10_1 LEN 27 8 255 TLV_ADC10_1_LEN TLV ADC10_1 LEN register 0 8 0 255 TLV_DCO_30_TAG TLV TAG_DCO30 TAG 54 8 255 TLV_DCO_30_TAG TLV TAG_DCO30 TAG register 0 8 0 255 TLV_DCO_30_LEN TLV TAG_DCO30 LEN 55 8 255 TLV_DCO_30_LEN TLV TAG_DCO30 LEN register 0 8 0 255 TLV_CHECKSUM TLV CHECK SUM 0 16 65535 TLV_CHECKSUM TLV CHECK SUM register 0 16 0 65535 CALIBRATION_DATA Calibration Data 4344 CALDCO_16MHZ DCOCTL Calibration Data for 16MHz 0 8 255 CALDCO_16MHZ DCOCTL Calibration Data for 16MHz register 0 8 0 255 CALBC1_16MHZ BCSCTL1 Calibration Data for 16MHz 1 8 255 CALBC1_16MHZ BCSCTL1 Calibration Data for 16MHz register 0 8 0 255 CALDCO_12MHZ DCOCTL Calibration Data for 12MHz 2 8 255 CALDCO_12MHZ DCOCTL Calibration Data for 12MHz register 0 8 0 255 CALBC1_12MHZ BCSCTL1 Calibration Data for 12MHz 3 8 255 CALBC1_12MHZ BCSCTL1 Calibration Data for 12MHz register 0 8 0 255 CALDCO_8MHZ DCOCTL Calibration Data for 8MHz 4 8 255 CALDCO_8MHZ DCOCTL Calibration Data for 8MHz register 0 8 0 255 CALBC1_8MHZ BCSCTL1 Calibration Data for 8MHz 5 8 255 CALBC1_8MHZ BCSCTL1 Calibration Data for 8MHz register 0 8 0 255 CALDCO_1MHZ DCOCTL Calibration Data for 1MHz 6 8 255 CALDCO_1MHZ DCOCTL Calibration Data for 1MHz register 0 8 0 255 CALBC1_1MHZ BCSCTL1 Calibration Data for 1MHz 7 8 255 CALBC1_1MHZ BCSCTL1 Calibration Data for 1MHz register 0 8 0 255 TIMER1_A3 Timer1_A3 286 WATCHDOG_TIMER Watchdog Timer 288 WDTCTL Watchdog Timer Control 0 16 65535 WDTSSEL WDTSSEL 2 1 read-write WDTCNTCL WDTCNTCL 3 1 read-write WDTTMSEL WDTTMSEL 4 1 read-write WDTNMI WDTNMI 5 1 read-write WDTNMIES WDTNMIES 6 1 read-write WDTHOLD WDTHOLD 7 1 read-write WDTPW Watchdog Timer Password 8 8 WDTPWR read PASSWORD Value always read from the Watchdog Password register 105 WDTPWW write PASSWORD Value which must be written to the Watchdog Password register 90 WDTIS WDTIS0 0 2 0 3 FLASH Flash 296 FCTL1 FLASH Control 1 0 16 65535 ERASE Enable bit for Flash segment erase 1 1 read-write MERAS Enable bit for Flash mass erase 2 1 read-write WRT Enable bit for Flash write 6 1 read-write BLKWRT Enable bit for Flash segment write 7 1 read-write FWKEY FCTL1 Password 8 8 FWKEYR read PASSWORD Value always read from the FCTL1 Password register 150 FWKEYW write PASSWORD Value which must be written to the FCTL1 Password register 165 FCTL2 FLASH Control 2 2 16 65535 FSSEL Flash clock select 0 */ /* to distinguish from USART SSELx 6 2 read-write FSSEL_0 Flash clock select: 0 - ACLK 0 FSSEL_1 Flash clock select: 1 - MCLK 1 FSSEL_2 Flash clock select: 2 - SMCLK 2 FSSEL_3 Flash clock select: 3 - SMCLK 3 FWKEY FCTL2 Password 8 8 FWKEYR read PASSWORD Value always read from the FCTL2 Password register 150 FWKEYW write PASSWORD Value which must be written to the FCTL2 Password register 165 FN Divide Flash clock by 1 to 64 using FN0 to FN5 according to: 0 6 0 63 FCTL3 FLASH Control 3 4 16 65535 BUSY Flash busy: 1 0 1 read-write KEYV Flash Key violation flag 1 1 read-write ACCVIFG Flash Access violation flag 2 1 read-write WAIT Wait flag for segment write 3 1 read-write LOCK Lock bit: 1 - Flash is locked (read only) 4 1 read-write EMEX Flash Emergency Exit 5 1 read-write LOCKA Segment A Lock bit: read = 1 - Segment is locked (read only) 6 1 read-write FAIL Last Program or Erase failed 7 1 read-write FWKEY FCTL3 Password 8 8 FWKEYR read PASSWORD Value always read from the FCTL3 Password register 150 FWKEYW write PASSWORD Value which must be written to the FCTL3 Password register 165 TIMER0_A3 Timer A3 302 TAIV Timer0_A3 Interrupt Vector Word 0 16 65535 TAIV Timer A Interrupt Vector value 0 4 TAIV read-write NONE No interrupt pending 0 TACCR1 Capture/Compare 1 2 TACCR2 Capture/Compare 2 4 TAIFG Timer overflow 10 TACTL Timer0_A3 Control 50 16 65535 TAIFG Timer A counter interrupt flag 0 1 read-write TAIE Timer A counter interrupt enable 1 1 read-write TACLR Timer A counter clear 2 1 read-write MC Timer A mode control 1 4 2 read-write MC_0 Timer A mode control: 0 - Stop 0 MC_1 Timer A mode control: 1 - Up to CCR0 1 MC_2 Timer A mode control: 2 - Continous up 2 MC_3 Timer A mode control: 3 - Up/Down 3 ID Timer A clock input divider 1 6 2 read-write ID_0 Timer A input divider: 0 - /1 0 ID_1 Timer A input divider: 1 - /2 1 ID_2 Timer A input divider: 2 - /4 2 ID_3 Timer A input divider: 3 - /8 3 TASSEL Timer A clock source select 1 8 2 read-write TASSEL_0 Timer A clock source select: 0 - TACLK 0 TASSEL_1 Timer A clock source select: 1 - ACLK 1 TASSEL_2 Timer A clock source select: 2 - SMCLK 2 TASSEL_3 Timer A clock source select: 3 - INCLK 3 TACCTL0 Timer0_A3 Capture/Compare Control 0 52 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TACCTL1 Timer0_A3 Capture/Compare Control 1 54 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TACCTL2 Timer0_A3 Capture/Compare Control 2 56 16 65535 CCIFG Capture/compare interrupt flag 0 1 read-write COV Capture/compare overflow flag 1 1 read-write OUT PWM Output signal if output mode 0 2 1 read-write CCI Capture input signal (read) 3 1 read-write CCIE Capture/compare interrupt enable 4 1 read-write OUTMOD Output mode 2 5 3 read-write OUTMOD_0 PWM output mode: 0 - output only 0 OUTMOD_1 PWM output mode: 1 - set 1 OUTMOD_2 PWM output mode: 2 - PWM toggle/reset 2 OUTMOD_3 PWM output mode: 3 - PWM set/reset 3 OUTMOD_4 PWM output mode: 4 - toggle 4 OUTMOD_5 PWM output mode: 5 - Reset 5 OUTMOD_6 PWM output mode: 6 - PWM toggle/set 6 OUTMOD_7 PWM output mode: 7 - PWM reset/set 7 CAP Capture mode: 1 /Compare mode : 0 8 1 read-write SCCI Latched capture signal (read) 10 1 read-write SCS Capture sychronize 11 1 read-write CCIS Capture input select 1 12 2 read-write CCIS_0 Capture input select: 0 - CCIxA 0 CCIS_1 Capture input select: 1 - CCIxB 1 CCIS_2 Capture input select: 2 - GND 2 CCIS_3 Capture input select: 3 - Vcc 3 CM Capture mode 1 14 2 read-write CM_0 Capture mode: 0 - disabled 0 CM_1 Capture mode: 1 - pos. edge 1 CM_2 Capture mode: 1 - neg. edge 2 CM_3 Capture mode: 1 - both edges 3 TAR Timer0_A3 Counter Register 66 16 65535 TAR Timer A Counter Register 0 16 0 65535 TACCR0 Timer0_A3 Capture/Compare 0 68 16 65535 TACCR0 Timer A Capture/Compare register 0 0 16 0 65535 TACCR1 Timer0_A3 Capture/Compare 1 70 16 65535 TACCR1 Timer A Capture/Compare register 1 0 16 0 65535 TACCR2 Timer0_A3 Capture/Compare 2 72 16 65535 TACCR2 Timer A Capture/Compare register 2 0 16 0 65535 _INTERRUPTS 65504 TRAPINT 0xFFE0 TRAPINT 0 PORT1 0xFFE4 Port 1 2 PORT2 0xFFE6 Port 2 3 ADC10 0xFFEA ADC10 5 USCIAB0TX 0xFFEC USCI A0/B0 Transmit 6 USCIAB0RX 0xFFEE USCI A0/B0 Receive 7 TIMER0_A1 0xFFF0 Timer0_A CC1, TA0 8 TIMER0_A0 0xFFF2 Timer0_A CC0 9 WDT 0xFFF4 Watchdog Timer 10 COMPARATORA 0xFFF6 Comparator A 11 TIMER1_A1 0xFFF8 Timer1_A CC1-4, TA1 12 TIMER1_A0 0xFFFA Timer1_A CC0 13 NMI 0xFFFC Non-maskable 14