Texas Instruments ti.com MSP432P401R 3.230 ARM Cortex-M4 MSP432P4xx Device \n Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met: \n Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n \n Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the\n distribution.\n \n Neither the name of Texas Instruments Incorporated nor the names of\n its contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n \n 8 32 32 TLV 356.0 TLV 0x201000 0x0 0x15C registers TLV_CHECKSUM TLV_CHECKSUM TLV Checksum 0x0 32 read-only 0x00000000 0xffffffff DEVICE_INFO_TAG DEVICE_INFO_TAG Device Info Tag 0x4 32 read-only 0x0000000b 0xffffffff DEVICE_INFO_LEN DEVICE_INFO_LEN Device Info Length 0x8 32 read-only 0x00000000 0xffffffff DEVICE_ID DEVICE_ID Device ID 0xC 32 read-only 0x00000000 0xffffffff HWREV HWREV HW Revision 0x10 32 read-only 0x00000000 0xffffffff BCREV BCREV Boot Code Revision 0x14 32 read-only 0x00000000 0xffffffff ROM_DRVLIB_REV ROM_DRVLIB_REV ROM Driver Library Revision 0x18 32 read-only 0x00000000 0xffffffff DIE_REC_TAG DIE_REC_TAG Die Record Tag 0x1C 32 read-only 0x0000000c 0xffffffff DIE_REC_LEN DIE_REC_LEN Die Record Length 0x20 32 read-only 0x00000000 0xffffffff DIE_XPOS DIE_XPOS Die X-Position 0x24 32 read-only 0x00000000 0xffffffff DIE_YPOS DIE_YPOS Die Y-Position 0x28 32 read-only 0x00000000 0xffffffff WAFER_ID WAFER_ID Wafer ID 0x2C 32 read-only 0x00000000 0xffffffff LOT_ID LOT_ID Lot ID 0x30 32 read-only 0x00000000 0xffffffff RESERVED0 RESERVED0 Reserved 0x34 32 read-only 0x00000000 0xffffffff RESERVED1 RESERVED1 Reserved 0x38 32 read-only 0x00000000 0xffffffff RESERVED2 RESERVED2 Reserved 0x3C 32 read-only 0x00000000 0xffffffff TEST_RESULTS TEST_RESULTS Test Results 0x40 32 read-only 0x00000000 0xffffffff CS_CAL_TAG CS_CAL_TAG Clock System Calibration Tag 0x44 32 read-only 0x00000003 0xffffffff CS_CAL_LEN CS_CAL_LEN Clock System Calibration Length 0x48 32 read-only 0x00000000 0xffffffff DCOIR_FCAL_RSEL04 DCOIR_FCAL_RSEL04 DCO IR mode: Frequency calibration for DCORSEL 0 to 4 0x4C 32 read-only 0x00000000 0xffffffff DCOIR_FCAL_RSEL5 DCOIR_FCAL_RSEL5 DCO IR mode: Frequency calibration for DCORSEL 5 0x50 32 read-only 0x00000000 0xffffffff RESERVED3 RESERVED3 Reserved 0x54 32 read-only 0x00000000 0xffffffff RESERVED4 RESERVED4 Reserved 0x58 32 read-only 0x00000000 0xffffffff RESERVED5 RESERVED5 Reserved 0x5C 32 read-only 0x00000000 0xffffffff RESERVED6 RESERVED6 Reserved 0x60 32 read-only 0x00000000 0xffffffff DCOIR_CONSTK_RSEL04 DCOIR_CONSTK_RSEL04 DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 0x64 32 read-only 0x00000000 0xffffffff DCOIR_CONSTK_RSEL5 DCOIR_CONSTK_RSEL5 DCO IR mode: DCO Constant (K) for DCORSEL 5 0x68 32 read-only 0x00000000 0xffffffff DCOER_FCAL_RSEL04 DCOER_FCAL_RSEL04 DCO ER mode: Frequency calibration for DCORSEL 0 to 4 0x6C 32 read-only 0x00000000 0xffffffff DCOER_FCAL_RSEL5 DCOER_FCAL_RSEL5 DCO ER mode: Frequency calibration for DCORSEL 5 0x70 32 read-only 0x00000000 0xffffffff RESERVED7 RESERVED7 Reserved 0x74 32 read-only 0x00000000 0xffffffff RESERVED8 RESERVED8 Reserved 0x78 32 read-only 0x00000000 0xffffffff RESERVED9 RESERVED9 Reserved 0x7C 32 read-only 0x00000000 0xffffffff RESERVED10 RESERVED10 Reserved 0x80 32 read-only 0x00000000 0xffffffff DCOER_CONSTK_RSEL04 DCOER_CONSTK_RSEL04 DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 0x84 32 read-only 0x00000000 0xffffffff DCOER_CONSTK_RSEL5 DCOER_CONSTK_RSEL5 DCO ER mode: DCO Constant (K) for DCORSEL 5 0x88 32 read-only 0x00000000 0xffffffff ADC14_CAL_TAG ADC14_CAL_TAG ADC14 Calibration Tag 0x8C 32 read-only 0x00000005 0xffffffff ADC14_CAL_LEN ADC14_CAL_LEN ADC14 Calibration Length 0x90 32 read-only 0x00000000 0xffffffff ADC_GAIN_FACTOR ADC_GAIN_FACTOR ADC Gain Factor 0x94 32 read-only 0x00000000 0xffffffff ADC_OFFSET ADC_OFFSET ADC Offset 0x98 32 read-only 0x00000000 0xffffffff RESERVED11 RESERVED11 Reserved 0x9C 32 read-only 0x00000000 0xffffffff RESERVED12 RESERVED12 Reserved 0xA0 32 read-only 0x00000000 0xffffffff RESERVED13 RESERVED13 Reserved 0xA4 32 read-only 0x00000000 0xffffffff RESERVED14 RESERVED14 Reserved 0xA8 32 read-only 0x00000000 0xffffffff RESERVED15 RESERVED15 Reserved 0xAC 32 read-only 0x00000000 0xffffffff RESERVED16 RESERVED16 Reserved 0xB0 32 read-only 0x00000000 0xffffffff RESERVED17 RESERVED17 Reserved 0xB4 32 read-only 0x00000000 0xffffffff RESERVED18 RESERVED18 Reserved 0xB8 32 read-only 0x00000000 0xffffffff RESERVED19 RESERVED19 Reserved 0xBC 32 read-only 0x00000000 0xffffffff RESERVED20 RESERVED20 Reserved 0xC0 32 read-only 0x00000000 0xffffffff RESERVED21 RESERVED21 Reserved 0xC4 32 read-only 0x00000000 0xffffffff RESERVED22 RESERVED22 Reserved 0xC8 32 read-only 0x00000000 0xffffffff RESERVED23 RESERVED23 Reserved 0xCC 32 read-only 0x00000000 0xffffffff RESERVED24 RESERVED24 Reserved 0xD0 32 read-only 0x00000000 0xffffffff RESERVED25 RESERVED25 Reserved 0xD4 32 read-only 0x00000000 0xffffffff RESERVED26 RESERVED26 Reserved 0xD8 32 read-only 0x00000000 0xffffffff ADC14_REF1P2V_TS30C ADC14_REF1P2V_TS30C ADC14 1.2V Reference Temp. Sensor 30C 0xDC 32 read-only 0x00000000 0xffffffff ADC14_REF1P2V_TS85C ADC14_REF1P2V_TS85C ADC14 1.2V Reference Temp. Sensor 85C 0xE0 32 read-only 0x00000000 0xffffffff ADC14_REF1P45V_TS30C ADC14_REF1P45V_TS30C ADC14 1.45V Reference Temp. Sensor 30C 0xE4 32 read-only 0x00000000 0xffffffff ADC14_REF1P45V_TS85C ADC14_REF1P45V_TS85C ADC14 1.45V Reference Temp. Sensor 85C 0xE8 32 read-only 0x00000000 0xffffffff ADC14_REF2P5V_TS30C ADC14_REF2P5V_TS30C ADC14 2.5V Reference Temp. Sensor 30C 0xEC 32 read-only 0x00000000 0xffffffff ADC14_REF2P5V_TS85C ADC14_REF2P5V_TS85C ADC14 2.5V Reference Temp. Sensor 85C 0xF0 32 read-only 0x00000000 0xffffffff REF_CAL_TAG REF_CAL_TAG REF Calibration Tag 0xF4 32 read-only 0x00000008 0xffffffff REF_CAL_LEN REF_CAL_LEN REF Calibration Length 0xF8 32 read-only 0x00000000 0xffffffff REF_1P2V REF_1P2V REF 1.2V Reference 0xFC 32 read-only 0x00000000 0xffffffff REF_1P45V REF_1P45V REF 1.45V Reference 0x100 32 read-only 0x00000000 0xffffffff REF_2P5V REF_2P5V REF 2.5V Reference 0x104 32 read-only 0x00000000 0xffffffff FLASH_INFO_TAG FLASH_INFO_TAG Flash Info Tag 0x108 32 read-only 0x00000004 0xffffffff FLASH_INFO_LEN FLASH_INFO_LEN Flash Info Length 0x10C 32 read-only 0x00000000 0xffffffff FLASH_MAX_PROG_PULSES FLASH_MAX_PROG_PULSES Flash Maximum Programming Pulses 0x110 32 read-only 0x00000000 0xffffffff FLASH_MAX_ERASE_PULSES FLASH_MAX_ERASE_PULSES Flash Maximum Erase Pulses 0x114 32 read-only 0x00000000 0xffffffff RANDOM_NUM_TAG RANDOM_NUM_TAG 128-bit Random Number Tag 0x118 32 read-only 0x0000000d 0xffffffff RANDOM_NUM_LEN RANDOM_NUM_LEN 128-bit Random Number Length 0x11C 32 read-only 0x00000000 0xffffffff RANDOM_NUM_1 RANDOM_NUM_1 32-bit Random Number 1 0x120 32 read-only 0x00000000 0xffffffff RANDOM_NUM_2 RANDOM_NUM_2 32-bit Random Number 2 0x124 32 read-only 0x00000000 0xffffffff RANDOM_NUM_3 RANDOM_NUM_3 32-bit Random Number 3 0x128 32 read-only 0x00000000 0xffffffff RANDOM_NUM_4 RANDOM_NUM_4 32-bit Random Number 4 0x12C 32 read-only 0x00000000 0xffffffff BSL_CFG_TAG BSL_CFG_TAG BSL Configuration Tag 0x130 32 read-only 0x0000000f 0xffffffff BSL_CFG_LEN BSL_CFG_LEN BSL Configuration Length 0x134 32 read-only 0x00000000 0xffffffff BSL_PERIPHIF_SEL BSL_PERIPHIF_SEL BSL Peripheral Interface Selection 0x138 32 read-only 0x00000000 0xffffffff BSL_PORTIF_CFG_UART BSL_PORTIF_CFG_UART BSL Port Interface Configuration for UART 0x13C 32 read-only 0x00000000 0xffffffff BSL_PORTIF_CFG_SPI BSL_PORTIF_CFG_SPI BSL Port Interface Configuration for SPI 0x140 32 read-only 0x00000000 0xffffffff BSL_PORTIF_CFG_I2C BSL_PORTIF_CFG_I2C BSL Port Interface Configuration for I2C 0x144 32 read-only 0x00000000 0xffffffff TLV_END TLV_END TLV End Word 0x148 32 read-only 0x0bd0e11d 0xffffffff TIMER_A0 356.0 TIMER_A0 0x40000000 TA0_0_IRQ TA0_0 Interrupt 8 TA0_N_IRQ TA0_N Interrupt 9 0x0 0x30 registers TAxCTL CTL TimerAx Control Register 0x0 16 read-write 0x00000000 0x0000ffff TAIFG TimerA interrupt flag 0x0 0x1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TAIE TimerA interrupt enable 0x1 0x1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TACLR TimerA clear 0x2 0x1 read-write MC Mode control 0x4 0x2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 ID Input divider 0x6 0x2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 TASSEL TimerA clock source select 0x8 0x2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 5 2 0,1,2,3,4 TAxCCTL[%s] CCTL[%s] Timer_A Capture/Compare Control Register 0x2 16 read-write 0x00000000 0x0000fff7 CCIFG Capture/compare interrupt flag 0x0 0x1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 0x1 0x1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 0x2 0x1 read-write OUT_0 Output low 0 OUT_1 Output high 1 CCI Capture/compare input 0x3 0x1 read-only CCIE Capture/compare interrupt enable 0x4 0x1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 0x5 0x3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 0x8 0x1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 SCCI Synchronized capture/compare input 0xA 0x1 read-write SCS Synchronize capture source 0xB 0x1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 CCIS Capture/compare input select 0xC 0x2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 0xE 0x2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 TAxR R TimerA register 0x10 16 read-write 0x00000000 0x0000ffff 5 2 0,1,2,3,4 TAxCCR[%s] CCR[%s] Timer_A Capture/Compare Register 0x12 16 read-write 0x00000000 0x0000ffff TAxR TimerA register 0x0 0x10 read-write TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write 0x00000000 0x0000ffff TAIDEX Input divider expansion 0x0 0x3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff TAIV TimerA interrupt vector value 0x0 0x10 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG 8 TAIV_10 Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 14 TIMER_A1 356.0 TIMER_A1 0x40000400 TA1_0_IRQ TA1_0 Interrupt 10 TA1_N_IRQ TA1_N Interrupt 11 0x0 0x30 registers TAxCTL CTL TimerAx Control Register 0x0 16 read-write 0x00000000 0x0000ffff TAIFG TimerA interrupt flag 0x0 0x1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TAIE TimerA interrupt enable 0x1 0x1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TACLR TimerA clear 0x2 0x1 read-write MC Mode control 0x4 0x2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 ID Input divider 0x6 0x2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 TASSEL TimerA clock source select 0x8 0x2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 5 2 0,1,2,3,4 TAxCCTL[%s] CCTL[%s] Timer_A Capture/Compare Control Register 0x2 16 read-write 0x00000000 0x0000fff7 CCIFG Capture/compare interrupt flag 0x0 0x1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 0x1 0x1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 0x2 0x1 read-write OUT_0 Output low 0 OUT_1 Output high 1 CCI Capture/compare input 0x3 0x1 read-only CCIE Capture/compare interrupt enable 0x4 0x1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 0x5 0x3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 0x8 0x1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 SCCI Synchronized capture/compare input 0xA 0x1 read-write SCS Synchronize capture source 0xB 0x1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 CCIS Capture/compare input select 0xC 0x2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 0xE 0x2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 TAxR R TimerA register 0x10 16 read-write 0x00000000 0x0000ffff 5 2 0,1,2,3,4 TAxCCR[%s] CCR[%s] Timer_A Capture/Compare Register 0x12 16 read-write 0x00000000 0x0000ffff TAxR TimerA register 0x0 0x10 read-write TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write 0x00000000 0x0000ffff TAIDEX Input divider expansion 0x0 0x3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff TAIV TimerA interrupt vector value 0x0 0x10 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG 8 TAIV_10 Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 14 TIMER_A2 356.0 TIMER_A2 0x40000800 TA2_0_IRQ TA2_0 Interrupt 12 TA2_N_IRQ TA2_N Interrupt 13 0x0 0x30 registers TAxCTL CTL TimerAx Control Register 0x0 16 read-write 0x00000000 0x0000ffff TAIFG TimerA interrupt flag 0x0 0x1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TAIE TimerA interrupt enable 0x1 0x1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TACLR TimerA clear 0x2 0x1 read-write MC Mode control 0x4 0x2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 ID Input divider 0x6 0x2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 TASSEL TimerA clock source select 0x8 0x2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 5 2 0,1,2,3,4 TAxCCTL[%s] CCTL[%s] Timer_A Capture/Compare Control Register 0x2 16 read-write 0x00000000 0x0000fff7 CCIFG Capture/compare interrupt flag 0x0 0x1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 0x1 0x1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 0x2 0x1 read-write OUT_0 Output low 0 OUT_1 Output high 1 CCI Capture/compare input 0x3 0x1 read-only CCIE Capture/compare interrupt enable 0x4 0x1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 0x5 0x3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 0x8 0x1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 SCCI Synchronized capture/compare input 0xA 0x1 read-write SCS Synchronize capture source 0xB 0x1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 CCIS Capture/compare input select 0xC 0x2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 0xE 0x2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 TAxR R TimerA register 0x10 16 read-write 0x00000000 0x0000ffff 5 2 0,1,2,3,4 TAxCCR[%s] CCR[%s] Timer_A Capture/Compare Register 0x12 16 read-write 0x00000000 0x0000ffff TAxR TimerA register 0x0 0x10 read-write TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write 0x00000000 0x0000ffff TAIDEX Input divider expansion 0x0 0x3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff TAIV TimerA interrupt vector value 0x0 0x10 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG 8 TAIV_10 Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 14 TIMER_A3 356.0 TIMER_A3 0x40000C00 TA3_0_IRQ TA3_0 Interrupt 14 TA3_N_IRQ TA3_N Interrupt 15 0x0 0x30 registers TAxCTL CTL TimerAx Control Register 0x0 16 read-write 0x00000000 0x0000ffff TAIFG TimerA interrupt flag 0x0 0x1 read-write TAIFG_0 No interrupt pending 0 TAIFG_1 Interrupt pending 1 TAIE TimerA interrupt enable 0x1 0x1 read-write TAIE_0 Interrupt disabled 0 TAIE_1 Interrupt enabled 1 TACLR TimerA clear 0x2 0x1 read-write MC Mode control 0x4 0x2 read-write MC_0 Stop mode: Timer is halted 0 MC_1 Up mode: Timer counts up to TAxCCR0 1 MC_2 Continuous mode: Timer counts up to 0FFFFh 2 MC_3 Up/down mode: Timer counts up to TAxCCR0 then down to 0000h 3 ID Input divider 0x6 0x2 read-write ID_0 /1 0 ID_1 /2 1 ID_2 /4 2 ID_3 /8 3 TASSEL TimerA clock source select 0x8 0x2 read-write TASSEL_0 TAxCLK 0 TASSEL_1 ACLK 1 TASSEL_2 SMCLK 2 TASSEL_3 INCLK 3 5 2 0,1,2,3,4 TAxCCTL[%s] CCTL[%s] Timer_A Capture/Compare Control Register 0x2 16 read-write 0x00000000 0x0000fff7 CCIFG Capture/compare interrupt flag 0x0 0x1 read-write CCIFG_0 No interrupt pending 0 CCIFG_1 Interrupt pending 1 COV Capture overflow 0x1 0x1 read-write COV_0 No capture overflow occurred 0 COV_1 Capture overflow occurred 1 OUT Output 0x2 0x1 read-write OUT_0 Output low 0 OUT_1 Output high 1 CCI Capture/compare input 0x3 0x1 read-only CCIE Capture/compare interrupt enable 0x4 0x1 read-write CCIE_0 Interrupt disabled 0 CCIE_1 Interrupt enabled 1 OUTMOD Output mode 0x5 0x3 read-write OUTMOD_0 OUT bit value 0 OUTMOD_1 Set 1 OUTMOD_2 Toggle/reset 2 OUTMOD_3 Set/reset 3 OUTMOD_4 Toggle 4 OUTMOD_5 Reset 5 OUTMOD_6 Toggle/set 6 OUTMOD_7 Reset/set 7 CAP Capture mode 0x8 0x1 read-write CAP_0 Compare mode 0 CAP_1 Capture mode 1 SCCI Synchronized capture/compare input 0xA 0x1 read-write SCS Synchronize capture source 0xB 0x1 read-write SCS_0 Asynchronous capture 0 SCS_1 Synchronous capture 1 CCIS Capture/compare input select 0xC 0x2 read-write CCIS_0 CCIxA 0 CCIS_1 CCIxB 1 CCIS_2 GND 2 CCIS_3 VCC 3 CM Capture mode 0xE 0x2 read-write CM_0 No capture 0 CM_1 Capture on rising edge 1 CM_2 Capture on falling edge 2 CM_3 Capture on both rising and falling edges 3 TAxR R TimerA register 0x10 16 read-write 0x00000000 0x0000ffff 5 2 0,1,2,3,4 TAxCCR[%s] CCR[%s] Timer_A Capture/Compare Register 0x12 16 read-write 0x00000000 0x0000ffff TAxR TimerA register 0x0 0x10 read-write TAxEX0 EX0 TimerAx Expansion 0 Register 0x20 16 read-write 0x00000000 0x0000ffff TAIDEX Input divider expansion 0x0 0x3 read-write TAIDEX_0 Divide by 1 0 TAIDEX_1 Divide by 2 1 TAIDEX_2 Divide by 3 2 TAIDEX_3 Divide by 4 3 TAIDEX_4 Divide by 5 4 TAIDEX_5 Divide by 6 5 TAIDEX_6 Divide by 7 6 TAIDEX_7 Divide by 8 7 TAxIV IV TimerAx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff TAIV TimerA interrupt vector value 0x0 0x10 read-only TAIV_enum_read read TAIV_0 No interrupt pending 0 TAIV_2 Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 CCIFG; Interrupt Priority: Highest 2 TAIV_4 Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG 4 TAIV_6 Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG 6 TAIV_8 Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG 8 TAIV_10 Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG 10 TAIV_12 Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 12 TAIV_14 Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest 14 EUSCI_A0 356.0 EUSCI_A0 0x40001000 EUSCIA0_IRQ EUSCIA0 Interrupt 16 0x0 0x20 registers UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write 0x00000001 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCTXBRK Transmit break 0x1 0x1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCTXADDR Transmit address 0x2 0x1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCDORM Dormant 0x3 0x1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCBRKIE Receive break character interrupt enable 0x4 0x1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCRXEIE Receive erroneous-character interrupt enable 0x5 0x1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSSEL eUSCI_A clock source select 0x6 0x2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_A mode 0x9 0x2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCSPB Stop bit select 0xB 0x1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UC7BIT Character length 0xC 0x1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCMSB MSB first select 0xD 0x1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 0xE 0x1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 0xF 0x1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x000000ff UCBR Clock prescaler setting of the Baud rate generator 0x0 0x10 read-write UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write 0x00000000 0x0000ffff UCOS16 Oversampling mode enabled 0x0 0x1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCBRF First modulation stage select 0x4 0x4 read-write UCBRS Second modulation stage select 0x8 0x8 read-write UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write 0x00000000 0x0000ffff UCBUSY eUSCI_A busy 0x0 0x1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCADDR_UCIDLE Address received / Idle line detected 0x1 0x1 read-write UCRXERR Receive error flag 0x2 0x1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCBRK Break detect flag 0x3 0x1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 0x4 0x1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCOE Overrun error flag 0x5 0x1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 0x6 0x1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 0x7 0x1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write 0x00000000 0x0000ffff UCABDEN Automatic baud-rate detect enable 0x0 0x1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 0x2 0x1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCSTOE Synch field time out error 0x3 0x1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCDELIM Break/synch delimiter length 0x4 0x2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write 0x00000000 0x0000ffff UCIREN IrDA encoder/decoder enable 0x0 0x1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 0x2 0x6 read-write UCIRRXFE IrDA receive filter enabled 0x8 0x1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRRXFL Receive filter length 0xA 0x4 read-write UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write 0x00000000 0x0000ffff UCRXIE Receive interrupt enable 0x0 0x1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 0x1 0x1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 0x3 0x1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write 0x00000002 0x0000ffff UCRXIFG Receive interrupt flag 0x0 0x1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 0x1 0x1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 0x3 0x1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_A interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 8 EUSCI_A1 356.0 EUSCI_A1 0x40001400 EUSCIA1_IRQ EUSCIA1 Interrupt 17 0x0 0x20 registers UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write 0x00000001 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCTXBRK Transmit break 0x1 0x1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCTXADDR Transmit address 0x2 0x1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCDORM Dormant 0x3 0x1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCBRKIE Receive break character interrupt enable 0x4 0x1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCRXEIE Receive erroneous-character interrupt enable 0x5 0x1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSSEL eUSCI_A clock source select 0x6 0x2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_A mode 0x9 0x2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCSPB Stop bit select 0xB 0x1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UC7BIT Character length 0xC 0x1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCMSB MSB first select 0xD 0x1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 0xE 0x1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 0xF 0x1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x000000ff UCBR Clock prescaler setting of the Baud rate generator 0x0 0x10 read-write UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write 0x00000000 0x0000ffff UCOS16 Oversampling mode enabled 0x0 0x1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCBRF First modulation stage select 0x4 0x4 read-write UCBRS Second modulation stage select 0x8 0x8 read-write UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write 0x00000000 0x0000ffff UCBUSY eUSCI_A busy 0x0 0x1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCADDR_UCIDLE Address received / Idle line detected 0x1 0x1 read-write UCRXERR Receive error flag 0x2 0x1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCBRK Break detect flag 0x3 0x1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 0x4 0x1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCOE Overrun error flag 0x5 0x1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 0x6 0x1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 0x7 0x1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write 0x00000000 0x0000ffff UCABDEN Automatic baud-rate detect enable 0x0 0x1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 0x2 0x1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCSTOE Synch field time out error 0x3 0x1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCDELIM Break/synch delimiter length 0x4 0x2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write 0x00000000 0x0000ffff UCIREN IrDA encoder/decoder enable 0x0 0x1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 0x2 0x6 read-write UCIRRXFE IrDA receive filter enabled 0x8 0x1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRRXFL Receive filter length 0xA 0x4 read-write UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write 0x00000000 0x0000ffff UCRXIE Receive interrupt enable 0x0 0x1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 0x1 0x1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 0x3 0x1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write 0x00000002 0x0000ffff UCRXIFG Receive interrupt flag 0x0 0x1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 0x1 0x1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 0x3 0x1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_A interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 8 EUSCI_A2 356.0 EUSCI_A2 0x40001800 EUSCIA2_IRQ EUSCIA2 Interrupt 18 0x0 0x20 registers UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write 0x00000001 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCTXBRK Transmit break 0x1 0x1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCTXADDR Transmit address 0x2 0x1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCDORM Dormant 0x3 0x1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCBRKIE Receive break character interrupt enable 0x4 0x1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCRXEIE Receive erroneous-character interrupt enable 0x5 0x1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSSEL eUSCI_A clock source select 0x6 0x2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_A mode 0x9 0x2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCSPB Stop bit select 0xB 0x1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UC7BIT Character length 0xC 0x1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCMSB MSB first select 0xD 0x1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 0xE 0x1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 0xF 0x1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x000000ff UCBR Clock prescaler setting of the Baud rate generator 0x0 0x10 read-write UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write 0x00000000 0x0000ffff UCOS16 Oversampling mode enabled 0x0 0x1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCBRF First modulation stage select 0x4 0x4 read-write UCBRS Second modulation stage select 0x8 0x8 read-write UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write 0x00000000 0x0000ffff UCBUSY eUSCI_A busy 0x0 0x1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCADDR_UCIDLE Address received / Idle line detected 0x1 0x1 read-write UCRXERR Receive error flag 0x2 0x1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCBRK Break detect flag 0x3 0x1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 0x4 0x1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCOE Overrun error flag 0x5 0x1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 0x6 0x1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 0x7 0x1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write 0x00000000 0x0000ffff UCABDEN Automatic baud-rate detect enable 0x0 0x1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 0x2 0x1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCSTOE Synch field time out error 0x3 0x1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCDELIM Break/synch delimiter length 0x4 0x2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write 0x00000000 0x0000ffff UCIREN IrDA encoder/decoder enable 0x0 0x1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 0x2 0x6 read-write UCIRRXFE IrDA receive filter enabled 0x8 0x1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRRXFL Receive filter length 0xA 0x4 read-write UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write 0x00000000 0x0000ffff UCRXIE Receive interrupt enable 0x0 0x1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 0x1 0x1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 0x3 0x1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write 0x00000002 0x0000ffff UCRXIFG Receive interrupt flag 0x0 0x1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 0x1 0x1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 0x3 0x1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_A interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 8 EUSCI_A3 356.0 EUSCI_A3 0x40001C00 EUSCIA3_IRQ EUSCIA3 Interrupt 19 0x0 0x20 registers UCAxCTLW0 CTLW0 eUSCI_Ax Control Word Register 0 0x0 16 read-write 0x00000001 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_A reset released for operation 0 UCSWRST_1 Enabled. eUSCI_A logic held in reset state 1 UCTXBRK Transmit break 0x1 0x1 read-write UCTXBRK_0 Next frame transmitted is not a break 0 UCTXBRK_1 Next frame transmitted is a break or a break/synch 1 UCTXADDR Transmit address 0x2 0x1 read-write UCTXADDR_0 Next frame transmitted is data 0 UCTXADDR_1 Next frame transmitted is an address 1 UCDORM Dormant 0x3 0x1 read-write UCDORM_0 Not dormant. All received characters set UCRXIFG. 0 UCDORM_1 Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG. 1 UCBRKIE Receive break character interrupt enable 0x4 0x1 read-write UCBRKIE_0 Received break characters do not set UCRXIFG 0 UCBRKIE_1 Received break characters set UCRXIFG 1 UCRXEIE Receive erroneous-character interrupt enable 0x5 0x1 read-write UCRXEIE_0 Erroneous characters rejected and UCRXIFG is not set 0 UCRXEIE_1 Erroneous characters received set UCRXIFG 1 UCSSEL eUSCI_A clock source select 0x6 0x2 read-write UCSSEL_0 UCLK 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_A mode 0x9 0x2 read-write UCMODE_0 UART mode 0 UCMODE_1 Idle-line multiprocessor mode 1 UCMODE_2 Address-bit multiprocessor mode 2 UCMODE_3 UART mode with automatic baud-rate detection 3 UCSPB Stop bit select 0xB 0x1 read-write UCSPB_0 One stop bit 0 UCSPB_1 Two stop bits 1 UC7BIT Character length 0xC 0x1 read-write UC7BIT_0 8-bit data 0 UC7BIT_1 7-bit data 1 UCMSB MSB first select 0xD 0x1 read-write UCMSB_0 LSB first 0 UCMSB_1 MSB first 1 UCPAR Parity select 0xE 0x1 read-write UCPAR_0 Odd parity 0 UCPAR_1 Even parity 1 UCPEN Parity enable 0xF 0x1 read-write UCPEN_0 Parity disabled 0 UCPEN_1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. 1 UCAxCTLW1 CTLW1 eUSCI_Ax Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 Approximately 2 ns (equivalent of 1 delay element) 0 UCGLIT_1 Approximately 50 ns 1 UCGLIT_2 Approximately 100 ns 2 UCGLIT_3 Approximately 200 ns 3 UCAxBRW BRW eUSCI_Ax Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x000000ff UCBR Clock prescaler setting of the Baud rate generator 0x0 0x10 read-write UCAxMCTLW MCTLW eUSCI_Ax Modulation Control Word Register 0x8 16 read-write 0x00000000 0x0000ffff UCOS16 Oversampling mode enabled 0x0 0x1 read-write UCOS16_0 Disabled 0 UCOS16_1 Enabled 1 UCBRF First modulation stage select 0x4 0x4 read-write UCBRS Second modulation stage select 0x8 0x8 read-write UCAxSTATW STATW eUSCI_Ax Status Register 0xA 16 read-write 0x00000000 0x0000ffff UCBUSY eUSCI_A busy 0x0 0x1 read-only UCBUSY_enum_read read UCBUSY_0 eUSCI_A inactive 0 UCBUSY_1 eUSCI_A transmitting or receiving 1 UCADDR_UCIDLE Address received / Idle line detected 0x1 0x1 read-write UCRXERR Receive error flag 0x2 0x1 read-write UCRXERR_0 No receive errors detected 0 UCRXERR_1 Receive error detected 1 UCBRK Break detect flag 0x3 0x1 read-write UCBRK_0 No break condition 0 UCBRK_1 Break condition occurred 1 UCPE Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read. 0x4 0x1 read-write UCPE_0 No error 0 UCPE_1 Character received with parity error 1 UCOE Overrun error flag 0x5 0x1 read-write UCOE_0 No error 0 UCOE_1 Overrun error occurred 1 UCFE Framing error flag 0x6 0x1 read-write UCFE_0 No error 0 UCFE_1 Character received with low stop bit 1 UCLISTEN Listen enable 0x7 0x1 read-write UCLISTEN_0 Disabled 0 UCLISTEN_1 Enabled. UCAxTXD is internally fed back to the receiver 1 UCAxRXBUF RXBUF eUSCI_Ax Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCAxTXBUF TXBUF eUSCI_Ax Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCAxABCTL ABCTL eUSCI_Ax Auto Baud Rate Control Register 0x10 16 read-write 0x00000000 0x0000ffff UCABDEN Automatic baud-rate detect enable 0x0 0x1 read-write UCABDEN_0 Baud-rate detection disabled. Length of break and synch field is not measured. 0 UCABDEN_1 Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. 1 UCBTOE Break time out error 0x2 0x1 read-write UCBTOE_0 No error 0 UCBTOE_1 Length of break field exceeded 22 bit times 1 UCSTOE Synch field time out error 0x3 0x1 read-write UCSTOE_0 No error 0 UCSTOE_1 Length of synch field exceeded measurable time 1 UCDELIM Break/synch delimiter length 0x4 0x2 read-write UCDELIM_0 1 bit time 0 UCDELIM_1 2 bit times 1 UCDELIM_2 3 bit times 2 UCDELIM_3 4 bit times 3 UCAxIRCTL IRCTL eUSCI_Ax IrDA Control Word Register 0x12 16 read-write 0x00000000 0x0000ffff UCIREN IrDA encoder/decoder enable 0x0 0x1 read-write UCIREN_0 IrDA encoder/decoder disabled 0 UCIREN_1 IrDA encoder/decoder enabled 1 UCIRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write UCIRTXCLK_0 BRCLK 0 UCIRTXCLK_1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. 1 UCIRTXPL Transmit pulse length 0x2 0x6 read-write UCIRRXFE IrDA receive filter enabled 0x8 0x1 read-write UCIRRXFE_0 Receive filter disabled 0 UCIRRXFE_1 Receive filter enabled 1 UCIRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write UCIRRXPL_0 IrDA transceiver delivers a high pulse when a light pulse is seen 0 UCIRRXPL_1 IrDA transceiver delivers a low pulse when a light pulse is seen 1 UCIRRXFL Receive filter length 0xA 0x4 read-write UCAxIE IE eUSCI_Ax Interrupt Enable Register 0x1A 16 read-write 0x00000000 0x0000ffff UCRXIE Receive interrupt enable 0x0 0x1 read-write UCRXIE_0 Interrupt disabled 0 UCRXIE_1 Interrupt enabled 1 UCTXIE Transmit interrupt enable 0x1 0x1 read-write UCTXIE_0 Interrupt disabled 0 UCTXIE_1 Interrupt enabled 1 UCSTTIE Start bit interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCTXCPTIE Transmit complete interrupt enable 0x3 0x1 read-write UCTXCPTIE_0 Interrupt disabled 0 UCTXCPTIE_1 Interrupt enabled 1 UCAxIFG IFG eUSCI_Ax Interrupt Flag Register 0x1C 16 read-write 0x00000002 0x0000ffff UCRXIFG Receive interrupt flag 0x0 0x1 read-write UCRXIFG_0 No interrupt pending 0 UCRXIFG_1 Interrupt pending 1 UCTXIFG Transmit interrupt flag 0x1 0x1 read-write UCTXIFG_0 No interrupt pending 0 UCTXIFG_1 Interrupt pending 1 UCSTTIFG Start bit interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCTXCPTIFG Transmit ready interrupt enable 0x3 0x1 read-write UCTXCPTIFG_0 No interrupt pending 0 UCTXCPTIFG_1 Interrupt pending 1 UCAxIV IV eUSCI_Ax Interrupt Vector Register 0x1E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_A interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Receive buffer full; Interrupt Flag: UCRXIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG 4 UCIV_6 Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest 8 EUSCI_B0 356.0 EUSCI_B0 0x40002000 EUSCIB0_IRQ EUSCIB0 Interrupt 20 0x0 0x30 registers UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write 0x000001c1 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCTXSTT Transmit START condition in master mode 0x1 0x1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCTXSTP Transmit STOP condition in master mode 0x2 0x1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXNACK Transmit a NACK 0x3 0x1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTR Transmitter/receiver 0x4 0x1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 0x5 0x1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCSSEL eUSCI_B clock source select 0x6 0x2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_B mode 0x9 0x2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 0xB 0x1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCMM Multi-master environment select 0xD 0x1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCSLA10 Slave addressing mode select 0xE 0x1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCA10 Own addressing mode select 0xF 0x1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCASTP Automatic STOP condition generation 0x2 0x2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCSWACK SW or HW ACK control 0x4 0x1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCSTPNACK ACK all master bytes 0x5 0x1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCCLTO Clock low timeout select 0x6 0x2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 0x8 0x1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x0000ffff UCBR Bit clock prescaler 0x0 0x10 read-write UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write 0x00000000 0x0000ffff UCBBUSY Bus busy 0x4 0x1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCGC General call address received 0x5 0x1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 0x6 0x1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBCNT Hardware byte counter value 0x8 0x8 read-only UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write 0x00000000 0x0000ffff UCTBCNT Byte counter threshold value 0x0 0x8 read-write UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write 0x00000000 0x0000ffff I2COA0 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCGCEN General call response enable 0xF 0x1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write 0x00000000 0x0000ffff I2COA1 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write 0x00000000 0x0000ffff I2COA2 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write 0x00000000 0x0000ffff I2COA3 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only 0x00000000 0x0000ffff ADDRX Received Address Register 0x0 0xA read-only UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write 0x000003ff 0x0000ffff ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0x0 0xA read-write UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write 0x00000000 0x0000ffff I2CSA I2C slave address 0x0 0xA read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write 0x00000000 0x0000ffff UCRXIE0 Receive interrupt enable 0 0x0 0x1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 0x1 0x1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 0x3 0x1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCALIE Arbitration lost interrupt enable 0x4 0x1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 0x5 0x1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 0x6 0x1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 0x7 0x1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 0x8 0x1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 0x9 0x1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 0xA 0x1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 0xB 0x1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 0xC 0x1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 0xD 0x1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 0xE 0x1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write 0x00000002 0x0000ffff UCRXIFG0 eUSCI_B receive interrupt flag 0 0x0 0x1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 0x1 0x1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 0x3 0x1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCALIFG Arbitration lost interrupt flag 0x4 0x1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 0x5 0x1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 0x6 0x1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 0x7 0x1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 0x8 0x1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 0x9 0x1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 0xA 0x1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 0xB 0x1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 0xC 0x1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 0xD 0x1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 0xE 0x1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_B interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG 8 UCIV_10 Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 18 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 30 EUSCI_B1 356.0 EUSCI_B1 0x40002400 EUSCIB1_IRQ EUSCIB1 Interrupt 21 0x0 0x30 registers UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write 0x000001c1 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCTXSTT Transmit START condition in master mode 0x1 0x1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCTXSTP Transmit STOP condition in master mode 0x2 0x1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXNACK Transmit a NACK 0x3 0x1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTR Transmitter/receiver 0x4 0x1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 0x5 0x1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCSSEL eUSCI_B clock source select 0x6 0x2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_B mode 0x9 0x2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 0xB 0x1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCMM Multi-master environment select 0xD 0x1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCSLA10 Slave addressing mode select 0xE 0x1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCA10 Own addressing mode select 0xF 0x1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCASTP Automatic STOP condition generation 0x2 0x2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCSWACK SW or HW ACK control 0x4 0x1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCSTPNACK ACK all master bytes 0x5 0x1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCCLTO Clock low timeout select 0x6 0x2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 0x8 0x1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x0000ffff UCBR Bit clock prescaler 0x0 0x10 read-write UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write 0x00000000 0x0000ffff UCBBUSY Bus busy 0x4 0x1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCGC General call address received 0x5 0x1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 0x6 0x1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBCNT Hardware byte counter value 0x8 0x8 read-only UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write 0x00000000 0x0000ffff UCTBCNT Byte counter threshold value 0x0 0x8 read-write UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write 0x00000000 0x0000ffff I2COA0 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCGCEN General call response enable 0xF 0x1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write 0x00000000 0x0000ffff I2COA1 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write 0x00000000 0x0000ffff I2COA2 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write 0x00000000 0x0000ffff I2COA3 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only 0x00000000 0x0000ffff ADDRX Received Address Register 0x0 0xA read-only UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write 0x000003ff 0x0000ffff ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0x0 0xA read-write UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write 0x00000000 0x0000ffff I2CSA I2C slave address 0x0 0xA read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write 0x00000000 0x0000ffff UCRXIE0 Receive interrupt enable 0 0x0 0x1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 0x1 0x1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 0x3 0x1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCALIE Arbitration lost interrupt enable 0x4 0x1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 0x5 0x1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 0x6 0x1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 0x7 0x1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 0x8 0x1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 0x9 0x1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 0xA 0x1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 0xB 0x1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 0xC 0x1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 0xD 0x1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 0xE 0x1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write 0x00000002 0x0000ffff UCRXIFG0 eUSCI_B receive interrupt flag 0 0x0 0x1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 0x1 0x1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 0x3 0x1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCALIFG Arbitration lost interrupt flag 0x4 0x1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 0x5 0x1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 0x6 0x1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 0x7 0x1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 0x8 0x1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 0x9 0x1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 0xA 0x1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 0xB 0x1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 0xC 0x1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 0xD 0x1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 0xE 0x1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_B interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG 8 UCIV_10 Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 18 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 30 EUSCI_B2 356.0 EUSCI_B2 0x40002800 EUSCIB2_IRQ EUSCIB2 Interrupt 22 0x0 0x30 registers UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write 0x000001c1 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCTXSTT Transmit START condition in master mode 0x1 0x1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCTXSTP Transmit STOP condition in master mode 0x2 0x1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXNACK Transmit a NACK 0x3 0x1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTR Transmitter/receiver 0x4 0x1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 0x5 0x1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCSSEL eUSCI_B clock source select 0x6 0x2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_B mode 0x9 0x2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 0xB 0x1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCMM Multi-master environment select 0xD 0x1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCSLA10 Slave addressing mode select 0xE 0x1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCA10 Own addressing mode select 0xF 0x1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCASTP Automatic STOP condition generation 0x2 0x2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCSWACK SW or HW ACK control 0x4 0x1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCSTPNACK ACK all master bytes 0x5 0x1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCCLTO Clock low timeout select 0x6 0x2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 0x8 0x1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x0000ffff UCBR Bit clock prescaler 0x0 0x10 read-write UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write 0x00000000 0x0000ffff UCBBUSY Bus busy 0x4 0x1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCGC General call address received 0x5 0x1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 0x6 0x1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBCNT Hardware byte counter value 0x8 0x8 read-only UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write 0x00000000 0x0000ffff UCTBCNT Byte counter threshold value 0x0 0x8 read-write UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write 0x00000000 0x0000ffff I2COA0 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCGCEN General call response enable 0xF 0x1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write 0x00000000 0x0000ffff I2COA1 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write 0x00000000 0x0000ffff I2COA2 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write 0x00000000 0x0000ffff I2COA3 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only 0x00000000 0x0000ffff ADDRX Received Address Register 0x0 0xA read-only UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write 0x000003ff 0x0000ffff ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0x0 0xA read-write UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write 0x00000000 0x0000ffff I2CSA I2C slave address 0x0 0xA read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write 0x00000000 0x0000ffff UCRXIE0 Receive interrupt enable 0 0x0 0x1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 0x1 0x1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 0x3 0x1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCALIE Arbitration lost interrupt enable 0x4 0x1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 0x5 0x1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 0x6 0x1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 0x7 0x1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 0x8 0x1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 0x9 0x1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 0xA 0x1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 0xB 0x1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 0xC 0x1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 0xD 0x1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 0xE 0x1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write 0x00000002 0x0000ffff UCRXIFG0 eUSCI_B receive interrupt flag 0 0x0 0x1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 0x1 0x1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 0x3 0x1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCALIFG Arbitration lost interrupt flag 0x4 0x1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 0x5 0x1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 0x6 0x1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 0x7 0x1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 0x8 0x1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 0x9 0x1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 0xA 0x1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 0xB 0x1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 0xC 0x1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 0xD 0x1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 0xE 0x1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_B interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG 8 UCIV_10 Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 18 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 30 EUSCI_B3 356.0 EUSCI_B3 0x40002C00 EUSCIB3_IRQ EUSCIB3 Interrupt 23 0x0 0x30 registers UCBxCTLW0 CTLW0 eUSCI_Bx Control Word Register 0 0x0 16 read-write 0x000001c1 0x0000ffff UCSWRST Software reset enable 0x0 0x1 read-write UCSWRST_0 Disabled. eUSCI_B reset released for operation 0 UCSWRST_1 Enabled. eUSCI_B logic held in reset state 1 UCTXSTT Transmit START condition in master mode 0x1 0x1 read-write UCTXSTT_0 Do not generate START condition 0 UCTXSTT_1 Generate START condition 1 UCTXSTP Transmit STOP condition in master mode 0x2 0x1 read-write UCTXSTP_0 No STOP generated 0 UCTXSTP_1 Generate STOP 1 UCTXNACK Transmit a NACK 0x3 0x1 read-write UCTXNACK_0 Acknowledge normally 0 UCTXNACK_1 Generate NACK 1 UCTR Transmitter/receiver 0x4 0x1 read-write UCTR_0 Receiver 0 UCTR_1 Transmitter 1 UCTXACK Transmit ACK condition in slave mode 0x5 0x1 read-write UCTXACK_0 Do not acknowledge the slave address 0 UCTXACK_1 Acknowledge the slave address 1 UCSSEL eUSCI_B clock source select 0x6 0x2 read-write UCSSEL_0 UCLKI 0 UCSSEL_1 ACLK 1 UCSSEL_2 SMCLK 2 UCSSEL_3 SMCLK 3 UCSYNC Synchronous mode enable 0x8 0x1 read-write UCSYNC_0 Asynchronous mode 0 UCSYNC_1 Synchronous mode 1 UCMODE eUSCI_B mode 0x9 0x2 read-write UCMODE_0 3-pin SPI 0 UCMODE_1 4-pin SPI (master or slave enabled if STE = 1) 1 UCMODE_2 4-pin SPI (master or slave enabled if STE = 0) 2 UCMODE_3 I2C mode 3 UCMST Master mode select 0xB 0x1 read-write UCMST_0 Slave mode 0 UCMST_1 Master mode 1 UCMM Multi-master environment select 0xD 0x1 read-write UCMM_0 Single master environment. There is no other master in the system. The address compare unit is disabled. 0 UCMM_1 Multi-master environment 1 UCSLA10 Slave addressing mode select 0xE 0x1 read-write UCSLA10_0 Address slave with 7-bit address 0 UCSLA10_1 Address slave with 10-bit address 1 UCA10 Own addressing mode select 0xF 0x1 read-write UCA10_0 Own address is a 7-bit address 0 UCA10_1 Own address is a 10-bit address 1 UCBxCTLW1 CTLW1 eUSCI_Bx Control Word Register 1 0x2 16 read-write 0x00000003 0x0000ffff UCGLIT Deglitch time 0x0 0x2 read-write UCGLIT_0 50 ns 0 UCGLIT_1 25 ns 1 UCGLIT_2 12.5 ns 2 UCGLIT_3 6.25 ns 3 UCASTP Automatic STOP condition generation 0x2 0x2 read-write UCASTP_0 No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. 0 UCASTP_1 UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT 1 UCASTP_2 A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold 2 UCSWACK SW or HW ACK control 0x4 0x1 read-write UCSWACK_0 The address acknowledge of the slave is controlled by the eUSCI_B module 0 UCSWACK_1 The user needs to trigger the sending of the address ACK by issuing UCTXACK 1 UCSTPNACK ACK all master bytes 0x5 0x1 read-write UCSTPNACK_0 Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard) 0 UCSTPNACK_1 All bytes are acknowledged by the eUSCI_B when configured as master receiver 1 UCCLTO Clock low timeout select 0x6 0x2 read-write UCCLTO_0 Disable clock low timeout counter 0 UCCLTO_1 135 000 SYSCLK cycles (approximately 28 ms) 1 UCCLTO_2 150 000 SYSCLK cycles (approximately 31 ms) 2 UCCLTO_3 165 000 SYSCLK cycles (approximately 34 ms) 3 UCETXINT Early UCTXIFG0 0x8 0x1 read-write UCETXINT_0 UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit 0 UCETXINT_1 UCTXIFG0 is set for each START condition 1 UCBxBRW BRW eUSCI_Bx Baud Rate Control Word Register 0x6 16 read-write 0x00000000 0x0000ffff UCBR Bit clock prescaler 0x0 0x10 read-write UCBxSTATW STATW eUSCI_Bx Status Register 0x8 16 read-write 0x00000000 0x0000ffff UCBBUSY Bus busy 0x4 0x1 read-only UCBBUSY_enum_read read UCBBUSY_0 Bus inactive 0 UCBBUSY_1 Bus busy 1 UCGC General call address received 0x5 0x1 read-only UCGC_enum_read read UCGC_0 No general call address received 0 UCGC_1 General call address received 1 UCSCLLOW SCL low 0x6 0x1 read-only UCSCLLOW_enum_read read UCSCLLOW_0 SCL is not held low 0 UCSCLLOW_1 SCL is held low 1 UCBCNT Hardware byte counter value 0x8 0x8 read-only UCBxTBCNT TBCNT eUSCI_Bx Byte Counter Threshold Register 0xA 16 read-write 0x00000000 0x0000ffff UCTBCNT Byte counter threshold value 0x0 0x8 read-write UCBxRXBUF RXBUF eUSCI_Bx Receive Buffer Register 0xC 16 read-only 0x00000000 0x0000ffff UCRXBUF Receive data buffer 0x0 0x8 read-only UCBxTXBUF TXBUF eUSCI_Bx Transmit Buffer Register 0xE 16 read-write 0x00000000 0x0000ffff UCTXBUF Transmit data buffer 0x0 0x8 read-write UCBxI2COA0 I2COA0 eUSCI_Bx I2C Own Address 0 Register 0x14 16 read-write 0x00000000 0x0000ffff I2COA0 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA0 is disabled 0 UCOAEN_1 The slave address defined in I2COA0 is enabled 1 UCGCEN General call response enable 0xF 0x1 read-write UCGCEN_0 Do not respond to a general call 0 UCGCEN_1 Respond to a general call 1 UCBxI2COA1 I2COA1 eUSCI_Bx I2C Own Address 1 Register 0x16 16 read-write 0x00000000 0x0000ffff I2COA1 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA1 is disabled 0 UCOAEN_1 The slave address defined in I2COA1 is enabled 1 UCBxI2COA2 I2COA2 eUSCI_Bx I2C Own Address 2 Register 0x18 16 read-write 0x00000000 0x0000ffff I2COA2 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA2 is disabled 0 UCOAEN_1 The slave address defined in I2COA2 is enabled 1 UCBxI2COA3 I2COA3 eUSCI_Bx I2C Own Address 3 Register 0x1A 16 read-write 0x00000000 0x0000ffff I2COA3 I2C own address 0x0 0xA read-write UCOAEN Own Address enable register 0xA 0x1 read-write UCOAEN_0 The slave address defined in I2COA3 is disabled 0 UCOAEN_1 The slave address defined in I2COA3 is enabled 1 UCBxADDRX ADDRX eUSCI_Bx I2C Received Address Register 0x1C 16 read-only 0x00000000 0x0000ffff ADDRX Received Address Register 0x0 0xA read-only UCBxADDMASK ADDMASK eUSCI_Bx I2C Address Mask Register 0x1E 16 read-write 0x000003ff 0x0000ffff ADDMASK Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1. 0x0 0xA read-write UCBxI2CSA I2CSA eUSCI_Bx I2C Slave Address Register 0x20 16 read-write 0x00000000 0x0000ffff I2CSA I2C slave address 0x0 0xA read-write UCBxIE IE eUSCI_Bx Interrupt Enable Register 0x2A 16 read-write 0x00000000 0x0000ffff UCRXIE0 Receive interrupt enable 0 0x0 0x1 read-write UCRXIE0_0 Interrupt disabled 0 UCRXIE0_1 Interrupt enabled 1 UCTXIE0 Transmit interrupt enable 0 0x1 0x1 read-write UCTXIE0_0 Interrupt disabled 0 UCTXIE0_1 Interrupt enabled 1 UCSTTIE START condition interrupt enable 0x2 0x1 read-write UCSTTIE_0 Interrupt disabled 0 UCSTTIE_1 Interrupt enabled 1 UCSTPIE STOP condition interrupt enable 0x3 0x1 read-write UCSTPIE_0 Interrupt disabled 0 UCSTPIE_1 Interrupt enabled 1 UCALIE Arbitration lost interrupt enable 0x4 0x1 read-write UCALIE_0 Interrupt disabled 0 UCALIE_1 Interrupt enabled 1 UCNACKIE Not-acknowledge interrupt enable 0x5 0x1 read-write UCNACKIE_0 Interrupt disabled 0 UCNACKIE_1 Interrupt enabled 1 UCBCNTIE Byte counter interrupt enable 0x6 0x1 read-write UCBCNTIE_0 Interrupt disabled 0 UCBCNTIE_1 Interrupt enabled 1 UCCLTOIE Clock low timeout interrupt enable 0x7 0x1 read-write UCCLTOIE_0 Interrupt disabled 0 UCCLTOIE_1 Interrupt enabled 1 UCRXIE1 Receive interrupt enable 1 0x8 0x1 read-write UCRXIE1_0 Interrupt disabled 0 UCRXIE1_1 Interrupt enabled 1 UCTXIE1 Transmit interrupt enable 1 0x9 0x1 read-write UCTXIE1_0 Interrupt disabled 0 UCTXIE1_1 Interrupt enabled 1 UCRXIE2 Receive interrupt enable 2 0xA 0x1 read-write UCRXIE2_0 Interrupt disabled 0 UCRXIE2_1 Interrupt enabled 1 UCTXIE2 Transmit interrupt enable 2 0xB 0x1 read-write UCTXIE2_0 Interrupt disabled 0 UCTXIE2_1 Interrupt enabled 1 UCRXIE3 Receive interrupt enable 3 0xC 0x1 read-write UCRXIE3_0 Interrupt disabled 0 UCRXIE3_1 Interrupt enabled 1 UCTXIE3 Transmit interrupt enable 3 0xD 0x1 read-write UCTXIE3_0 Interrupt disabled 0 UCTXIE3_1 Interrupt enabled 1 UCBIT9IE Bit position 9 interrupt enable 0xE 0x1 read-write UCBIT9IE_0 Interrupt disabled 0 UCBIT9IE_1 Interrupt enabled 1 UCBxIFG IFG eUSCI_Bx Interrupt Flag Register 0x2C 16 read-write 0x00000002 0x0000ffff UCRXIFG0 eUSCI_B receive interrupt flag 0 0x0 0x1 read-write UCRXIFG0_0 No interrupt pending 0 UCRXIFG0_1 Interrupt pending 1 UCTXIFG0 eUSCI_B transmit interrupt flag 0 0x1 0x1 read-write UCTXIFG0_0 No interrupt pending 0 UCTXIFG0_1 Interrupt pending 1 UCSTTIFG START condition interrupt flag 0x2 0x1 read-write UCSTTIFG_0 No interrupt pending 0 UCSTTIFG_1 Interrupt pending 1 UCSTPIFG STOP condition interrupt flag 0x3 0x1 read-write UCSTPIFG_0 No interrupt pending 0 UCSTPIFG_1 Interrupt pending 1 UCALIFG Arbitration lost interrupt flag 0x4 0x1 read-write UCALIFG_0 No interrupt pending 0 UCALIFG_1 Interrupt pending 1 UCNACKIFG Not-acknowledge received interrupt flag 0x5 0x1 read-write UCNACKIFG_0 No interrupt pending 0 UCNACKIFG_1 Interrupt pending 1 UCBCNTIFG Byte counter interrupt flag 0x6 0x1 read-write UCBCNTIFG_0 No interrupt pending 0 UCBCNTIFG_1 Interrupt pending 1 UCCLTOIFG Clock low timeout interrupt flag 0x7 0x1 read-write UCCLTOIFG_0 No interrupt pending 0 UCCLTOIFG_1 Interrupt pending 1 UCRXIFG1 eUSCI_B receive interrupt flag 1 0x8 0x1 read-write UCRXIFG1_0 No interrupt pending 0 UCRXIFG1_1 Interrupt pending 1 UCTXIFG1 eUSCI_B transmit interrupt flag 1 0x9 0x1 read-write UCTXIFG1_0 No interrupt pending 0 UCTXIFG1_1 Interrupt pending 1 UCRXIFG2 eUSCI_B receive interrupt flag 2 0xA 0x1 read-write UCRXIFG2_0 No interrupt pending 0 UCRXIFG2_1 Interrupt pending 1 UCTXIFG2 eUSCI_B transmit interrupt flag 2 0xB 0x1 read-write UCTXIFG2_0 No interrupt pending 0 UCTXIFG2_1 Interrupt pending 1 UCRXIFG3 eUSCI_B receive interrupt flag 3 0xC 0x1 read-write UCRXIFG3_0 No interrupt pending 0 UCRXIFG3_1 Interrupt pending 1 UCTXIFG3 eUSCI_B transmit interrupt flag 3 0xD 0x1 read-write UCTXIFG3_0 No interrupt pending 0 UCTXIFG3_1 Interrupt pending 1 UCBIT9IFG Bit position 9 interrupt flag 0xE 0x1 read-write UCBIT9IFG_0 No interrupt pending 0 UCBIT9IFG_1 Interrupt pending 1 UCBxIV IV eUSCI_Bx Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff UCIV eUSCI_B interrupt vector value 0x0 0x10 read-only UCIV_enum_read read UCIV_0 No interrupt pending 0 UCIV_2 Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest 2 UCIV_4 Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG 4 UCIV_6 Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 6 UCIV_8 Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG 8 UCIV_10 Interrupt Source: Slave 3 Data received; Interrupt Flag: UCRXIFG3 10 UCIV_12 Interrupt Source: Slave 3 Transmit buffer empty; Interrupt Flag: UCTXIFG3 12 UCIV_14 Interrupt Source: Slave 2 Data received; Interrupt Flag: UCRXIFG2 14 UCIV_16 Interrupt Source: Slave 2 Transmit buffer empty; Interrupt Flag: UCTXIFG2 16 UCIV_18 Interrupt Source: Slave 1 Data received; Interrupt Flag: UCRXIFG1 18 UCIV_20 Interrupt Source: Slave 1 Transmit buffer empty; Interrupt Flag: UCTXIFG1 20 UCIV_22 Interrupt Source: Data received; Interrupt Flag: UCRXIFG0 22 UCIV_24 Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG0 24 UCIV_26 Interrupt Source: Byte counter zero; Interrupt Flag: UCBCNTIFG 26 UCIV_28 Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 28 UCIV_30 Interrupt Source: Nineth bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest 30 REF_A 356.0 REF_A 0x40003000 0x0 0xC registers REFCTL0 CTL0 REF Control Register 0 0x0 16 read-write REFON Reference enable 0x0 0x1 read-write REFON_0 Disables reference if no other reference requests are pending 0 REFON_1 Enables reference in static mode 1 REFOUT Reference output buffer 0x1 0x1 read-write REFOUT_0 Reference output not available externally 0 REFOUT_1 Reference output available externally. If ADC14REFBURST = 0, output is available continuously. If ADC14REFBURST = 1, output is available only during an ADC14 conversion. 1 REFTCOFF Temperature sensor disabled 0x3 0x1 read-write REFTCOFF_0 Temperature sensor enabled 0 REFTCOFF_1 Temperature sensor disabled to save power 1 REFVSEL Reference voltage level select 0x4 0x2 read-write REFVSEL_0 1.2 V available when reference requested or REFON = 1 0 REFVSEL_1 1.45 V available when reference requested or REFON = 1 1 REFVSEL_3 2.5 V available when reference requested or REFON = 1 3 REFGENOT Reference generator one-time trigger 0x6 0x1 read-write REFGENOT_0 No trigger 0 REFGENOT_1 Generation of the reference voltage is started by writing 1 or by a hardware trigger 1 REFBGOT Bandgap and bandgap buffer one-time trigger 0x7 0x1 read-write REFBGOT_0 No trigger 0 REFBGOT_1 Generation of the bandgap voltage is started by writing 1 or by a hardware trigger 1 REFGENACT Reference generator active 0x8 0x1 read-only REFGENACT_enum_read read REFGENACT_0 Reference generator not active 0 REFGENACT_1 Reference generator active 1 REFBGACT Reference bandgap active 0x9 0x1 read-only REFBGACT_enum_read read REFBGACT_0 Reference bandgap buffer not active 0 REFBGACT_1 Reference bandgap buffer active 1 REFGENBUSY Reference generator busy 0xA 0x1 read-only REFGENBUSY_enum_read read REFGENBUSY_0 Reference generator not busy 0 REFGENBUSY_1 Reference generator busy 1 BGMODE Bandgap mode 0xB 0x1 read-only BGMODE_enum_read read BGMODE_0 Static mode 0 BGMODE_1 Sampled mode 1 REFGENRDY Variable reference voltage ready status 0xC 0x1 read-only REFGENRDY_enum_read read REFGENRDY_0 Reference voltage output is not ready to be used 0 REFGENRDY_1 Reference voltage output is ready to be used 1 REFBGRDY Buffered bandgap voltage ready status 0xD 0x1 read-only REFBGRDY_enum_read read REFBGRDY_0 Buffered bandgap voltage is not ready to be used 0 REFBGRDY_1 Buffered bandgap voltage is ready to be used 1 COMP_E0 356.0 COMP_E0 0x40003400 COMP_E0_IRQ COMP_E0 Interrupt 6 0x0 0x10 registers CExCTL0 CTL0 Comparator Control Register 0 0x0 16 read-write 0x00000000 0x0000ffff CEIPSEL Channel input selected for the V+ terminal 0x0 0x4 read-write CEIPSEL_0 Channel 0 selected 0 CEIPSEL_1 Channel 1 selected 1 CEIPSEL_2 Channel 2 selected 2 CEIPSEL_3 Channel 3 selected 3 CEIPSEL_4 Channel 4 selected 4 CEIPSEL_5 Channel 5 selected 5 CEIPSEL_6 Channel 6 selected 6 CEIPSEL_7 Channel 7 selected 7 CEIPSEL_8 Channel 8 selected 8 CEIPSEL_9 Channel 9 selected 9 CEIPSEL_10 Channel 10 selected 10 CEIPSEL_11 Channel 11 selected 11 CEIPSEL_12 Channel 12 selected 12 CEIPSEL_13 Channel 13 selected 13 CEIPSEL_14 Channel 14 selected 14 CEIPSEL_15 Channel 15 selected 15 CEIPEN Channel input enable for the V+ terminal 0x7 0x1 read-write CEIPEN_0 Selected analog input channel for V+ terminal is disabled 0 CEIPEN_1 Selected analog input channel for V+ terminal is enabled 1 CEIMSEL Channel input selected for the - terminal 0x8 0x4 read-write CEIMSEL_0 Channel 0 selected 0 CEIMSEL_1 Channel 1 selected 1 CEIMSEL_2 Channel 2 selected 2 CEIMSEL_3 Channel 3 selected 3 CEIMSEL_4 Channel 4 selected 4 CEIMSEL_5 Channel 5 selected 5 CEIMSEL_6 Channel 6 selected 6 CEIMSEL_7 Channel 7 selected 7 CEIMSEL_8 Channel 8 selected 8 CEIMSEL_9 Channel 9 selected 9 CEIMSEL_10 Channel 10 selected 10 CEIMSEL_11 Channel 11 selected 11 CEIMSEL_12 Channel 12 selected 12 CEIMSEL_13 Channel 13 selected 13 CEIMSEL_14 Channel 14 selected 14 CEIMSEL_15 Channel 15 selected 15 CEIMEN Channel input enable for the - terminal 0xF 0x1 read-write CEIMEN_0 Selected analog input channel for V- terminal is disabled 0 CEIMEN_1 Selected analog input channel for V- terminal is enabled 1 CExCTL1 CTL1 Comparator Control Register 1 0x2 16 read-write 0x00000000 0x0000ffff CEOUT Comparator output value 0x0 0x1 read-write CEOUTPOL Comparator output polarity 0x1 0x1 read-write CEOUTPOL_0 Noninverted 0 CEOUTPOL_1 Inverted 1 CEF Comparator output filter 0x2 0x1 read-write CEF_0 Comparator output is not filtered 0 CEF_1 Comparator output is filtered 1 CEIES Interrupt edge select for CEIIFG and CEIFG 0x3 0x1 read-write CEIES_0 Rising edge for CEIFG, falling edge for CEIIFG 0 CEIES_1 Falling edge for CEIFG, rising edge for CEIIFG 1 CESHORT Input short 0x4 0x1 read-write CESHORT_0 Inputs not shorted 0 CESHORT_1 Inputs shorted 1 CEEX Exchange 0x5 0x1 read-write CEFDLY Filter delay 0x6 0x2 read-write CEFDLY_0 Typical filter delay of TBD (450) ns 0 CEFDLY_1 Typical filter delay of TBD (900) ns 1 CEFDLY_2 Typical filter delay of TBD (1800) ns 2 CEFDLY_3 Typical filter delay of TBD (3600) ns 3 CEPWRMD Power Mode 0x8 0x2 read-write CEPWRMD_0 High-speed mode 0 CEPWRMD_1 Normal mode 1 CEPWRMD_2 Ultra-low power mode 2 CEON Comparator On 0xA 0x1 read-write CEON_0 Off 0 CEON_1 On 1 CEMRVL This bit is valid of CEMRVS is set to 1 0xB 0x1 read-write CEMRVL_0 VREF0 is selected if CERS = 00, 01, or 10 0 CEMRVL_1 VREF1 is selected if CERS = 00, 01, or 10 1 CEMRVS This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10. 0xC 0x1 read-write CEMRVS_0 Comparator output state selects between VREF0 or VREF1 0 CEMRVS_1 CEMRVL selects between VREF0 or VREF1 1 CExCTL2 CTL2 Comparator Control Register 2 0x4 16 read-write 0x00000000 0x0000ffff CEREF0 Reference resistor tap 0 0x0 0x5 read-write CEREF0_0 Reference resistor tap for setting 0. 0 CEREF0_1 Reference resistor tap for setting 1. 1 CEREF0_2 Reference resistor tap for setting 2. 2 CEREF0_3 Reference resistor tap for setting 3. 3 CEREF0_4 Reference resistor tap for setting 4. 4 CEREF0_5 Reference resistor tap for setting 5. 5 CEREF0_6 Reference resistor tap for setting 6. 6 CEREF0_7 Reference resistor tap for setting 7. 7 CEREF0_8 Reference resistor tap for setting 8. 8 CEREF0_9 Reference resistor tap for setting 9. 9 CEREF0_10 Reference resistor tap for setting 10. 10 CEREF0_11 Reference resistor tap for setting 11. 11 CEREF0_12 Reference resistor tap for setting 12. 12 CEREF0_13 Reference resistor tap for setting 13. 13 CEREF0_14 Reference resistor tap for setting 14. 14 CEREF0_15 Reference resistor tap for setting 15. 15 CEREF0_16 Reference resistor tap for setting 16. 16 CEREF0_17 Reference resistor tap for setting 17. 17 CEREF0_18 Reference resistor tap for setting 18. 18 CEREF0_19 Reference resistor tap for setting 19. 19 CEREF0_20 Reference resistor tap for setting 20. 20 CEREF0_21 Reference resistor tap for setting 21. 21 CEREF0_22 Reference resistor tap for setting 22. 22 CEREF0_23 Reference resistor tap for setting 23. 23 CEREF0_24 Reference resistor tap for setting 24. 24 CEREF0_25 Reference resistor tap for setting 25. 25 CEREF0_26 Reference resistor tap for setting 26. 26 CEREF0_27 Reference resistor tap for setting 27. 27 CEREF0_28 Reference resistor tap for setting 28. 28 CEREF0_29 Reference resistor tap for setting 29. 29 CEREF0_30 Reference resistor tap for setting 30. 30 CEREF0_31 Reference resistor tap for setting 31. 31 CERSEL Reference select 0x5 0x1 read-write CERSEL_0 When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal 0 CERSEL_1 When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal 1 CERS Reference source 0x6 0x2 read-write CERS_0 No current is drawn by the reference circuitry 0 CERS_1 VCC applied to the resistor ladder 1 CERS_2 Shared reference voltage applied to the resistor ladder 2 CERS_3 Shared reference voltage supplied to V(CREF). Resistor ladder is off 3 CEREF1 Reference resistor tap 1 0x8 0x5 read-write CEREF1_0 Reference resistor tap for setting 0. 0 CEREF1_1 Reference resistor tap for setting 1. 1 CEREF1_2 Reference resistor tap for setting 2. 2 CEREF1_3 Reference resistor tap for setting 3. 3 CEREF1_4 Reference resistor tap for setting 4. 4 CEREF1_5 Reference resistor tap for setting 5. 5 CEREF1_6 Reference resistor tap for setting 6. 6 CEREF1_7 Reference resistor tap for setting 7. 7 CEREF1_8 Reference resistor tap for setting 8. 8 CEREF1_9 Reference resistor tap for setting 9. 9 CEREF1_10 Reference resistor tap for setting 10. 10 CEREF1_11 Reference resistor tap for setting 11. 11 CEREF1_12 Reference resistor tap for setting 12. 12 CEREF1_13 Reference resistor tap for setting 13. 13 CEREF1_14 Reference resistor tap for setting 14. 14 CEREF1_15 Reference resistor tap for setting 15. 15 CEREF1_16 Reference resistor tap for setting 16. 16 CEREF1_17 Reference resistor tap for setting 17. 17 CEREF1_18 Reference resistor tap for setting 18. 18 CEREF1_19 Reference resistor tap for setting 19. 19 CEREF1_20 Reference resistor tap for setting 20. 20 CEREF1_21 Reference resistor tap for setting 21. 21 CEREF1_22 Reference resistor tap for setting 22. 22 CEREF1_23 Reference resistor tap for setting 23. 23 CEREF1_24 Reference resistor tap for setting 24. 24 CEREF1_25 Reference resistor tap for setting 25. 25 CEREF1_26 Reference resistor tap for setting 26. 26 CEREF1_27 Reference resistor tap for setting 27. 27 CEREF1_28 Reference resistor tap for setting 28. 28 CEREF1_29 Reference resistor tap for setting 29. 29 CEREF1_30 Reference resistor tap for setting 30. 30 CEREF1_31 Reference resistor tap for setting 31. 31 CEREFL Reference voltage level 0xD 0x2 read-write CEREFL_0 Reference amplifier is disabled. No reference voltage is requested 0 CEREFL_1 1.2 V is selected as shared reference voltage input 1 CEREFL_2 2.0 V is selected as shared reference voltage input 2 CEREFL_3 2.5 V is selected as shared reference voltage input 3 CEREFACC Reference accuracy 0xF 0x1 read-write CEREFACC_0 Static mode 0 CEREFACC_1 Clocked (low power, low accuracy) mode 1 CExCTL3 CTL3 Comparator Control Register 3 0x6 16 read-write 0x00000000 0x0000ffff CEPD0 Port disable 0x0 0x1 read-write CEPD0_0 The input buffer is enabled 0 CEPD0_1 The input buffer is disabled 1 CEPD1 Port disable 0x1 0x1 read-write CEPD1_0 The input buffer is enabled 0 CEPD1_1 The input buffer is disabled 1 CEPD2 Port disable 0x2 0x1 read-write CEPD2_0 The input buffer is enabled 0 CEPD2_1 The input buffer is disabled 1 CEPD3 Port disable 0x3 0x1 read-write CEPD3_0 The input buffer is enabled 0 CEPD3_1 The input buffer is disabled 1 CEPD4 Port disable 0x4 0x1 read-write CEPD4_0 The input buffer is enabled 0 CEPD4_1 The input buffer is disabled 1 CEPD5 Port disable 0x5 0x1 read-write CEPD5_0 The input buffer is enabled 0 CEPD5_1 The input buffer is disabled 1 CEPD6 Port disable 0x6 0x1 read-write CEPD6_0 The input buffer is enabled 0 CEPD6_1 The input buffer is disabled 1 CEPD7 Port disable 0x7 0x1 read-write CEPD7_0 The input buffer is enabled 0 CEPD7_1 The input buffer is disabled 1 CEPD8 Port disable 0x8 0x1 read-write CEPD8_0 The input buffer is enabled 0 CEPD8_1 The input buffer is disabled 1 CEPD9 Port disable 0x9 0x1 read-write CEPD9_0 The input buffer is enabled 0 CEPD9_1 The input buffer is disabled 1 CEPD10 Port disable 0xA 0x1 read-write CEPD10_0 The input buffer is enabled 0 CEPD10_1 The input buffer is disabled 1 CEPD11 Port disable 0xB 0x1 read-write CEPD11_0 The input buffer is enabled 0 CEPD11_1 The input buffer is disabled 1 CEPD12 Port disable 0xC 0x1 read-write CEPD12_0 The input buffer is enabled 0 CEPD12_1 The input buffer is disabled 1 CEPD13 Port disable 0xD 0x1 read-write CEPD13_0 The input buffer is enabled 0 CEPD13_1 The input buffer is disabled 1 CEPD14 Port disable 0xE 0x1 read-write CEPD14_0 The input buffer is enabled 0 CEPD14_1 The input buffer is disabled 1 CEPD15 Port disable 0xF 0x1 read-write CEPD15_0 The input buffer is enabled 0 CEPD15_1 The input buffer is disabled 1 CExINT INT Comparator Interrupt Control Register 0xC 16 read-write 0x00000000 0x0000ffff CEIFG Comparator output interrupt flag 0x0 0x1 read-write CEIFG_0 No interrupt pending 0 CEIFG_1 Interrupt pending 1 CEIIFG Comparator output inverted interrupt flag 0x1 0x1 read-write CEIIFG_0 No interrupt pending 0 CEIIFG_1 Interrupt pending 1 CERDYIFG Comparator ready interrupt flag 0x4 0x1 read-write CERDYIFG_0 No interrupt pending 0 CERDYIFG_1 Interrupt pending 1 CEIE Comparator output interrupt enable 0x8 0x1 read-write CEIE_0 Interrupt disabled 0 CEIE_1 Interrupt enabled 1 CEIIE Comparator output interrupt enable inverted polarity 0x9 0x1 read-write CEIIE_0 Interrupt disabled 0 CEIIE_1 Interrupt enabled 1 CERDYIE Comparator ready interrupt enable 0xC 0x1 read-write CERDYIE_0 Interrupt disabled 0 CERDYIE_1 Interrupt enabled 1 CExIV IV Comparator Interrupt Vector Word Register 0xE 16 read-only 0x00000000 0x0000ffff CEIV Comparator interrupt vector word register 0x0 0x10 read-only CEIV_enum_read read CEIV_0 No interrupt pending 0 CEIV_2 Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest 2 CEIV_4 Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG 4 CEIV_10 Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest 10 COMP_E1 356.0 COMP_E1 0x40003800 COMP_E1_IRQ COMP_E1 Interrupt 7 0x0 0x10 registers CExCTL0 CTL0 Comparator Control Register 0 0x0 16 read-write 0x00000000 0x0000ffff CEIPSEL Channel input selected for the V+ terminal 0x0 0x4 read-write CEIPSEL_0 Channel 0 selected 0 CEIPSEL_1 Channel 1 selected 1 CEIPSEL_2 Channel 2 selected 2 CEIPSEL_3 Channel 3 selected 3 CEIPSEL_4 Channel 4 selected 4 CEIPSEL_5 Channel 5 selected 5 CEIPSEL_6 Channel 6 selected 6 CEIPSEL_7 Channel 7 selected 7 CEIPSEL_8 Channel 8 selected 8 CEIPSEL_9 Channel 9 selected 9 CEIPSEL_10 Channel 10 selected 10 CEIPSEL_11 Channel 11 selected 11 CEIPSEL_12 Channel 12 selected 12 CEIPSEL_13 Channel 13 selected 13 CEIPSEL_14 Channel 14 selected 14 CEIPSEL_15 Channel 15 selected 15 CEIPEN Channel input enable for the V+ terminal 0x7 0x1 read-write CEIPEN_0 Selected analog input channel for V+ terminal is disabled 0 CEIPEN_1 Selected analog input channel for V+ terminal is enabled 1 CEIMSEL Channel input selected for the - terminal 0x8 0x4 read-write CEIMSEL_0 Channel 0 selected 0 CEIMSEL_1 Channel 1 selected 1 CEIMSEL_2 Channel 2 selected 2 CEIMSEL_3 Channel 3 selected 3 CEIMSEL_4 Channel 4 selected 4 CEIMSEL_5 Channel 5 selected 5 CEIMSEL_6 Channel 6 selected 6 CEIMSEL_7 Channel 7 selected 7 CEIMSEL_8 Channel 8 selected 8 CEIMSEL_9 Channel 9 selected 9 CEIMSEL_10 Channel 10 selected 10 CEIMSEL_11 Channel 11 selected 11 CEIMSEL_12 Channel 12 selected 12 CEIMSEL_13 Channel 13 selected 13 CEIMSEL_14 Channel 14 selected 14 CEIMSEL_15 Channel 15 selected 15 CEIMEN Channel input enable for the - terminal 0xF 0x1 read-write CEIMEN_0 Selected analog input channel for V- terminal is disabled 0 CEIMEN_1 Selected analog input channel for V- terminal is enabled 1 CExCTL1 CTL1 Comparator Control Register 1 0x2 16 read-write 0x00000000 0x0000ffff CEOUT Comparator output value 0x0 0x1 read-write CEOUTPOL Comparator output polarity 0x1 0x1 read-write CEOUTPOL_0 Noninverted 0 CEOUTPOL_1 Inverted 1 CEF Comparator output filter 0x2 0x1 read-write CEF_0 Comparator output is not filtered 0 CEF_1 Comparator output is filtered 1 CEIES Interrupt edge select for CEIIFG and CEIFG 0x3 0x1 read-write CEIES_0 Rising edge for CEIFG, falling edge for CEIIFG 0 CEIES_1 Falling edge for CEIFG, rising edge for CEIIFG 1 CESHORT Input short 0x4 0x1 read-write CESHORT_0 Inputs not shorted 0 CESHORT_1 Inputs shorted 1 CEEX Exchange 0x5 0x1 read-write CEFDLY Filter delay 0x6 0x2 read-write CEFDLY_0 Typical filter delay of TBD (450) ns 0 CEFDLY_1 Typical filter delay of TBD (900) ns 1 CEFDLY_2 Typical filter delay of TBD (1800) ns 2 CEFDLY_3 Typical filter delay of TBD (3600) ns 3 CEPWRMD Power Mode 0x8 0x2 read-write CEPWRMD_0 High-speed mode 0 CEPWRMD_1 Normal mode 1 CEPWRMD_2 Ultra-low power mode 2 CEON Comparator On 0xA 0x1 read-write CEON_0 Off 0 CEON_1 On 1 CEMRVL This bit is valid of CEMRVS is set to 1 0xB 0x1 read-write CEMRVL_0 VREF0 is selected if CERS = 00, 01, or 10 0 CEMRVL_1 VREF1 is selected if CERS = 00, 01, or 10 1 CEMRVS This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10. 0xC 0x1 read-write CEMRVS_0 Comparator output state selects between VREF0 or VREF1 0 CEMRVS_1 CEMRVL selects between VREF0 or VREF1 1 CExCTL2 CTL2 Comparator Control Register 2 0x4 16 read-write 0x00000000 0x0000ffff CEREF0 Reference resistor tap 0 0x0 0x5 read-write CEREF0_0 Reference resistor tap for setting 0. 0 CEREF0_1 Reference resistor tap for setting 1. 1 CEREF0_2 Reference resistor tap for setting 2. 2 CEREF0_3 Reference resistor tap for setting 3. 3 CEREF0_4 Reference resistor tap for setting 4. 4 CEREF0_5 Reference resistor tap for setting 5. 5 CEREF0_6 Reference resistor tap for setting 6. 6 CEREF0_7 Reference resistor tap for setting 7. 7 CEREF0_8 Reference resistor tap for setting 8. 8 CEREF0_9 Reference resistor tap for setting 9. 9 CEREF0_10 Reference resistor tap for setting 10. 10 CEREF0_11 Reference resistor tap for setting 11. 11 CEREF0_12 Reference resistor tap for setting 12. 12 CEREF0_13 Reference resistor tap for setting 13. 13 CEREF0_14 Reference resistor tap for setting 14. 14 CEREF0_15 Reference resistor tap for setting 15. 15 CEREF0_16 Reference resistor tap for setting 16. 16 CEREF0_17 Reference resistor tap for setting 17. 17 CEREF0_18 Reference resistor tap for setting 18. 18 CEREF0_19 Reference resistor tap for setting 19. 19 CEREF0_20 Reference resistor tap for setting 20. 20 CEREF0_21 Reference resistor tap for setting 21. 21 CEREF0_22 Reference resistor tap for setting 22. 22 CEREF0_23 Reference resistor tap for setting 23. 23 CEREF0_24 Reference resistor tap for setting 24. 24 CEREF0_25 Reference resistor tap for setting 25. 25 CEREF0_26 Reference resistor tap for setting 26. 26 CEREF0_27 Reference resistor tap for setting 27. 27 CEREF0_28 Reference resistor tap for setting 28. 28 CEREF0_29 Reference resistor tap for setting 29. 29 CEREF0_30 Reference resistor tap for setting 30. 30 CEREF0_31 Reference resistor tap for setting 31. 31 CERSEL Reference select 0x5 0x1 read-write CERSEL_0 When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal 0 CERSEL_1 When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal 1 CERS Reference source 0x6 0x2 read-write CERS_0 No current is drawn by the reference circuitry 0 CERS_1 VCC applied to the resistor ladder 1 CERS_2 Shared reference voltage applied to the resistor ladder 2 CERS_3 Shared reference voltage supplied to V(CREF). Resistor ladder is off 3 CEREF1 Reference resistor tap 1 0x8 0x5 read-write CEREF1_0 Reference resistor tap for setting 0. 0 CEREF1_1 Reference resistor tap for setting 1. 1 CEREF1_2 Reference resistor tap for setting 2. 2 CEREF1_3 Reference resistor tap for setting 3. 3 CEREF1_4 Reference resistor tap for setting 4. 4 CEREF1_5 Reference resistor tap for setting 5. 5 CEREF1_6 Reference resistor tap for setting 6. 6 CEREF1_7 Reference resistor tap for setting 7. 7 CEREF1_8 Reference resistor tap for setting 8. 8 CEREF1_9 Reference resistor tap for setting 9. 9 CEREF1_10 Reference resistor tap for setting 10. 10 CEREF1_11 Reference resistor tap for setting 11. 11 CEREF1_12 Reference resistor tap for setting 12. 12 CEREF1_13 Reference resistor tap for setting 13. 13 CEREF1_14 Reference resistor tap for setting 14. 14 CEREF1_15 Reference resistor tap for setting 15. 15 CEREF1_16 Reference resistor tap for setting 16. 16 CEREF1_17 Reference resistor tap for setting 17. 17 CEREF1_18 Reference resistor tap for setting 18. 18 CEREF1_19 Reference resistor tap for setting 19. 19 CEREF1_20 Reference resistor tap for setting 20. 20 CEREF1_21 Reference resistor tap for setting 21. 21 CEREF1_22 Reference resistor tap for setting 22. 22 CEREF1_23 Reference resistor tap for setting 23. 23 CEREF1_24 Reference resistor tap for setting 24. 24 CEREF1_25 Reference resistor tap for setting 25. 25 CEREF1_26 Reference resistor tap for setting 26. 26 CEREF1_27 Reference resistor tap for setting 27. 27 CEREF1_28 Reference resistor tap for setting 28. 28 CEREF1_29 Reference resistor tap for setting 29. 29 CEREF1_30 Reference resistor tap for setting 30. 30 CEREF1_31 Reference resistor tap for setting 31. 31 CEREFL Reference voltage level 0xD 0x2 read-write CEREFL_0 Reference amplifier is disabled. No reference voltage is requested 0 CEREFL_1 1.2 V is selected as shared reference voltage input 1 CEREFL_2 2.0 V is selected as shared reference voltage input 2 CEREFL_3 2.5 V is selected as shared reference voltage input 3 CEREFACC Reference accuracy 0xF 0x1 read-write CEREFACC_0 Static mode 0 CEREFACC_1 Clocked (low power, low accuracy) mode 1 CExCTL3 CTL3 Comparator Control Register 3 0x6 16 read-write 0x00000000 0x0000ffff CEPD0 Port disable 0x0 0x1 read-write CEPD0_0 The input buffer is enabled 0 CEPD0_1 The input buffer is disabled 1 CEPD1 Port disable 0x1 0x1 read-write CEPD1_0 The input buffer is enabled 0 CEPD1_1 The input buffer is disabled 1 CEPD2 Port disable 0x2 0x1 read-write CEPD2_0 The input buffer is enabled 0 CEPD2_1 The input buffer is disabled 1 CEPD3 Port disable 0x3 0x1 read-write CEPD3_0 The input buffer is enabled 0 CEPD3_1 The input buffer is disabled 1 CEPD4 Port disable 0x4 0x1 read-write CEPD4_0 The input buffer is enabled 0 CEPD4_1 The input buffer is disabled 1 CEPD5 Port disable 0x5 0x1 read-write CEPD5_0 The input buffer is enabled 0 CEPD5_1 The input buffer is disabled 1 CEPD6 Port disable 0x6 0x1 read-write CEPD6_0 The input buffer is enabled 0 CEPD6_1 The input buffer is disabled 1 CEPD7 Port disable 0x7 0x1 read-write CEPD7_0 The input buffer is enabled 0 CEPD7_1 The input buffer is disabled 1 CEPD8 Port disable 0x8 0x1 read-write CEPD8_0 The input buffer is enabled 0 CEPD8_1 The input buffer is disabled 1 CEPD9 Port disable 0x9 0x1 read-write CEPD9_0 The input buffer is enabled 0 CEPD9_1 The input buffer is disabled 1 CEPD10 Port disable 0xA 0x1 read-write CEPD10_0 The input buffer is enabled 0 CEPD10_1 The input buffer is disabled 1 CEPD11 Port disable 0xB 0x1 read-write CEPD11_0 The input buffer is enabled 0 CEPD11_1 The input buffer is disabled 1 CEPD12 Port disable 0xC 0x1 read-write CEPD12_0 The input buffer is enabled 0 CEPD12_1 The input buffer is disabled 1 CEPD13 Port disable 0xD 0x1 read-write CEPD13_0 The input buffer is enabled 0 CEPD13_1 The input buffer is disabled 1 CEPD14 Port disable 0xE 0x1 read-write CEPD14_0 The input buffer is enabled 0 CEPD14_1 The input buffer is disabled 1 CEPD15 Port disable 0xF 0x1 read-write CEPD15_0 The input buffer is enabled 0 CEPD15_1 The input buffer is disabled 1 CExINT INT Comparator Interrupt Control Register 0xC 16 read-write 0x00000000 0x0000ffff CEIFG Comparator output interrupt flag 0x0 0x1 read-write CEIFG_0 No interrupt pending 0 CEIFG_1 Interrupt pending 1 CEIIFG Comparator output inverted interrupt flag 0x1 0x1 read-write CEIIFG_0 No interrupt pending 0 CEIIFG_1 Interrupt pending 1 CERDYIFG Comparator ready interrupt flag 0x4 0x1 read-write CERDYIFG_0 No interrupt pending 0 CERDYIFG_1 Interrupt pending 1 CEIE Comparator output interrupt enable 0x8 0x1 read-write CEIE_0 Interrupt disabled 0 CEIE_1 Interrupt enabled 1 CEIIE Comparator output interrupt enable inverted polarity 0x9 0x1 read-write CEIIE_0 Interrupt disabled 0 CEIIE_1 Interrupt enabled 1 CERDYIE Comparator ready interrupt enable 0xC 0x1 read-write CERDYIE_0 Interrupt disabled 0 CERDYIE_1 Interrupt enabled 1 CExIV IV Comparator Interrupt Vector Word Register 0xE 16 read-only 0x00000000 0x0000ffff CEIV Comparator interrupt vector word register 0x0 0x10 read-only CEIV_enum_read read CEIV_0 No interrupt pending 0 CEIV_2 Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt Priority: Highest 2 CEIV_4 Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG 4 CEIV_10 Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest 10 AES256 356.0 AES256 0x40003C00 AES256_IRQ AES256 Interrupt 28 0x0 0x10 registers AESACTL0 CTL0 AES Accelerator Control Register 0 0x0 16 read-write 0x00000000 0x0000ffff AESOPx AES operation 0x0 0x2 read-write AESOPx_0 Encryption 0 AESOPx_1 Decryption. The provided key is the same key used for encryption 1 AESOPx_2 Generate first round key required for decryption 2 AESOPx_3 Decryption. The provided key is the first round key required for decryption 3 AESKLx AES key length 0x2 0x2 read-write AESKLx_0 AES128. The key size is 128 bit 0 AESKLx_1 AES192. The key size is 192 bit. 1 AESKLx_2 AES256. The key size is 256 bit 2 AESCMx AES cipher mode select 0x5 0x2 read-write AESCMx_0 ECB 0 AESCMx_1 CBC 1 AESCMx_2 OFB 2 AESCMx_3 CFB 3 AESSWRST AES software reset 0x7 0x1 read-write AESSWRST_0 No reset 0 AESSWRST_1 Reset AES accelerator module 1 AESRDYIFG AES ready interrupt flag 0x8 0x1 read-write AESRDYIFG_0 No interrupt pending 0 AESRDYIFG_1 Interrupt pending 1 AESERRFG AES error flag 0xB 0x1 read-write AESERRFG_0 No error 0 AESERRFG_1 Error occurred 1 AESRDYIE AES ready interrupt enable 0xC 0x1 read-write AESRDYIE_0 Interrupt disabled 0 AESRDYIE_1 Interrupt enabled 1 AESCMEN AES cipher mode enable 0xF 0x1 read-write AESCMEN_0 No DMA triggers are generated 0 AESCMEN_1 DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated 1 AESACTL1 CTL1 AES Accelerator Control Register 1 0x2 16 read-write 0x00000000 0x0000ffff AESBLKCNTx Cipher Block Counter 0x0 0x8 read-write AESASTAT STAT AES Accelerator Status Register 0x4 16 read-write 0x00000000 0x0000ffff AESBUSY AES accelerator module busy 0x0 0x1 read-write AESBUSY_0 Not busy 0 AESBUSY_1 Busy 1 AESKEYWR All 16 bytes written to AESAKEY 0x1 0x1 read-write AESKEYWR_0 Not all bytes written 0 AESKEYWR_1 All bytes written 1 AESDINWR All 16 bytes written to AESADIN, AESAXDIN or AESAXIN 0x2 0x1 read-write AESDINWR_0 Not all bytes written 0 AESDINWR_1 All bytes written 1 AESDOUTRD All 16 bytes read from AESADOUT 0x3 0x1 read-only AESDOUTRD_enum_read read AESDOUTRD_0 Not all bytes read 0 AESDOUTRD_1 All bytes read 1 AESKEYCNTx Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY 0x4 0x4 read-only AESDINCNTx Bytes written via AESADIN, AESAXDIN or AESAXIN 0x8 0x4 read-only AESDOUTCNTx Bytes read via AESADOUT 0xC 0x4 read-only AESAKEY KEY AES Accelerator Key Register 0x6 16 write-only 0x00000000 0x0000ffff AESKEY0x AES key byte n when AESAKEY is written as half-word 0x0 0x8 write-only AESKEY1x AES key byte n+1 when AESAKEY is written as half-word 0x8 0x8 write-only AESADIN DIN AES Accelerator Data In Register 0x8 16 write-only 0x00000000 0x0000ffff AESDIN0x AES data in byte n when AESADIN is written as half-word 0x0 0x8 write-only AESDIN1x AES data in byte n+1 when AESADIN is written as half-word 0x8 0x8 write-only AESADOUT DOUT AES Accelerator Data Out Register 0xA 16 write-only 0x00000000 0x0000ffff AESDOUT0x AES data out byte n when AESADOUT is read as half-word 0x0 0x8 write-only AESDOUT1x AES data out byte n+1 when AESADOUT is read as half-word 0x8 0x8 write-only AESAXDIN XDIN AES Accelerator XORed Data In Register 0xC 16 write-only 0x00000000 0x0000ffff AESXDIN0x AES data in byte n when AESAXDIN is written as half-word 0x0 0x8 write-only AESXDIN1x AES data in byte n+1 when AESAXDIN is written as half-word 0x8 0x8 write-only AESAXIN XIN AES Accelerator XORed Data In Register 0xE 16 write-only 0x00000000 0x0000ffff AESXIN0x AES data in byte n when AESAXIN is written as half-word 0x0 0x8 write-only AESXIN1x AES data in byte n+1 when AESAXIN is written as half-word 0x8 0x8 write-only CRC32 356.0 CRC32 0x40004000 0x0 0x20 registers CRC32DI CRC32DI Data Input for CRC32 Signature Computation 0x0 16 read-write 0x00000000 0x0000ffff CRC32DI Data input register 0x0 0x10 read-write CRC32DIRB CRC32DIRB Data In Reverse for CRC32 Computation 0x4 16 read-write 0x00000000 0x0000ffff CRC32DIRB Data input register reversed 0x0 0x10 read-write CRC32INIRES_LO CRC32INIRES_LO CRC32 Initialization and Result, lower 16 bits 0x8 16 read-write 0x00000000 0x0000ffff CRC32INIRES_LO CRC32 initialization and result, lower 16 bits 0x0 0x10 read-write CRC32INIRES_HI CRC32INIRES_HI CRC32 Initialization and Result, upper 16 bits 0xA 16 read-write 0x00000000 0x0000ffff CRC32INIRES_HI CRC32 initialization and result, upper 16 bits 0x0 0x10 read-write CRC32RESR_LO CRC32RESR_LO CRC32 Result Reverse, lower 16 bits 0xC 16 read-write 0x0000ffff 0x0000ffff CRC32RESR_LO CRC32 reverse result, lower 16 bits 0x0 0x10 read-write CRC32RESR_HI CRC32RESR_HI CRC32 Result Reverse, Upper 16 bits 0xE 16 read-write 0x0000ffff 0x0000ffff CRC32RESR_HI CRC32 reverse result, upper 16 bits 0x0 0x10 read-write CRC16DI CRC16DI Data Input for CRC16 computation 0x10 16 read-write 0x00000000 0x0000ffff CRC16DI CRC16 data in 0x0 0x10 read-write CRC16DIRB CRC16DIRB CRC16 Data In Reverse 0x14 16 read-write 0x00000000 0x0000ffff CRC16DIRB CRC16 data in reverse byte 0x0 0x10 read-write CRC16INIRES CRC16INIRES CRC16 Initialization and Result register 0x18 16 read-write 0x0000ffff 0x0000ffff CRC16INIRES CRC16 initialization and result 0x0 0x10 read-write CRC16RESR CRC16RESR CRC16 Result Reverse 0x1E 16 read-write 0x0000ffff 0x0000ffff CRC16RESR CRC16 reverse result 0x0 0x10 read-write RTC_C 356.0 RTC_C 0x40004400 RTC_C_IRQ RTC_C Interrupt 29 0x0 0x20 registers RTCCTL0 CTL0 RTCCTL0 Register 0x0 16 read-write 0x00009608 0x0000ffff RTCRDYIFG Real-time clock ready interrupt flag 0x0 0x1 read-write RTCRDYIFG_0 RTC cannot be read safely 0 RTCRDYIFG_1 RTC can be read safely 1 RTCAIFG Real-time clock alarm interrupt flag 0x1 0x1 read-write RTCAIFG_0 No time event occurred 0 RTCAIFG_1 Time event occurred 1 RTCTEVIFG Real-time clock time event interrupt flag 0x2 0x1 read-write RTCTEVIFG_0 No time event occurred 0 RTCTEVIFG_1 Time event occurred 1 RTCOFIFG 32-kHz crystal oscillator fault interrupt flag 0x3 0x1 read-write RTCOFIFG_0 No interrupt pending 0 RTCOFIFG_1 Interrupt pending. A 32-kHz crystal oscillator fault occurred after last reset. 1 RTCRDYIE Real-time clock ready interrupt enable 0x4 0x1 read-write RTCRDYIE_0 Interrupt not enabled 0 RTCRDYIE_1 Interrupt enabled 1 RTCAIE Real-time clock alarm interrupt enable 0x5 0x1 read-write RTCAIE_0 Interrupt not enabled 0 RTCAIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RTCTEVIE Real-time clock time event interrupt enable 0x6 0x1 read-write RTCTEVIE_0 Interrupt not enabled 0 RTCTEVIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RTCOFIE 32-kHz crystal oscillator fault interrupt enable 0x7 0x1 read-write RTCOFIE_0 Interrupt not enabled 0 RTCOFIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RTCKEY Real-time clock key 0x8 0x8 read-write RTCCTL13 CTL13 RTCCTL13 Register 0x2 16 read-write 0x00000070 0x0000ffff RTCTEV Real-time clock time event 0x0 0x2 read-write RTCTEV_0 Minute changed 0 RTCTEV_1 Hour changed 1 RTCTEV_2 Every day at midnight (00:00) 2 RTCTEV_3 Every day at noon (12:00) 3 RTCSSEL Real-time clock source select 0x2 0x2 read-write RTCSSEL_0 BCLK 0 RTCRDY Real-time clock ready 0x4 0x1 read-only RTCRDY_enum_read read RTCRDY_0 RTC time values in transition 0 RTCRDY_1 RTC time values safe for reading. This bit indicates when the real-time clock time values are safe for reading. 1 RTCMODE 0x5 0x1 read-only RTCMODE_enum_read read RTCMODE_1 Calendar mode. Always reads a value of 1. 1 RTCHOLD Real-time clock hold 0x6 0x1 read-write RTCHOLD_0 Real-time clock is operational 0 RTCHOLD_1 When set, the calendar is stopped as well as the prescale counters, RT0PS and RT1PS are don't care 1 RTCBCD Real-time clock BCD select 0x7 0x1 read-write RTCBCD_0 Binary (hexadecimal) code selected 0 RTCBCD_1 Binary coded decimal (BCD) code selected 1 RTCCALF Real-time clock calibration frequency 0x8 0x2 read-write RTCCALF_0 No frequency output to RTCCLK pin 0 RTCCALF_1 512 Hz 1 RTCCALF_2 256 Hz 2 RTCCALF_3 1 Hz 3 RTCOCAL OCAL RTCOCAL Register 0x4 16 read-write 0x00000000 0x0000ffff RTCOCAL Real-time clock offset error calibration 0x0 0x8 read-write RTCOCALS Real-time clock offset error calibration sign 0xF 0x1 read-write RTCOCALS_0 Down calibration. Frequency adjusted down. 0 RTCOCALS_1 Up calibration. Frequency adjusted up. 1 RTCTCMP TCMP RTCTCMP Register 0x6 16 read-write 0x00004000 0x0000ffff RTCTCMP Real-time clock temperature compensation 0x0 0x8 read-write RTCTCOK Real-time clock temperature compensation write OK 0xD 0x1 read-only RTCTCOK_enum_read read RTCTCOK_0 Write to RTCTCMPx is unsuccessful 0 RTCTCOK_1 Write to RTCTCMPx is successful 1 RTCTCRDY Real-time clock temperature compensation ready 0xE 0x1 read-only RTCTCMPS Real-time clock temperature compensation sign 0xF 0x1 read-write RTCTCMPS_0 Down calibration. Frequency adjusted down 0 RTCTCMPS_1 Up calibration. Frequency adjusted up 1 RTCPS0CTL PS0CTL Real-Time Clock Prescale Timer 0 Control Register 0x8 16 read-write 0x00000000 0x0000ffff RT0PSIFG Prescale timer 0 interrupt flag 0x0 0x1 read-write RT0PSIFG_0 No time event occurred 0 RT0PSIFG_1 Time event occurred 1 RT0PSIE Prescale timer 0 interrupt enable 0x1 0x1 read-write RT0PSIE_0 Interrupt not enabled 0 RT0PSIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RT0IP Prescale timer 0 interrupt interval 0x2 0x3 read-write RT0IP_0 Divide by 2 0 RT0IP_1 Divide by 4 1 RT0IP_2 Divide by 8 2 RT0IP_3 Divide by 16 3 RT0IP_4 Divide by 32 4 RT0IP_5 Divide by 64 5 RT0IP_6 Divide by 128 6 RT0IP_7 Divide by 256 7 RTCPS1CTL PS1CTL Real-Time Clock Prescale Timer 1 Control Register 0xA 16 read-write 0x00000000 0x0000ffff RT1PSIFG Prescale timer 1 interrupt flag 0x0 0x1 read-write RT1PSIFG_0 No time event occurred 0 RT1PSIFG_1 Time event occurred 1 RT1PSIE Prescale timer 1 interrupt enable 0x1 0x1 read-write RT1PSIE_0 Interrupt not enabled 0 RT1PSIE_1 Interrupt enabled (LPM3/LPM3.5 wake-up enabled) 1 RT1IP Prescale timer 1 interrupt interval 0x2 0x3 read-write RT1IP_0 Divide by 2 0 RT1IP_1 Divide by 4 1 RT1IP_2 Divide by 8 2 RT1IP_3 Divide by 16 3 RT1IP_4 Divide by 32 4 RT1IP_5 Divide by 64 5 RT1IP_6 Divide by 128 6 RT1IP_7 Divide by 256 7 RTCPS PS Real-Time Clock Prescale Timer Counter Register 0xC 16 read-write 0x00000000 0x00000000 RT0PS Prescale timer 0 counter value 0x0 0x8 read-write RT1PS Prescale timer 1 counter value 0x8 0x8 read-write RTCIV IV Real-Time Clock Interrupt Vector Register 0xE 16 read-only 0x00000000 0x0000ffff RTCIV Real-time clock interrupt vector value 0x0 0x10 read-only RTCIV_enum_read read RTCIV_0 No interrupt pending 0 RTCIV_2 Interrupt Source: RTC oscillator failure; Interrupt Flag: RTCOFIFG; Interrupt Priority: Highest 2 RTCIV_4 Interrupt Source: RTC ready; Interrupt Flag: RTCRDYIFG 4 RTCIV_6 Interrupt Source: RTC interval timer; Interrupt Flag: RTCTEVIFG 6 RTCIV_8 Interrupt Source: RTC user alarm; Interrupt Flag: RTCAIFG 8 RTCIV_10 Interrupt Source: RTC prescaler 0; Interrupt Flag: RT0PSIFG 10 RTCIV_12 Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 12 RTCTIM0 TIM0 RTCTIM0 Register Hexadecimal Format 0x10 16 read-write 0x00000000 0x0000c0c0 Seconds Seconds (0 to 59) 0x0 0x6 read-write Minutes Minutes (0 to 59) 0x8 0x6 read-write RTCTIM1 TIM1 Real-Time Clock Hour, Day of Week 0x12 16 read-write 0x00000000 0x0000f8e0 Hours Hours (0 to 23) 0x0 0x5 read-write DayofWeek Day of week (0 to 6) 0x8 0x3 read-write RTCDATE DATE RTCDATE - Hexadecimal Format 0x14 16 read-write 0x00000000 0x0000f0e0 Day Day of month (1 to 28, 29, 30, 31) 0x0 0x5 read-write Month Month (1 to 12) 0x8 0x4 read-write RTCYEAR YEAR RTCYEAR Register Hexadecimal Format 0x16 16 read-write 0x00000000 0x0000f000 YearLowByte Year low byte. Valid values for Year are 0 to 4095. 0x0 0x8 read-write YearHighByte Year high byte. Valid values for Year are 0 to 4095. 0x8 0x4 read-write RTCAMINHR AMINHR RTCMINHR - Hexadecimal Format 0x18 16 read-write 0x00000000 0x00006040 Minutes Minutes (0 to 59) 0x0 0x6 read-write MINAE Alarm enable 0x7 0x1 read-write Hours Hours (0 to 23) 0x8 0x5 read-write HOURAE Alarm enable 0xF 0x1 read-write RTCADOWDAY ADOWDAY RTCADOWDAY - Hexadecimal Format 0x1A 16 read-write 0x00000000 0x00006078 DayofWeek Day of week (0 to 6) 0x0 0x3 read-write DOWAE Alarm enable 0x7 0x1 read-write DayofMonth Day of month (1 to 28, 29, 30, 31) 0x8 0x5 read-write DAYAE Alarm enable 0xF 0x1 read-write RTCBIN2BCD BIN2BCD Binary-to-BCD Conversion Register 0x1C 16 read-write 0x00000000 0x0000ffff BIN2BCD bin to bcd conversion 0x0 0x10 read-write RTCBCD2BIN BCD2BIN BCD-to-Binary Conversion Register 0x1E 16 read-write 0x00000000 0x0000ffff BCD2BIN bcd to bin conversion 0x0 0x10 read-write WDT_A 356.0 WDT_A 0x40004800 WDT_A_IRQ WDT_A Interrupt 3 0x0 0xE registers WDTCTL CTL Watchdog Timer Control Register 0xC 16 read-write 0x00006904 0x0000ffff WDTIS Watchdog timer interval select 0x0 0x3 read-write WDTIS_0 Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) 0 WDTIS_1 Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) 1 WDTIS_2 Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) 2 WDTIS_3 Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) 3 WDTIS_4 Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) 4 WDTIS_5 Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) 5 WDTIS_6 Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) 6 WDTIS_7 Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) 7 WDTCNTCL Watchdog timer counter clear 0x3 0x1 write-only WDTCNTCL_enum_write write WDTCNTCL_0 No action 0 WDTCNTCL_1 WDTCNT = 0000h 1 WDTTMSEL Watchdog timer mode select 0x4 0x1 read-write WDTTMSEL_0 Watchdog mode 0 WDTTMSEL_1 Interval timer mode 1 WDTSSEL Watchdog timer clock source select 0x5 0x2 read-write WDTSSEL_0 SMCLK 0 WDTSSEL_1 ACLK 1 WDTSSEL_2 VLOCLK 2 WDTSSEL_3 BCLK 3 WDTHOLD Watchdog timer hold 0x7 0x1 read-write WDTHOLD_0 Watchdog timer is not stopped 0 WDTHOLD_1 Watchdog timer is stopped 1 WDTPW Watchdog timer password 0x8 0x8 read-write DIO 356.0 DIO 0x40004C00 PORT1_IRQ Port1 Interrupt 35 PORT2_IRQ Port2 Interrupt 36 PORT3_IRQ Port3 Interrupt 37 PORT4_IRQ Port4 Interrupt 38 PORT5_IRQ Port5 Interrupt 39 PORT6_IRQ Port6 Interrupt 40 0x0 0x138 registers PAIN PAIN Port A Input 0x0 16 read-only 0x00000000 0x00000000 P1IN Port 1 Input 0x0 0x8 read-only P2IN Port 2 Input 0x8 0x8 read-only PAOUT PAOUT Port A Output 0x2 16 read-write 0x00000000 0x00000000 P2OUT Port 2 Output 0x8 0x8 read-write P1OUT Port 1 Output 0x0 0x8 read-write PADIR PADIR Port A Direction 0x4 16 read-write 0x00000000 0x0000ffff P1DIR Port 1 Direction 0x0 0x8 read-write P2DIR Port 2 Direction 0x8 0x8 read-write PAREN PAREN Port A Resistor Enable 0x6 16 read-write 0x00000000 0x0000ffff P1REN Port 1 Resistor Enable 0x0 0x8 read-write P2REN Port 2 Resistor Enable 0x8 0x8 read-write PADS PADS Port A Drive Strength 0x8 16 read-write P1DS Port 1 Drive Strength 0x0 0x8 read-write P2DS Port 2 Drive Strength 0x8 0x8 read-write PASEL0 PASEL0 Port A Select 0 0xA 16 read-write 0x00000000 0x0000ffff P1SEL0 Port 1 Select 0 0x0 0x8 read-write P2SEL0 Port 2 Select 0 0x8 0x8 read-write PASEL1 PASEL1 Port A Select 1 0xC 16 read-write 0x00000000 0x0000ffff P1SEL1 Port 1 Select 1 0x0 0x8 read-write P2SEL1 Port 2 Select 1 0x8 0x8 read-write P1IV P1IV Port 1 Interrupt Vector Register 0xE 16 read-only 0x00000000 0x0000ffff P1IV Port 1 interrupt vector value 0x0 0x5 read-only P1IV_enum_read read P1IV_0 No interrupt pending 0 P1IV_2 Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest 2 P1IV_4 Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 4 P1IV_6 Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 6 P1IV_8 Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 8 P1IV_10 Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 10 P1IV_12 Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 12 P1IV_14 Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 14 P1IV_16 Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest 16 PASELC PASELC Port A Complement Select 0x16 16 read-write 0x00000000 0x0000ffff P1SELC Port 1 Complement Select 0x0 0x8 read-write P2SELC Port 2 Complement Select 0x8 0x8 read-write PAIES PAIES Port A Interrupt Edge Select 0x18 16 read-write 0x00000000 0x00000000 P1IES Port 1 Interrupt Edge Select 0x0 0x8 read-write P2IES Port 2 Interrupt Edge Select 0x8 0x8 read-write PAIE PAIE Port A Interrupt Enable 0x1A 16 read-write 0x00000000 0x0000ffff P1IE Port 1 Interrupt Enable 0x0 0x8 read-write P2IE Port 2 Interrupt Enable 0x8 0x8 read-write PAIFG PAIFG Port A Interrupt Flag 0x1C 16 read-write 0x00000000 0x0000ffff P1IFG Port 1 Interrupt Flag 0x0 0x8 read-write P2IFG Port 2 Interrupt Flag 0x8 0x8 read-write P2IV P2IV Port 2 Interrupt Vector Register 0x1E 16 read-only P2IV Port 2 interrupt vector value 0x0 0x5 read-only P2IV_enum_read read P2IV_0 No interrupt pending 0 P2IV_2 Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest 2 P2IV_4 Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 4 P2IV_6 Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 6 P2IV_8 Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 8 P2IV_10 Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 10 P2IV_12 Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 12 P2IV_14 Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 14 P2IV_16 Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest 16 PBIN PBIN Port B Input 0x20 16 read-only 0x00000000 0x00000000 P3IN Port 3 Input 0x0 0x8 read-only P4IN Port 4 Input 0x8 0x8 read-only PBOUT PBOUT Port B Output 0x22 16 read-write 0x00000000 0x00000000 P3OUT Port 3 Output 0x0 0x8 read-write P4OUT Port 4 Output 0x8 0x8 read-write PBDIR PBDIR Port B Direction 0x24 16 read-write 0x00000000 0x0000ffff P3DIR Port 3 Direction 0x0 0x8 read-write P4DIR Port 4 Direction 0x8 0x8 read-write PBREN PBREN Port B Resistor Enable 0x26 16 read-write 0x00000000 0x0000ffff P3REN Port 3 Resistor Enable 0x0 0x8 read-write P4REN Port 4 Resistor Enable 0x8 0x8 read-write PBDS PBDS Port B Drive Strength 0x28 16 read-write P3DS Port 3 Drive Strength 0x0 0x8 read-write P4DS Port 4 Drive Strength 0x8 0x8 read-write PBSEL0 PBSEL0 Port B Select 0 0x2A 16 read-write 0x00000000 0x0000ffff P4SEL0 Port 4 Select 0 0x8 0x8 read-write P3SEL0 Port 3 Select 0 0x0 0x8 read-write PBSEL1 PBSEL1 Port B Select 1 0x2C 16 read-write 0x00000000 0x0000ffff P3SEL1 Port 3 Select 1 0x0 0x8 read-write P4SEL1 Port 4 Select 1 0x8 0x8 read-write P3IV P3IV Port 3 Interrupt Vector Register 0x2E 16 read-only 0x00000000 0x0000ffff P3IV Port 3 interrupt vector value 0x0 0x5 read-only P3IV_enum_read read P3IV_0 No interrupt pending 0 P3IV_2 Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest 2 P3IV_4 Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 4 P3IV_6 Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 6 P3IV_8 Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 8 P3IV_10 Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 10 P3IV_12 Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 12 P3IV_14 Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 14 P3IV_16 Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest 16 PBSELC PBSELC Port B Complement Select 0x36 16 read-write 0x00000000 0x0000ffff P3SELC Port 3 Complement Select 0x0 0x8 read-write P4SELC Port 4 Complement Select 0x8 0x8 read-write PBIES PBIES Port B Interrupt Edge Select 0x38 16 read-write 0x00000000 0x00000000 P3IES Port 3 Interrupt Edge Select 0x0 0x8 read-write P4IES Port 4 Interrupt Edge Select 0x8 0x8 read-write PBIE PBIE Port B Interrupt Enable 0x3A 16 read-write 0x00000000 0x0000ffff P3IE Port 3 Interrupt Enable 0x0 0x8 read-write P4IE Port 4 Interrupt Enable 0x8 0x8 read-write PBIFG PBIFG Port B Interrupt Flag 0x3C 16 read-write 0x00000000 0x0000ffff P3IFG Port 3 Interrupt Flag 0x0 0x8 read-write P4IFG Port 4 Interrupt Flag 0x8 0x8 read-write P4IV P4IV Port 4 Interrupt Vector Register 0x3E 16 read-only P4IV Port 4 interrupt vector value 0x0 0x5 read-only P4IV_enum_read read P4IV_0 No interrupt pending 0 P4IV_2 Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest 2 P4IV_4 Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 4 P4IV_6 Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 6 P4IV_8 Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 8 P4IV_10 Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 10 P4IV_12 Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 12 P4IV_14 Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 14 P4IV_16 Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest 16 PCIN PCIN Port C Input 0x40 16 read-only 0x00000000 0x00000000 P5IN Port 5 Input 0x0 0x8 read-only P6IN Port 6 Input 0x8 0x8 read-only PCOUT PCOUT Port C Output 0x42 16 read-write 0x00000000 0x00000000 P5OUT Port 5 Output 0x0 0x8 read-write P6OUT Port 6 Output 0x8 0x8 read-write PCDIR PCDIR Port C Direction 0x44 16 read-write 0x00000000 0x0000ffff P5DIR Port 5 Direction 0x0 0x8 read-write P6DIR Port 6 Direction 0x8 0x8 read-write PCREN PCREN Port C Resistor Enable 0x46 16 read-write 0x00000000 0x0000ffff P5REN Port 5 Resistor Enable 0x0 0x8 read-write P6REN Port 6 Resistor Enable 0x8 0x8 read-write PCDS PCDS Port C Drive Strength 0x48 16 read-write P5DS Port 5 Drive Strength 0x0 0x8 read-write P6DS Port 6 Drive Strength 0x8 0x8 read-write PCSEL0 PCSEL0 Port C Select 0 0x4A 16 read-write 0x00000000 0x0000ffff P5SEL0 Port 5 Select 0 0x0 0x8 read-write P6SEL0 Port 6 Select 0 0x8 0x8 read-write PCSEL1 PCSEL1 Port C Select 1 0x4C 16 read-write 0x00000000 0x0000ffff P5SEL1 Port 5 Select 1 0x0 0x8 read-write P6SEL1 Port 6 Select 1 0x8 0x8 read-write P5IV P5IV Port 5 Interrupt Vector Register 0x4E 16 read-only 0x00000000 0x0000ffff P5IV Port 5 interrupt vector value 0x0 0x5 read-only P5IV_enum_read read P5IV_0 No interrupt pending 0 P5IV_2 Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest 2 P5IV_4 Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 4 P5IV_6 Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 6 P5IV_8 Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 8 P5IV_10 Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 10 P5IV_12 Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 12 P5IV_14 Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 14 P5IV_16 Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest 16 PCSELC PCSELC Port C Complement Select 0x56 16 read-write 0x00000000 0x0000ffff P5SELC Port 5 Complement Select 0x0 0x8 read-write P6SELC Port 6 Complement Select 0x8 0x8 read-write PCIES PCIES Port C Interrupt Edge Select 0x58 16 read-write 0x00000000 0x00000000 P5IES Port 5 Interrupt Edge Select 0x0 0x8 read-write P6IES Port 6 Interrupt Edge Select 0x8 0x8 read-write PCIE PCIE Port C Interrupt Enable 0x5A 16 read-write 0x00000000 0x0000ffff P5IE Port 5 Interrupt Enable 0x0 0x8 read-write P6IE Port 6 Interrupt Enable 0x8 0x8 read-write PCIFG PCIFG Port C Interrupt Flag 0x5C 16 read-write 0x00000000 0x0000ffff P5IFG Port 5 Interrupt Flag 0x0 0x8 read-write P6IFG Port 6 Interrupt Flag 0x8 0x8 read-write P6IV P6IV Port 6 Interrupt Vector Register 0x5E 16 read-only P6IV Port 6 interrupt vector value 0x0 0x5 read-only P6IV_enum_read read P6IV_0 No interrupt pending 0 P6IV_2 Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest 2 P6IV_4 Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 4 P6IV_6 Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 6 P6IV_8 Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 8 P6IV_10 Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 10 P6IV_12 Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 12 P6IV_14 Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 14 P6IV_16 Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest 16 PDIN PDIN Port D Input 0x60 16 read-only 0x00000000 0x00000000 P7IN Port 7 Input 0x0 0x8 read-only P8IN Port 8 Input 0x8 0x8 read-only PDOUT PDOUT Port D Output 0x62 16 read-write 0x00000000 0x00000000 P7OUT Port 7 Output 0x0 0x8 read-write P8OUT Port 8 Output 0x8 0x8 read-write PDDIR PDDIR Port D Direction 0x64 16 read-write 0x00000000 0x0000ffff P7DIR Port 7 Direction 0x0 0x8 read-write P8DIR Port 8 Direction 0x8 0x8 read-write PDREN PDREN Port D Resistor Enable 0x66 16 read-write 0x00000000 0x0000ffff P7REN Port 7 Resistor Enable 0x0 0x8 read-write P8REN Port 8 Resistor Enable 0x8 0x8 read-write PDDS PDDS Port D Drive Strength 0x68 16 read-write P7DS Port 7 Drive Strength 0x0 0x8 read-write P8DS Port 8 Drive Strength 0x8 0x8 read-write PDSEL0 PDSEL0 Port D Select 0 0x6A 16 read-write 0x00000000 0x0000ffff P7SEL0 Port 7 Select 0 0x0 0x8 read-write P8SEL0 Port 8 Select 0 0x8 0x8 read-write PDSEL1 PDSEL1 Port D Select 1 0x6C 16 read-write 0x00000000 0x0000ffff P7SEL1 Port 7 Select 1 0x0 0x8 read-write P8SEL1 Port 8 Select 1 0x8 0x8 read-write P7IV P7IV Port 7 Interrupt Vector Register 0x6E 16 read-only 0x00000000 0x0000ffff P7IV Port 7 interrupt vector value 0x0 0x5 read-only P7IV_enum_read read P7IV_0 No interrupt pending 0 P7IV_2 Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest 2 P7IV_4 Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 4 P7IV_6 Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 6 P7IV_8 Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 8 P7IV_10 Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 10 P7IV_12 Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 12 P7IV_14 Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 14 P7IV_16 Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest 16 PDSELC PDSELC Port D Complement Select 0x76 16 read-write 0x00000000 0x0000ffff P7SELC Port 7 Complement Select 0x0 0x8 read-write P8SELC Port 8 Complement Select 0x8 0x8 read-write PDIES PDIES Port D Interrupt Edge Select 0x78 16 read-write 0x00000000 0x00000000 P7IES Port 7 Interrupt Edge Select 0x0 0x8 read-write P8IES Port 8 Interrupt Edge Select 0x8 0x8 read-write PDIE PDIE Port D Interrupt Enable 0x7A 16 read-write 0x00000000 0x0000ffff P7IE Port 7 Interrupt Enable 0x0 0x8 read-write P8IE Port 8 Interrupt Enable 0x8 0x8 read-write PDIFG PDIFG Port D Interrupt Flag 0x7C 16 read-write 0x00000000 0x0000ffff P7IFG Port 7 Interrupt Flag 0x0 0x8 read-write P8IFG Port 8 Interrupt Flag 0x8 0x8 read-write P8IV P8IV Port 8 Interrupt Vector Register 0x7E 16 read-only P8IV Port 8 interrupt vector value 0x0 0x5 read-only P8IV_enum_read read P8IV_0 No interrupt pending 0 P8IV_2 Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest 2 P8IV_4 Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 4 P8IV_6 Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 6 P8IV_8 Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 8 P8IV_10 Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 10 P8IV_12 Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 12 P8IV_14 Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 14 P8IV_16 Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest 16 PEIN PEIN Port E Input 0x80 16 read-only 0x00000000 0x00000000 P9IN Port 9 Input 0x0 0x8 read-only P10IN Port 10 Input 0x8 0x8 read-only PEOUT PEOUT Port E Output 0x82 16 read-write 0x00000000 0x00000000 P9OUT Port 9 Output 0x0 0x8 read-write P10OUT Port 10 Output 0x8 0x8 read-write PEDIR PEDIR Port E Direction 0x84 16 read-write 0x00000000 0x0000ffff P9DIR Port 9 Direction 0x0 0x8 read-write P10DIR Port 10 Direction 0x8 0x8 read-write PEREN PEREN Port E Resistor Enable 0x86 16 read-write 0x00000000 0x0000ffff P9REN Port 9 Resistor Enable 0x0 0x8 read-write P10REN Port 10 Resistor Enable 0x8 0x8 read-write PEDS PEDS Port E Drive Strength 0x88 16 read-write P9DS Port 9 Drive Strength 0x0 0x8 read-write P10DS Port 10 Drive Strength 0x8 0x8 read-write PESEL0 PESEL0 Port E Select 0 0x8A 16 read-write 0x00000000 0x0000ffff P9SEL0 Port 9 Select 0 0x0 0x8 read-write P10SEL0 Port 10 Select 0 0x8 0x8 read-write PESEL1 PESEL1 Port E Select 1 0x8C 16 read-write 0x00000000 0x0000ffff P9SEL1 Port 9 Select 1 0x0 0x8 read-write P10SEL1 Port 10 Select 1 0x8 0x8 read-write P9IV P9IV Port 9 Interrupt Vector Register 0x8E 16 read-only 0x00000000 0x0000ffff P9IV Port 9 interrupt vector value 0x0 0x5 read-only P9IV_enum_read read P9IV_0 No interrupt pending 0 P9IV_2 Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest 2 P9IV_4 Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 4 P9IV_6 Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 6 P9IV_8 Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 8 P9IV_10 Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 10 P9IV_12 Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 12 P9IV_14 Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 14 P9IV_16 Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest 16 PESELC PESELC Port E Complement Select 0x96 16 read-write 0x00000000 0x0000ffff P9SELC Port 9 Complement Select 0x0 0x8 read-write P10SELC Port 10 Complement Select 0x8 0x8 read-write PEIES PEIES Port E Interrupt Edge Select 0x98 16 read-write 0x00000000 0x00000000 P9IES Port 9 Interrupt Edge Select 0x0 0x8 read-write P10IES Port 10 Interrupt Edge Select 0x8 0x8 read-write PEIE PEIE Port E Interrupt Enable 0x9A 16 read-write 0x00000000 0x0000ffff P9IE Port 9 Interrupt Enable 0x0 0x8 read-write P10IE Port 10 Interrupt Enable 0x8 0x8 read-write PEIFG PEIFG Port E Interrupt Flag 0x9C 16 read-write 0x00000000 0x0000ffff P9IFG Port 9 Interrupt Flag 0x0 0x8 read-write P10IFG Port 10 Interrupt Flag 0x8 0x8 read-write P10IV P10IV Port 10 Interrupt Vector Register 0x9E 16 read-only P10IV Port 10 interrupt vector value 0x0 0x5 read-only P10IV_enum_read read P10IV_0 No interrupt pending 0 P10IV_2 Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest 2 P10IV_4 Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 4 P10IV_6 Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 6 P10IV_8 Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 8 P10IV_10 Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 10 P10IV_12 Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 12 P10IV_14 Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 14 P10IV_16 Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest 16 PJIN PJIN Port J Input 0x120 16 read-only 0x00000000 0x00000000 PJIN Port J Input 0x0 0x10 read-only PJOUT PJOUT Port J Output 0x122 16 read-write 0x00000000 0x00000000 PJOUT Port J Output 0x0 0x10 read-write PJDIR PJDIR Port J Direction 0x124 16 read-write 0x00000000 0x0000ffff PJDIR Port J Direction 0x0 0x10 read-write PJREN PJREN Port J Resistor Enable 0x126 16 read-write 0x00000000 0x0000ffff PJREN Port J Resistor Enable 0x0 0x10 read-write PJDS PJDS Port J Drive Strength 0x128 16 read-write PJDS Port J Drive Strength 0x0 0x10 read-write PJSEL0 PJSEL0 Port J Select 0 0x12A 16 read-write 0x00000000 0x0000ffff PJSEL0 Port J Select 0 0x0 0x10 read-write PJSEL1 PJSEL1 Port J Select 1 0x12C 16 read-write 0x00000000 0x0000ffff PJSEL1 Port J Select 1 0x0 0x10 read-write PJSELC PJSELC Port J Complement Select 0x136 16 read-write 0x00000000 0x0000ffff PJSELC Port J Complement Select 0x0 0x10 read-write PMAP 356.0 PMAP 0x40005000 0x0 0x40 registers PMAPKEYID KEYID Port Mapping Key Register 0x0 16 read-write 0x000096a5 0x0000ffff PMAPKEY Port mapping controller write access key 0x0 0x10 read-write PMAPCTL CTL Port Mapping Control Register 0x2 16 read-write 0x00000001 0x0000ffff PMAPLOCKED Port mapping lock bit 0x0 0x1 read-only PMAPLOCKED_enum_read read PMAPLOCKED_0 Access to mapping registers is granted 0 PMAPLOCKED_1 Access to mapping registers is locked 1 PMAPRECFG Port mapping reconfiguration control bit 0x1 0x1 read-write PMAPRECFG_0 Configuration allowed only once 0 PMAPRECFG_1 Allow reconfiguration of port mapping 1 P1MAP01 P1MAP01 Port mapping register, P1.0 and P1.1 0x8 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P1MAP23 P1MAP23 Port mapping register, P1.2 and P1.3 0xA 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P1MAP45 P1MAP45 Port mapping register, P1.4 and P1.5 0xC 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P1MAP67 P1MAP67 Port mapping register, P1.6 and P1.7 0xE 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P2MAP01 P2MAP01 Port mapping register, P2.0 and P2.1 0x10 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P2MAP23 P2MAP23 Port mapping register, P2.2 and P2.3 0x12 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P2MAP45 P2MAP45 Port mapping register, P2.4 and P2.5 0x14 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P2MAP67 P2MAP67 Port mapping register, P2.6 and P2.7 0x16 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P3MAP01 P3MAP01 Port mapping register, P3.0 and P3.1 0x18 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P3MAP23 P3MAP23 Port mapping register, P3.2 and P3.3 0x1A 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P3MAP45 P3MAP45 Port mapping register, P3.4 and P3.5 0x1C 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P3MAP67 P3MAP67 Port mapping register, P3.6 and P3.7 0x1E 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P4MAP01 P4MAP01 Port mapping register, P4.0 and P4.1 0x20 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P4MAP23 P4MAP23 Port mapping register, P4.2 and P4.3 0x22 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P4MAP45 P4MAP45 Port mapping register, P4.4 and P4.5 0x24 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P4MAP67 P4MAP67 Port mapping register, P4.6 and P4.7 0x26 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P5MAP01 P5MAP01 Port mapping register, P5.0 and P5.1 0x28 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P5MAP23 P5MAP23 Port mapping register, P5.2 and P5.3 0x2A 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P5MAP45 P5MAP45 Port mapping register, P5.4 and P5.5 0x2C 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P5MAP67 P5MAP67 Port mapping register, P5.6 and P5.7 0x2E 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P6MAP01 P6MAP01 Port mapping register, P6.0 and P6.1 0x30 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P6MAP23 P6MAP23 Port mapping register, P6.2 and P6.3 0x32 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P6MAP45 P6MAP45 Port mapping register, P6.4 and P6.5 0x34 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P6MAP67 P6MAP67 Port mapping register, P6.6 and P6.7 0x36 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P7MAP01 P7MAP01 Port mapping register, P7.0 and P7.1 0x38 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P7MAP23 P7MAP23 Port mapping register, P7.2 and P7.3 0x3A 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P7MAP45 P7MAP45 Port mapping register, P7.4 and P7.5 0x3C 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write P7MAP67 P7MAP67 Port mapping register, P7.6 and P7.7 0x3E 16 read-write PMAPx Selects secondary port function 0x0 0x10 read-write CAPTIO0 356.0 CAPTIO0 0x40005400 0x0 0x10 registers CAPTIOxCTL CTL Capacitive Touch IO x Control Register 0xE 16 read-write 0x00000000 0x0000ffff CAPTIOPISELx Capacitive Touch IO pin select 0x1 0x3 read-write CAPTIOPISELx_0 Px.0 0 CAPTIOPISELx_1 Px.1 1 CAPTIOPISELx_2 Px.2 2 CAPTIOPISELx_3 Px.3 3 CAPTIOPISELx_4 Px.4 4 CAPTIOPISELx_5 Px.5 5 CAPTIOPISELx_6 Px.6 6 CAPTIOPISELx_7 Px.7 7 CAPTIOPOSELx Capacitive Touch IO port select 0x4 0x4 read-write CAPTIOPOSELx_0 Px = PJ 0 CAPTIOPOSELx_1 Px = P1 1 CAPTIOPOSELx_2 Px = P2 2 CAPTIOPOSELx_3 Px = P3 3 CAPTIOPOSELx_4 Px = P4 4 CAPTIOPOSELx_5 Px = P5 5 CAPTIOPOSELx_6 Px = P6 6 CAPTIOPOSELx_7 Px = P7 7 CAPTIOPOSELx_8 Px = P8 8 CAPTIOPOSELx_9 Px = P9 9 CAPTIOPOSELx_10 Px = P10 10 CAPTIOPOSELx_11 Px = P11 11 CAPTIOPOSELx_12 Px = P12 12 CAPTIOPOSELx_13 Px = P13 13 CAPTIOPOSELx_14 Px = P14 14 CAPTIOPOSELx_15 Px = P15 15 CAPTIOEN Capacitive Touch IO enable 0x8 0x1 read-write CAPTIOEN_0 All Capacitive Touch IOs are disabled. Signal towards timers is 0. 0 CAPTIOEN_1 Selected Capacitive Touch IO is enabled 1 CAPTIOSTATE Capacitive Touch IO state 0x9 0x1 read-only CAPTIOSTATE_enum_read read CAPTIOSTATE_0 Curent state 0 or Capacitive Touch IO is disabled 0 CAPTIOSTATE_1 Current state 1 1 CAPTIO1 356.0 CAPTIO1 0x40005800 0x0 0x10 registers CAPTIOxCTL CTL Capacitive Touch IO x Control Register 0xE 16 read-write 0x00000000 0x0000ffff CAPTIOPISELx Capacitive Touch IO pin select 0x1 0x3 read-write CAPTIOPISELx_0 Px.0 0 CAPTIOPISELx_1 Px.1 1 CAPTIOPISELx_2 Px.2 2 CAPTIOPISELx_3 Px.3 3 CAPTIOPISELx_4 Px.4 4 CAPTIOPISELx_5 Px.5 5 CAPTIOPISELx_6 Px.6 6 CAPTIOPISELx_7 Px.7 7 CAPTIOPOSELx Capacitive Touch IO port select 0x4 0x4 read-write CAPTIOPOSELx_0 Px = PJ 0 CAPTIOPOSELx_1 Px = P1 1 CAPTIOPOSELx_2 Px = P2 2 CAPTIOPOSELx_3 Px = P3 3 CAPTIOPOSELx_4 Px = P4 4 CAPTIOPOSELx_5 Px = P5 5 CAPTIOPOSELx_6 Px = P6 6 CAPTIOPOSELx_7 Px = P7 7 CAPTIOPOSELx_8 Px = P8 8 CAPTIOPOSELx_9 Px = P9 9 CAPTIOPOSELx_10 Px = P10 10 CAPTIOPOSELx_11 Px = P11 11 CAPTIOPOSELx_12 Px = P12 12 CAPTIOPOSELx_13 Px = P13 13 CAPTIOPOSELx_14 Px = P14 14 CAPTIOPOSELx_15 Px = P15 15 CAPTIOEN Capacitive Touch IO enable 0x8 0x1 read-write CAPTIOEN_0 All Capacitive Touch IOs are disabled. Signal towards timers is 0. 0 CAPTIOEN_1 Selected Capacitive Touch IO is enabled 1 CAPTIOSTATE Capacitive Touch IO state 0x9 0x1 read-only CAPTIOSTATE_enum_read read CAPTIOSTATE_0 Curent state 0 or Capacitive Touch IO is disabled 0 CAPTIOSTATE_1 Current state 1 1 TIMER32 356.0 TIMER32 0x4000C000 T32_INT1_IRQ T32_INT1 Interrupt 25 T32_INT2_IRQ T32_INT2 Interrupt 26 T32_INTC_IRQ T32_INTC Interrupt 27 0x0 0xF0C registers T32LOAD1 LOAD1 Timer 1 Load Register 0x0 32 read-write 0x00000000 0xffffffff LOAD The value from which the Timer 1 counter decrements 0x0 0x20 read-write T32VALUE1 VALUE1 Timer 1 Current Value Register 0x4 32 read-only 0xffffffff 0xffffffff VALUE Current value 0x0 0x20 read-only T32CONTROL1 CONTROL1 Timer 1 Timer Control Register 0x8 32 read-write 0x00000020 0xffffffff ONESHOT Selects one-shot or wrapping counter mode 0x0 0x1 read-write ONESHOT_0 wrapping mode 0 ONESHOT_1 one-shot mode 1 SIZE Selects 16 or 32 bit counter operation 0x1 0x1 read-write SIZE_0 16-bit counter 0 SIZE_1 32-bit counter 1 PRESCALE Prescale bits 0x2 0x2 read-write PRESCALE_0 0 stages of prescale, clock is divided by 1 0 PRESCALE_1 4 stages of prescale, clock is divided by 16 1 PRESCALE_2 8 stages of prescale, clock is divided by 256 2 IE Interrupt enable bit 0x5 0x1 read-write IE_0 Timer interrupt disabled 0 IE_1 Timer interrupt enabled 1 MODE Mode bit 0x6 0x1 read-write MODE_0 Timer is in free-running mode 0 MODE_1 Timer is in periodic mode 1 ENABLE Enable bit 0x7 0x1 read-write ENABLE_0 Timer disabled 0 ENABLE_1 Timer enabled 1 T32INTCLR1 INTCLR1 Timer 1 Interrupt Clear Register 0xC 32 write-only 0x00000000 0x00000000 INTCLR Write clears interrupt output 0x0 0x20 write-only T32RIS1 RIS1 Timer 1 Raw Interrupt Status Register 0x10 32 read-only 0x00000000 0xffffffff RAW_IFG Raw interrupt status 0x0 0x1 read-only T32MIS1 MIS1 Timer 1 Interrupt Status Register 0x14 32 read-only 0x00000000 0xffffffff IFG Enabled interrupt status 0x0 0x1 read-only T32BGLOAD1 BGLOAD1 Timer 1 Background Load Register 0x18 32 read-write 0x00000000 0xffffffff BGLOAD Value from which the counter decrements 0x0 0x20 read-write T32LOAD2 LOAD2 Timer 2 Load Register 0x20 32 read-write 0x00000000 0xffffffff LOAD The value from which the Timer 2 counter decrements 0x0 0x20 read-write T32VALUE2 VALUE2 Timer 2 Current Value Register 0x24 32 read-only 0xffffffff 0xffffffff VALUE Current value of the decrementing counter 0x0 0x20 read-only T32CONTROL2 CONTROL2 Timer 2 Timer Control Register 0x28 32 read-write 0x00000020 0xffffffff ONESHOT Selects one-shot or wrapping counter mode 0x0 0x1 read-write ONESHOT_0 wrapping mode 0 ONESHOT_1 one-shot mode 1 SIZE Selects 16 or 32 bit counter operation 0x1 0x1 read-write SIZE_0 16-bit counter 0 SIZE_1 32-bit counter 1 PRESCALE Prescale bits 0x2 0x2 read-write PRESCALE_0 0 stages of prescale, clock is divided by 1 0 PRESCALE_1 4 stages of prescale, clock is divided by 16 1 PRESCALE_2 8 stages of prescale, clock is divided by 256 2 IE Interrupt enable bit 0x5 0x1 read-write IE_0 Timer interrupt disabled 0 IE_1 Timer interrupt enabled 1 MODE Mode bit 0x6 0x1 read-write MODE_0 Timer is in free-running mode 0 MODE_1 Timer is in periodic mode 1 ENABLE Enable bit 0x7 0x1 read-write ENABLE_0 Timer disabled 0 ENABLE_1 Timer enabled 1 T32INTCLR2 INTCLR2 Timer 2 Interrupt Clear Register 0x2C 32 write-only 0x00000000 0x00000000 INTCLR Write clears the interrupt output 0x0 0x20 write-only T32RIS2 RIS2 Timer 2 Raw Interrupt Status Register 0x30 32 read-only 0x00000000 0xffffffff RAW_IFG Raw interrupt status 0x0 0x1 read-only T32MIS2 MIS2 Timer 2 Interrupt Status Register 0x34 32 read-only 0x00000000 0xffffffff IFG Enabled interrupt status 0x0 0x1 read-only T32BGLOAD2 BGLOAD2 Timer 2 Background Load Register 0x38 32 read-write 0x00000000 0xffffffff BGLOAD Value from which the counter decrements 0x0 0x20 read-write DMA 356.0 DMA 0x4000E000 DMA_ERR_IRQ DMA_ERR Interrupt 30 DMA_INT3_IRQ DMA_INT3 Interrupt 31 DMA_INT2_IRQ DMA_INT2 Interrupt 32 DMA_INT1_IRQ DMA_INT1 Interrupt 33 DMA_INT0_IRQ DMA_INT0 Interrupt 34 0x0 0x1050 registers DMA_DEVICE_CFG DEVICE_CFG Device Configuration Status 0x0 32 read-only 0x00000000 0xffff0000 NUM_DMA_CHANNELS Number of DMA channels available 0x0 0x8 read-only NUM_SRC_PER_CHANNEL Number of DMA sources per channel 0x8 0x8 read-only DMA_SW_CHTRIG SW_CHTRIG Software Channel Trigger Register 0x4 32 read-write 0x00000000 0xffffffff CH0 Write 1, triggers DMA_CHANNEL0 0x0 0x1 read-write CH1 Write 1, triggers DMA_CHANNEL1 0x1 0x1 read-write CH2 Write 1, triggers DMA_CHANNEL2 0x2 0x1 read-write CH3 Write 1, triggers DMA_CHANNEL3 0x3 0x1 read-write CH4 Write 1, triggers DMA_CHANNEL4 0x4 0x1 read-write CH5 Write 1, triggers DMA_CHANNEL5 0x5 0x1 read-write CH6 Write 1, triggers DMA_CHANNEL6 0x6 0x1 read-write CH7 Write 1, triggers DMA_CHANNEL7 0x7 0x1 read-write CH8 Write 1, triggers DMA_CHANNEL8 0x8 0x1 read-write CH9 Write 1, triggers DMA_CHANNEL9 0x9 0x1 read-write CH10 Write 1, triggers DMA_CHANNEL10 0xA 0x1 read-write CH11 Write 1, triggers DMA_CHANNEL11 0xB 0x1 read-write CH12 Write 1, triggers DMA_CHANNEL12 0xC 0x1 read-write CH13 Write 1, triggers DMA_CHANNEL13 0xD 0x1 read-write CH14 Write 1, triggers DMA_CHANNEL14 0xE 0x1 read-write CH15 Write 1, triggers DMA_CHANNEL15 0xF 0x1 read-write CH16 Write 1, triggers DMA_CHANNEL16 0x10 0x1 read-write CH17 Write 1, triggers DMA_CHANNEL17 0x11 0x1 read-write CH18 Write 1, triggers DMA_CHANNEL18 0x12 0x1 read-write CH19 Write 1, triggers DMA_CHANNEL19 0x13 0x1 read-write CH20 Write 1, triggers DMA_CHANNEL20 0x14 0x1 read-write CH21 Write 1, triggers DMA_CHANNEL21 0x15 0x1 read-write CH22 Write 1, triggers DMA_CHANNEL22 0x16 0x1 read-write CH23 Write 1, triggers DMA_CHANNEL23 0x17 0x1 read-write CH24 Write 1, triggers DMA_CHANNEL24 0x18 0x1 read-write CH25 Write 1, triggers DMA_CHANNEL25 0x19 0x1 read-write CH26 Write 1, triggers DMA_CHANNEL26 0x1A 0x1 read-write CH27 Write 1, triggers DMA_CHANNEL27 0x1B 0x1 read-write CH28 Write 1, triggers DMA_CHANNEL28 0x1C 0x1 read-write CH29 Write 1, triggers DMA_CHANNEL29 0x1D 0x1 read-write CH30 Write 1, triggers DMA_CHANNEL30 0x1E 0x1 read-write CH31 Write 1, triggers DMA_CHANNEL31 0x1F 0x1 read-write 32 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 DMA_CH_SRCCFG[%s] CH_SRCCFG[%s] Channel n Source Configuration Register 0x10 32 read-write 0x00000000 0xffffffff DMA_SRC Device level DMA source mapping to channel input 0x0 0x8 read-write DMA_INT1_SRCCFG INT1_SRCCFG Interrupt 1 Source Channel Configuration 0x100 32 read-write 0x00000000 0xffffffff INT_SRC Controls which channel's completion event is mapped as a source of this Interrupt 0x0 0x5 read-write EN Enables DMA_INT1 mapping 0x5 0x1 read-write DMA_INT2_SRCCFG INT2_SRCCFG Interrupt 2 Source Channel Configuration Register 0x104 32 read-write 0x00000000 0xffffffff INT_SRC Controls which channel's completion event is mapped as a source of this Interrupt 0x0 0x5 read-write EN Enables DMA_INT2 mapping 0x5 0x1 read-write DMA_INT3_SRCCFG INT3_SRCCFG Interrupt 3 Source Channel Configuration Register 0x108 32 read-write 0x00000000 0xffffffff INT_SRC Controls which channel's completion event is mapped as a source of this Interrupt 0x0 0x5 read-write EN Enables DMA_INT3 mapping 0x5 0x1 read-write DMA_INT0_SRCFLG INT0_SRCFLG Interrupt 0 Source Channel Flag Register 0x110 32 read-only 0x00000000 0xffffffff CH0 Channel 0 was the source of DMA_INT0 0x0 0x1 read-only CH1 Channel 1 was the source of DMA_INT0 0x1 0x1 read-only CH2 Channel 2 was the source of DMA_INT0 0x2 0x1 read-only CH3 Channel 3 was the source of DMA_INT0 0x3 0x1 read-only CH4 Channel 4 was the source of DMA_INT0 0x4 0x1 read-only CH5 Channel 5 was the source of DMA_INT0 0x5 0x1 read-only CH6 Channel 6 was the source of DMA_INT0 0x6 0x1 read-only CH7 Channel 7 was the source of DMA_INT0 0x7 0x1 read-only CH8 Channel 8 was the source of DMA_INT0 0x8 0x1 read-only CH9 Channel 9 was the source of DMA_INT0 0x9 0x1 read-only CH10 Channel 10 was the source of DMA_INT0 0xA 0x1 read-only CH11 Channel 11 was the source of DMA_INT0 0xB 0x1 read-only CH12 Channel 12 was the source of DMA_INT0 0xC 0x1 read-only CH13 Channel 13 was the source of DMA_INT0 0xD 0x1 read-only CH14 Channel 14 was the source of DMA_INT0 0xE 0x1 read-only CH15 Channel 15 was the source of DMA_INT0 0xF 0x1 read-only CH16 Channel 16 was the source of DMA_INT0 0x10 0x1 read-only CH17 Channel 17 was the source of DMA_INT0 0x11 0x1 read-only CH18 Channel 18 was the source of DMA_INT0 0x12 0x1 read-only CH19 Channel 19 was the source of DMA_INT0 0x13 0x1 read-only CH20 Channel 20 was the source of DMA_INT0 0x14 0x1 read-only CH21 Channel 21 was the source of DMA_INT0 0x15 0x1 read-only CH22 Channel 22 was the source of DMA_INT0 0x16 0x1 read-only CH23 Channel 23 was the source of DMA_INT0 0x17 0x1 read-only CH24 Channel 24 was the source of DMA_INT0 0x18 0x1 read-only CH25 Channel 25 was the source of DMA_INT0 0x19 0x1 read-only CH26 Channel 26 was the source of DMA_INT0 0x1A 0x1 read-only CH27 Channel 27 was the source of DMA_INT0 0x1B 0x1 read-only CH28 Channel 28 was the source of DMA_INT0 0x1C 0x1 read-only CH29 Channel 29 was the source of DMA_INT0 0x1D 0x1 read-only CH30 Channel 30 was the source of DMA_INT0 0x1E 0x1 read-only CH31 Channel 31 was the source of DMA_INT0 0x1F 0x1 read-only DMA_INT0_CLRFLG INT0_CLRFLG Interrupt 0 Source Channel Clear Flag Register 0x114 32 write-only 0x00000000 0x00000000 CH0 Clear corresponding DMA_INT0_SRCFLG_REG 0x0 0x1 write-only CH1 Clear corresponding DMA_INT0_SRCFLG_REG 0x1 0x1 write-only CH2 Clear corresponding DMA_INT0_SRCFLG_REG 0x2 0x1 write-only CH3 Clear corresponding DMA_INT0_SRCFLG_REG 0x3 0x1 write-only CH4 Clear corresponding DMA_INT0_SRCFLG_REG 0x4 0x1 write-only CH5 Clear corresponding DMA_INT0_SRCFLG_REG 0x5 0x1 write-only CH6 Clear corresponding DMA_INT0_SRCFLG_REG 0x6 0x1 write-only CH7 Clear corresponding DMA_INT0_SRCFLG_REG 0x7 0x1 write-only CH8 Clear corresponding DMA_INT0_SRCFLG_REG 0x8 0x1 write-only CH9 Clear corresponding DMA_INT0_SRCFLG_REG 0x9 0x1 write-only CH10 Clear corresponding DMA_INT0_SRCFLG_REG 0xA 0x1 write-only CH11 Clear corresponding DMA_INT0_SRCFLG_REG 0xB 0x1 write-only CH12 Clear corresponding DMA_INT0_SRCFLG_REG 0xC 0x1 write-only CH13 Clear corresponding DMA_INT0_SRCFLG_REG 0xD 0x1 write-only CH14 Clear corresponding DMA_INT0_SRCFLG_REG 0xE 0x1 write-only CH15 Clear corresponding DMA_INT0_SRCFLG_REG 0xF 0x1 write-only CH16 Clear corresponding DMA_INT0_SRCFLG_REG 0x10 0x1 write-only CH17 Clear corresponding DMA_INT0_SRCFLG_REG 0x11 0x1 write-only CH18 Clear corresponding DMA_INT0_SRCFLG_REG 0x12 0x1 write-only CH19 Clear corresponding DMA_INT0_SRCFLG_REG 0x13 0x1 write-only CH20 Clear corresponding DMA_INT0_SRCFLG_REG 0x14 0x1 write-only CH21 Clear corresponding DMA_INT0_SRCFLG_REG 0x15 0x1 write-only CH22 Clear corresponding DMA_INT0_SRCFLG_REG 0x16 0x1 write-only CH23 Clear corresponding DMA_INT0_SRCFLG_REG 0x17 0x1 write-only CH24 Clear corresponding DMA_INT0_SRCFLG_REG 0x18 0x1 write-only CH25 Clear corresponding DMA_INT0_SRCFLG_REG 0x19 0x1 write-only CH26 Clear corresponding DMA_INT0_SRCFLG_REG 0x1A 0x1 write-only CH27 Clear corresponding DMA_INT0_SRCFLG_REG 0x1B 0x1 write-only CH28 Clear corresponding DMA_INT0_SRCFLG_REG 0x1C 0x1 write-only CH29 Clear corresponding DMA_INT0_SRCFLG_REG 0x1D 0x1 write-only CH30 Clear corresponding DMA_INT0_SRCFLG_REG 0x1E 0x1 write-only CH31 Clear corresponding DMA_INT0_SRCFLG_REG 0x1F 0x1 write-only DMA_STAT STAT Status Register 0x1000 32 read-only 0x00000000 0x0f00ffff MASTEN Enable status of the controller 0x0 0x1 read-only MASTEN_enum_read read MASTEN_0 Controller disabled 0 MASTEN_1 Controller enabled 1 STATE Current state of the control state machine. State can be one of the following: 0x4 0x4 read-only STATE_enum_read read STATE_0 idle 0 STATE_1 reading channel controller data 1 STATE_2 reading source data end pointer 2 STATE_3 reading destination data end pointer 3 STATE_4 reading source data 4 STATE_5 writing destination data 5 STATE_6 waiting for DMA request to clear 6 STATE_7 writing channel controller data 7 STATE_8 stalled 8 STATE_9 done 9 STATE_10 peripheral scatter-gather transition 10 DMACHANS Number of available DMA channels minus one. 0x10 0x5 read-only DMACHANS_enum_read read DMACHANS_0 Controller configured to use 1 DMA channel 0 DMACHANS_1 Controller configured to use 2 DMA channels 1 DMACHANS_30 Controller configured to use 31 DMA channels 30 DMACHANS_31 Controller configured to use 32 DMA channels 31 TESTSTAT To reduce the gate count the controller can be configured to exclude the integration test logic. The values 2h to Fh are Reserved. 0x1C 0x4 read-only TESTSTAT_enum_read read TESTSTAT_0 Controller does not include the integration test logic 0 TESTSTAT_1 Controller includes the integration test logic 1 DMA_CFG CFG Configuration Register 0x1004 32 write-only 0x00000000 0x00000000 MASTEN Enable status of the controller 0x0 0x1 write-only MASTEN_enum_write write MASTEN_0 Controller disabled 0 MASTEN_1 Controller enabled 1 CHPROTCTRL Sets the AHB-Lite protection by controlling the HPROT[3:1] signal levels as follows: Bit [7] Controls HPROT[3] to indicate if a cacheable access is occurring. Bit [6] Controls HPROT[2] to indicate if a bufferable access is occurring. Bit [5] Controls HPROT[1] to indicate if a privileged access is occurring. Note: When bit [n] = 1 then the corresponding HPROT is HIGH. When bit [n] = 0 then the corresponding HPROT is LOW. 0x5 0x3 write-only DMA_CTLBASE CTLBASE Channel Control Data Base Pointer Register 0x1008 32 read-write 0x00000000 0xffffffff ADDR Pointer to the base address of the primary data structure. 0x5 0x1B read-write DMA_ALTBASE ALTBASE Channel Alternate Control Data Base Pointer Register 0x100C 32 read-only 0x00000000 0xffffff00 ADDR Base address of the alternate data structure 0x0 0x20 read-only DMA_WAITSTAT WAITSTAT Channel Wait on Request Status Register 0x1010 32 read-only 0x00000000 0xffffffff WAITREQ Channel wait on request status. 0x0 0x20 read-only WAITREQ_enum_read read WAITREQ_0 dma_waitonreq[C] is LOW. 0 WAITREQ_1 dma_waitonreq[C] is HIGH. 1 DMA_SWREQ SWREQ Channel Software Request Register 0x1014 32 write-only 0x00000000 0x00000000 CHNL_SW_REQ Set the appropriate bit to generate a software DMA request on the corresponding DMA channel. Writing to a bit where a DMA channel is not implemented does not create a DMA request for that channel. 0x0 0x20 write-only CHNL_SW_REQ_enum_write write CHNL_SW_REQ_0 Does not create a DMA request for the channel 0 CHNL_SW_REQ_1 Creates a DMA request for the channel 1 DMA_USEBURSTSET USEBURSTSET Channel Useburst Set Register 0x1018 32 read-write 0x00000000 0xffffffff SET Returns the useburst status, or disables dma_sreq from generating DMA requests. 0x0 0x20 read-write SET_enum_read read SET_0_READ DMA channel C responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2R, or single, bus transfers. 0 SET_1_READ DMA channel C does not respond to requests that it receives on dma_sreq[C]. The controller only responds to dma_req[C] requests and performs 2R transfers. 1 SET_enum_write write SET_0_WRITE No effect. Use the DMA_USEBURST_CLR Register to set bit [C] to 0. 0 SET_1_WRITE Disables dma_sreq[C] from generating DMA requests. The controller performs 2R transfers. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_USEBURSTCLR USEBURSTCLR Channel Useburst Clear Register 0x101C 32 write-only 0x00000000 0x00000000 CLR Set the appropriate bit to enable dma_sreq to generate requests. 0x0 0x20 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests. 0 CLR_1 Enables dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_REQMASKSET REQMASKSET Channel Request Mask Set Register 0x1020 32 read-write 0x00000000 0xffffffff SET Returns the request mask status of dma_req and dma_sreq, or disables the corresponding channel from generating DMA requests. 0x0 0x20 read-write SET_enum_read read SET_0_READ External requests are enabled for channel C. 0 SET_1_READ External requests are disabled for channel C. 1 SET_enum_write write SET_0_WRITE No effect. Use the DMA_REQMASKCLR Register to enable DMA requests. 0 SET_1_WRITE Disables dma_req[C] and dma_sreq[C] from generating DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_REQMASKCLR REQMASKCLR Channel Request Mask Clear Register 0x1024 32 write-only 0x00000000 0x00000000 CLR Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req and dma_sreq. 0x0 0x20 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_REQMASKSET Register to disable dma_req and dma_sreq from generating requests. 0 CLR_1 Enables dma_req[C] or dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_ENASET ENASET Channel Enable Set Register 0x1028 32 read-write 0x00000000 0xffffffff SET Returns the enable status of the channels, or enables the corresponding channels. 0x0 0x20 read-write SET_enum_read read SET_0_READ Channel C is disabled. 0 SET_1_READ Channel C is enabled. 1 SET_enum_write write SET_0_WRITE No effect. Use the DMA_ENACLR Register to disable a channel. 0 SET_1_WRITE Enables channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_ENACLR ENACLR Channel Enable Clear Register 0x102C 32 write-only 0x00000000 0x00000000 CLR Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus. 0x0 0x20 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_ENASET Register to enable DMA channels. 0 CLR_1 Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_ALTSET ALTSET Channel Primary-Alternate Set Register 0x1030 32 read-write 0x00000000 0xffffffff SET Channel Primary-Alternate Set Register 0x0 0x20 read-write SET_enum_read read SET_0_READ DMA channel C is using the primary data structure. 0 SET_1_READ DMA channel C is using the alternate data structure. 1 SET_enum_write write SEL_0_WRITE No effect. Use the DMA_ALTCLR Register to set bit [C] to 0. 0 SEL_1_WRITE Selects the alternate data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_ALTCLR ALTCLR Channel Primary-Alternate Clear Register 0x1034 32 write-only 0x00000000 0x00000000 CLR Channel Primary-Alternate Clear Register 0x0 0x20 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_ALTSET Register to select the alternate data structure. 0 CLR_1 Selects the primary data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_PRIOSET PRIOSET Channel Priority Set Register 0x1038 32 read-write 0x00000000 0xffffffff SET Returns the channel priority mask status, or sets the channel priority to high. 0x0 0x20 read-write SET_enum_read read SET_0_READ DMA channel C is using the default priority level. 0 SET_1_READ DMA channel C is using a high priority level. 1 SET_enum_write write SET_0_WRITE No effect. Use the DMA_PRIOCLR Register to set channel C to the default priority level. 0 SET_1_WRITE Channel C uses the high priority level. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_PRIOCLR PRIOCLR Channel Priority Clear Register 0x103C 32 write-only 0x00000000 0x00000000 CLR Set the appropriate bit to select the default priority level for the specified DMA channel. 0x0 0x20 write-only CLR_enum_write write CLR_0 No effect. Use the DMA_PRIOSET Register to set channel C to the high priority level. 0 CLR_1 Channel C uses the default priority level. Writing to a bit where a DMA channel is not implemented has no effect. 1 DMA_ERRCLR ERRCLR Bus Error Clear Register 0x104C 32 read-write 0x00000000 0xffffffff ERRCLR Returns the status of dma_err, or sets the signal LOW. For test purposes, use the ERRSET register to set dma_err HIGH. Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted. 0x0 0x1 read-write ERRCLR_enum_read read ERRCLR_0_READ dma_err is LOW 0 ERRCLR_1_READ dma_err is HIGH. 1 ERRCLR_enum_write write ERRCLR_0_WRITE No effect, status of dma_err is unchanged. 0 ERRCLR_1_WRITE Sets dma_err LOW. 1 PCM 356.0 PCM 0x40010000 PCM_IRQ PCM Interrupt 2 0x0 0x14 registers PCMCTL0 CTL0 Control 0 Register 0x0 32 read-write 0xa5960000 0xffffffff AMR Active Mode Request 0x0 0x4 read-write AMR_0 LDO based Active Mode at Core voltage setting 0. 0 AMR_1 LDO based Active Mode at Core voltage setting 1. 1 AMR_4 DC-DC based Active Mode at Core voltage setting 0. 4 AMR_5 DC-DC based Active Mode at Core voltage setting 1. 5 AMR_8 Low-Frequency Active Mode at Core voltage setting 0. 8 AMR_9 Low-Frequency Active Mode at Core voltage setting 1. 9 LPMR Low Power Mode Request 0x4 0x4 read-write LPMR_0 LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. 0 LPMR_10 LPM3.5. Core voltage setting 0. 10 LPMR_12 LPM4.5 12 CPM Current Power Mode 0x8 0x6 read-only CPM_enum_read read CPM_0 LDO based Active Mode at Core voltage setting 0. 0 CPM_1 LDO based Active Mode at Core voltage setting 1. 1 CPM_4 DC-DC based Active Mode at Core voltage setting 0. 4 CPM_5 DC-DC based Active Mode at Core voltage setting 1. 5 CPM_8 Low-Frequency Active Mode at Core voltage setting 0. 8 CPM_9 Low-Frequency Active Mode at Core voltage setting 1. 9 CPM_16 LDO based LPM0 at Core voltage setting 0. 16 CPM_17 LDO based LPM0 at Core voltage setting 1. 17 CPM_20 DC-DC based LPM0 at Core voltage setting 0. 20 CPM_21 DC-DC based LPM0 at Core voltage setting 1. 21 CPM_24 Low-Frequency LPM0 at Core voltage setting 0. 24 CPM_25 Low-Frequency LPM0 at Core voltage setting 1. 25 CPM_32 LPM3 32 PCMKEY PCM key 0x10 0x10 read-write PCMCTL1 CTL1 Control 1 Register 0x4 32 read-write 0xa5960000 0xffffffff LOCKLPM5 Lock LPM5 0x0 0x1 read-write LOCKLPM5_0 LPMx.5 configuration defaults to reset condition 0 LOCKLPM5_1 LPMx.5 configuration remains locked during LPMx.5 entry and exit 1 LOCKBKUP Lock Backup 0x1 0x1 read-write LOCKBKUP_0 Backup domain configuration defaults to reset condition 0 LOCKBKUP_1 Backup domain configuration remains locked during LPM3.5 entry and exit 1 FORCE_LPM_ENTRY Force LPM entry 0x2 0x1 read-write FORCE_LPM_ENTRY_0 PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry. 0 FORCE_LPM_ENTRY_1 PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off. 1 PMR_BUSY Power mode request busy flag 0x8 0x1 read-write PCMKEY PCM key 0x10 0x10 read-write PCMIE IE Interrupt Enable Register 0x8 32 read-write 0x00000000 0xffffffff LPM_INVALID_TR_IE LPM invalid transition interrupt enable 0x0 0x1 read-write LPM_INVALID_TR_IE_0 Disabled 0 LPM_INVALID_TR_IE_1 Enabled 1 LPM_INVALID_CLK_IE LPM invalid clock interrupt enable 0x1 0x1 read-write LPM_INVALID_CLK_IE_0 Disabled 0 LPM_INVALID_CLK_IE_1 Enabled 1 AM_INVALID_TR_IE Active mode invalid transition interrupt enable 0x2 0x1 read-write AM_INVALID_TR_IE_0 Disabled 0 AM_INVALID_TR_IE_1 Enabled 1 DCDC_ERROR_IE DC-DC error interrupt enable 0x6 0x1 read-write DCDC_ERROR_IE_0 Disabled 0 DCDC_ERROR_IE_1 Enabled 1 PCMIFG IFG Interrupt Flag Register 0xC 32 read-only 0x00000000 0xffffffff LPM_INVALID_TR_IFG LPM invalid transition flag 0x0 0x1 read-only LPM_INVALID_CLK_IFG LPM invalid clock flag 0x1 0x1 read-only AM_INVALID_TR_IFG Active mode invalid transition flag 0x2 0x1 read-only DCDC_ERROR_IFG DC-DC error flag 0x6 0x1 read-only PCMCLRIFG CLRIFG Clear Interrupt Flag Register 0x10 32 write-only 0x00000000 0xffffffff CLR_LPM_INVALID_TR_IFG Clear LPM invalid transition flag 0x0 0x1 write-only CLR_LPM_INVALID_CLK_IFG Clear LPM invalid clock flag 0x1 0x1 write-only CLR_AM_INVALID_TR_IFG Clear active mode invalid transition flag 0x2 0x1 write-only CLR_DCDC_ERROR_IFG Clear DC-DC error flag 0x6 0x1 write-only CS 356.0 CS 0x40010400 CS_IRQ CS Interrupt 1 0x0 0x68 registers CSKEY KEY Key Register 0x0 32 read-write 0x0000a596 CSKEY Write xxxx_695Ah to unlock 0x0 0x10 read-write CSCTL0 CTL0 Control 0 Register 0x4 32 read-write 0x00010000 DCOTUNE DCO frequency tuning select 0x0 0xA read-write DCORSEL DCO frequency range select 0x10 0x3 read-write DCORSEL_0 Nominal DCO Frequency Range (MHz): 1 to 2 0 DCORSEL_1 Nominal DCO Frequency Range (MHz): 2 to 4 1 DCORSEL_2 Nominal DCO Frequency Range (MHz): 4 to 8 2 DCORSEL_3 Nominal DCO Frequency Range (MHz): 8 to 16 3 DCORSEL_4 Nominal DCO Frequency Range (MHz): 16 to 32 4 DCORSEL_5 Nominal DCO Frequency Range (MHz): 32 to 64 5 DCORES Enables the DCO external resistor mode 0x16 0x1 read-write DCORES_0 Internal resistor mode 0 DCORES_1 External resistor mode 1 DCOEN Enables the DCO oscillator 0x17 0x1 read-write DCOEN_0 DCO is on if it is used as a source for MCLK, HSMCLK , or SMCLK and clock is requested, otherwise it is disabled. 0 DCOEN_1 DCO is on 1 CSCTL1 CTL1 Control 1 Register 0x8 32 read-write 0x00000033 SELM Selects the MCLK source 0x0 0x3 read-write SELM_0 when LFXT available, otherwise REFOCLK 0 SELM_1 1 SELM_2 2 SELM_3 3 SELM_4 4 SELM_5 when HFXT available, otherwise DCOCLK 5 SELM_6 when HFXT2 available, otherwise DCOCLK 6 SELM_7 for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities. 7 SELS Selects the SMCLK and HSMCLK source 0x4 0x3 read-write SELS_0 when LFXT available, otherwise REFOCLK 0 SELS_1 1 SELS_2 2 SELS_3 3 SELS_4 4 SELS_5 when HFXT available, otherwise DCOCLK 5 SELS_6 when HFXT2 available, otherwise DCOCLK 6 SELS_7 for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities. 7 SELA Selects the ACLK source 0x8 0x3 read-write SELA_0 when LFXT available, otherwise REFOCLK 0 SELA_1 1 SELA_2 2 SELA_3 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 3 SELA_4 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 4 SELA_5 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 5 SELA_6 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 6 SELA_7 for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. 7 SELB Selects the BCLK source 0xC 0x1 read-write SELB_0 LFXTCLK 0 SELB_1 REFOCLK 1 DIVM MCLK source divider 0x10 0x3 read-write DIVM_0 f(MCLK)/1 0 DIVM_1 f(MCLK)/2 1 DIVM_2 f(MCLK)/4 2 DIVM_3 f(MCLK)/8 3 DIVM_4 f(MCLK)/16 4 DIVM_5 f(MCLK)/32 5 DIVM_6 f(MCLK)/64 6 DIVM_7 f(MCLK)/128 7 DIVHS HSMCLK source divider 0x14 0x3 read-write DIVHS_0 f(HSMCLK)/1 0 DIVHS_1 f(HSMCLK)/2 1 DIVHS_2 f(HSMCLK)/4 2 DIVHS_3 f(HSMCLK)/8 3 DIVHS_4 f(HSMCLK)/16 4 DIVHS_5 f(HSMCLK)/32 5 DIVHS_6 f(HSMCLK)/64 6 DIVHS_7 f(HSMCLK)/128 7 DIVA ACLK source divider 0x18 0x3 read-write DIVA_0 f(ACLK)/1 0 DIVA_1 f(ACLK)/2 1 DIVA_2 f(ACLK)/4 2 DIVA_3 f(ACLK)/8 3 DIVA_4 f(ACLK)/16 4 DIVA_5 f(ACLK)/32 5 DIVA_6 f(ACLK)/64 6 DIVA_7 f(ACLK)/128 7 DIVS SMCLK source divider 0x1C 0x3 read-write DIVS_0 f(SMCLK)/1 0 DIVS_1 f(SMCLK)/2 1 DIVS_2 f(SMCLK)/4 2 DIVS_3 f(SMCLK)/8 3 DIVS_4 f(SMCLK)/16 4 DIVS_5 f(SMCLK)/32 5 DIVS_6 f(SMCLK)/64 6 DIVS_7 f(SMCLK)/128 7 CSCTL2 CTL2 Control 2 Register 0xC 32 read-write 0x00010003 LFXTDRIVE LFXT oscillator current can be adjusted to its drive needs 0x0 0x2 read-write LFXTDRIVE_0 Lowest drive strength and current consumption LFXT oscillator. 0 LFXTDRIVE_1 Increased drive strength LFXT oscillator. 1 LFXTDRIVE_2 Increased drive strength LFXT oscillator. 2 LFXTDRIVE_3 Maximum drive strength and maximum current consumption LFXT oscillator. 3 LFXTAGCOFF Disables the automatic gain control of the LFXT crystal 0x7 0x1 read-write LFXTAGCOFF_0 AGC enabled. 0 LFXTAGCOFF_1 AGC disabled. 1 LFXT_EN Turns on the LFXT oscillator regardless if used as a clock resource 0x8 0x1 read-write LFXT_EN_0 LFXT is on if it is used as a source for ACLK, MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation. 0 LFXT_EN_1 LFXT is on if LFXT is selected via the port selection and LFXT is not in bypass mode of operation. 1 LFXTBYPASS LFXT bypass select 0x9 0x1 read-write LFXTBYPASS_0 LFXT sourced by external crystal. 0 LFXTBYPASS_1 LFXT sourced by external square wave. 1 HFXTDRIVE HFXT oscillator drive selection 0x10 0x1 read-write HFXTDRIVE_0 To be used for HFXTFREQ setting 000b 0 HFXTDRIVE_1 To be used for HFXTFREQ settings 001b to 110b 1 HFXTFREQ HFXT frequency selection 0x14 0x3 read-write HFXTFREQ_0 1 MHz to 4 MHz 0 HFXTFREQ_1 >4 MHz to 8 MHz 1 HFXTFREQ_2 >8 MHz to 16 MHz 2 HFXTFREQ_3 >16 MHz to 24 MHz 3 HFXTFREQ_4 >24 MHz to 32 MHz 4 HFXTFREQ_5 >32 MHz to 40 MHz 5 HFXTFREQ_6 >40 MHz to 48 MHz 6 HFXT_EN Turns on the HFXT oscillator regardless if used as a clock resource 0x18 0x1 read-write HFXT_EN_0 HFXT is on if it is used as a source for MCLK, HSMCLK , or SMCLK and is selected via the port selection and not in bypass mode of operation. 0 HFXT_EN_1 HFXT is on if HFXT is selected via the port selection and HFXT is not in bypass mode of operation. 1 HFXTBYPASS HFXT bypass select 0x19 0x1 read-write HFXTBYPASS_0 HFXT sourced by external crystal. 0 HFXTBYPASS_1 HFXT sourced by external square wave. 1 CSCTL3 CTL3 Control 3 Register 0x10 32 read-write 0x00000bbb 0xffffffff FCNTLF Start flag counter for LFXT 0x0 0x2 read-write FCNTLF_0 4096 cycles 0 FCNTLF_1 8192 cycles 1 FCNTLF_2 16384 cycles 2 FCNTLF_3 32768 cycles 3 RFCNTLF Reset start fault counter for LFXT 0x2 0x1 write-only RFCNTLF_enum_write write RFCNTLF_0 Not applicable. Always reads as zero due to self clearing. 0 RFCNTLF_1 Restarts the counter immediately. 1 FCNTLF_EN Enable start fault counter for LFXT 0x3 0x1 read-write FCNTLF_EN_0 Startup fault counter disabled. Counter is cleared. 0 FCNTLF_EN_1 Startup fault counter enabled. 1 FCNTHF Start flag counter for HFXT 0x4 0x2 read-write FCNTHF_0 2048 cycles 0 FCNTHF_1 4096 cycles 1 FCNTHF_2 8192 cycles 2 FCNTHF_3 16384 cycles 3 RFCNTHF Reset start fault counter for HFXT 0x6 0x1 write-only RFCNTHF_enum_write write RFCNTHF_0 Not applicable. Always reads as zero due to self clearing. 0 RFCNTHF_1 Restarts the counter immediately. 1 FCNTHF_EN Enable start fault counter for HFXT 0x7 0x1 read-write FCNTHF_EN_0 Startup fault counter disabled. Counter is cleared. 0 FCNTHF_EN_1 Startup fault counter enabled. 1 FCNTHF2 Start flag counter for HFXT2 0x8 0x2 read-write FCNTHF2_0 2048 cycles 0 FCNTHF2_1 4096 cycles 1 FCNTHF2_2 8192 cycles 2 FCNTHF2_3 16384 cycles 3 RFCNTHF2 Reset start fault counter for HFXT2 0xA 0x1 write-only RFCNTHF2_enum_write write RFCNTHF2_0 Not applicable. Always reads as zero due to self clearing. 0 RFCNTHF2_1 Restarts the counter immediately. 1 FCNTHF2_EN Enable start fault counter for HFXT2 0xB 0x1 read-write FCNTHF2_EN_0 Startup fault counter disabled. Counter is cleared. 0 FCNTHF2_EN_1 Startup fault counter enabled. 1 CSCLKEN CLKEN Clock Enable Register 0x30 32 read-write 0x0000000f 0xffff847f ACLK_EN ACLK system clock conditional request enable 0x0 0x1 read-write ACLK_EN_0 ACLK disabled regardless of conditional clock requests 0 ACLK_EN_1 ACLK enabled based on any conditional clock requests 1 MCLK_EN MCLK system clock conditional request enable 0x1 0x1 read-write MCLK_EN_0 MCLK disabled regardless of conditional clock requests 0 MCLK_EN_1 MCLK enabled based on any conditional clock requests 1 HSMCLK_EN HSMCLK system clock conditional request enable 0x2 0x1 read-write HSMCLK_EN_0 HSMCLK disabled regardless of conditional clock requests 0 HSMCLK_EN_1 HSMCLK enabled based on any conditional clock requests 1 SMCLK_EN SMCLK system clock conditional request enable 0x3 0x1 read-write SMCLK_EN_0 SMCLK disabled regardless of conditional clock requests. 0 SMCLK_EN_1 SMCLK enabled based on any conditional clock requests 1 VLO_EN Turns on the VLO oscillator 0x8 0x1 read-write VLO_EN_0 VLO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK. 0 VLO_EN_1 VLO is on 1 REFO_EN Turns on the REFO oscillator 0x9 0x1 read-write REFO_EN_0 REFO is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK 0 REFO_EN_1 REFO is on 1 MODOSC_EN Turns on the MODOSC oscillator 0xA 0x1 read-write MODOSC_EN_0 MODOSC is on only if it is used as a source for ACLK, MCLK, HSMCLK or SMCLK 0 MODOSC_EN_1 MODOSC is on 1 REFOFSEL Selects REFO nominal frequency 0xF 0x1 read-write REFOFSEL_0 32 kHz 0 REFOFSEL_1 128 kHz 1 CSSTAT STAT Status Register 0x34 32 read-only 0x00000003 0xffff01ff DCO_ON DCO status 0x0 0x1 read-only DCO_ON_enum_read read DCO_ON_0 Inactive 0 DCO_ON_1 Active 1 DCOBIAS_ON DCO bias status 0x1 0x1 read-only DCOBIAS_ON_enum_read read DCOBIAS_ON_0 Inactive 0 DCOBIAS_ON_1 Active 1 HFXT_ON HFXT status 0x2 0x1 read-only HFXT_ON_enum_read read HFXT_ON_0 Inactive 0 HFXT_ON_1 Active 1 HFXT2_ON HFXT2 status 0x3 0x1 read-only HFXT2_ON_enum_read read HFXT2_ON_0 Inactive 0 HFXT2_ON_1 Active 1 MODOSC_ON MODOSC status 0x4 0x1 read-only MODOSC_ON_enum_read read MODOSC_ON_0 Inactive 0 MODOSC_ON_1 Active 1 VLO_ON VLO status 0x5 0x1 read-only VLO_ON_enum_read read VLO_ON_0 Inactive 0 VLO_ON_1 Active 1 LFXT_ON LFXT status 0x6 0x1 read-only LFXT_ON_enum_read read LFXT_ON_0 Inactive 0 LFXT_ON_1 Active 1 REFO_ON REFO status 0x7 0x1 read-only REFO_ON_enum_read read REFO_ON_0 Inactive 0 REFO_ON_1 Active 1 ACLK_ON ACLK system clock status 0x10 0x1 read-only ACLK_ON_enum_read read ACLK_ON_0 Inactive 0 ACLK_ON_1 Active 1 MCLK_ON MCLK system clock status 0x11 0x1 read-only MCLK_ON_enum_read read MCLK_ON_0 Inactive 0 MCLK_ON_1 Active 1 HSMCLK_ON HSMCLK system clock status 0x12 0x1 read-only HSMCLK_ON_enum_read read HSMCLK_ON_0 Inactive 0 HSMCLK_ON_1 Active 1 SMCLK_ON SMCLK system clock status 0x13 0x1 read-only SMCLK_ON_enum_read read SMCLK_ON_0 Inactive 0 SMCLK_ON_1 Active 1 MODCLK_ON MODCLK system clock status 0x14 0x1 read-only MODCLK_ON_enum_read read MODCLK_ON_0 Inactive 0 MODCLK_ON_1 Active 1 VLOCLK_ON VLOCLK system clock status 0x15 0x1 read-only VLOCLK_ON_enum_read read VLOCLK_ON_0 Inactive 0 VLOCLK_ON_1 Active 1 LFXTCLK_ON LFXTCLK system clock status 0x16 0x1 read-only LFXTCLK_ON_enum_read read LFXTCLK_ON_0 Inactive 0 LFXTCLK_ON_1 Active 1 REFOCLK_ON REFOCLK system clock status 0x17 0x1 read-only REFOCLK_ON_enum_read read REFOCLK_ON_0 Inactive 0 REFOCLK_ON_1 Active 1 ACLK_READY ACLK Ready status 0x18 0x1 read-only ACLK_READY_enum_read read ACLK_READY_0 Not ready 0 ACLK_READY_1 Ready 1 MCLK_READY MCLK Ready status 0x19 0x1 read-only MCLK_READY_enum_read read MCLK_READY_0 Not ready 0 MCLK_READY_1 Ready 1 HSMCLK_READY HSMCLK Ready status 0x1A 0x1 read-only HSMCLK_READY_enum_read read HSMCLK_READY_0 Not ready 0 HSMCLK_READY_1 Ready 1 SMCLK_READY SMCLK Ready status 0x1B 0x1 read-only SMCLK_READY_enum_read read SMCLK_READY_0 Not ready 0 SMCLK_READY_1 Ready 1 BCLK_READY BCLK Ready status 0x1C 0x1 read-only BCLK_READY_enum_read read BCLK_READY_0 Not ready 0 BCLK_READY_1 Ready 1 CSIE IE Interrupt Enable Register 0x40 32 read-write 0x00000000 0xffffffff LFXTIE LFXT oscillator fault flag interrupt enable 0x0 0x1 read-write LFXTIE_0 Interrupt disabled 0 LFXTIE_1 Interrupt enabled 1 HFXTIE HFXT oscillator fault flag interrupt enable 0x1 0x1 read-write HFXTIE_0 Interrupt disabled 0 HFXTIE_1 Interrupt enabled 1 HFXT2IE HFXT2 oscillator fault flag interrupt enable 0x2 0x1 read-write HFXT2IE_0 Interrupt disabled 0 HFXT2IE_1 Interrupt enabled 1 DCOR_OPNIE DCO external resistor open circuit fault flag interrupt enable. 0x6 0x1 read-write DCOR_OPNIE_0 Interrupt disabled 0 DCOR_OPNIE_1 Interrupt enabled 1 FCNTLFIE Start fault counter interrupt enable LFXT 0x8 0x1 read-write FCNTLFIE_0 Interrupt disabled 0 FCNTLFIE_1 Interrupt enabled 1 FCNTHFIE Start fault counter interrupt enable HFXT 0x9 0x1 read-write FCNTHFIE_0 Interrupt disabled 0 FCNTHFIE_1 Interrupt enabled 1 FCNTHF2IE Start fault counter interrupt enable HFXT2 0xA 0x1 read-write FCNTHF2IE_0 Interrupt disabled 0 FCNTHF2IE_1 Interrupt enabled 1 PLLOOLIE PLL out-of-lock interrupt enable 0xC 0x1 read-write PLLOOLIE_0 Interrupt disabled 0 PLLOOLIE_1 Interrupt enabled 1 PLLLOSIE PLL loss-of-signal interrupt enable 0xD 0x1 read-write PLLLOSIE_0 Interrupt disabled 0 PLLLOSIE_1 Interrupt enabled 1 PLLOORIE PLL out-of-range interrupt enable 0xE 0x1 read-write PLLOORIE_0 Interrupt disabled 0 PLLOORIE_1 Interrupt enabled 1 CALIE REFCNT period counter interrupt enable 0xF 0x1 read-write CALIE_0 Interrupt disabled 0 CALIE_1 Interrupt enabled 1 CSIFG IFG Interrupt Flag Register 0x48 32 read-only 0x00000001 0xffffffff LFXTIFG LFXT oscillator fault flag 0x0 0x1 read-only LFXTIFG_enum_read read LFXTIFG_0 No fault condition occurred after the last reset 0 LFXTIFG_1 LFXT fault. A LFXT fault occurred after the last reset 1 HFXTIFG HFXT oscillator fault flag 0x1 0x1 read-only HFXTIFG_enum_read read HFXTIFG_0 No fault condition occurred after the last reset 0 HFXTIFG_1 HFXT fault. A HFXT fault occurred after the last reset 1 HFXT2IFG HFXT2 oscillator fault flag 0x2 0x1 read-only HFXT2IFG_enum_read read HFXT2IFG_0 No fault condition occurred after the last reset 0 HFXT2IFG_1 HFXT2 fault. A HFXT2 fault occurred after the last reset 1 DCOR_SHTIFG DCO external resistor short circuit fault flag. 0x5 0x1 read-only DCOR_SHTIFG_enum_read read DCOR_SHTIFG_0 DCO external resistor present 0 DCOR_SHTIFG_1 DCO external resistor short circuit fault 1 DCOR_OPNIFG DCO external resistor open circuit fault flag. 0x6 0x1 read-only DCOR_OPNIFG_enum_read read DCOR_OPNIFG_0 DCO external resistor present 0 DCOR_OPNIFG_1 DCO external resistor open circuit fault 1 FCNTLFIFG Start fault counter interrupt flag LFXT 0x8 0x1 read-only FCNTLFIFG_enum_read read FCNTLFIFG_0 Start counter not expired 0 FCNTLFIFG_1 Start counter expired 1 FCNTHFIFG Start fault counter interrupt flag HFXT 0x9 0x1 read-only FCNTHFIFG_enum_read read FCNTHFIFG_0 Start counter not expired 0 FCNTHFIFG_1 Start counter expired 1 FCNTHF2IFG Start fault counter interrupt flag HFXT2 0xB 0x1 read-only FCNTHF2IFG_enum_read read FCNTHF2IFG_0 Start counter not expired 0 FCNTHF2IFG_1 Start counter expired 1 PLLOOLIFG PLL out-of-lock interrupt flag 0xC 0x1 read-only PLLOOLIFG_enum_read read PLLOOLIFG_0 No interrupt pending 0 PLLOOLIFG_1 Interrupt pending 1 PLLLOSIFG PLL loss-of-signal interrupt flag 0xD 0x1 read-only PLLLOSIFG_enum_read read PLLLOSIFG_0 No interrupt pending 0 PLLLOSIFG_1 Interrupt pending 1 PLLOORIFG PLL out-of-range interrupt flag 0xE 0x1 read-only PLLOORIFG_enum_read read PLLOORIFG_0 No interrupt pending 0 PLLOORIFG_1 Interrupt pending 1 CALIFG REFCNT period counter expired 0xF 0x1 read-only CALIFG_enum_read read CALIFG_0 REFCNT period counter not expired 0 CALIFG_1 REFCNT period counter expired 1 CSCLRIFG CLRIFG Clear Interrupt Flag Register 0x50 32 write-only 0x00000000 0xffffffff CLR_LFXTIFG Clear LFXT oscillator fault interrupt flag 0x0 0x1 write-only CLR_LFXTIFG_enum_write write CLR_LFXTIFG_0 No effect 0 CLR_LFXTIFG_1 Clear pending interrupt flag 1 CLR_HFXTIFG Clear HFXT oscillator fault interrupt flag 0x1 0x1 write-only CLR_HFXTIFG_enum_write write CLR_HFXTIFG_0 No effect 0 CLR_HFXTIFG_1 Clear pending interrupt flag 1 CLR_HFXT2IFG Clear HFXT2 oscillator fault interrupt flag 0x2 0x1 write-only CLR_HFXT2IFG_enum_write write CLR_HFXT2IFG_0 No effect 0 CLR_HFXT2IFG_1 Clear pending interrupt flag 1 CLR_DCOR_OPNIFG Clear DCO external resistor open circuit fault interrupt flag. 0x6 0x1 write-only CLR_DCOR_OPNIFG_enum_write write CLR_DCOR_OPNIFG_0 No effect 0 CLR_DCOR_OPNIFG_1 Clear pending interrupt flag 1 CLR_CALIFG REFCNT period counter clear interrupt flag 0xF 0x1 write-only CLR_CALIFG_enum_write write CLR_CALIFG_0 No effect 0 CLR_CALIFG_1 Clear pending interrupt flag 1 CLR_FCNTLFIFG Start fault counter clear interrupt flag LFXT 0x8 0x1 write-only CLR_FCNTLFIFG_enum_write write CLR_FCNTLFIFG_0 No effect 0 CLR_FCNTLFIFG_1 Clear pending interrupt flag 1 CLR_FCNTHFIFG Start fault counter clear interrupt flag HFXT 0x9 0x1 write-only CLR_FCNTHFIFG_enum_write write CLR_FCNTHFIFG_0 No effect 0 CLR_FCNTHFIFG_1 Clear pending interrupt flag 1 CLR_FCNTHF2IFG Start fault counter clear interrupt flag HFXT2 0xA 0x1 write-only CLR_FCNTHF2IFG_enum_write write CLR_FCNTHF2IFG_0 No effect 0 CLR_FCNTHF2IFG_1 Clear pending interrupt flag 1 CLR_PLLOOLIFG PLL out-of-lock clear interrupt flag 0xC 0x1 write-only CLR_PLLOOLIFG_enum_write write CLR_PLLOOLIFG_0 No effect 0 CLR_PLLOOLIFG_1 Clear pending interrupt flag 1 CLR_PLLLOSIFG PLL loss-of-signal clear interrupt flag 0xD 0x1 write-only CLR_PLLLOSIFG_enum_write write CLR_PLLLOSIFG_0 No effect 0 CLR_PLLLOSIFG_1 Clear pending interrupt flag 1 CLR_PLLOORIFG PLL out-of-range clear interrupt flag 0xE 0x1 write-only CLR_PLLOORIFG_enum_write write CLR_PLLOORIFG_0 No effect 0 CLR_PLLOORIFG_1 Clear pending interrupt flag 1 CSSETIFG SETIFG Set Interrupt Flag Register 0x58 32 write-only 0x00000000 0xffffffff SET_LFXTIFG Set LFXT oscillator fault interrupt flag 0x0 0x1 write-only SET_LFXTIFG_enum_write write SET_LFXTIFG_0 No effect 0 SET_LFXTIFG_1 Set pending interrupt flag 1 SET_HFXTIFG Set HFXT oscillator fault interrupt flag 0x1 0x1 write-only SET_HFXTIFG_enum_write write SET_HFXTIFG_0 No effect 0 SET_HFXTIFG_1 Set pending interrupt flag 1 SET_HFXT2IFG Set HFXT2 oscillator fault interrupt flag 0x2 0x1 write-only SET_HFXT2IFG_enum_write write SET_HFXT2IFG_0 No effect 0 SET_HFXT2IFG_1 Set pending interrupt flag 1 SET_DCOR_OPNIFG Set DCO external resistor open circuit fault interrupt flag. 0x6 0x1 write-only SET_DCOR_OPNIFG_enum_write write SET_DCOR_OPNIFG_0 No effect 0 SET_DCOR_OPNIFG_1 Set pending interrupt flag 1 SET_CALIFG REFCNT period counter set interrupt flag 0xF 0x1 write-only SET_CALIFG_enum_write write SET_CALIFG_0 No effect 0 SET_CALIFG_1 Set pending interrupt flag 1 SET_FCNTHFIFG Start fault counter set interrupt flag HFXT 0x9 0x1 write-only SET_FCNTHFIFG_enum_write write SET_FCNTHFIFG_0 No effect 0 SET_FCNTHFIFG_1 Set pending interrupt flag 1 SET_FCNTHF2IFG Start fault counter set interrupt flag HFXT2 0xA 0x1 write-only SET_FCNTHF2IFG_enum_write write SET_FCNTHF2IFG_0 No effect 0 SET_FCNTHF2IFG_1 Set pending interrupt flag 1 SET_FCNTLFIFG Start fault counter set interrupt flag LFXT 0x8 0x1 write-only SET_FCNTLFIFG_enum_write write SET_FCNTLFIFG_0 No effect 0 SET_FCNTLFIFG_1 Set pending interrupt flag 1 SET_PLLOOLIFG PLL out-of-lock set interrupt flag 0xC 0x1 write-only SET_PLLOOLIFG_enum_write write SET_PLLOOLIFG_0 No effect 0 SET_PLLOOLIFG_1 Set pending interrupt flag 1 SET_PLLLOSIFG PLL loss-of-signal set interrupt flag 0xD 0x1 write-only SET_PLLLOSIFG_enum_write write SET_PLLLOSIFG_0 No effect 0 SET_PLLLOSIFG_1 Set pending interrupt flag 1 SET_PLLOORIFG PLL out-of-range set interrupt flag 0xE 0x1 write-only SET_PLLOORIFG_enum_write write SET_PLLOORIFG_0 No effect 0 SET_PLLOORIFG_1 Set pending interrupt flag 1 CSDCOERCAL0 DCOERCAL0 DCO External Resistor Cailbration 0 Register 0x60 32 read-write 0x01000000 DCO_TCCAL DCO Temperature compensation calibration 0x0 0x2 read-write DCO_FCAL_RSEL04 DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4. 0x10 0xA read-write CSDCOERCAL1 DCOERCAL1 DCO External Resistor Calibration 1 Register 0x64 32 read-write 0x00000100 0xffffffff DCO_FCAL_RSEL5 DCO frequency calibration for DCO frequency range (DCORSEL) 5. 0x0 0xA read-write PSS 356.0 PSS 0x40010800 PSS_IRQ PSS Interrupt 0 0x0 0x40 registers PSSKEY KEY Key Register 0x0 32 read-write 0x0000a596 0xffffffff PSSKEY PSS control key 0x0 0x10 read-write PSSCTL0 CTL0 Control 0 Register 0x4 32 read-write 0x00002000 0xffffffff SVSMHOFF SVSM high-side off 0x0 0x1 read-write SVSMHOFF_0 The SVSMH is on 0 SVSMHOFF_1 The SVSMH is off 1 SVSMHLP SVSM high-side low power normal performance mode 0x1 0x1 read-write SVSMHLP_0 Full performance mode. See the device-specific data sheet for response times. 0 SVSMHLP_1 Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times. 1 SVSMHS Supply supervisor or monitor selection for the high-side 0x2 0x1 read-write SVSMHS_0 Configure as SVSH 0 SVSMHS_1 Configure as SVMH 1 SVSMHTH SVSM high-side reset voltage level 0x3 0x3 read-write SVMHOE SVSM high-side output enable 0x6 0x1 read-write SVMHOE_0 SVSMHIFG bit is not output 0 SVMHOE_1 SVSMHIFG bit is output to the device SVMHOUT pin. The device-specific port logic must be configured accordingly 1 SVMHOUTPOLAL SVMHOUT pin polarity active low 0x7 0x1 read-write SVMHOUTPOLAL_0 SVMHOUT is active high. An error condition is signaled by a 1 at the SVMHOUT pin 0 SVMHOUTPOLAL_1 SVMHOUT is active low. An error condition is signaled by a 0 at the SVMHOUT pin 1 DCDC_FORCE Force DC-DC regulator operation 0xA 0x1 read-write DCDC_FORCE_0 DC-DC regulator operation not forced. Automatic fail-safe mechanism switches the core voltage regulator from DC-DC to LDO when the supply voltage falls below the minimum supply voltage necessary for DC-DC operation. 0 DCDC_FORCE_1 DC-DC regulator operation forced. Automatic fail-safe mechanism is disabled and device continues to operate out of DC-DC regulator. 1 VCORETRAN Controls core voltage level transition time 0xC 0x2 read-write VCORETRAN_0 32 s / 100 mV 0 VCORETRAN_1 64 s / 100 mV 1 VCORETRAN_2 128 s / 100 mV (default) 2 VCORETRAN_3 256 s / 100 mV 3 PSSIE IE Interrupt Enable Register 0x34 32 read-write 0x00000000 0xffffffff SVSMHIE High-side SVSM interrupt enable 0x1 0x1 read-write SVSMHIE_0 Interrupt disabled 0 SVSMHIE_1 Interrupt enabled 1 PSSIFG IFG Interrupt Flag Register 0x38 32 read-only 0x00000000 0xffffffff SVSMHIFG High-side SVSM interrupt flag 0x1 0x1 read-only SVSMHIFG_enum_read read SVSMHIFG_0 No interrupt pending 0 SVSMHIFG_1 Interrupt due to SVSMH 1 PSSCLRIFG CLRIFG Clear Interrupt Flag Register 0x3C 32 read-write 0x00000000 0xffffffff CLRSVSMHIFG SVSMH clear interrupt flag 0x1 0x1 write-only CLRSVSMHIFG_enum_write write CLRSVSMHIFG_0 No effect 0 CLRSVSMHIFG_1 Clear pending interrupt flag 1 FLCTL 356.0 FLCTL 0x40011000 FLCTL_IRQ Flash Controller Interrupt 5 0x0 0x124 registers FLCTL_POWER_STAT POWER_STAT Power Status Register 0x0 32 read-only 0x00000080 0xffffffff PSTAT Flash power status 0x0 0x3 read-only PSTAT_0 Flash IP in power-down mode 0 PSTAT_1 Flash IP Vdd domain power-up in progress 1 PSTAT_2 PSS LDO_GOOD, IREF_OK and VREF_OK check in progress 2 PSTAT_3 Flash IP SAFE_LV check in progress 3 PSTAT_4 Flash IP Active 4 PSTAT_5 Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. 5 PSTAT_6 Flash IP in Standby mode 6 PSTAT_7 Flash IP in Current mirror boost state 7 LDOSTAT PSS FLDO GOOD status 0x3 0x1 read-only LDOSTAT_0 FLDO not GOOD 0 LDOSTAT_1 FLDO GOOD 1 VREFSTAT PSS VREF stable status 0x4 0x1 read-only VREFSTAT_0 Flash LDO not stable 0 VREFSTAT_1 Flash LDO stable 1 IREFSTAT PSS IREF stable status 0x5 0x1 read-only IREFSTAT_0 IREF not stable 0 IREFSTAT_1 IREF stable 1 TRIMSTAT PSS trim done status 0x6 0x1 read-only TRIMSTAT_0 PSS trim not complete 0 TRIMSTAT_1 PSS trim complete 1 RD_2T Indicates if Flash is being accessed in 2T mode 0x7 0x1 read-only RD_2T_0 Flash reads are in 1T mode 0 RD_2T_1 Flash reads are in 2T mode 1 FLCTL_BANK0_RDCTL BANK0_RDCTL Bank0 Read Control Register 0x10 32 0x00000000 0xffffffff RD_MODE Flash read mode control setting for Bank 0 0x0 0x4 read-write RD_MODE_0 Normal read mode 0 RD_MODE_1 Read Margin 0 1 RD_MODE_2 Read Margin 1 2 RD_MODE_3 Program Verify 3 RD_MODE_4 Erase Verify 4 RD_MODE_5 Leakage Verify 5 RD_MODE_9 Read Margin 0B 9 RD_MODE_10 Read Margin 1B 10 BUFI Enables read buffering feature for instruction fetches to this Bank 0x4 0x1 read-write BUFD Enables read buffering feature for data reads to this Bank 0x5 0x1 read-write WAIT Number of wait states for read 0xC 0x4 read-write WAIT_0 0 wait states 0 WAIT_1 1 wait states 1 WAIT_2 2 wait states 2 WAIT_3 3 wait states 3 WAIT_4 4 wait states 4 WAIT_5 5 wait states 5 WAIT_6 6 wait states 6 WAIT_7 7 wait states 7 WAIT_8 8 wait states 8 WAIT_9 9 wait states 9 WAIT_10 10 wait states 10 WAIT_11 11 wait states 11 WAIT_12 12 wait states 12 WAIT_13 13 wait states 13 WAIT_14 14 wait states 14 WAIT_15 15 wait states 15 RD_MODE_STATUS Read mode 0x10 0x4 read-only RD_MODE_STATUS_0 Normal read mode 0 RD_MODE_STATUS_1 Read Margin 0 1 RD_MODE_STATUS_2 Read Margin 1 2 RD_MODE_STATUS_3 Program Verify 3 RD_MODE_STATUS_4 Erase Verify 4 RD_MODE_STATUS_5 Leakage Verify 5 RD_MODE_STATUS_9 Read Margin 0B 9 RD_MODE_STATUS_10 Read Margin 1B 10 FLCTL_BANK1_RDCTL BANK1_RDCTL Bank1 Read Control Register 0x14 32 0x00000000 0xffffffff RD_MODE Flash read mode control setting for Bank 0 0x0 0x4 read-write RD_MODE_0 Normal read mode 0 RD_MODE_1 Read Margin 0 1 RD_MODE_2 Read Margin 1 2 RD_MODE_3 Program Verify 3 RD_MODE_4 Erase Verify 4 RD_MODE_5 Leakage Verify 5 RD_MODE_9 Read Margin 0B 9 RD_MODE_10 Read Margin 1B 10 BUFI Enables read buffering feature for instruction fetches to this Bank 0x4 0x1 read-write BUFD Enables read buffering feature for data reads to this Bank 0x5 0x1 read-write RD_MODE_STATUS Read mode 0x10 0x4 read-only RD_MODE_STATUS_0 Normal read mode 0 RD_MODE_STATUS_1 Read Margin 0 1 RD_MODE_STATUS_2 Read Margin 1 2 RD_MODE_STATUS_3 Program Verify 3 RD_MODE_STATUS_4 Erase Verify 4 RD_MODE_STATUS_5 Leakage Verify 5 RD_MODE_STATUS_9 Read Margin 0B 9 RD_MODE_STATUS_10 Read Margin 1B 10 WAIT Number of wait states for read 0xC 0x4 read-write WAIT_0 0 wait states 0 WAIT_1 1 wait states 1 WAIT_2 2 wait states 2 WAIT_3 3 wait states 3 WAIT_4 4 wait states 4 WAIT_5 5 wait states 5 WAIT_6 6 wait states 6 WAIT_7 7 wait states 7 WAIT_8 8 wait states 8 WAIT_9 9 wait states 9 WAIT_10 10 wait states 10 WAIT_11 11 wait states 11 WAIT_12 12 wait states 12 WAIT_13 13 wait states 13 WAIT_14 14 wait states 14 WAIT_15 15 wait states 15 FLCTL_RDBRST_CTLSTAT RDBRST_CTLSTAT Read Burst/Compare Control and Status Register 0x20 32 0x00000000 0xffffffff START Start of burst/compare operation 0x0 0x1 write-only MEM_TYPE Type of memory that burst is carried out on 0x1 0x2 read-write MEM_TYPE_0 Main Memory 0 MEM_TYPE_1 Information Memory 1 MEM_TYPE_3 Engineering Memory 3 STOP_FAIL Terminate burst/compare operation 0x3 0x1 read-write DATA_CMP Data pattern used for comparison against memory read data 0x4 0x1 read-write DATA_CMP_0 0000_0000_0000_0000_0000_0000_0000_0000 0 DATA_CMP_1 FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF 1 TEST_EN Enable comparison against test data compare registers 0x6 0x1 read-write BRST_STAT Status of Burst/Compare operation 0x10 0x2 read-only BRST_STAT_0 Idle 0 BRST_STAT_1 Burst/Compare START bit written, but operation pending 1 BRST_STAT_2 Burst/Compare in progress 2 BRST_STAT_3 Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) 3 CMP_ERR Burst/Compare Operation encountered atleast one data 0x12 0x1 read-only ADDR_ERR Burst/Compare Operation was terminated due to access to 0x13 0x1 read-only CLR_STAT Clear status bits 19-16 of this register 0x17 0x1 write-only FLCTL_RDBRST_STARTADDR RDBRST_STARTADDR Read Burst/Compare Start Address Register 0x24 32 0x00000000 0xffffffff START_ADDRESS Start Address of Burst Operation 0x0 0x15 read-write FLCTL_RDBRST_LEN RDBRST_LEN Read Burst/Compare Length Register 0x28 32 0x00000000 0xffffffff BURST_LENGTH Length of Burst Operation 0x0 0x15 read-write FLCTL_RDBRST_FAILADDR RDBRST_FAILADDR Read Burst/Compare Fail Address Register 0x3C 32 0x00000000 0xffffffff FAIL_ADDRESS Reflects address of last failed compare 0x0 0x15 read-write FLCTL_RDBRST_FAILCNT RDBRST_FAILCNT Read Burst/Compare Fail Count Register 0x40 32 0x00000000 0xffffffff FAIL_COUNT Number of failures encountered in burst operation 0x0 0x11 read-write FLCTL_PRG_CTLSTAT PRG_CTLSTAT Program Control and Status Register 0x50 32 0x0000000c 0xffffffff ENABLE Master control for all word program operations 0x0 0x1 read-write ENABLE_0 Word program operation disabled 0 ENABLE_1 Word program operation enabled 1 MODE Write mode 0x1 0x1 read-write MODE_0 Write immediate mode. Starts program operation immediately on each write to the Flash 0 MODE_1 Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation 1 VER_PRE Controls automatic pre program verify operations 0x2 0x1 read-write VER_PRE_0 No pre program verification 0 VER_PRE_1 Pre verify feature automatically invoked for each write operation (irrespective of the mode) 1 VER_PST Controls automatic post program verify operations 0x3 0x1 read-write VER_PST_0 No post program verification 0 VER_PST_1 Post verify feature automatically invoked for each write operation (irrespective of the mode) 1 STATUS Status of program operations in the Flash memory 0x10 0x2 read-only STATUS_0 Idle (no program operation currently active) 0 STATUS_1 Single word program operation triggered, but pending 1 STATUS_2 Single word program in progress 2 BNK_ACT Bank active 0x12 0x1 read-only BNK_ACT_0 Word in Bank0 being programmed 0 BNK_ACT_1 Word in Bank1 being programmed 1 FLCTL_PRGBRST_CTLSTAT PRGBRST_CTLSTAT Program Burst Control and Status Register 0x54 32 0x000000c0 0xffffffff START Trigger start of burst program operation 0x0 0x1 write-only TYPE Type of memory that burst program is carried out on 0x1 0x2 read-write TYPE_0 Main Memory 0 TYPE_1 Information Memory 1 TYPE_3 Engineering Memory 3 LEN Length of burst 0x3 0x3 read-write LEN_0 No burst operation 0 LEN_1 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register 1 LEN_2 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register 2 LEN_3 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register 3 LEN_4 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register 4 AUTO_PRE Auto-Verify operation before the Burst Program 0x6 0x1 read-write AUTO_PRE_0 No program verify operations carried out 0 AUTO_PRE_1 Causes an automatic Burst Program Verify after the Burst Program Operation 1 AUTO_PST Auto-Verify operation after the Burst Program 0x7 0x1 read-write AUTO_PST_0 No program verify operations carried out 0 AUTO_PST_1 Causes an automatic Burst Program Verify before the Burst Program Operation 1 BURST_STATUS Status of a Burst Operation 0x10 0x3 read-only BURST_STATUS_0 Idle (Burst not active) 0 BURST_STATUS_1 Burst program started but pending 1 BURST_STATUS_2 Burst active, with 1st 128 bit word being written into Flash 2 BURST_STATUS_3 Burst active, with 2nd 128 bit word being written into Flash 3 BURST_STATUS_4 Burst active, with 3rd 128 bit word being written into Flash 4 BURST_STATUS_5 Burst active, with 4th 128 bit word being written into Flash 5 BURST_STATUS_7 Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) 7 PRE_ERR Burst Operation encountered preprogram auto-verify errors 0x13 0x1 read-only PST_ERR Burst Operation encountered postprogram auto-verify errors 0x14 0x1 read-only ADDR_ERR Burst Operation was terminated due to attempted program of reserved memory 0x15 0x1 read-only CLR_STAT Clear status bits 21-16 of this register 0x17 0x1 write-only FLCTL_PRGBRST_STARTADDR PRGBRST_STARTADDR Program Burst Start Address Register 0x58 32 0x00000000 0xffffffff START_ADDRESS Start Address of Program Burst Operation 0x0 0x16 read-write FLCTL_PRGBRST_DATA0_0 PRGBRST_DATA0_0 Program Burst Data0 Register0 0x60 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 0 0x0 0x20 read-write FLCTL_PRGBRST_DATA0_1 PRGBRST_DATA0_1 Program Burst Data0 Register1 0x64 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 0 0x0 0x20 read-write FLCTL_PRGBRST_DATA0_2 PRGBRST_DATA0_2 Program Burst Data0 Register2 0x68 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 0 0x0 0x20 read-write FLCTL_PRGBRST_DATA0_3 PRGBRST_DATA0_3 Program Burst Data0 Register3 0x6C 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 0 0x0 0x20 read-write FLCTL_PRGBRST_DATA1_0 PRGBRST_DATA1_0 Program Burst Data1 Register0 0x70 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 1 0x0 0x20 read-write FLCTL_PRGBRST_DATA1_1 PRGBRST_DATA1_1 Program Burst Data1 Register1 0x74 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 1 0x0 0x20 read-write FLCTL_PRGBRST_DATA1_2 PRGBRST_DATA1_2 Program Burst Data1 Register2 0x78 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 1 0x0 0x20 read-write FLCTL_PRGBRST_DATA1_3 PRGBRST_DATA1_3 Program Burst Data1 Register3 0x7C 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 1 0x0 0x20 read-write FLCTL_PRGBRST_DATA2_0 PRGBRST_DATA2_0 Program Burst Data2 Register0 0x80 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 2 0x0 0x20 read-write FLCTL_PRGBRST_DATA2_1 PRGBRST_DATA2_1 Program Burst Data2 Register1 0x84 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 2 0x0 0x20 read-write FLCTL_PRGBRST_DATA2_2 PRGBRST_DATA2_2 Program Burst Data2 Register2 0x88 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 2 0x0 0x20 read-write FLCTL_PRGBRST_DATA2_3 PRGBRST_DATA2_3 Program Burst Data2 Register3 0x8C 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 2 0x0 0x20 read-write FLCTL_PRGBRST_DATA3_0 PRGBRST_DATA3_0 Program Burst Data3 Register0 0x90 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 3 0x0 0x20 read-write FLCTL_PRGBRST_DATA3_1 PRGBRST_DATA3_1 Program Burst Data3 Register1 0x94 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 3 0x0 0x20 read-write FLCTL_PRGBRST_DATA3_2 PRGBRST_DATA3_2 Program Burst Data3 Register2 0x98 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 3 0x0 0x20 read-write FLCTL_PRGBRST_DATA3_3 PRGBRST_DATA3_3 Program Burst Data3 Register3 0x9C 32 0xffffffff 0xffffffff DATAIN Program Burst 128 bit Data Word 3 0x0 0x20 read-write FLCTL_ERASE_CTLSTAT ERASE_CTLSTAT Erase Control and Status Register 0xA0 32 0x00000000 0xffffffff START Start of Erase operation 0x0 0x1 write-only MODE Erase mode selected by application 0x1 0x1 read-write MODE_0 Sector Erase (controlled by FLTCTL_ERASE_SECTADDR) 0 MODE_1 Mass Erase (includes all Main and Information memory sectors that don't have corresponding WE bits set) 1 TYPE Type of memory that erase operation is carried out on 0x2 0x2 read-write TYPE_0 Main Memory 0 TYPE_1 Information Memory 1 TYPE_3 Engineering Memory 3 STATUS Status of erase operations in the Flash memory 0x10 0x2 read-only STATUS_0 Idle (no program operation currently active) 0 STATUS_1 Erase operation triggered to START but pending 1 STATUS_2 Erase operation in progress 2 STATUS_3 Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) 3 ADDR_ERR Erase Operation was terminated due to attempted erase of reserved memory address 0x12 0x1 read-only CLR_STAT Clear status bits 18-16 of this register 0x13 0x1 write-only FLCTL_ERASE_SECTADDR ERASE_SECTADDR Erase Sector Address Register 0xA4 32 0x00000000 0xffffffff SECT_ADDRESS Address of Sector being Erased 0x0 0x16 read-write FLCTL_BANK0_INFO_WEPROT BANK0_INFO_WEPROT Information Memory Bank0 Write/Erase Protection Register 0xB0 32 0x00000003 0xffffffff PROT0 Protects Sector 0 from program or erase 0x0 0x1 read-write PROT1 Protects Sector 1 from program or erase 0x1 0x1 read-write FLCTL_BANK0_MAIN_WEPROT BANK0_MAIN_WEPROT Main Memory Bank0 Write/Erase Protection Register 0xB4 32 0xffffffff 0xffffffff PROT0 Protects Sector 0 from program or erase 0x0 0x1 read-write PROT1 Protects Sector 1 from program or erase 0x1 0x1 read-write PROT2 Protects Sector 2 from program or erase 0x2 0x1 read-write PROT3 Protects Sector 3 from program or erase 0x3 0x1 read-write PROT4 Protects Sector 4 from program or erase 0x4 0x1 read-write PROT5 Protects Sector 5 from program or erase 0x5 0x1 read-write PROT6 Protects Sector 6 from program or erase 0x6 0x1 read-write PROT7 Protects Sector 7 from program or erase 0x7 0x1 read-write PROT8 Protects Sector 8 from program or erase 0x8 0x1 read-write PROT9 Protects Sector 9 from program or erase 0x9 0x1 read-write PROT10 Protects Sector 10 from program or erase 0xA 0x1 read-write PROT11 Protects Sector 11 from program or erase 0xB 0x1 read-write PROT12 Protects Sector 12 from program or erase 0xC 0x1 read-write PROT13 Protects Sector 13 from program or erase 0xD 0x1 read-write PROT14 Protects Sector 14 from program or erase 0xE 0x1 read-write PROT15 Protects Sector 15 from program or erase 0xF 0x1 read-write PROT16 Protects Sector 16 from program or erase 0x10 0x1 read-write PROT17 Protects Sector 17 from program or erase 0x11 0x1 read-write PROT18 Protects Sector 18 from program or erase 0x12 0x1 read-write PROT19 Protects Sector 19 from program or erase 0x13 0x1 read-write PROT20 Protects Sector 20 from program or erase 0x14 0x1 read-write PROT21 Protects Sector 21 from program or erase 0x15 0x1 read-write PROT22 Protects Sector 22 from program or erase 0x16 0x1 read-write PROT23 Protects Sector 23 from program or erase 0x17 0x1 read-write PROT24 Protects Sector 24 from program or erase 0x18 0x1 read-write PROT25 Protects Sector 25 from program or erase 0x19 0x1 read-write PROT26 Protects Sector 26 from program or erase 0x1A 0x1 read-write PROT27 Protects Sector 27 from program or erase 0x1B 0x1 read-write PROT28 Protects Sector 28 from program or erase 0x1C 0x1 read-write PROT29 Protects Sector 29 from program or erase 0x1D 0x1 read-write PROT30 Protects Sector 30 from program or erase 0x1E 0x1 read-write PROT31 Protects Sector 31 from program or erase 0x1F 0x1 read-write FLCTL_BANK1_INFO_WEPROT BANK1_INFO_WEPROT Information Memory Bank1 Write/Erase Protection Register 0xC0 32 0x00000003 0xffffffff PROT0 Protects Sector 0 from program or erase operations 0x0 0x1 read-write PROT1 Protects Sector 1 from program or erase operations 0x1 0x1 read-write FLCTL_BANK1_MAIN_WEPROT BANK1_MAIN_WEPROT Main Memory Bank1 Write/Erase Protection Register 0xC4 32 0xffffffff 0xffffffff PROT0 Protects Sector 0 from program or erase operations 0x0 0x1 read-write PROT1 Protects Sector 1 from program or erase operations 0x1 0x1 read-write PROT2 Protects Sector 2 from program or erase operations 0x2 0x1 read-write PROT3 Protects Sector 3 from program or erase operations 0x3 0x1 read-write PROT4 Protects Sector 4 from program or erase operations 0x4 0x1 read-write PROT5 Protects Sector 5 from program or erase operations 0x5 0x1 read-write PROT6 Protects Sector 6 from program or erase operations 0x6 0x1 read-write PROT7 Protects Sector 7 from program or erase operations 0x7 0x1 read-write PROT8 Protects Sector 8 from program or erase operations 0x8 0x1 read-write PROT9 Protects Sector 9 from program or erase operations 0x9 0x1 read-write PROT10 Protects Sector 10 from program or erase operations 0xA 0x1 read-write PROT11 Protects Sector 11 from program or erase operations 0xB 0x1 read-write PROT12 Protects Sector 12 from program or erase operations 0xC 0x1 read-write PROT13 Protects Sector 13 from program or erase operations 0xD 0x1 read-write PROT14 Protects Sector 14 from program or erase operations 0xE 0x1 read-write PROT15 Protects Sector 15 from program or erase operations 0xF 0x1 read-write PROT16 Protects Sector 16 from program or erase operations 0x10 0x1 read-write PROT17 Protects Sector 17 from program or erase operations 0x11 0x1 read-write PROT18 Protects Sector 18 from program or erase operations 0x12 0x1 read-write PROT19 Protects Sector 19 from program or erase operations 0x13 0x1 read-write PROT20 Protects Sector 20 from program or erase operations 0x14 0x1 read-write PROT21 Protects Sector 21 from program or erase operations 0x15 0x1 read-write PROT22 Protects Sector 22 from program or erase operations 0x16 0x1 read-write PROT23 Protects Sector 23 from program or erase operations 0x17 0x1 read-write PROT24 Protects Sector 24 from program or erase operations 0x18 0x1 read-write PROT25 Protects Sector 25 from program or erase operations 0x19 0x1 read-write PROT26 Protects Sector 26 from program or erase operations 0x1A 0x1 read-write PROT27 Protects Sector 27 from program or erase operations 0x1B 0x1 read-write PROT28 Protects Sector 28 from program or erase operations 0x1C 0x1 read-write PROT29 Protects Sector 29 from program or erase operations 0x1D 0x1 read-write PROT30 Protects Sector 30 from program or erase operations 0x1E 0x1 read-write PROT31 Protects Sector 31 from program or erase operations 0x1F 0x1 read-write FLCTL_BMRK_CTLSTAT BMRK_CTLSTAT Benchmark Control and Status Register 0xD0 32 0x00000000 0xffffffff I_BMRK When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash 0x0 0x1 read-write D_BMRK When 1, increments the Data Benchmark count register on each data read access to the Flash 0x1 0x1 read-write CMP_EN When 1, enables comparison of the Instruction or Data Benchmark Registers against the threshold value 0x2 0x1 read-write CMP_SEL Selects which benchmark register should be compared against the threshold 0x3 0x1 read-write en_1_0x0 Compares the Instruction Benchmark Register against the threshold value 0 en_2_0x1 Compares the Data Benchmark Register against the threshold value 1 FLCTL_BMRK_IFETCH BMRK_IFETCH Benchmark Instruction Fetch Count Register 0xD4 32 0x00000000 0xffffffff COUNT Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch) 0x0 0x20 read-write FLCTL_BMRK_DREAD BMRK_DREAD Benchmark Data Read Count Register 0xD8 32 0x00000000 0xffffffff COUNT Reflects the number of Data Read operations to the Flash (increments by one on each read) 0x0 0x20 read-write FLCTL_BMRK_CMP BMRK_CMP Benchmark Count Compare Register 0xDC 32 0x00010000 0xffffffff COUNT Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters 0x0 0x20 read-write FLCTL_IFG IFG Interrupt Flag Register 0xF0 32 0x00000000 0xffffffff RDBRST If set to 1, indicates that the Read Burst/Compare operation is complete 0x0 0x1 read-only AVPRE If set to 1, indicates that the pre-program verify operation has detected an error 0x1 0x1 read-only AVPST If set to 1, indicates that the post-program verify operation has failed comparison 0x2 0x1 read-only PRG If set to 1, indicates that a word Program operation is complete 0x3 0x1 read-only PRGB If set to 1, indicates that the configured Burst Program operation is complete 0x4 0x1 read-only ERASE If set to 1, indicates that the Erase operation is complete 0x5 0x1 read-only BMRK If set to 1, indicates that a Benchmark Compare match occurred 0x8 0x1 read-only PRG_ERR If set to 1, indicates a word composition error in full word write mode (possible data loss due to writes crossing over to a new 128bit boundary before full word has been composed) 0x9 0x1 read-only FLCTL_IE IE Interrupt Enable Register 0xF4 32 0x00000000 0xffffffff RDBRST If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x0 0x1 read-write AVPRE If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x1 0x1 read-write AVPST If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x2 0x1 read-write PRG If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x3 0x1 read-write PRGB If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x4 0x1 read-write ERASE If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x5 0x1 read-write BMRK If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x8 0x1 read-write PRG_ERR If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG 0x9 0x1 read-write FLCTL_CLRIFG CLRIFG Clear Interrupt Flag Register 0xF8 32 0x00000000 0xffffffff RDBRST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x0 0x1 write-only AVPRE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x1 0x1 write-only AVPST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x2 0x1 write-only PRG Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x3 0x1 write-only PRGB Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x4 0x1 write-only ERASE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x5 0x1 write-only BMRK Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x8 0x1 write-only PRG_ERR Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x9 0x1 write-only FLCTL_SETIFG SETIFG Set Interrupt Flag Register 0xFC 32 0x00000000 0xffffffff RDBRST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x0 0x1 write-only AVPRE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x1 0x1 write-only AVPST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x2 0x1 write-only PRG Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x3 0x1 write-only PRGB Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x4 0x1 write-only ERASE Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x5 0x1 write-only BMRK Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x8 0x1 write-only PRG_ERR Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG 0x9 0x1 write-only FLCTL_READ_TIMCTL READ_TIMCTL Read Timing Control Register 0x100 32 read-only SETUP Configures the length of the Setup phase for this operation 0x0 0x8 read-only IREF_BOOST1 Length of the IREF_BOOST1 signal of the IP 0xC 0x4 read-only SETUP_LONG Length of the Setup time into read mode when the device is recovering from one of the following conditions: Moving from Power-down or Standby back to Active and device is not trimmed. Moving from standby to active state in low-frequency active mode. Recovering from the LDO Boost operation after a Mass Erase. 0x10 0x8 read-only FLCTL_READMARGIN_TIMCTL READMARGIN_TIMCTL Read Margin Timing Control Register 0x104 32 read-only SETUP Length of the Setup phase for this operation 0x0 0x8 read-only FLCTL_PRGVER_TIMCTL PRGVER_TIMCTL Program Verify Timing Control Register 0x108 32 read-only SETUP Length of the Setup phase for this operation 0x0 0x8 read-only ACTIVE Length of the Active phase for this operation 0x8 0x4 read-only HOLD Length of the Hold phase for this operation 0xC 0x4 read-only FLCTL_ERSVER_TIMCTL ERSVER_TIMCTL Erase Verify Timing Control Register 0x10C 32 read-only SETUP Length of the Setup phase for this operation 0x0 0x8 read-only FLCTL_LKGVER_TIMCTL LKGVER_TIMCTL Leakage Verify Timing Control Register 0x110 32 read-only SETUP Length of the Setup phase for this operation 0x0 0x8 read-only FLCTL_PROGRAM_TIMCTL PROGRAM_TIMCTL Program Timing Control Register 0x114 32 read-only SETUP Length of the Setup phase for this operation 0x0 0x8 read-only ACTIVE Length of the Active phase for this operation 0x8 0x14 read-only HOLD Length of the Hold phase for this operation 0x1C 0x4 read-only FLCTL_ERASE_TIMCTL ERASE_TIMCTL Erase Timing Control Register 0x118 32 read-only SETUP Length of the Setup phase for this operation 0x0 0x8 read-only ACTIVE Length of the Active phase for this operation 0x8 0x14 read-only HOLD Length of the Hold phase for this operation 0x1C 0x4 read-only FLCTL_MASSERASE_TIMCTL MASSERASE_TIMCTL Mass Erase Timing Control Register 0x11C 32 read-only BOOST_ACTIVE Length of the time for which LDO Boost Signal is kept active 0x0 0x8 read-only BOOST_HOLD Length for which Flash deactivates the LDO Boost signal before processing any new commands 0x8 0x8 read-only FLCTL_BURSTPRG_TIMCTL BURSTPRG_TIMCTL Burst Program Timing Control Register 0x120 32 read-only ACTIVE Length of the Active phase for this operation 0x8 0x14 read-only ADC14 356.0 ADC14 0x40012000 ADC14_IRQ ADC14 Interrupt 24 0x0 0x158 registers ADC14CTL0 CTL0 Control 0 Register 0x0 32 read-write 0x00000000 0xffffffff ADC14SC ADC14 start conversion 0x0 0x1 read-write ADC14SC_0 No sample-and-conversion-start 0 ADC14SC_1 Start sample-and-conversion 1 ADC14ENC ADC14 enable conversion 0x1 0x1 read-write ADC14ENC_0 ADC14 disabled 0 ADC14ENC_1 ADC14 enabled 1 ADC14ON ADC14 on 0x4 0x1 read-write ADC14ON_0 ADC14 off 0 ADC14ON_1 ADC14 on. ADC core is ready to power up when a valid conversion is triggered. 1 ADC14MSC ADC14 multiple sample and conversion 0x7 0x1 read-write ADC14MSC_0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-convert 0 ADC14MSC_1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed 1 ADC14SHT0 ADC14 sample-and-hold time 0x8 0x4 read-write ADC14SHT0_0 4 0 ADC14SHT0_1 8 1 ADC14SHT0_2 16 2 ADC14SHT0_3 32 3 ADC14SHT0_4 64 4 ADC14SHT0_5 96 5 ADC14SHT0_6 128 6 ADC14SHT0_7 192 7 ADC14SHT1 ADC14 sample-and-hold time 0xC 0x4 read-write ADC14SHT1_0 4 0 ADC14SHT1_1 8 1 ADC14SHT1_2 16 2 ADC14SHT1_3 32 3 ADC14SHT1_4 64 4 ADC14SHT1_5 96 5 ADC14SHT1_6 128 6 ADC14SHT1_7 192 7 ADC14BUSY ADC14 busy 0x10 0x1 read-only ADC14BUSY_enum_read read ADC14BUSY_0 No operation is active 0 ADC14BUSY_1 A sequence, sample, or conversion is active 1 ADC14CONSEQ ADC14 conversion sequence mode select 0x11 0x2 read-write ADC14CONSEQ_0 Single-channel, single-conversion 0 ADC14CONSEQ_1 Sequence-of-channels 1 ADC14CONSEQ_2 Repeat-single-channel 2 ADC14CONSEQ_3 Repeat-sequence-of-channels 3 ADC14SSEL ADC14 clock source select 0x13 0x3 read-write ADC14SSEL_0 MODCLK 0 ADC14SSEL_1 SYSCLK 1 ADC14SSEL_2 ACLK 2 ADC14SSEL_3 MCLK 3 ADC14SSEL_4 SMCLK 4 ADC14SSEL_5 HSMCLK 5 ADC14DIV ADC14 clock divider 0x16 0x3 read-write ADC14DIV_0 /1 0 ADC14DIV_1 /2 1 ADC14DIV_2 /3 2 ADC14DIV_3 /4 3 ADC14DIV_4 /5 4 ADC14DIV_5 /6 5 ADC14DIV_6 /7 6 ADC14DIV_7 /8 7 ADC14ISSH ADC14 invert signal sample-and-hold 0x19 0x1 read-write ADC14ISSH_0 The sample-input signal is not inverted 0 ADC14ISSH_1 The sample-input signal is inverted 1 ADC14SHP ADC14 sample-and-hold pulse-mode select 0x1A 0x1 read-write ADC14SHP_0 SAMPCON signal is sourced from the sample-input signal 0 ADC14SHP_1 SAMPCON signal is sourced from the sampling timer 1 ADC14SHS ADC14 sample-and-hold source select 0x1B 0x3 read-write ADC14SHS_0 ADC14SC bit 0 ADC14SHS_1 See device-specific data sheet for source 1 ADC14SHS_2 See device-specific data sheet for source 2 ADC14SHS_3 See device-specific data sheet for source 3 ADC14SHS_4 See device-specific data sheet for source 4 ADC14SHS_5 See device-specific data sheet for source 5 ADC14SHS_6 See device-specific data sheet for source 6 ADC14SHS_7 See device-specific data sheet for source 7 ADC14PDIV ADC14 predivider 0x1E 0x2 read-write ADC14PDIV_0 Predivide by 1 0 ADC14PDIV_1 Predivide by 4 1 ADC14PDIV_2 Predivide by 32 2 ADC14PDIV_3 Predivide by 64 3 ADC14CTL1 CTL1 Control 1 Register 0x4 32 read-write 0x00000030 0xffffffff ADC14PWRMD ADC14 power modes 0x0 0x2 read-write ADC14PWRMD_0 Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps. 0 ADC14PWRMD_2 Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. 2 ADC14REFBURST ADC14 reference buffer burst 0x2 0x1 read-write ADC14REFBURST_0 ADC reference buffer on continuously 0 ADC14REFBURST_1 ADC reference buffer on only during sample-and-conversion 1 ADC14DF ADC14 data read-back format 0x3 0x1 read-write ADC14DF_0 Binary unsigned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 0000h, and the analog input voltage + V(REF) results in 3FFFh 0 ADC14DF_1 Signed binary (2s complement), left aligned. Theoretically, for ADC14DIF = 0 and 14-bit mode, the analog input voltage - V(REF) results in 8000h, and the analog input voltage + V(REF) results in 7FFCh 1 ADC14RES ADC14 resolution 0x4 0x2 read-write ADC14RES_0 8 bit (9 clock cycle conversion time) 0 ADC14RES_1 10 bit (11 clock cycle conversion time) 1 ADC14RES_2 12 bit (14 clock cycle conversion time) 2 ADC14RES_3 14 bit (16 clock cycle conversion time) 3 ADC14CSTARTADD ADC14 conversion start address 0x10 0x5 read-write ADC14BATMAP Controls 1/2 AVCC ADC input channel selection 0x16 0x1 read-write ADC14BATMAP_0 ADC internal 1/2 x AVCC channel is not selected for ADC 0 ADC14BATMAP_1 ADC internal 1/2 x AVCC channel is selected for ADC input channel MAX 1 ADC14TCMAP Controls temperature sensor ADC input channel selection 0x17 0x1 read-write ADC14TCMAP_0 ADC internal temperature sensor channel is not selected for ADC 0 ADC14TCMAP_1 ADC internal temperature sensor channel is selected for ADC input channel MAX-1 1 ADC14CH0MAP Controls internal channel 0 selection to ADC input channel MAX-2 0x18 0x1 read-write ADC14CH0MAP_0 ADC input channel internal 0 is not selected 0 ADC14CH0MAP_1 ADC input channel internal 0 is selected for ADC input channel MAX-2 1 ADC14CH1MAP Controls internal channel 1 selection to ADC input channel MAX-3 0x19 0x1 read-write ADC14CH1MAP_0 ADC input channel internal 1 is not selected 0 ADC14CH1MAP_1 ADC input channel internal 1 is selected for ADC input channel MAX-3 1 ADC14CH2MAP Controls internal channel 2 selection to ADC input channel MAX-4 0x1A 0x1 read-write ADC14CH2MAP_0 ADC input channel internal 2 is not selected 0 ADC14CH2MAP_1 ADC input channel internal 2 is selected for ADC input channel MAX-4 1 ADC14CH3MAP Controls internal channel 3 selection to ADC input channel MAX-5 0x1B 0x1 read-write ADC14CH3MAP_0 ADC input channel internal 3 is not selected 0 ADC14CH3MAP_1 ADC input channel internal 3 is selected for ADC input channel MAX-5 1 ADC14LO0 LO0 Window Comparator Low Threshold 0 Register 0x8 32 read-write 0x00000000 0xffffffff ADC14LO0 Low threshold 0 0x0 0x10 read-write ADC14HI0 HI0 Window Comparator High Threshold 0 Register 0xC 32 read-write 0x00003fff 0xffffffff ADC14HI0 High threshold 0 0x0 0x10 read-write ADC14LO1 LO1 Window Comparator Low Threshold 1 Register 0x10 32 read-write 0x00000000 0xffffffff ADC14LO1 Low threshold 1 0x0 0x10 read-write ADC14HI1 HI1 Window Comparator High Threshold 1 Register 0x14 32 read-write 0x00003fff 0xffffffff ADC14HI1 High threshold 1 0x0 0x10 read-write 32 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ADC14MCTL[%s] MCTL[%s] Conversion Memory Control Register 0x18 32 read-write 0x00000000 0xffffffff ADC14INCH Input channel select 0x0 0x5 read-write ADC14INCH_0 If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 0 ADC14INCH_1 If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 1 ADC14INCH_2 If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 2 ADC14INCH_3 If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 3 ADC14INCH_4 If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 4 ADC14INCH_5 If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 5 ADC14INCH_6 If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 6 ADC14INCH_7 If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 7 ADC14INCH_8 If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 8 ADC14INCH_9 If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 9 ADC14INCH_10 If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 10 ADC14INCH_11 If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 11 ADC14INCH_12 If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 12 ADC14INCH_13 If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 13 ADC14INCH_14 If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 14 ADC14INCH_15 If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 15 ADC14INCH_16 If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 16 ADC14INCH_17 If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 17 ADC14INCH_18 If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 18 ADC14INCH_19 If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 19 ADC14INCH_20 If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 20 ADC14INCH_21 If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 21 ADC14INCH_22 If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 22 ADC14INCH_23 If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 23 ADC14INCH_24 If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 24 ADC14INCH_25 If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 25 ADC14INCH_26 If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 26 ADC14INCH_27 If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 27 ADC14INCH_28 If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 28 ADC14INCH_29 If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 29 ADC14INCH_30 If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 30 ADC14INCH_31 If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 31 ADC14EOS End of sequence 0x7 0x1 read-write ADC14EOS_0 Not end of sequence 0 ADC14EOS_1 End of sequence 1 ADC14VRSEL Selects combinations of V(R+) and V(R-) sources 0x8 0x4 read-write ADC14VRSEL_0 V(R+) = AVCC, V(R-) = AVSS 0 ADC14VRSEL_1 V(R+) = VREF buffered, V(R-) = AVSS 1 ADC14VRSEL_14 V(R+) = VeREF+, V(R-) = VeREF- 14 ADC14VRSEL_15 V(R+) = VeREF+ buffered, V(R-) = VeREF 15 ADC14DIF Differential mode 0xD 0x1 read-write ADC14DIF_0 Single-ended mode enabled 0 ADC14DIF_1 Differential mode enabled 1 ADC14WINC Comparator window enable 0xE 0x1 read-write ADC14WINC_0 Comparator window disabled 0 ADC14WINC_1 Comparator window enabled 1 ADC14WINCTH Window comparator threshold register selection 0xF 0x1 read-write ADC14WINCTH_0 Use window comparator thresholds 0, ADC14LO0 and ADC14HI0 0 ADC14WINCTH_1 Use window comparator thresholds 1, ADC14LO1 and ADC14HI1 1 32 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ADC14MEM[%s] MEM[%s] Conversion Memory Register 0x98 32 read-write 0x00000000 0x00000000 Conversion_Results Conversion Result 0x0 0x10 read-write ADC14IER0 IER0 Interrupt Enable 0 Register 0x13C 32 read-write 0x00000000 0xffffffff ADC14IE0 Interrupt enable 0x0 0x1 read-write ADC14IE0_0 Interrupt disabled 0 ADC14IE0_1 Interrupt enabled 1 ADC14IE1 Interrupt enable 0x1 0x1 read-write ADC14IE1_0 Interrupt disabled 0 ADC14IE1_1 Interrupt enabled 1 ADC14IE2 Interrupt enable 0x2 0x1 read-write ADC14IE2_0 Interrupt disabled 0 ADC14IE2_1 Interrupt enabled 1 ADC14IE3 Interrupt enable 0x3 0x1 read-write ADC14IE3_0 Interrupt disabled 0 ADC14IE3_1 Interrupt enabled 1 ADC14IE4 Interrupt enable 0x4 0x1 read-write ADC14IE4_0 Interrupt disabled 0 ADC14IE4_1 Interrupt enabled 1 ADC14IE5 Interrupt enable 0x5 0x1 read-write ADC14IE5_0 Interrupt disabled 0 ADC14IE5_1 Interrupt enabled 1 ADC14IE6 Interrupt enable 0x6 0x1 read-write ADC14IE6_0 Interrupt disabled 0 ADC14IE6_1 Interrupt enabled 1 ADC14IE7 Interrupt enable 0x7 0x1 read-write ADC14IE7_0 Interrupt disabled 0 ADC14IE7_1 Interrupt enabled 1 ADC14IE8 Interrupt enable 0x8 0x1 read-write ADC14IE8_0 Interrupt disabled 0 ADC14IE8_1 Interrupt enabled 1 ADC14IE9 Interrupt enable 0x9 0x1 read-write ADC14IE9_0 Interrupt disabled 0 ADC14IE9_1 Interrupt enabled 1 ADC14IE10 Interrupt enable 0xA 0x1 read-write ADC14IE10_0 Interrupt disabled 0 ADC14IE10_1 Interrupt enabled 1 ADC14IE11 Interrupt enable 0xB 0x1 read-write ADC14IE11_0 Interrupt disabled 0 ADC14IE11_1 Interrupt enabled 1 ADC14IE12 Interrupt enable 0xC 0x1 read-write ADC14IE12_0 Interrupt disabled 0 ADC14IE12_1 Interrupt enabled 1 ADC14IE13 Interrupt enable 0xD 0x1 read-write ADC14IE13_0 Interrupt disabled 0 ADC14IE13_1 Interrupt enabled 1 ADC14IE14 Interrupt enable 0xE 0x1 read-write ADC14IE14_0 Interrupt disabled 0 ADC14IE14_1 Interrupt enabled 1 ADC14IE15 Interrupt enable 0xF 0x1 read-write ADC14IE15_0 Interrupt disabled 0 ADC14IE15_1 Interrupt enabled 1 ADC14IE16 Interrupt enable 0x10 0x1 read-write ADC14IE16_0 Interrupt disabled 0 ADC14IE16_1 Interrupt enabled 1 ADC14IE17 Interrupt enable 0x11 0x1 read-write ADC14IE17_0 Interrupt disabled 0 ADC14IE17_1 Interrupt enabled 1 ADC14IE19 Interrupt enable 0x13 0x1 read-write ADC14IE19_0 Interrupt disabled 0 ADC14IE19_1 Interrupt enabled 1 ADC14IE18 Interrupt enable 0x12 0x1 read-write ADC14IE18_0 Interrupt disabled 0 ADC14IE18_1 Interrupt enabled 1 ADC14IE20 Interrupt enable 0x14 0x1 read-write ADC14IE20_0 Interrupt disabled 0 ADC14IE20_1 Interrupt enabled 1 ADC14IE21 Interrupt enable 0x15 0x1 read-write ADC14IE21_0 Interrupt disabled 0 ADC14IE21_1 Interrupt enabled 1 ADC14IE22 Interrupt enable 0x16 0x1 read-write ADC14IE22_0 Interrupt disabled 0 ADC14IE22_1 Interrupt enabled 1 ADC14IE23 Interrupt enable 0x17 0x1 read-write ADC14IE23_0 Interrupt disabled 0 ADC14IE23_1 Interrupt enabled 1 ADC14IE24 Interrupt enable 0x18 0x1 read-write ADC14IE24_0 Interrupt disabled 0 ADC14IE24_1 Interrupt enabled 1 ADC14IE25 Interrupt enable 0x19 0x1 read-write ADC14IE25_0 Interrupt disabled 0 ADC14IE25_1 Interrupt enabled 1 ADC14IE26 Interrupt enable 0x1A 0x1 read-write ADC14IE26_0 Interrupt disabled 0 ADC14IE26_1 Interrupt enabled 1 ADC14IE27 Interrupt enable 0x1B 0x1 read-write ADC14IE27_0 Interrupt disabled 0 ADC14IE27_1 Interrupt enabled 1 ADC14IE28 Interrupt enable 0x1C 0x1 read-write ADC14IE28_0 Interrupt disabled 0 ADC14IE28_1 Interrupt enabled 1 ADC14IE29 Interrupt enable 0x1D 0x1 read-write ADC14IE29_0 Interrupt disabled 0 ADC14IE29_1 Interrupt enabled 1 ADC14IE30 Interrupt enable 0x1E 0x1 read-write ADC14IE30_0 Interrupt disabled 0 ADC14IE30_1 Interrupt enabled 1 ADC14IE31 Interrupt enable 0x1F 0x1 read-write ADC14IE31_0 Interrupt disabled 0 ADC14IE31_1 Interrupt enabled 1 ADC14IER1 IER1 Interrupt Enable 1 Register 0x140 32 read-write 0x00000000 0xffffffff ADC14INIE Interrupt enable for ADC14MEMx within comparator window 0x1 0x1 read-write ADC14INIE_0 Interrupt disabled 0 ADC14INIE_1 Interrupt enabled 1 ADC14LOIE Interrupt enable for ADC14MEMx below comparator window 0x2 0x1 read-write ADC14LOIE_0 Interrupt disabled 0 ADC14LOIE_1 Interrupt enabled 1 ADC14HIIE Interrupt enable for ADC14MEMx above comparator window 0x3 0x1 read-write ADC14HIIE_0 Interrupt disabled 0 ADC14HIIE_1 Interrupt enabled 1 ADC14OVIE ADC14MEMx overflow-interrupt enable 0x4 0x1 read-write ADC14OVIE_0 Interrupt disabled 0 ADC14OVIE_1 Interrupt enabled 1 ADC14TOVIE ADC14 conversion-time-overflow interrupt enable 0x5 0x1 read-write ADC14TOVIE_0 Interrupt disabled 0 ADC14TOVIE_1 Interrupt enabled 1 ADC14RDYIE ADC14 local buffered reference ready interrupt enable 0x6 0x1 read-write ADC14RDYIE_0 Interrupt disabled 0 ADC14RDYIE_1 Interrupt enabled 1 ADC14IFGR0 IFGR0 Interrupt Flag 0 Register 0x144 32 read-only 0x00000000 0xffffffff ADC14IFG0 ADC14MEM0 interrupt flag 0x0 0x1 read-only ADC14IFG0_enum_read read ADC14IFG0_0 No interrupt pending 0 ADC14IFG0_1 Interrupt pending 1 ADC14IFG1 ADC14MEM1 interrupt flag 0x1 0x1 read-only ADC14IFG1_enum_read read ADC14IFG1_0 No interrupt pending 0 ADC14IFG1_1 Interrupt pending 1 ADC14IFG2 ADC14MEM2 interrupt flag 0x2 0x1 read-only ADC14IFG2_enum_read read ADC14IFG2_0 No interrupt pending 0 ADC14IFG2_1 Interrupt pending 1 ADC14IFG3 ADC14MEM3 interrupt flag 0x3 0x1 read-only ADC14IFG3_enum_read read ADC14IFG3_0 No interrupt pending 0 ADC14IFG3_1 Interrupt pending 1 ADC14IFG4 ADC14MEM4 interrupt flag 0x4 0x1 read-only ADC14IFG4_enum_read read ADC14IFG4_0 No interrupt pending 0 ADC14IFG4_1 Interrupt pending 1 ADC14IFG5 ADC14MEM5 interrupt flag 0x5 0x1 read-only ADC14IFG5_enum_read read ADC14IFG5_0 No interrupt pending 0 ADC14IFG5_1 Interrupt pending 1 ADC14IFG6 ADC14MEM6 interrupt flag 0x6 0x1 read-only ADC14IFG6_enum_read read ADC14IFG6_0 No interrupt pending 0 ADC14IFG6_1 Interrupt pending 1 ADC14IFG7 ADC14MEM7 interrupt flag 0x7 0x1 read-only ADC14IFG7_enum_read read ADC14IFG7_0 No interrupt pending 0 ADC14IFG7_1 Interrupt pending 1 ADC14IFG8 ADC14MEM8 interrupt flag 0x8 0x1 read-only ADC14IFG8_enum_read read ADC14IFG8_0 No interrupt pending 0 ADC14IFG8_1 Interrupt pending 1 ADC14IFG9 ADC14MEM9 interrupt flag 0x9 0x1 read-only ADC14IFG9_enum_read read ADC14IFG9_0 No interrupt pending 0 ADC14IFG9_1 Interrupt pending 1 ADC14IFG10 ADC14MEM10 interrupt flag 0xA 0x1 read-only ADC14IFG10_enum_read read ADC14IFG10_0 No interrupt pending 0 ADC14IFG10_1 Interrupt pending 1 ADC14IFG11 ADC14MEM11 interrupt flag 0xB 0x1 read-only ADC14IFG11_enum_read read ADC14IFG11_0 No interrupt pending 0 ADC14IFG11_1 Interrupt pending 1 ADC14IFG12 ADC14MEM12 interrupt flag 0xC 0x1 read-only ADC14IFG12_enum_read read ADC14IFG12_0 No interrupt pending 0 ADC14IFG12_1 Interrupt pending 1 ADC14IFG13 ADC14MEM13 interrupt flag 0xD 0x1 read-only ADC14IFG13_enum_read read ADC14IFG13_0 No interrupt pending 0 ADC14IFG13_1 Interrupt pending 1 ADC14IFG14 ADC14MEM14 interrupt flag 0xE 0x1 read-only ADC14IFG14_enum_read read ADC14IFG14_0 No interrupt pending 0 ADC14IFG14_1 Interrupt pending 1 ADC14IFG15 ADC14MEM15 interrupt flag 0xF 0x1 read-only ADC14IFG15_enum_read read ADC14IFG15_0 No interrupt pending 0 ADC14IFG15_1 Interrupt pending 1 ADC14IFG16 ADC14MEM16 interrupt flag 0x10 0x1 read-only ADC14IFG16_enum_read read ADC14IFG16_0 No interrupt pending 0 ADC14IFG16_1 Interrupt pending 1 ADC14IFG17 ADC14MEM17 interrupt flag 0x11 0x1 read-only ADC14IFG17_enum_read read ADC14IFG17_0 No interrupt pending 0 ADC14IFG17_1 Interrupt pending 1 ADC14IFG18 ADC14MEM18 interrupt flag 0x12 0x1 read-only ADC14IFG18_enum_read read ADC14IFG18_0 No interrupt pending 0 ADC14IFG18_1 Interrupt pending 1 ADC14IFG19 ADC14MEM19 interrupt flag 0x13 0x1 read-only ADC14IFG19_enum_read read ADC14IFG19_0 No interrupt pending 0 ADC14IFG19_1 Interrupt pending 1 ADC14IFG20 ADC14MEM20 interrupt flag 0x14 0x1 read-only ADC14IFG20_enum_read read ADC14IFG20_0 No interrupt pending 0 ADC14IFG20_1 Interrupt pending 1 ADC14IFG21 ADC14MEM21 interrupt flag 0x15 0x1 read-only ADC14IFG21_enum_read read ADC14IFG21_0 No interrupt pending 0 ADC14IFG21_1 Interrupt pending 1 ADC14IFG22 ADC14MEM22 interrupt flag 0x16 0x1 read-only ADC14IFG22_enum_read read ADC14IFG22_0 No interrupt pending 0 ADC14IFG22_1 Interrupt pending 1 ADC14IFG23 ADC14MEM23 interrupt flag 0x17 0x1 read-only ADC14IFG23_enum_read read ADC14IFG23_0 No interrupt pending 0 ADC14IFG23_1 Interrupt pending 1 ADC14IFG24 ADC14MEM24 interrupt flag 0x18 0x1 read-only ADC14IFG24_enum_read read ADC14IFG24_0 No interrupt pending 0 ADC14IFG24_1 Interrupt pending 1 ADC14IFG25 ADC14MEM25 interrupt flag 0x19 0x1 read-only ADC14IFG25_enum_read read ADC14IFG25_0 No interrupt pending 0 ADC14IFG25_1 Interrupt pending 1 ADC14IFG26 ADC14MEM26 interrupt flag 0x1A 0x1 read-only ADC14IFG26_enum_read read ADC14IFG26_0 No interrupt pending 0 ADC14IFG26_1 Interrupt pending 1 ADC14IFG27 ADC14MEM27 interrupt flag 0x1B 0x1 read-only ADC14IFG27_enum_read read ADC14IFG27_0 No interrupt pending 0 ADC14IFG27_1 Interrupt pending 1 ADC14IFG28 ADC14MEM28 interrupt flag 0x1C 0x1 read-only ADC14IFG28_enum_read read ADC14IFG28_0 No interrupt pending 0 ADC14IFG28_1 Interrupt pending 1 ADC14IFG29 ADC14MEM29 interrupt flag 0x1D 0x1 read-only ADC14IFG29_enum_read read ADC14IFG29_0 No interrupt pending 0 ADC14IFG29_1 Interrupt pending 1 ADC14IFG30 ADC14MEM30 interrupt flag 0x1E 0x1 read-only ADC14IFG30_enum_read read ADC14IFG30_0 No interrupt pending 0 ADC14IFG30_1 Interrupt pending 1 ADC14IFG31 ADC14MEM31 interrupt flag 0x1F 0x1 read-only ADC14IFG31_enum_read read ADC14IFG31_0 No interrupt pending 0 ADC14IFG31_1 Interrupt pending 1 ADC14IFGR1 IFGR1 Interrupt Flag 1 Register 0x148 32 read-only 0x00000000 0xffffffff ADC14INIFG Interrupt flag for ADC14MEMx within comparator window 0x1 0x1 read-only ADC14INIFG_enum_read read ADC14INIFG_0 No interrupt pending 0 ADC14INIFG_1 Interrupt pending 1 ADC14LOIFG Interrupt flag for ADC14MEMx below comparator window 0x2 0x1 read-only ADC14LOIFG_enum_read read ADC14LOIFG_0 No interrupt pending 0 ADC14LOIFG_1 Interrupt pending 1 ADC14HIIFG Interrupt flag for ADC14MEMx above comparator window 0x3 0x1 read-only ADC14HIIFG_enum_read read ADC14HIIFG_0 No interrupt pending 0 ADC14HIIFG_1 Interrupt pending 1 ADC14OVIFG ADC14MEMx overflow interrupt flag 0x4 0x1 read-only ADC14OVIFG_enum_read read ADC14OVIFG_0 No interrupt pending 0 ADC14OVIFG_1 Interrupt pending 1 ADC14TOVIFG ADC14 conversion time overflow interrupt flag 0x5 0x1 read-only ADC14TOVIFG_enum_read read ADC14TOVIFG_0 No interrupt pending 0 ADC14TOVIFG_1 Interrupt pending 1 ADC14RDYIFG ADC14 local buffered reference ready interrupt flag 0x6 0x1 read-only ADC14RDYIFG_enum_read read ADC14RDYIFG_0 No interrupt pending 0 ADC14RDYIFG_1 Interrupt pending 1 ADC14CLRIFGR0 CLRIFGR0 Clear Interrupt Flag 0 Register 0x14C 32 write-only 0x00000000 0xffffffff CLRADC14IFG0 clear ADC14IFG0 0x0 0x1 write-only CLRADC14IFG0_enum_write write CLRADC14IFG0_0 no effect 0 CLRADC14IFG0_1 clear pending interrupt flag 1 CLRADC14IFG1 clear ADC14IFG1 0x1 0x1 write-only CLRADC14IFG1_enum_write write CLRADC14IFG1_0 no effect 0 CLRADC14IFG1_1 clear pending interrupt flag 1 CLRADC14IFG2 clear ADC14IFG2 0x2 0x1 write-only CLRADC14IFG2_enum_write write CLRADC14IFG2_0 no effect 0 CLRADC14IFG2_1 clear pending interrupt flag 1 CLRADC14IFG3 clear ADC14IFG3 0x3 0x1 write-only CLRADC14IFG3_enum_write write CLRADC14IFG3_0 no effect 0 CLRADC14IFG3_1 clear pending interrupt flag 1 CLRADC14IFG4 clear ADC14IFG4 0x4 0x1 write-only CLRADC14IFG4_enum_write write CLRADC14IFG4_0 no effect 0 CLRADC14IFG4_1 clear pending interrupt flag 1 CLRADC14IFG5 clear ADC14IFG5 0x5 0x1 write-only CLRADC14IFG5_enum_write write CLRADC14IFG5_0 no effect 0 CLRADC14IFG5_1 clear pending interrupt flag 1 CLRADC14IFG6 clear ADC14IFG6 0x6 0x1 write-only CLRADC14IFG6_enum_write write CLRADC14IFG6_0 no effect 0 CLRADC14IFG6_1 clear pending interrupt flag 1 CLRADC14IFG7 clear ADC14IFG7 0x7 0x1 write-only CLRADC14IFG7_enum_write write CLRADC14IFG7_0 no effect 0 CLRADC14IFG7_1 clear pending interrupt flag 1 CLRADC14IFG8 clear ADC14IFG8 0x8 0x1 write-only CLRADC14IFG8_enum_write write CLRADC14IFG8_0 no effect 0 CLRADC14IFG8_1 clear pending interrupt flag 1 CLRADC14IFG9 clear ADC14IFG9 0x9 0x1 write-only CLRADC14IFG9_enum_write write CLRADC14IFG9_0 no effect 0 CLRADC14IFG9_1 clear pending interrupt flag 1 CLRADC14IFG10 clear ADC14IFG10 0xA 0x1 write-only CLRADC14IFG10_enum_write write CLRADC14IFG10_0 no effect 0 CLRADC14IFG10_1 clear pending interrupt flag 1 CLRADC14IFG11 clear ADC14IFG11 0xB 0x1 write-only CLRADC14IFG11_enum_write write CLRADC14IFG11_0 no effect 0 CLRADC14IFG11_1 clear pending interrupt flag 1 CLRADC14IFG12 clear ADC14IFG12 0xC 0x1 write-only CLRADC14IFG12_enum_write write CLRADC14IFG12_0 no effect 0 CLRADC14IFG12_1 clear pending interrupt flag 1 CLRADC14IFG13 clear ADC14IFG13 0xD 0x1 write-only CLRADC14IFG13_enum_write write CLRADC14IFG13_0 no effect 0 CLRADC14IFG13_1 clear pending interrupt flag 1 CLRADC14IFG14 clear ADC14IFG14 0xE 0x1 write-only CLRADC14IFG14_enum_write write CLRADC14IFG14_0 no effect 0 CLRADC14IFG14_1 clear pending interrupt flag 1 CLRADC14IFG15 clear ADC14IFG15 0xF 0x1 write-only CLRADC14IFG15_enum_write write CLRADC14IFG15_0 no effect 0 CLRADC14IFG15_1 clear pending interrupt flag 1 CLRADC14IFG16 clear ADC14IFG16 0x10 0x1 write-only CLRADC14IFG16_enum_write write CLRADC14IFG16_0 no effect 0 CLRADC14IFG16_1 clear pending interrupt flag 1 CLRADC14IFG17 clear ADC14IFG17 0x11 0x1 write-only CLRADC14IFG17_enum_write write CLRADC14IFG17_0 no effect 0 CLRADC14IFG17_1 clear pending interrupt flag 1 CLRADC14IFG18 clear ADC14IFG18 0x12 0x1 write-only CLRADC14IFG18_enum_write write CLRADC14IFG18_0 no effect 0 CLRADC14IFG18_1 clear pending interrupt flag 1 CLRADC14IFG19 clear ADC14IFG19 0x13 0x1 write-only CLRADC14IFG19_enum_write write CLRADC14IFG19_0 no effect 0 CLRADC14IFG19_1 clear pending interrupt flag 1 CLRADC14IFG20 clear ADC14IFG20 0x14 0x1 write-only CLRADC14IFG20_enum_write write CLRADC14IFG20_0 no effect 0 CLRADC14IFG20_1 clear pending interrupt flag 1 CLRADC14IFG21 clear ADC14IFG21 0x15 0x1 write-only CLRADC14IFG21_enum_write write CLRADC14IFG21_0 no effect 0 CLRADC14IFG21_1 clear pending interrupt flag 1 CLRADC14IFG22 clear ADC14IFG22 0x16 0x1 write-only CLRADC14IFG22_enum_write write CLRADC14IFG22_0 no effect 0 CLRADC14IFG22_1 clear pending interrupt flag 1 CLRADC14IFG23 clear ADC14IFG23 0x17 0x1 write-only CLRADC14IFG23_enum_write write CLRADC14IFG23_0 no effect 0 CLRADC14IFG23_1 clear pending interrupt flag 1 CLRADC14IFG24 clear ADC14IFG24 0x18 0x1 write-only CLRADC14IFG24_enum_write write CLRADC14IFG24_0 no effect 0 CLRADC14IFG24_1 clear pending interrupt flag 1 CLRADC14IFG25 clear ADC14IFG25 0x19 0x1 write-only CLRADC14IFG25_enum_write write CLRADC14IFG25_0 no effect 0 CLRADC14IFG25_1 clear pending interrupt flag 1 CLRADC14IFG26 clear ADC14IFG26 0x1A 0x1 write-only CLRADC14IFG26_enum_write write CLRADC14IFG26_0 no effect 0 CLRADC14IFG26_1 clear pending interrupt flag 1 CLRADC14IFG27 clear ADC14IFG27 0x1B 0x1 write-only CLRADC14IFG27_enum_write write CLRADC14IFG27_0 no effect 0 CLRADC14IFG27_1 clear pending interrupt flag 1 CLRADC14IFG28 clear ADC14IFG28 0x1C 0x1 write-only CLRADC14IFG28_enum_write write CLRADC14IFG28_0 no effect 0 CLRADC14IFG28_1 clear pending interrupt flag 1 CLRADC14IFG29 clear ADC14IFG29 0x1D 0x1 write-only CLRADC14IFG29_enum_write write CLRADC14IFG29_0 no effect 0 CLRADC14IFG29_1 clear pending interrupt flag 1 CLRADC14IFG30 clear ADC14IFG30 0x1E 0x1 write-only CLRADC14IFG30_enum_write write CLRADC14IFG30_0 no effect 0 CLRADC14IFG30_1 clear pending interrupt flag 1 CLRADC14IFG31 clear ADC14IFG31 0x1F 0x1 write-only CLRADC14IFG31_enum_write write CLRADC14IFG31_0 no effect 0 CLRADC14IFG31_1 clear pending interrupt flag 1 ADC14CLRIFGR1 CLRIFGR1 Clear Interrupt Flag 1 Register 0x150 32 read-write 0x00000000 0xffffffff CLRADC14INIFG clear ADC14INIFG 0x1 0x1 write-only CLRADC14INIFG_enum_write write CLRADC14INIFG_0 no effect 0 CLRADC14INIFG_1 clear pending interrupt flag 1 CLRADC14LOIFG clear ADC14LOIFG 0x2 0x1 write-only CLRADC14LOIFG_enum_write write CLRADC14LOIFG_0 no effect 0 CLRADC14LOIFG_1 clear pending interrupt flag 1 CLRADC14HIIFG clear ADC14HIIFG 0x3 0x1 write-only CLRADC14HIIFG_enum_write write CLRADC14HIIFG_0 no effect 0 CLRADC14HIIFG_1 clear pending interrupt flag 1 CLRADC14OVIFG clear ADC14OVIFG 0x4 0x1 write-only CLRADC14OVIFG_enum_write write CLRADC14OVIFG_0 no effect 0 CLRADC14OVIFG_1 clear pending interrupt flag 1 CLRADC14TOVIFG clear ADC14TOVIFG 0x5 0x1 write-only CLRADC14TOVIFG_enum_write write CLRADC14TOVIFG_0 no effect 0 CLRADC14TOVIFG_1 clear pending interrupt flag 1 CLRADC14RDYIFG clear ADC14RDYIFG 0x6 0x1 write-only CLRADC14RDYIFG_enum_write write CLRADC14RDYIFG_0 no effect 0 CLRADC14RDYIFG_1 clear pending interrupt flag 1 ADC14IV IV Interrupt Vector Register 0x154 32 read-write 0x00000000 0xffffffff ADC14IV ADC14 interrupt vector value 0x0 0x20 read-write ADC14IV_0 No interrupt pending 0 ADC14IV_2 Interrupt Source: ADC14MEMx overflow; Interrupt Flag: ADC14OVIFG; Interrupt Priority: Highest 2 ADC14IV_4 Interrupt Source: Conversion time overflow; Interrupt Flag: ADC14TOVIFG 4 ADC14IV_6 Interrupt Source: ADC14 window high interrupt flag; Interrupt Flag: ADC14HIIFG 6 ADC14IV_8 Interrupt Source: ADC14 window low interrupt flag; Interrupt Flag: ADC14LOIFG 8 ADC14IV_10 Interrupt Source: ADC14 in-window interrupt flag; Interrupt Flag: ADC14INIFG 10 ADC14IV_12 Interrupt Source: ADC14MEM0 interrupt flag; Interrupt Flag: ADC14IFG0 12 ADC14IV_14 Interrupt Source: ADC14MEM1 interrupt flag; Interrupt Flag: ADC14IFG1 14 ADC14IV_16 Interrupt Source: ADC14MEM2 interrupt flag; Interrupt Flag: ADC14IFG2 16 ADC14IV_18 Interrupt Source: ADC14MEM3 interrupt flag; Interrupt Flag: ADC14IFG3 18 ADC14IV_20 Interrupt Source: ADC14MEM4 interrupt flag; Interrupt Flag: ADC14IFG4 20 ADC14IV_22 Interrupt Source: ADC14MEM5 interrupt flag; Interrupt Flag: ADC14IFG5 22 ADC14IV_24 Interrupt Source: ADC14MEM6 interrupt flag; Interrupt Flag: ADC14IFG6 24 ADC14IV_26 Interrupt Source: ADC14MEM7 interrupt flag; Interrupt Flag: ADC14IFG7 26 ADC14IV_28 Interrupt Source: ADC14MEM8 interrupt flag; Interrupt Flag: ADC14IFG8 28 ADC14IV_30 Interrupt Source: ADC14MEM9 interrupt flag; Interrupt Flag: ADC14IFG9 30 ADC14IV_32 Interrupt Source: ADC14MEM10 interrupt flag; Interrupt Flag: ADC14IFG10 32 ADC14IV_34 Interrupt Source: ADC14MEM11 interrupt flag; Interrupt Flag: ADC14IFG11 34 ADC14IV_36 Interrupt Source: ADC14MEM12 interrupt flag; Interrupt Flag: ADC14IFG12 36 ADC14IV_38 Interrupt Source: ADC14MEM13 interrupt flag; Interrupt Flag: ADC14IFG13 38 ADC14IV_40 Interrupt Source: ADC14MEM14 interrupt flag; Interrupt Flag: ADC14IFG14 40 ADC14IV_42 Interrupt Source: ADC14MEM15 interrupt flag; Interrupt Flag: ADC14IFG15 42 ADC14IV_44 Interrupt Source: ADC14MEM16 interrupt flag; Interrupt Flag: ADC14IFG16 44 ADC14IV_46 Interrupt Source: ADC14MEM17 interrupt flag; Interrupt Flag: ADC14IFG17 46 ADC14IV_48 Interrupt Source: ADC14MEM18 interrupt flag; Interrupt Flag: ADC14IFG18 48 ADC14IV_50 Interrupt Source: ADC14MEM19 interrupt flag; Interrupt Flag: ADC14IFG19 50 ADC14IV_52 Interrupt Source: ADC14MEM20 interrupt flag; Interrupt Flag: ADC14IFG20 52 ADC14IV_54 Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22 54 ADC14IV_56 Interrupt Source: ADC14MEM22 interrupt flag; Interrupt Flag: ADC14IFG22 56 ADC14IV_58 Interrupt Source: ADC14MEM23 interrupt flag; Interrupt Flag: ADC14IFG23 58 ADC14IV_60 Interrupt Source: ADC14MEM24 interrupt flag; Interrupt Flag: ADC14IFG24 60 ADC14IV_62 Interrupt Source: ADC14MEM25 interrupt flag; Interrupt Flag: ADC14IFG25 62 ADC14IV_64 Interrupt Source: ADC14MEM26 interrupt flag; Interrupt Flag: ADC14IFG26 64 ADC14IV_66 Interrupt Source: ADC14MEM27 interrupt flag; Interrupt Flag: ADC14IFG27 66 ADC14IV_68 Interrupt Source: ADC14MEM28 interrupt flag; Interrupt Flag: ADC14IFG28 68 ADC14IV_70 Interrupt Source: ADC14MEM29 interrupt flag; Interrupt Flag: ADC14IFG29 70 ADC14IV_72 Interrupt Source: ADC14MEM30 interrupt flag; Interrupt Flag: ADC14IFG30 72 ADC14IV_74 Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31 74 ADC14IV_76 Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Interrupt Priority: Lowest 76 ITM 356.0 ITM 0xE0000000 0x0 0x1000 registers ITM_STIM0 STIM0 ITM Stimulus Port 0 0x0 32 read-write ITM_STIM1 STIM1 ITM Stimulus Port 1 0x4 32 read-write ITM_STIM2 STIM2 ITM Stimulus Port 2 0x8 32 read-write ITM_STIM3 STIM3 ITM Stimulus Port 3 0xC 32 read-write ITM_STIM4 STIM4 ITM Stimulus Port 4 0x10 32 read-write ITM_STIM5 STIM5 ITM Stimulus Port 5 0x14 32 read-write ITM_STIM6 STIM6 ITM Stimulus Port 6 0x18 32 read-write ITM_STIM7 STIM7 ITM Stimulus Port 7 0x1C 32 read-write ITM_STIM8 STIM8 ITM Stimulus Port 8 0x20 32 read-write ITM_STIM9 STIM9 ITM Stimulus Port 9 0x24 32 read-write ITM_STIM10 STIM10 ITM Stimulus Port 10 0x28 32 read-write ITM_STIM11 STIM11 ITM Stimulus Port 11 0x2C 32 read-write ITM_STIM12 STIM12 ITM Stimulus Port 12 0x30 32 read-write ITM_STIM13 STIM13 ITM Stimulus Port 13 0x34 32 read-write ITM_STIM14 STIM14 ITM Stimulus Port 14 0x38 32 read-write ITM_STIM15 STIM15 ITM Stimulus Port 15 0x3C 32 read-write ITM_STIM16 STIM16 ITM Stimulus Port 16 0x40 32 read-write ITM_STIM17 STIM17 ITM Stimulus Port 17 0x44 32 read-write ITM_STIM18 STIM18 ITM Stimulus Port 18 0x48 32 read-write ITM_STIM19 STIM19 ITM Stimulus Port 19 0x4C 32 read-write ITM_STIM20 STIM20 ITM Stimulus Port 20 0x50 32 read-write ITM_STIM21 STIM21 ITM Stimulus Port 21 0x54 32 read-write ITM_STIM22 STIM22 ITM Stimulus Port 22 0x58 32 read-write ITM_STIM23 STIM23 ITM Stimulus Port 23 0x5C 32 read-write ITM_STIM24 STIM24 ITM Stimulus Port 24 0x60 32 read-write ITM_STIM25 STIM25 ITM Stimulus Port 25 0x64 32 read-write ITM_STIM26 STIM26 ITM Stimulus Port 26 0x68 32 read-write ITM_STIM27 STIM27 ITM Stimulus Port 27 0x6C 32 read-write ITM_STIM28 STIM28 ITM Stimulus Port 28 0x70 32 read-write ITM_STIM29 STIM29 ITM Stimulus Port 29 0x74 32 read-write ITM_STIM30 STIM30 ITM Stimulus Port 30 0x78 32 read-write ITM_STIM31 STIM31 ITM Stimulus Port 31 0x7C 32 read-write ITM_TER TER ITM Trace Enable Register 0xE00 32 read-write 0x00000000 STIMENA Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port. 0x0 0x20 read-write ITM_TPR TPR ITM Trace Privilege Register 0xE40 32 read-write 0x00000000 PRIVMASK Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0], bit [1] = stimulus ports [15:8], bit [2] = stimulus ports [23:16], bit [3] = stimulus ports [31:24]. 0x0 0x4 read-write ITM_TCR TCR ITM Trace Control Register 0xE80 32 read-write 0x00000000 ITMENA Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. 0x0 0x1 read-write TSENA Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle. 0x1 0x1 read-write SYNCENA Enables sync packets for TPIU. 0x2 0x1 read-write DWTENA Enables the DWT stimulus. 0x3 0x1 read-write SWOENA Enables asynchronous clocking of the timestamp counter. 0x4 0x1 read-write TSPRESCALE TSPrescale Timestamp prescaler. 0x8 0x2 read-write en_0b00 no prescaling 0 en_0b01 divide by 4 1 en_0b10 divide by 16 2 en_0b11 divide by 64 3 ATBID ATB ID for CoreSight system. 0x10 0x7 read-write BUSY Set when ITM events present and being drained. 0x17 0x1 read-write ITM_IWR IWR ITM Integration Write Register 0xEF8 32 write-only 0x00000000 ATVALIDM When the integration mode is set: 0 = ATVALIDM clear. 1 = ATVALIDM set. 0x0 0x1 write-only en_0b0 ATVALIDM clear 0 en_0b1 ATVALIDM set 1 ITM_IMCR IMCR ITM Integration Mode Control Register 0xF00 32 read-write 0x00000000 INTEGRATION 0x0 0x1 read-write en_0b0 ATVALIDM normal 0 en_0b1 ATVALIDM driven from Integration Write Register 1 ITM_LAR LAR ITM Lock Access Register 0xFB0 32 write-only 0x00000000 LOCK_ACCESS A privileged write of 0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC. An invalid write removes write access. 0x0 0x20 write-only ITM_LSR LSR ITM Lock Status Register 0xFB4 32 read-only 0x00000003 PRESENT Indicates that a lock mechanism exists for this component. 0x0 0x1 read-only ACCESS Write access to component is blocked. All writes are ignored, reads are permitted. 0x1 0x1 read-only BYTEACC You cannot implement 8-bit lock accesses. 0x2 0x1 read-only DWT 356.0 DWT 0xE0001000 0x0 0x1000 registers DWT_CTRL CTRL DWT Control Register 0x0 32 read-write 0x40000000 CYCCNTENA Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0. 0x0 0x1 read-write POSTPRESET Reload value for POSTCNT, bits [8:5], post-scalar counter. If this value is 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change. 0x1 0x4 read-write POSTCNT Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]). 0x5 0x4 read-write CYCTAP Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]. When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT. 0x9 0x1 read-write en_0b0 selects bit [6] to tap 0 en_0b1 selects bit [10] to tap. 1 SYNCTAP Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1. 0xA 0x2 read-write en_0b00 Disabled. No synch counting. 0 en_0b01 Tap at CYCCNT bit 24. 1 en_0b10 Tap at CYCCNT bit 26. 2 en_0b11 Tap at CYCCNT bit 28. 3 PCSAMPLEENA Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]). Reset clears the PCSAMPLENA bit. 0xC 0x1 read-write en_0b0 PC Sampling event disabled. 0 en_0b1 Sampling event enabled. 1 EXCTRCENA Enables Interrupt event tracing. Reset clears the EXCEVTENA bit. 0x10 0x1 read-write en_0b0 interrupt event trace disabled. 0 en_0b1 interrupt event trace enabled. 1 CPIEVTENA Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions). Reset clears the CPIEVTENA bit. 0x11 0x1 read-write en_0b0 CPI counter events disabled. 0 en_0b1 CPI counter events enabled. 1 EXCEVTENA Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). Reset clears the EXCEVTENA bit. 0x12 0x1 read-write en_0b0 Interrupt overhead event disabled. 0 en_0b1 Interrupt overhead event enabled. 1 SLEEPEVTENA Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit. 0x13 0x1 read-write en_0b0 Sleep count events disabled. 0 en_0b1 Sleep count events enabled. 1 LSUEVTENA Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. Reset clears the LSUEVTENA bit. 0x14 0x1 read-write en_0b0 LSU count events disabled. 0 en_0b1 LSU count events enabled. 1 FOLDEVTENA Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. Reset clears the FOLDEVTENA bit. 0x15 0x1 read-write en_0b0 Folded instruction count events disabled. 0 en_0b1 Folded instruction count events enabled. 1 CYCEVTENA Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit. 0x16 0x1 read-write en_0b0 Cycle count events disabled. 0 en_0b1 Cycle count events enabled. 1 NOPRFCNT When set, DWT_FOLDCNT, DWT_LSUCNT, DWT_SLEEPCNT, DWT_EXCCNT, and DWT_CPICNT are not supported. 0x18 0x1 read-write NOCYCCNT When set, DWT_CYCCNT is not supported. 0x19 0x1 read-write DWT_CYCCNT CYCCNT DWT Current PC Sampler Cycle Count Register 0x4 32 read-write 0x00000000 CYCCNT Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. 0x0 0x20 read-write DWT_CPICNT CPICNT DWT CPI Count Register 0x8 32 read-write CPICNT Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by DWT_LSUCNT. This counter also increments on all instruction fetch stalls. If CPIEVTENA is set, an event is emitted when the counter overflows. Clears to 0 on enabling. 0x0 0x8 read-write DWT_EXCCNT EXCCNT DWT Exception Overhead Count Register 0xC 32 read-write EXCCNT Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling. 0x0 0x8 read-write DWT_SLEEPCNT SLEEPCNT DWT Sleep Count Register 0x10 32 read-write SLEEPCNT Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Note that SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep. 0x0 0x8 read-write DWT_LSUCNT LSUCNT DWT LSU Count Register 0x14 32 read-write LSUCNT LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling. 0x0 0x8 read-write DWT_FOLDCNT FOLDCNT DWT Fold Count Register 0x18 32 read-write FOLDCNT This counts the total number folded instructions. This counter initializes to 0 when enabled. 0x0 0x8 read-write DWT_PCSR PCSR DWT Program Counter Sample Register 0x1C 32 read-only EIASAMPLE Execution instruction address sample, or 0xFFFFFFFF if the core is halted. 0x0 0x20 read-only DWT_COMP0 COMP0 DWT Comparator Register 0 0x20 32 read-write COMP Data value to compare against PC and the data address as given by DWT_FUNCTION0. DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT). 0x0 0x20 read-write DWT_MASK0 MASK0 DWT Mask Register 0 0x24 32 read-write MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0x0 0x4 read-write DWT_FUNCTION0 FUNCTION0 DWT Function Register 0 0x28 32 read-write 0x00000000 FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0x0 0x4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 0x5 0x1 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 0x8 0x1 read-write LNK1ENA 0x9 0x1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 0xA 0x2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 0xC 0x4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 0x10 0x4 read-write MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 0x18 0x1 read-write DWT_COMP1 COMP1 DWT Comparator Register 1 0x30 32 read-write COMP Data value to compare against PC and the data address as given by DWT_FUNCTION1. 0x0 0x20 read-write DWT_MASK1 MASK1 DWT Mask Register 1 0x34 32 read-write MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0x0 0x4 read-write DWT_FUNCTION1 FUNCTION1 DWT Function Register 1 0x38 32 read-write 0x00000000 FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 in DWT_FUNCTION1if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0x0 0x4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 0x5 0x1 read-write CYCMATCH Only available in comparator 0. When set, this comparator compares against the clock cycle counter. 0x7 0x1 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 0x8 0x1 read-write LNK1ENA 0x9 0x1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 0xA 0x2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 0xC 0x4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 0x10 0x4 read-write MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 0x18 0x1 read-write DWT_COMP2 COMP2 DWT Comparator Register 2 0x40 32 read-write COMP Data value to compare against PC and the data address as given by DWT_FUNCTION2. 0x0 0x20 read-write DWT_MASK2 MASK2 DWT Mask Register 2 0x44 32 read-write MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0x0 0x4 read-write DWT_FUNCTION2 FUNCTION2 DWT Function Register 2 0x48 32 read-write 0x00000000 FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0x0 0x4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 0x5 0x1 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 0x8 0x1 read-write LNK1ENA 0x9 0x1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 0xA 0x2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 0xC 0x4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 0x10 0x4 read-write MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 0x18 0x1 read-write DWT_COMP3 COMP3 DWT Comparator Register 3 0x50 32 read-write COMP Data value to compare against PC and the data address as given by DWT_FUNCTION3. 0x0 0x20 read-write DWT_MASK3 MASK3 DWT Mask Register 3 0x54 32 read-write MASK Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. 0x0 0x4 read-write DWT_FUNCTION3 FUNCTION3 DWT Function Register 3 0x58 32 read-write 0x00000000 FUNCTION Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. 0x0 0x4 read-write en_0b0000 Disabled 0 en_0b0001 EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM 1 en_0b0010 EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. 2 en_0b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. 3 en_0b0100 Watchpoint on PC match. 4 en_0b0101 Watchpoint on read. 5 en_0b0110 Watchpoint on write. 6 en_0b0111 Watchpoint on read or write. 7 en_0b1000 ETM trigger on PC match 8 en_0b1001 ETM trigger on read 9 en_0b1010 ETM trigger on write 10 en_0b1011 ETM trigger on read or write 11 en_0b1100 EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers 12 en_0b1101 EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers 13 en_0b1110 EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers 14 en_0b1111 EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers 15 EMITRANGE Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. 0x5 0x1 read-write DATAVMATCH This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison. 0x8 0x1 read-write LNK1ENA 0x9 0x1 read-only en_0b0 DATAVADDR1 not supported 0 en_0b1 DATAVADDR1 supported (enabled). 1 DATAVSIZE Defines the size of the data in the COMP register that is to be matched: 0xA 0x2 read-write en_0b00 byte 0 en_0b01 halfword 1 en_0b10 word 2 en_0b11 Unpredictable. 3 DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 1. 0xC 0x4 read-write DATAVADDR1 Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. 0x10 0x4 read-write MATCHED This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. 0x18 0x1 read-write FPB 356.0 FPB 0xE0002000 0x0 0x1000 registers FP_CTRL FP_CTRL Flash Patch Control Register 0x0 32 read-write 0x00000130 ENABLE Flash patch unit enable bit 0x0 0x1 read-write en_0b0 flash patch unit disabled 0 en_0b1 flash patch unit enabled 1 KEY Key field. To write to the Flash Patch Control Register, you must write a 1 to this write-only bit. 0x1 0x1 write-only NUM_CODE1 Number of code slots field. 0x4 0x4 read-only en_0b0000 no code slots 0 en_0b0010 two code slots 2 en_0b0110 six code slots 6 NUM_LIT Number of literal slots field. 0x8 0x4 read-only en_0b0000 no literal slots 0 en_0b0010 two literal slots 2 NUM_CODE2 Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE. This read only field contains 3'b000 to indicate 0 banks for Cortex-M4 processor. 0xC 0x2 read-only FP_REMAP FP_REMAP Flash Patch Remap Register 0x4 32 read-write REMAP Remap base address field. 0x5 0x18 read-write FP_COMP0 FP_COMP0 Flash Patch Comparator Registers 0x8 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 0. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 0 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 0 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP1 FP_COMP1 Flash Patch Comparator Registers 0xC 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 1. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 1 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 1 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP2 FP_COMP2 Flash Patch Comparator Registers 0x10 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 2. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 2 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 2 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP3 FP_COMP3 Flash Patch Comparator Registers 0x14 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 3. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 3 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 3 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP4 FP_COMP4 Flash Patch Comparator Registers 0x18 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 4. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 4 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 4 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP5 FP_COMP5 Flash Patch Comparator Registers 0x1C 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 5. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 5 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 5 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP6 FP_COMP6 Flash Patch Comparator Registers 0x20 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 6. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 6 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 6 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 FP_COMP7 FP_COMP7 Flash Patch Comparator Registers 0x24 32 read-write 0x00000000 0x00000001 ENABLE Compare and remap enable for Flash Patch Comparator Register 7. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 Flash Patch Comparator Register 7 compare and remap disabled 0 en_0b1 Flash Patch Comparator Register 7 compare and remap enabled 1 COMP Comparison address. 0x2 0x1B read-write REPLACE This selects what happens when the COMP address is matched. Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings. Address remapping only takes place for the b00 setting. 0x1E 0x2 read-write en_0b00 remap to remap address. See FP_REMAP 0 en_0b01 set BKPT on lower halfword, upper is unaffected 1 en_0b10 set BKPT on upper halfword, lower is unaffected 2 en_0b11 set BKPT on both lower and upper halfwords. 3 SystemControlSpace 356.0 System Control Space for ARM core: SCnSCB, SCB, SysTick, NVIC, CoreDebug, MPU, FPU 0xE000E000 0x0 0x1000 registers ICTR ICTR Interrupt Control Type Register 0x4 32 read-only 0x00000000 INTLINESNUM Total number of interrupt lines in groups of 32. 0x0 0x5 read-only ACTLR ACTLR Auxiliary Control Register 0x8 32 read-write 0x00000000 DISMCYCINT Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. 0x0 0x1 read-write DISDEFWBUF Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed. 0x1 0x1 read-write DISFOLD Disables IT folding. 0x2 0x1 read-write DISFPCA Disable automatic update of CONTROL.FPCA 0x8 0x1 read-write DISOOFP Disables floating point instructions completing out of order with respect to integer instructions. 0x9 0x1 read-write 0x0 0x1000 registers ISER0 ISER0 Irq 0 to 31 Set Enable Register 0x100 32 read-write 0x00000000 SETENA Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields. 0x0 0x20 read-write ISER1 ISER1 Irq 32 to 63 Set Enable Register 0x104 32 read-write 0x00000000 SETENA Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields. 0x0 0x20 read-write ICER0 ICER0 Irq 0 to 31 Clear Enable Register 0x180 32 read-write 0x00000000 CLRENA Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field. 0x0 0x20 read-write ICER1 ICER1 Irq 32 to 63 Clear Enable Register 0x184 32 read-write 0x00000000 CLRENA Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field. 0x0 0x20 read-write ISPR0 ISPR0 Irq 0 to 31 Set Pending Register 0x200 32 read-write 0x00000000 SETPEND Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state. 0x0 0x20 read-write ISPR1 ISPR1 Irq 32 to 63 Set Pending Register 0x204 32 read-write 0x00000000 SETPEND Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state. 0x0 0x20 read-write ICPR0 ICPR0 Irq 0 to 31 Clear Pending Register 0x280 32 read-write 0x00000000 CLRPEND Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state. 0x0 0x20 read-write ICPR1 ICPR1 Irq 32 to 63 Clear Pending Register 0x284 32 read-write 0x00000000 CLRPEND Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state. 0x0 0x20 read-write IABR0 IABR0 Irq 0 to 31 Active Bit Register 0x300 32 read-only 0x00000000 ACTIVE Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked. 0x0 0x20 read-only IABR1 IABR1 Irq 32 to 63 Active Bit Register 0x304 32 read-only 0x00000000 ACTIVE Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked. 0x0 0x20 read-only IPR0 IPR0 Irq 0 to 3 Priority Register 0x400 32 read-write 0x00000000 PRI_0 Priority of interrupt 0 0x0 0x8 read-write PRI_1 Priority of interrupt 1 0x8 0x8 read-write PRI_2 Priority of interrupt 2 0x10 0x8 read-write PRI_3 Priority of interrupt 3 0x18 0x8 read-write IPR1 IPR1 Irq 4 to 7 Priority Register 0x404 32 read-write 0x00000000 PRI_4 Priority of interrupt 4 0x0 0x8 read-write PRI_5 Priority of interrupt 5 0x8 0x8 read-write PRI_6 Priority of interrupt 6 0x10 0x8 read-write PRI_7 Priority of interrupt 7 0x18 0x8 read-write IPR2 IPR2 Irq 8 to 11 Priority Register 0x408 32 read-write 0x00000000 PRI_8 Priority of interrupt 8 0x0 0x8 read-write PRI_9 Priority of interrupt 9 0x8 0x8 read-write PRI_10 Priority of interrupt 10 0x10 0x8 read-write PRI_11 Priority of interrupt 11 0x18 0x8 read-write IPR3 IPR3 Irq 12 to 15 Priority Register 0x40C 32 read-write 0x00000000 PRI_12 Priority of interrupt 12 0x0 0x8 read-write PRI_13 Priority of interrupt 13 0x8 0x8 read-write PRI_14 Priority of interrupt 14 0x10 0x8 read-write PRI_15 Priority of interrupt 15 0x18 0x8 read-write IPR4 IPR4 Irq 16 to 19 Priority Register 0x410 32 read-write 0x00000000 PRI_16 Priority of interrupt 16 0x0 0x8 read-write PRI_17 Priority of interrupt 17 0x8 0x8 read-write PRI_18 Priority of interrupt 18 0x10 0x8 read-write PRI_19 Priority of interrupt 19 0x18 0x8 read-write IPR5 IPR5 Irq 20 to 23 Priority Register 0x414 32 read-write 0x00000000 PRI_20 Priority of interrupt 20 0x0 0x8 read-write PRI_21 Priority of interrupt 21 0x8 0x8 read-write PRI_22 Priority of interrupt 22 0x10 0x8 read-write PRI_23 Priority of interrupt 23 0x18 0x8 read-write IPR6 IPR6 Irq 24 to 27 Priority Register 0x418 32 read-write 0x00000000 PRI_24 Priority of interrupt 24 0x0 0x8 read-write PRI_25 Priority of interrupt 25 0x8 0x8 read-write PRI_26 Priority of interrupt 26 0x10 0x8 read-write PRI_27 Priority of interrupt 27 0x18 0x8 read-write IPR7 IPR7 Irq 28 to 31 Priority Register 0x41C 32 read-write 0x00000000 PRI_28 Priority of interrupt 28 0x0 0x8 read-write PRI_29 Priority of interrupt 29 0x8 0x8 read-write PRI_30 Priority of interrupt 30 0x10 0x8 read-write PRI_31 Priority of interrupt 31 0x18 0x8 read-write IPR8 IPR8 Irq 32 to 35 Priority Register 0x420 32 read-write 0x00000000 PRI_32 Priority of interrupt 32 0x0 0x8 read-write PRI_33 Priority of interrupt 33 0x8 0x8 read-write PRI_34 Priority of interrupt 34 0x10 0x8 read-write PRI_35 Priority of interrupt 35 0x18 0x8 read-write IPR9 IPR9 Irq 36 to 39 Priority Register 0x424 32 read-write 0x00000000 PRI_36 Priority of interrupt 36 0x0 0x8 read-write PRI_37 Priority of interrupt 37 0x8 0x8 read-write PRI_38 Priority of interrupt 38 0x10 0x8 read-write PRI_39 Priority of interrupt 39 0x18 0x8 read-write IPR10 IPR10 Irq 40 to 43 Priority Register 0x428 32 read-write 0x00000000 PRI_40 Priority of interrupt 40 0x0 0x8 read-write PRI_41 Priority of interrupt 41 0x8 0x8 read-write PRI_42 Priority of interrupt 42 0x10 0x8 read-write PRI_43 Priority of interrupt 43 0x18 0x8 read-write IPR11 IPR11 Irq 44 to 47 Priority Register 0x42C 32 read-write 0x00000000 PRI_44 Priority of interrupt 44 0x0 0x8 read-write PRI_45 Priority of interrupt 45 0x8 0x8 read-write PRI_46 Priority of interrupt 46 0x10 0x8 read-write PRI_47 Priority of interrupt 47 0x18 0x8 read-write IPR12 IPR12 Irq 48 to 51 Priority Register 0x430 32 read-write 0x00000000 PRI_48 Priority of interrupt 48 0x0 0x8 read-write PRI_49 Priority of interrupt 49 0x8 0x8 read-write PRI_50 Priority of interrupt 50 0x10 0x8 read-write PRI_51 Priority of interrupt 51 0x18 0x8 read-write IPR13 IPR13 Irq 52 to 55 Priority Register 0x434 32 read-write 0x00000000 PRI_52 Priority of interrupt 52 0x0 0x8 read-write PRI_53 Priority of interrupt 53 0x8 0x8 read-write PRI_54 Priority of interrupt 54 0x10 0x8 read-write PRI_55 Priority of interrupt 55 0x18 0x8 read-write IPR14 IPR14 Irq 56 to 59 Priority Register 0x438 32 read-write 0x00000000 PRI_56 Priority of interrupt 56 0x0 0x8 read-write PRI_57 Priority of interrupt 57 0x8 0x8 read-write PRI_58 Priority of interrupt 58 0x10 0x8 read-write PRI_59 Priority of interrupt 59 0x18 0x8 read-write IPR15 IPR15 Irq 60 to 63 Priority Register 0x43C 32 read-write 0x00000000 PRI_60 Priority of interrupt 60 0x0 0x8 read-write PRI_61 Priority of interrupt 61 0x8 0x8 read-write PRI_62 Priority of interrupt 62 0x10 0x8 read-write PRI_63 Priority of interrupt 63 0x18 0x8 read-write STIR STIR Software Trigger Interrupt Register 0xF00 32 write-only 0x00000000 INTID Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register. 0x0 0x9 write-only 0x0 0x1000 registers STCSR STCSR SysTick Control and Status Register 0x10 32 read-write 0x00000004 0xffffffff ENABLE Enable SysTick counter 0x0 0x1 read-write First Counter disabled 0 TICKINT 0x1 0x1 read-write VAL_0 Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. 0 VAL_1 Counting down to zero pends the SysTick handler. 1 CLKSOURCE Clock source. 0x2 0x1 read-only CLKSOURCE_enum_read read VAL_0 Not applicable 0 VAL_1 Core clock 1 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 0x10 0x1 read-only STRVR STRVR SysTick Reload Value Register 0x14 32 read-write RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0. 0x0 0x18 read-write STCVR STCVR SysTick Current Value Register 0x18 32 read-write CURRENT Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 0x0 0x18 read-write STCR STCR SysTick Calibration Value Register 0x1C 32 read-only TENMS Reads as zero. Indicates calibration value is not known. 0x0 0x18 read-only SKEW Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. 0x1E 0x1 read-only NOREF Reads as one. Indicates that no separate reference clock is provided. 0x1F 0x1 read-only 0x0 0x1000 registers CPUID CPUID CPUID Base Register 0xD00 32 read-only 0x410fc241 REVISION Implementation defined revision number. 0x0 0x4 read-only PARTNO Number of processor within family. 0x4 0xC read-only CONSTANT Reads as 0xC 0x10 0x4 read-only VARIANT Implementation defined variant number. 0x14 0x4 read-only IMPLEMENTER Implementor code. 0x18 0x8 read-only ICSR ICSR Interrupt Control State Register 0xD04 32 read-write 0x00000000 VECTACTIVE Active ISR number field. Reset clears the VECTACTIVE field. 0x0 0x9 read-only RETTOBASE This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set. 0xB 0x1 read-only VECTPENDING Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR. 0xC 0x6 read-only ISRPENDING Interrupt pending flag. Excludes NMI and faults. 0x16 0x1 read-only en_0b0 interrupt not pending 0 en_0b1 interrupt pending 1 ISRPREEMPT You must only use this at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. 0x17 0x1 read-only en_0b0 a pending exception is not serviced. 0 en_0b1 a pending exception is serviced on exit from the debug halt state 1 PENDSTCLR Clear pending SysTick bit 0x19 0x1 write-only en_0b0 do not clear pending SysTick 0 en_0b1 clear pending SysTick 1 PENDSTSET Set a pending SysTick bit. 0x1A 0x1 read-write en_0b0 do not set pending SysTick 0 en_0b1 set pending SysTick 1 PENDSVCLR Clear pending pendSV bit 0x1B 0x1 write-only en_0b0 do not clear pending pendSV 0 en_0b1 clear pending pendSV 1 PENDSVSET Set pending pendSV bit. 0x1C 0x1 read-write en_0b0 do not set pending pendSV 0 en_0b1 set pending PendSV 1 NMIPENDSET Set pending NMI bit. NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 0x1F 0x1 read-write en_0b0 do not set pending NMI 0 en_0b1 set pending NMI 1 VTOR VTOR Vector Table Offset Register 0xD08 32 read-write 0x00000000 TBLOFF Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space. 0x7 0x16 read-write TBLBASE Table base is in Code (0) or RAM (1). 0x1D 0x1 read-write AIRCR AIRCR Application Interrupt/Reset Control Register 0xD0C 32 read-write 0xfa050000 0xffff7fff VECTRESET System Reset bit. Resets the system, with the exception of debug components. The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted. 0x0 0x1 write-only VECTCLRACTIVE Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. The VECTCLRACTIVE bit is for returning to a known state during debug. The VECTCLRACTIVE bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. 0x1 0x1 write-only SYSRESETREQ Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running. 0x2 0x1 write-only PRIGROUP Interrupt priority grouping field. The PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices 0x8 0x3 read-write ENDIANESS Data endianness bit. ENDIANNESS is sampled from the BIGEND input port during reset. You cannot change ENDIANNESS outside of reset. 0xF 0x1 read-only en_0b0 little endian 0 en_0b1 big endian 1 VECTKEY Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored. 0x10 0x10 write-only SCR SCR System Control Register 0xD10 32 read-write 0x00000000 SLEEPONEXIT Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 0x1 0x1 read-write en_0b0 do not sleep when returning to thread mode 0 en_0b1 sleep on ISR exit 1 SLEEPDEEP Sleep deep bit. 0x2 0x1 read-write en_0b0 not OK to turn off system clock 0 en_0b1 indicates to the system that Cortex-M4 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped. 1 SEVONPEND When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE. 0x4 0x1 read-write CCR CCR Configuration Control Register 0xD14 32 read-write 0x00000200 NONBASETHREDENA When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value. 0x0 0x1 read-write USERSETMPEND If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer. 0x1 0x1 read-write UNALIGN_TRP Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED. 0x3 0x1 read-write DIV_0_TRP Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO. 0x4 0x1 read-write BFHFNMIGN When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored therefore you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them. 0x8 0x1 read-write STKALIGN Stack alignment bit. 0x9 0x1 read-write en_0b0 Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry. 0 en_0b1 On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. 1 SHPR1 SHPR1 System Handlers 4-7 Priority Register 0xD18 32 read-write 0x00000000 PRI_4 Priority of system handler 4. 0x0 0x8 read-write PRI_5 Priority of system handler 5. 0x8 0x8 read-write PRI_6 Priority of system handler 6. 0x10 0x8 read-write PRI_7 Priority of system handler 7. 0x18 0x8 read-write SHPR2 SHPR2 System Handlers 8-11 Priority Register 0xD1C 32 read-write 0x00000000 PRI_8 Priority of system handler 8. 0x0 0x8 read-write PRI_9 Priority of system handler 9. 0x8 0x8 read-write PRI_10 Priority of system handler 10. 0x10 0x8 read-write PRI_11 Priority of system handler 11. 0x18 0x8 read-write SHPR3 SHPR3 System Handlers 12-15 Priority Register 0xD20 32 read-write 0x00000000 PRI_12 Priority of system handler 12. 0x0 0x8 read-write PRI_13 Priority of system handler 13. 0x8 0x8 read-write PRI_14 Priority of system handler 14. 0x10 0x8 read-write PRI_15 Priority of system handler 15. 0x18 0x8 read-write SHCSR SHCSR System Handler Control and State Register 0xD24 32 read-write 0x00000000 MEMFAULTACT MemManage active flag. 0x0 0x1 read-only en_0b0 not active 0 en_0b1 active 1 BUSFAULTACT BusFault active flag. 0x1 0x1 read-only en_0b0 not active 0 en_0b1 active 1 USGFAULTACT UsageFault active flag. 0x3 0x1 read-only en_0b0 not active 0 en_0b1 active 1 SVCALLACT SVCall active flag. 0x7 0x1 read-only en_0b0 not active 0 en_0b1 active 1 MONITORACT the Monitor active flag. 0x8 0x1 read-only en_0b0 not active 0 en_0b1 active 1 PENDSVACT PendSV active flag. 0xA 0x1 read-only en_0b0 not active 0 en_0b1 active 1 SYSTICKACT SysTick active flag. 0xB 0x1 read-only en_0b0 not active 0 en_0b1 active 1 USGFAULTPENDED usage fault pended flag. 0xC 0x1 read-only en_0b0 not pended 0 en_0b1 pended 1 MEMFAULTPENDED MemManage pended flag. 0xD 0x1 read-only en_0b0 not pended 0 en_0b1 pended 1 BUSFAULTPENDED BusFault pended flag. 0xE 0x1 read-only en_0b0 not pended 0 en_0b1 pended 1 SVCALLPENDED SVCall pended flag. 0xF 0x1 read-only en_0b0 not pended 0 en_0b1 pended 1 MEMFAULTENA MemManage fault system handler enable 0x10 0x1 read-write en_0b0 disabled 0 en_0b1 enabled 1 BUSFAULTENA Bus fault system handler enable 0x11 0x1 read-write en_0b0 disabled 0 en_0b1 enabled 1 USGFAULTENA Usage fault system handler enable 0x12 0x1 read-write en_0b0 disabled 0 en_0b1 enabled 1 CFSR CFSR Configurable Fault Status Registers 0xD28 32 read-write 0x00000000 IACCVIOL Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written. 0x0 0x1 read-write DACCVIOL Data access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access. 0x1 0x1 read-write MUNSTKERR Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written. 0x3 0x1 read-write MSTKERR Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written. 0x4 0x1 read-write MMARVALID Memory Manage Address Register (MMAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten. 0x7 0x1 read-write IBUSERR Instruction bus error flag. The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written. 0x8 0x1 read-write PRECISERR Precise data bus error return. 0x9 0x1 read-write IMPRECISERR Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written. 0xA 0x1 read-write UNSTKERR Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written. 0xB 0x1 read-write STKERR Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written. 0xC 0x1 read-write BFARVALID This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. 0xF 0x1 read-write UNDEFINSTR The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. 0x10 0x1 read-write INVSTATE Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state. 0x11 0x1 read-write INVPC Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. 0x12 0x1 read-write NOCP Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. 0x13 0x1 read-write UNALIGNED When UNALIGN_TRP is enabled (see Configuration Control Register on page 8-26), and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP. 0x18 0x1 read-write DIVBYZERO When DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0. 0x19 0x1 read-write MLSPERR Indicates if MemManage fault occurred during FP lazy state preservation. 0x5 0x1 read-write LSPERR Indicates if bus fault occurred during FP lazy state preservation. 0xD 0x1 read-write HFSR HFSR Hard Fault Status Register 0xD2C 32 read-write 0x00000000 VECTTBL This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. 0x1 0x1 read-write FORCED Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. 0x1E 0x1 read-write DEBUGEVT This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. 0x1F 0x1 read-write DFSR DFSR Debug Fault Status Register 0xD30 32 read-write 0x00000000 HALTED Halt request flag. The processor is halted on the next instruction. 0x0 0x1 read-write en_0b0 no halt request 0 en_0b1 halt requested by NVIC, including step 1 BKPT BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 0x1 0x1 read-write en_0b0 no BKPT instruction execution 0 en_0b1 BKPT instruction execution 1 DWTTRAP Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. 0x2 0x1 read-write en_0b0 no DWT match 0 en_0b1 DWT match 1 VCATCH Vector catch flag. When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. 0x3 0x1 read-write en_0b0 no vector catch occurred 0 en_0b1 vector catch occurred 1 EXTERNAL External debug request flag. The processor stops on next instruction boundary. 0x4 0x1 read-write en_0b0 EDBGRQ signal not asserted 0 en_0b1 EDBGRQ signal asserted 1 MMFAR MMFAR Mem Manage Fault Address Register 0xD34 32 read-write ADDRESS Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault 0x0 0x20 read-write BFAR BFAR Bus Fault Address Register 0xD38 32 read-write ADDRESS Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault 0x0 0x20 read-write AFSR AFSR Auxiliary Fault Status Register 0xD3C 32 read-write 0x00000000 IMPDEF Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs. 0x0 0x20 read-write PFR0 PFR0 Processor Feature register0 0xD40 32 read-only 0x00000030 STATE0 State0 (T-bit == 0) 0x0 0x4 read-only en_0b0000 no ARM encoding 0 en_0b0001 N/A 1 STATE1 State1 (T-bit == 1) 0x4 0x4 read-only en_0b0000 N/A 0 en_0b0001 N/A 1 en_0b0010 Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) 2 en_0b0011 Thumb-2 encoding with all Thumb-2 basic instructions 3 PFR1 PFR1 Processor Feature register1 0xD44 32 read-only 0x00000200 MICROCONTROLLER_PROGRAMMERS_MODEL Microcontroller programmer's model 0x8 0x4 read-only en_0b0000 not supported 0 en_0b0010 two-stack support 2 DFR0 DFR0 Debug Feature register0 0xD48 32 read-only 0x00100000 MICROCONTROLLER_DEBUG_MODEL Microcontroller Debug Model - memory mapped 0x14 0x4 read-only en_0b0000 not supported 0 en_0b0001 Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) 1 AFR0 AFR0 Auxiliary Feature register0 0xD4C 32 read-only 0x00000000 MMFR0 MMFR0 Memory Model Feature register0 0xD50 32 read-only 0x00100030 PMSA_SUPPORT PMSA support 0x4 0x4 read-only en_0b0000 not supported 0 en_0b0001 IMPLEMENTATION DEFINED (N/A) 1 en_0b0010 PMSA base (features as defined for ARMv6) (N/A) 2 en_0b0011 PMSAv7 (base plus subregion support) 3 CACHE_COHERENCE_SUPPORT Cache coherence support 0x8 0x4 read-only en_0b0000 no shared support 0 en_0b0001 partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain) 1 en_0b0010 full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain) 2 en_0b0011 full coherency (coherency amongst all of the entities) 3 OUTER_NON_SHARABLE_SUPPORT Outer non-sharable support 0xC 0x4 read-only en_0b0000 Outer non-sharable not supported 0 en_0b0001 Outer sharable supported 1 AUXILIARY_REGISTER_SUPPORT Auxiliary register support 0x14 0x4 read-only en_0b0000 not supported 0 en_0b0001 Auxiliary control register 1 MMFR1 MMFR1 Memory Model Feature register1 0xD54 32 read-only 0x00000000 MMFR2 MMFR2 Memory Model Feature register2 0xD58 32 read-only 0x00000000 WAIT_FOR_INTERRUPT_STALLING wait for interrupt stalling 0x18 0x4 read-only en_0b0000 not supported 0 en_0b0001 wait for interrupt supported 1 MMFR3 MMFR3 Memory Model Feature register3 0xD5C 32 read-only 0x00000000 ISAR0 ISAR0 ISA Feature register0 0xD60 32 read-only 0x01141110 BITCOUNT_INSTRS BitCount instructions 0x4 0x4 read-only en_0b0000 no bit-counting instructions present 0 en_0b0001 adds CLZ 1 BITFIELD_INSTRS BitField instructions 0x8 0x4 read-only en_0b0000 no bitfield instructions present 0 en_0b0001 adds BFC, BFI, SBFX, UBFX 1 CMPBRANCH_INSTRS CmpBranch instructions 0xC 0x4 read-only en_0b0000 no combined compare-and-branch instructions present 0 en_0b0001 adds CB{N}Z 1 COPROC_INSTRS Coprocessor instructions 0x10 0x4 read-only en_0b0000 no coprocessor support, other than for separately attributed architectures such as CP15 or VFP 0 en_0b0001 adds generic CDP, LDC, MCR, MRC, STC 1 en_0b0010 adds generic CDP2, LDC2, MCR2, MRC2, STC2 2 en_0b0011 adds generic MCRR, MRRC 3 en_0b0100 adds generic MCRR2, MRRC2 4 DEBUG_INSTRS Debug instructions 0x14 0x4 read-only en_0b0000 no debug instructions present 0 en_0b0001 adds BKPT 1 DIVIDE_INSTRS Divide instructions 0x18 0x4 read-only en_0b0000 no divide instructions present 0 en_0b0001 adds SDIV, UDIV (v1 quotient only result) 1 ISAR1 ISAR1 ISA Feature register1 0xD64 32 read-only 0x02112000 EXTEND_INSRS Extend instructions. Note that the shift options on these instructions are also controlled by the WithShifts_instrs attribute. 0xC 0x4 read-only en_0b0000 no scalar (i.e. non-SIMD) sign/zero-extend instructions present 0 en_0b0001 adds SXTB, SXTH, UXTB, UXTH 1 en_0b0010 N/A 2 IFTHEN_INSTRS IfThen instructions 0x10 0x4 read-only en_0b0000 IT instructions not present 0 en_0b0001 adds IT instructions (and IT bits in PSRs) 1 IMMEDIATE_INSTRS Immediate instructions 0x14 0x4 read-only en_0b0000 no special immediate-generating instructions present 0 en_0b0001 adds ADDW, MOVW, MOVT, SUBW 1 INTERWORK_INSTRS Interwork instructions 0x18 0x4 read-only en_0b0000 no interworking instructions supported 0 en_0b0001 adds BX (and T bit in PSRs) 1 en_0b0010 adds BLX, and PC loads have BX-like behavior 2 en_0b0011 N/A 3 ISAR2 ISAR2 ISA Feature register2 0xD68 32 read-only 0x21232231 LOADSTORE_INSTRS LoadStore instructions 0x0 0x4 read-only en_0b0000 no additional normal load/store instructions present 0 en_0b0001 adds LDRD/STRD 1 MEMHINT_INSTRS MemoryHint instructions 0x4 0x4 read-only en_0b0000 no memory hint instructions presen 0 en_0b0001 adds PLD 1 en_0b0010 adds PLD (ie a repeat on value 1) 2 en_0b0011 adds PLI 3 MULTIACCESSINT_INSTRS Multi-Access interruptible instructions 0x8 0x4 read-only en_0b0000 the (LDM/STM) instructions are non-interruptible 0 en_0b0001 the (LDM/STM) instructions are restartable 1 en_0b0010 the (LDM/STM) instructions are continuable 2 MULT_INSTRS Multiply instructions 0xC 0x4 read-only en_0b0000 only MUL present 0 en_0b0001 adds MLA 1 en_0b0010 adds MLS 2 MULTS_INSTRS Multiply instructions (advanced, signed) 0x10 0x4 read-only en_0b0000 no signed multiply instructions present 0 en_0b0001 adds SMULL, SMLAL 1 en_0b0010 N/A 2 en_0b0011 N/A 3 MULTU_INSTRS Multiply instructions (advanced, unsigned) 0x14 0x4 read-only en_0b0000 no unsigned multiply instructions present 0 en_0b0001 adds UMULL, UMLAL 1 en_0b0010 N/A 2 REVERSAL_INSTRS Reversal instructions 0x1C 0x4 read-only en_0b0000 no reversal instructions present 0 en_0b0001 adds REV, REV16, REVSH 1 en_0b0010 adds RBIT 2 ISAR3 ISAR3 ISA Feature register3 0xD6C 32 read-only 0x01111131 SATRUATE_INSTRS Saturate instructions 0x0 0x4 read-only en_0b0000 no non-SIMD saturate instructions present 0 en_0b0001 N/A 1 SIMD_INSTRS SIMD instructions 0x4 0x4 read-only en_0b0000 no SIMD instructions present 0 en_0b0001 adds SSAT, USAT (and the Q flag in the PSRs) 1 en_0b0011 N/A 3 SVC_INSTRS SVC instructions 0x8 0x4 read-only en_0b0000 no SVC (SWI) instructions present 0 en_0b0001 adds SVC (SWI) 1 SYNCPRIM_INSTRS SyncPrim instructions. Note there are no LDREXD or STREXD in ARMv7-M. This attribute is used in conjunction with the SyncPrim_instrs_frac attribute in ID_ISAR4[23:20]. 0xC 0x4 read-only en_0b0000 no synchronization primitives present 0 en_0b0001 adds LDREX, STREX 1 en_0b0010 adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) 2 TABBRANCH_INSTRS TableBranch instructions 0x10 0x4 read-only en_0b0000 no table-branch instructions present 0 en_0b0001 adds TBB, TBH 1 THUMBCOPY_INSTRS ThumbCopy instructions 0x14 0x4 read-only en_0b0000 Thumb MOV(register) instruction does not allow low reg -> low reg 0 en_0b0001 adds Thumb MOV(register) low reg -> low reg and the CPY alias 1 TRUENOP_INSTRS TrueNOP instructions 0x18 0x4 read-only en_0b0000 true NOP instructions not present - that is, NOP instructions with no register dependencies 0 en_0b0001 adds "true NOP", and the capability of additional "NOP compatible hints" 1 ISAR4 ISAR4 ISA Feature register4 0xD70 32 read-only 0x01310102 UNPRIV_INSTRS Unprivileged instructions 0x0 0x4 read-only en_0b0000 no "T variant" instructions exist 0 en_0b0001 adds LDRBT, LDRT, STRBT, STRT 1 en_0b0010 adds LDRHT, LDRSBT, LDRSHT, STRHT 2 WITHSHIFTS_INSTRS WithShift instructions. Note that all additions only apply in cases where the encoding supports them - e.g. there is no difference between levels 3 and 4 in the Thumb-2 instruction set. Also note that MOV instructions with shift options should instead be treated as ASR, LSL, LSR, ROR or RRX instructions. 0x4 0x4 read-only en_0b0000 non-zero shifts only support MOV and shift instructions (see notes) 0 en_0b0001 shifts of loads/stores over the range LSL 0-3 1 en_0b0010 adds other constant shift options. 3 en_0b0100 adds register-controlled shift options. 4 WRITEBACK_INSTRS Writeback instructions 0x8 0x4 read-only en_0b0000 only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing. 0 en_0b0001 adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) 1 BARRIER_INSTRS Barrier instructions 0x10 0x4 read-only en_0b0000 no barrier instructions supported 0 en_0b0001 adds DMB, DSB, ISB barrier instructions 1 SYNCPRIM_INSTRS_FRAC SyncPrim_instrs_frac 0x14 0x4 read-only en_0b0000 no additional support 0 en_0b0011 adds CLREX, LDREXB, STREXB, LDREXH, STREXH 3 PSR_M_INSTRS PSR_M_instrs 0x18 0x4 read-only en_0b0000 instructions not present 0 en_0b0001 adds CPS, MRS, and MSR instructions (M-profile forms) 1 CPACR CPACR Coprocessor Access Control Register 0xD88 32 read-write CP11 Access privileges for coprocessor 11. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP10, this controls access to the Floating Point Coprocessor. 0x16 0x2 read-write CP10 Access privileges for coprocessor 10. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP11, this controls access to the Floating Point Coprocessor. 0x14 0x2 read-write 0x0 0x1000 registers FPCCR FPCCR Floating Point Context Control Register 0xF34 32 read-write 0xc0000000 ASPEN Automatic State Preservation ENable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry. 0x1F 0x1 read-write LSPEN Lazy State Preservation ENable. When the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation. 0x1E 0x1 read-write MONRDY Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending. 0x8 0x1 read-write BFRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending. 0x6 0x1 read-write MMRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending. 0x5 0x1 read-write HFRDY Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending. 0x4 0x1 read-write THREAD Indicates the processor mode was Thread when it allocated the FP stack frame. 0x3 0x1 read-write USER Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame. 0x1 0x1 read-write LSPACT Indicates whether Lazy preservation of the FP state is active. 0x0 0x1 read-write FPCAR FPCAR Floating-Point Context Address Register 0xF38 32 read-write 0x00000000 ADDRESS Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame. 0x2 0x1D read-write FPDSCR FPDSCR Floating Point Default Status Control Register 0xF3C 32 read-write 0x00000000 AHP Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected). 0x1A 0x1 read-write DN Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN). 0x19 0x1 read-write FZ Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled). 0x18 0x1 read-write RMODE Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode, 0b01 Round towards Plus Infinity (RP) mode, 0b10 Round towards Minus Infinity (RM) mode, 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions). 0x16 0x2 read-write MVFR0 MVFR0 Media and FP Feature Register 0 (MVFR0) 0xF40 32 read-only 0x10110021 FP_ROUNDING_MODES Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported. 0x1C 0x4 read-only SHORT_VECTORS Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported in ARMv7-M. 0x18 0x4 read-only SQUARE_ROOT Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported. 0x14 0x4 read-only DIVIDE Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported. 0x10 0x4 read-only FP_EXCEPTION_TRAPPING Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported in ARMv7-M. 0xC 0x4 read-only DOUBLE_PRECISION Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported in ARMv7-M. 0x8 0x4 read-only SINGLE_PRECISION Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported. 0x4 0x4 read-only A_SIMD_REGISTERS Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers. 0x0 0x4 read-only MVFR1 MVFR1 Media and FP Feature Register 1 (MVFR1) 0xF44 32 read-only 0x11000011 FP_FUSED_MAC Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported. 0x1C 0x4 read-only FP_HPFP Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported. 0x18 0x4 read-only D_NAN_MODE Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values. 0x4 0x4 read-only FTZ_MODE Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic. 0x0 0x4 read-only 0x0 0x1000 registers MPU_TYPE TYPE MPU Type Register 0xD90 32 read-only 0x00000800 SEPARATE Because the processor core uses only a unified MPU, SEPARATE is always 0. 0x0 0x1 read-only DREGION Number of supported MPU regions field. DREGION contains 0x08 if the implementation contains an MPU indicating eight MPU regions, otherwise it contains 0x00. 0x8 0x8 read-only IREGION Because the processor core uses only a unified MPU, IREGION always contains 0x00. 0x10 0x8 read-only MPU_CTRL CTRL MPU Control Register 0xD94 32 read-write 0x00000000 ENABLE MPU enable bit. Reset clears the ENABLE bit. 0x0 0x1 read-write en_0b0 disable MPU 0 en_0b1 enable MPU 1 HFNMIENA This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit = 0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit =1 and ENABLE = 0, behavior is Unpredictable. Reset clears the HFNMIENA bit. 0x1 0x1 read-write PRIVDEFENA This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit = 0, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the System partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. Reset clears the PRIVDEFENA bit. 0x2 0x1 read-write MPU_RNR RNR MPU Region Number Register 0xD98 32 read-write REGION Region select field. Selects the region to operate on when using the Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this. 0x0 0x8 read-write MPU_RBAR RBAR MPU Region Base Address Register 0xD9C 32 read-write 0x00000000 REGION MPU region override field. 0x0 0x4 read-write VALID MPU Region Number valid bit. 0x4 0x1 read-write en_0b0 MPU Region Number Register remains unchanged and is interpreted. 0 en_0b1 MPU Region Number Register is overwritten by bits 3:0 (the REGION value). 1 ADDR Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used. 0x5 0x1B read-write MPU_RASR RASR MPU Region Attribute and Size Register 0xDA0 32 read-write 0x00000000 ENABLE Region enable bit. 0x0 0x1 read-write SIZE MPU Protection Region Size Field. 0x1 0x5 read-write en_0b00100 32B 4 en_0b00101 64B 5 en_0b00110 128B 6 en_0b00111 256B 7 en_0b01000 512B 8 en_0b01001 1KB 9 en_0b01010 2KB 10 en_0b01011 4KB 11 en_0b01100 8KB 12 en_0b01101 16KB 13 en_0b01110 32KB 14 en_0b01111 64KB 15 en_0b10000 128KB 16 en_0b10001 256KB 17 en_0b10010 512KB 18 en_0b10011 1MB 19 en_0b10100 2MB 20 en_0b10101 4MB 21 en_0b10110 8MB 22 en_0b10111 16MB 23 en_0b11000 32MB 24 en_0b11001 64MB 25 en_0b11010 128MB 26 en_0b11011 256MB 27 en_0b11100 512MB 28 en_0b11101 1GB 29 en_0b11110 2GB 30 en_0b11111 4GB 31 SRD Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less. 0x8 0x8 read-write B Bufferable bit 0x10 0x1 read-write en_0b0 not bufferable 0 en_0b1 bufferable 1 C Cacheable bit 0x11 0x1 read-write en_0b0 not cacheable 0 en_0b1 cacheable 1 S Shareable bit 0x12 0x1 read-write en_0b0 not shareable 0 en_0b1 shareable 1 TEX Type extension field 0x13 0x3 read-write AP Data access permission field 0x18 0x3 read-write en_0b000 Priviliged permissions: No access. User permissions: No access. 0 en_0b001 Priviliged permissions: Read-write. User permissions: No access. 1 en_0b010 Priviliged permissions: Read-write. User permissions: Read-only. 2 en_0b011 Priviliged permissions: Read-write. User permissions: Read-write. 3 en_0b101 Priviliged permissions: Read-only. User permissions: No access. 5 en_0b110 Priviliged permissions: Read-only. User permissions: Read-only. 6 en_0b111 Priviliged permissions: Read-only. User permissions: Read-only. 7 XN Instruction access disable bit 0x1C 0x1 read-write en_0b0 enable instruction fetches 0 en_0b1 disable instruction fetches 1 MPU_RBAR_A1 RBAR_A1 MPU Alias 1 Region Base Address register 0xDA4 32 read-write 0x00000000 MPU_RASR_A1 RASR_A1 MPU Alias 1 Region Attribute and Size register 0xDA8 32 read-write 0x00000000 MPU_RBAR_A2 RBAR_A2 MPU Alias 2 Region Base Address register 0xDAC 32 read-write 0x00000000 MPU_RASR_A2 RASR_A2 MPU Alias 2 Region Attribute and Size register 0xDB0 32 read-write 0x00000000 MPU_RBAR_A3 RBAR_A3 MPU Alias 3 Region Base Address register 0xDB4 32 read-write MPU_RASR_A3 RASR_A3 MPU Alias 3 Region Attribute and Size register 0xDB8 32 read-write 0x00000000 FPU_IRQ FPU Interrupt 4 0x0 0x1000 registers DHCSR DHCSR Debug Halting Control and Status Register 0xDF0 32 read-write 0x00000000 0xfffeffff C_DEBUGEN Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. 0x0 0x1 read-write C_HALT Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. This bit can only be written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0] is 2'b11). The core can halt itself, but only if C_DEBUGEN is already 1 and only if it writes with b11). 0x1 0x1 read-write C_STEP Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). 0x2 0x1 read-write C_MASKINTS Mask interrupts when stepping or running in halted debug. Does not affect NMI, which is not maskable. Must only be modified when the processor is halted (S_HALT == 1). Also does not affect fault exceptions and SVC caused by execution of the instructions. CMASKINTS must be set or cleared before halt is released. This means that the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate. 0x3 0x1 read-write C_SNAPSTALL If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE can detect core stalls on load/store operations. 0x5 0x1 read-write S_REGRDY Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. 0x10 0x1 read-only S_HALT The core is in debug state when S_HALT is set. 0x11 0x1 read-only S_SLEEP Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up. 0x12 0x1 read-only S_LOCKUP Reads as one if the core is running (not halted) and a lockup condition is present. 0x13 0x1 read-only S_RETIRE_ST Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. 0x18 0x1 read-only S_RESET_ST Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). 0x19 0x1 read-only DCRSR DCRSR Deubg Core Register Selector Register 0xDF4 32 write-only REGSEL Register select 0x0 0x5 write-only en_0b00000 R0 0 en_0b00001 R1 1 en_0b00010 R2 2 en_0b00011 R3 3 en_0b00100 R4 4 en_0b00101 R5 5 en_0b00110 R6 6 en_0b00111 R7 7 en_0b01000 R8 8 en_0b01001 R9 9 en_0b01010 R10 10 en_0b01011 R11 11 en_0b01100 R12 12 en_0b01101 Current SP 13 en_0b01110 LR 14 en_0b01111 DebugReturnAddress 15 en_0b10000 xPSR/flags, execution state information, and exception number 16 en_0b10001 MSP (Main SP) 17 en_0b10010 PSP (Process SP) 18 en_0b10100 CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] 20 REGWNR Write = 1, Read = 0 0x10 0x1 write-only DCRDR DCRDR Debug Core Register Data Register 0xDF8 32 read-write DEMCR DEMCR Debug Exception and Monitor Control Register 0xDFC 32 read-write 0x00000000 VC_CORERESET Reset Vector Catch. Halt running system if Core reset occurs. 0x0 0x1 read-write VC_MMERR Debug trap on Memory Management faults. 0x4 0x1 read-write VC_NOCPERR Debug trap on Usage Fault access to Coprocessor that is not present or marked as not present in CAR register. 0x5 0x1 read-write VC_CHKERR Debug trap on Usage Fault enabled checking errors. 0x6 0x1 read-write VC_STATERR Debug trap on Usage Fault state errors. 0x7 0x1 read-write VC_BUSERR Debug Trap on normal Bus error. 0x8 0x1 read-write VC_INTERR Debug Trap on interrupt/exception service errors. These are a subset of other faults and catches before BUSERR or HARDERR. 0x9 0x1 read-write VC_HARDERR Debug trap on Hard Fault. 0xA 0x1 read-write MON_EN Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue register overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. 0x10 0x1 read-write MON_PEND Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a POR reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. 0x11 0x1 read-write MON_STEP When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. 0x12 0x1 read-write MON_REQ This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. 0x13 0x1 read-write en_0b0 woken up by debug exception. 0 en_0b1 woken up by MON_PEND 1 TRCENA This bit must be set to 1 to enable use of the trace and debug blocks: Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Embedded Trace Macrocell (ETM), Trace Port Interface Unit (TPIU). This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. Note that if no debug or trace components are present in the implementation then it is not possible to set TRCENA. 0x18 0x1 read-write RSTCTL 356.0 RSTCTL 0xE0042000 0x0 0x128 registers RSTCTL_RESET_REQ RESET_REQ Reset Request Register 0x0 32 read-write 0x00000000 0xffff00fc SOFT_REQ Soft Reset request 0x0 0x1 write-only HARD_REQ Hard Reset request 0x1 0x1 write-only RSTKEY Write key to unlock reset request bits 0x8 0x8 write-only RSTCTL_HARDRESET_STAT HARDRESET_STAT Hard Reset Status Register 0x4 32 read-only 0x00000000 0xffffffff SRC0 Indicates that SRC0 was the source of the Hard Reset 0x0 0x1 read-only SRC1 Indicates that SRC1 was the source of the Hard Reset 0x1 0x1 read-only SRC2 Indicates that SRC2 was the source of the Hard Reset 0x2 0x1 read-only SRC3 Indicates that SRC3 was the source of the Hard Reset 0x3 0x1 read-only SRC4 Indicates that SRC4 was the source of the Hard Reset 0x4 0x1 read-only SRC5 Indicates that SRC5 was the source of the Hard Reset 0x5 0x1 read-only SRC6 Indicates that SRC6 was the source of the Hard Reset 0x6 0x1 read-only SRC7 Indicates that SRC7 was the source of the Hard Reset 0x7 0x1 read-only SRC8 Indicates that SRC8 was the source of the Hard Reset 0x8 0x1 read-only SRC9 Indicates that SRC9 was the source of the Hard Reset 0x9 0x1 read-only SRC10 Indicates that SRC10 was the source of the Hard Reset 0xA 0x1 read-only SRC11 Indicates that SRC11 was the source of the Hard Reset 0xB 0x1 read-only SRC12 Indicates that SRC12 was the source of the Hard Reset 0xC 0x1 read-only SRC13 Indicates that SRC13 was the source of the Hard Reset 0xD 0x1 read-only SRC14 Indicates that SRC14 was the source of the Hard Reset 0xE 0x1 read-only SRC15 Indicates that SRC15 was the source of the Hard Reset 0xF 0x1 read-only RSTCTL_HARDRESET_CLR HARDRESET_CLR Hard Reset Status Clear Register 0x8 32 read-write 0x00000000 0xffff0000 SRC0 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x0 0x1 write-only SRC1 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x1 0x1 write-only SRC2 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x2 0x1 write-only SRC3 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x3 0x1 write-only SRC4 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x4 0x1 write-only SRC5 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x5 0x1 write-only SRC6 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x6 0x1 write-only SRC7 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x7 0x1 write-only SRC8 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x8 0x1 write-only SRC9 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0x9 0x1 write-only SRC10 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0xA 0x1 write-only SRC11 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0xB 0x1 write-only SRC12 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0xC 0x1 write-only SRC13 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0xD 0x1 write-only SRC14 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT 0xE 0x1 write-only SRC15 Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG 0xF 0x1 write-only RSTCTL_HARDRESET_SET HARDRESET_SET Hard Reset Status Set Register 0xC 32 read-write 0x00000000 0xffffffff SRC0 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x0 0x1 write-only SRC1 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x1 0x1 write-only SRC2 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x2 0x1 write-only SRC3 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x3 0x1 write-only SRC4 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x4 0x1 write-only SRC5 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x5 0x1 write-only SRC6 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x6 0x1 write-only SRC7 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x7 0x1 write-only SRC8 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x8 0x1 write-only SRC9 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0x9 0x1 write-only SRC10 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0xA 0x1 write-only SRC11 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0xB 0x1 write-only SRC12 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0xC 0x1 write-only SRC13 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0xD 0x1 write-only SRC14 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0xE 0x1 write-only SRC15 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) 0xF 0x1 write-only RSTCTL_SOFTRESET_STAT SOFTRESET_STAT Soft Reset Status Register 0x10 32 read-only 0x00000000 0xffffffff SRC0 If 1, indicates that SRC0 was the source of the Soft Reset 0x0 0x1 read-only SRC1 If 1, indicates that SRC1 was the source of the Soft Reset 0x1 0x1 read-only SRC2 If 1, indicates that SRC2 was the source of the Soft Reset 0x2 0x1 read-only SRC3 If 1, indicates that SRC3 was the source of the Soft Reset 0x3 0x1 read-only SRC4 If 1, indicates that SRC4 was the source of the Soft Reset 0x4 0x1 read-only SRC5 If 1, indicates that SRC5 was the source of the Soft Reset 0x5 0x1 read-only SRC6 If 1, indicates that SRC6 was the source of the Soft Reset 0x6 0x1 read-only SRC7 If 1, indicates that SRC7 was the source of the Soft Reset 0x7 0x1 read-only SRC8 If 1, indicates that SRC8 was the source of the Soft Reset 0x8 0x1 read-only SRC9 If 1, indicates that SRC9 was the source of the Soft Reset 0x9 0x1 read-only SRC10 If 1, indicates that SRC10 was the source of the Soft Reset 0xA 0x1 read-only SRC11 If 1, indicates that SRC11 was the source of the Soft Reset 0xB 0x1 read-only SRC12 If 1, indicates that SRC12 was the source of the Soft Reset 0xC 0x1 read-only SRC13 If 1, indicates that SRC13 was the source of the Soft Reset 0xD 0x1 read-only SRC14 If 1, indicates that SRC14 was the source of the Soft Reset 0xE 0x1 read-only SRC15 If 1, indicates that SRC15 was the source of the Soft Reset 0xF 0x1 read-only RSTCTL_SOFTRESET_CLR SOFTRESET_CLR Soft Reset Status Clear Register 0x14 32 read-write 0x00000000 0xffffffff SRC0 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x0 0x1 write-only SRC1 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x1 0x1 write-only SRC2 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x2 0x1 write-only SRC3 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x3 0x1 write-only SRC4 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x4 0x1 write-only SRC5 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x5 0x1 write-only SRC6 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x6 0x1 write-only SRC7 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x7 0x1 write-only SRC8 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x8 0x1 write-only SRC9 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0x9 0x1 write-only SRC10 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0xA 0x1 write-only SRC11 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0xB 0x1 write-only SRC12 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0xC 0x1 write-only SRC13 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0xD 0x1 write-only SRC14 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0xE 0x1 write-only SRC15 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT 0xF 0x1 write-only RSTCTL_SOFTRESET_SET SOFTRESET_SET Soft Reset Status Set Register 0x18 32 read-write 0x00000000 0xffffffff SRC0 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x0 0x1 write-only SRC1 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x1 0x1 write-only SRC2 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x2 0x1 write-only SRC3 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x3 0x1 write-only SRC4 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x4 0x1 write-only SRC5 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x5 0x1 write-only SRC6 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x6 0x1 write-only SRC7 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x7 0x1 write-only SRC8 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x8 0x1 write-only SRC9 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0x9 0x1 write-only SRC10 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0xA 0x1 write-only SRC11 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0xB 0x1 write-only SRC12 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0xC 0x1 write-only SRC13 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0xD 0x1 write-only SRC14 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0xE 0x1 write-only SRC15 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) 0xF 0x1 write-only RSTCTL_PSSRESET_STAT PSSRESET_STAT PSS Reset Status Register 0x100 32 read-only 0x0000000f 0xffffffff SVSMH Indicates if POR was caused by an SVSMH trip condition int the PSS 0x1 0x1 read-only BGREF Indicates if POR was caused by a BGREF not okay condition in the PSS 0x2 0x1 read-only VCCDET Indicates if POR was caused by a VCCDET trip condition in the PSS 0x3 0x1 read-only SVSL Indicates if POR was caused by an SVSL trip condition in the PSS 0x0 0x1 read-only RSTCTL_PSSRESET_CLR PSSRESET_CLR PSS Reset Status Clear Register 0x104 32 read-write 0x00000000 0xffffffff CLR Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT 0x0 0x1 write-only RSTCTL_PCMRESET_STAT PCMRESET_STAT PCM Reset Status Register 0x108 32 read-only 0x00000000 0xffffffff LPM35 Indicates if POR was caused by PCM due to an exit from LPM3.5 0x0 0x1 read-only LPM45 Indicates if POR was caused by PCM due to an exit from LPM4.5 0x1 0x1 read-only RSTCTL_PCMRESET_CLR PCMRESET_CLR PCM Reset Status Clear Register 0x10C 32 read-write 0x00000000 0xffffffff CLR Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT 0x0 0x1 write-only RSTCTL_PINRESET_STAT PINRESET_STAT Pin Reset Status Register 0x110 32 read-only 0x00000000 0xffffffff RSTNMI POR was caused by RSTn/NMI pin based reset event 0x0 0x1 read-only RSTCTL_PINRESET_CLR PINRESET_CLR Pin Reset Status Clear Register 0x114 32 read-write 0x00000000 0xffffffff CLR Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT 0x0 0x1 write-only RSTCTL_REBOOTRESET_STAT REBOOTRESET_STAT Reboot Reset Status Register 0x118 32 read-only 0x00000000 0xffffffff REBOOT Indicates if Reboot reset was caused by the SYSCTL module. 0x0 0x1 read-only RSTCTL_REBOOTRESET_CLR REBOOTRESET_CLR Reboot Reset Status Clear Register 0x11C 32 read-write 0x00000000 0xffffffff CLR Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT 0x0 0x1 write-only RSTCTL_CSRESET_STAT CSRESET_STAT CS Reset Status Register 0x120 32 read-only 0x00000000 0xffffffff DCOR_SHT Indicates if POR was caused by DCO short circuit fault in the external resistor mode 0x0 0x1 read-only RSTCTL_CSRESET_CLR CSRESET_CLR CS Reset Status Clear Register 0x124 32 read-write 0x00000000 0xffffffff CLR Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG flag in CSIFG register of clock system 0x0 0x1 write-only SYSCTL 356.0 SYSCTL 0xE0043000 0x0 0x1028 registers SYS_REBOOT_CTL REBOOT_CTL Reboot Control Register 0x0 32 read-write 0x000000fe 0xffffffff REBOOT Write 1 initiates a Reboot of the device 0x0 0x1 read-write WKEY Key to enable writes to bit 0 0x8 0x8 write-only SYS_NMI_CTLSTAT NMI_CTLSTAT NMI Control and Status Register 0x4 32 read-write 0x00000007 0xffffffff CS_SRC CS interrupt as a source of NMI 0x0 0x1 read-write CS_SRC_0 Disables CS interrupt as a source of NMI 0 CS_SRC_1 Enables CS interrupt as a source of NMI 1 PSS_SRC PSS interrupt as a source of NMI 0x1 0x1 read-write PSS_SRC_0 Disables the PSS interrupt as a source of NMI 0 PSS_SRC_1 Enables the PSS interrupt as a source of NMI 1 PCM_SRC PCM interrupt as a source of NMI 0x2 0x1 read-write PCM_SRC_0 Disbles the PCM interrupt as a source of NMI 0 PCM_SRC_1 Enables the PCM interrupt as a source of NMI 1 PIN_SRC RSTn/NMI pin configuration Note: When the device enters LPM3/LPM4 modes of operation, the functionality selected by this bit is retained. If selected as an NMI, activity on this pin in LPM3/LPM4 wakes the device and processes the interrupt, without causing a POR. If selected as a Reset, activity on this pin in LPM3/LPM4 causes a device-level POR When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes. 0x3 0x1 read-write PIN_SRC_0 Configures the RSTn_NMI pin as a source of POR Class Reset 0 PIN_SRC_1 Configures the RSTn_NMI pin as a source of NMI 1 CS_FLG CS interrupt was the source of NMI 0x10 0x1 read-only CS_FLG_enum_read read CS_FLG_0 indicates CS interrupt was not the source of NMI 0 CS_FLG_1 indicates CS interrupt was the source of NMI 1 PSS_FLG PSS interrupt was the source of NMI 0x11 0x1 read-only PSS_FLG_enum_read read PSS_FLG_0 indicates the PSS interrupt was not the source of NMI 0 PSS_FLG_1 indicates the PSS interrupt was the source of NMI 1 PCM_FLG PCM interrupt was the source of NMI 0x12 0x1 read-only PCM_FLG_enum_read read PCM_FLG_0 indicates the PCM interrupt was not the source of NMI 0 PCM_FLG_1 indicates the PCM interrupt was the source of NMI 1 PIN_FLG RSTn/NMI pin was the source of NMI 0x13 0x1 read-write PIN_FLG_0 Indicates the RSTn_NMI pin was not the source of NMI 0 PIN_FLG_1 Indicates the RSTn_NMI pin was the source of NMI 1 SYS_WDTRESET_CTL WDTRESET_CTL Watchdog Reset Control Register 0x8 32 read-write 0x00000003 0xffffffff TIMEOUT WDT timeout reset type 0x0 0x1 read-write TIMEOUT_0 WDT timeout event generates Soft reset 0 TIMEOUT_1 WDT timeout event generates Hard reset 1 VIOLATION WDT password violation reset type 0x1 0x1 read-write VIOLATION_0 WDT password violation event generates Soft reset 0 VIOLATION_1 WDT password violation event generates Hard reset 1 SYS_PERIHALT_CTL PERIHALT_CTL Peripheral Halt Control Register 0xC 32 read-write 0x00004000 0xffffffff HALT_T16_0 Freezes IP operation when CPU is halted 0x0 0x1 read-write HALT_T16_0_0 IP operation unaffected when CPU is halted 0 HALT_T16_0_1 freezes IP operation when CPU is halted 1 HALT_T16_1 Freezes IP operation when CPU is halted 0x1 0x1 read-write HALT_T16_1_0 IP operation unaffected when CPU is halted 0 HALT_T16_1_1 freezes IP operation when CPU is halted 1 HALT_T16_2 Freezes IP operation when CPU is halted 0x2 0x1 read-write HALT_T16_2_0 IP operation unaffected when CPU is halted 0 HALT_T16_2_1 freezes IP operation when CPU is halted 1 HALT_T16_3 Freezes IP operation when CPU is halted 0x3 0x1 read-write HALT_T16_3_0 IP operation unaffected when CPU is halted 0 HALT_T16_3_1 freezes IP operation when CPU is halted 1 HALT_T32_0 Freezes IP operation when CPU is halted 0x4 0x1 read-write HALT_T32_0_0 IP operation unaffected when CPU is halted 0 HALT_T32_0_1 freezes IP operation when CPU is halted 1 HALT_eUA0 Freezes IP operation when CPU is halted 0x5 0x1 read-write HALT_eUA0_0 IP operation unaffected when CPU is halted 0 HALT_eUA0_1 freezes IP operation when CPU is halted 1 HALT_eUA1 Freezes IP operation when CPU is halted 0x6 0x1 read-write HALT_eUA1_0 IP operation unaffected when CPU is halted 0 HALT_eUA1_1 freezes IP operation when CPU is halted 1 HALT_eUA2 Freezes IP operation when CPU is halted 0x7 0x1 read-write HALT_eUA2_0 IP operation unaffected when CPU is halted 0 HALT_eUA2_1 freezes IP operation when CPU is halted 1 HALT_eUA3 Freezes IP operation when CPU is halted 0x8 0x1 read-write HALT_eUA3_0 IP operation unaffected when CPU is halted 0 HALT_eUA3_1 freezes IP operation when CPU is halted 1 HALT_eUB0 Freezes IP operation when CPU is halted 0x9 0x1 read-write HALT_eUB0_0 IP operation unaffected when CPU is halted 0 HALT_eUB0_1 freezes IP operation when CPU is halted 1 HALT_eUB1 Freezes IP operation when CPU is halted 0xA 0x1 read-write HALT_eUB1_0 IP operation unaffected when CPU is halted 0 HALT_eUB1_1 freezes IP operation when CPU is halted 1 HALT_eUB2 Freezes IP operation when CPU is halted 0xB 0x1 read-write HALT_eUB2_0 IP operation unaffected when CPU is halted 0 HALT_eUB2_1 freezes IP operation when CPU is halted 1 HALT_eUB3 Freezes IP operation when CPU is halted 0xC 0x1 read-write HALT_eUB3_0 IP operation unaffected when CPU is halted 0 HALT_eUB3_1 freezes IP operation when CPU is halted 1 HALT_ADC Freezes IP operation when CPU is halted 0xD 0x1 read-write HALT_ADC_0 IP operation unaffected when CPU is halted 0 HALT_ADC_1 freezes IP operation when CPU is halted 1 HALT_WDT Freezes IP operation when CPU is halted 0xE 0x1 read-write HALT_WDT_0 IP operation unaffected when CPU is halted 0 HALT_WDT_1 freezes IP operation when CPU is halted 1 HALT_DMA Freezes IP operation when CPU is halted 0xF 0x1 read-write HALT_DMA_0 IP operation unaffected when CPU is halted 0 HALT_DMA_1 freezes IP operation when CPU is halted 1 SYS_SRAM_SIZE SRAM_SIZE SRAM Size Register 0x10 32 read-only SIZE Indicates the size of SRAM on the device 0x0 0x20 read-only SYS_SRAM_BANKEN SRAM_BANKEN SRAM Bank Enable Register 0x14 32 read-write 0x000000ff 0xffffffff BNK0_EN SRAM Bank0 enable 0x0 0x1 read-only BNK1_EN SRAM Bank1 enable 0x1 0x1 read-write BNK1_EN_0 Disables Bank1 of the SRAM 0 BNK1_EN_1 Enables Bank1 of the SRAM 1 BNK2_EN SRAM Bank1 enable 0x2 0x1 read-write BNK2_EN_0 Disables Bank2 of the SRAM 0 BNK2_EN_1 Enables Bank2 of the SRAM 1 BNK3_EN SRAM Bank1 enable 0x3 0x1 read-write BNK3_EN_0 Disables Bank3 of the SRAM 0 BNK3_EN_1 Enables Bank3 of the SRAM 1 BNK4_EN SRAM Bank1 enable 0x4 0x1 read-write BNK4_EN_0 Disables Bank4 of the SRAM 0 BNK4_EN_1 Enables Bank4 of the SRAM 1 BNK5_EN SRAM Bank1 enable 0x5 0x1 read-write BNK5_EN_0 Disables Bank5 of the SRAM 0 BNK5_EN_1 Enables Bank5 of the SRAM 1 BNK6_EN SRAM Bank1 enable 0x6 0x1 read-write BNK6_EN_0 Disables Bank6 of the SRAM 0 BNK6_EN_1 Enables Bank6 of the SRAM 1 BNK7_EN SRAM Bank1 enable 0x7 0x1 read-write BNK7_EN_0 Disables Bank7 of the SRAM 0 BNK7_EN_1 Enables Bank7 of the SRAM 1 SRAM_RDY SRAM ready 0x10 0x1 read-only SRAM_RDY_enum_read read SRAM_RDY_0 SRAM is not ready for accesses. Banks are undergoing an enable or disable sequence, and reads or writes to SRAM are stalled until the banks are ready 0 SRAM_RDY_1 SRAM is ready for accesses. All SRAM banks are enabled/disabled according to values of bits 7:0 of this register 1 SYS_SRAM_BANKRET SRAM_BANKRET SRAM Bank Retention Control Register 0x18 32 read-write 0x000000ff 0xffffffff BNK0_RET Bank0 retention 0x0 0x1 read-only BNK1_RET Bank1 retention 0x1 0x1 read-write BNK1_RET_0 Bank1 of the SRAM is not retained in LPM3 or LPM4 0 BNK1_RET_1 Bank1 of the SRAM is retained in LPM3 and LPM4 1 BNK2_RET Bank2 retention 0x2 0x1 read-write BNK2_RET_0 Bank2 of the SRAM is not retained in LPM3 or LPM4 0 BNK2_RET_1 Bank2 of the SRAM is retained in LPM3 and LPM4 1 BNK3_RET Bank3 retention 0x3 0x1 read-write BNK3_RET_0 Bank3 of the SRAM is not retained in LPM3 or LPM4 0 BNK3_RET_1 Bank3 of the SRAM is retained in LPM3 and LPM4 1 BNK4_RET Bank4 retention 0x4 0x1 read-write BNK4_RET_0 Bank4 of the SRAM is not retained in LPM3 or LPM4 0 BNK4_RET_1 Bank4 of the SRAM is retained in LPM3 and LPM4 1 BNK5_RET Bank5 retention 0x5 0x1 read-write BNK5_RET_0 Bank5 of the SRAM is not retained in LPM3 or LPM4 0 BNK5_RET_1 Bank5 of the SRAM is retained in LPM3 and LPM4 1 BNK6_RET Bank6 retention 0x6 0x1 read-write BNK6_RET_0 Bank6 of the SRAM is not retained in LPM3 or LPM4 0 BNK6_RET_1 Bank6 of the SRAM is retained in LPM3 and LPM4 1 BNK7_RET Bank7 retention 0x7 0x1 read-write BNK7_RET_0 Bank7 of the SRAM is not retained in LPM3 or LPM4 0 BNK7_RET_1 Bank7 of the SRAM is retained in LPM3 and LPM4 1 SRAM_RDY SRAM ready 0x10 0x1 read-only SRAM_RDY_enum_read read SRAM_RDY_0 SRAM banks are being set up for retention. Entry into LPM3, LPM4 should not be attempted until this bit is set to 1 0 SRAM_RDY_1 SRAM is ready for accesses. All SRAM banks are enabled/disabled for retention according to values of bits 7:0 of this register 1 SYS_FLASH_SIZE FLASH_SIZE Flash Size Register 0x20 32 read-only SIZE Flash User Region size 0x0 0x20 read-only SYS_DIO_GLTFLT_CTL DIO_GLTFLT_CTL Digital I/O Glitch Filter Control Register 0x30 32 read-write 0x00000001 0xffffffff GLTCH_EN Glitch filter enable 0x0 0x1 read-write GLTCH_EN_0 Disables glitch filter on the digital I/Os 0 GLTCH_EN_1 Enables glitch filter on the digital I/Os 1 SYS_SECDATA_UNLOCK SECDATA_UNLOCK IP Protected Secure Zone Data Access Unlock Register 0x40 32 read-write 0x00000000 0xffffffff UNLKEY Unlock key 0x0 0x10 read-write SYS_MASTER_UNLOCK MASTER_UNLOCK Master Unlock Register 0x1000 32 read-write 0x00000000 0xffffffff UNLKEY Unlock Key 0x0 0x10 read-write 2 4 0,1 SYS_BOOTOVER_REQ[%s] BOOTOVER_REQ[%s] Boot Override Request Register 0x1004 32 read-write 0x00000000 0xffffffff REGVAL Value set by debugger, read and clear by the CPU 0x0 0x20 read-write SYS_BOOTOVER_ACK BOOTOVER_ACK Boot Override Acknowledge Register 0x100C 32 read-write 0x00000000 0xffffffff REGVAL Value set by CPU, read/clear by the debugger 0x0 0x20 read-write SYS_RESET_REQ RESET_REQ Reset Request Register 0x1010 32 read-write POR Generate POR 0x0 0x1 write-only REBOOT Generate Reboot_Reset 0x1 0x1 write-only WKEY Write key 0x8 0x8 write-only SYS_RESET_STATOVER RESET_STATOVER Reset Status and Override Register 0x1014 32 read-write 0x00000000 0x00000700 SOFT Indicates if SOFT Reset is active 0x0 0x1 read-only HARD Indicates if HARD Reset is active 0x1 0x1 read-only REBOOT Indicates if Reboot Reset is active 0x2 0x1 read-only SOFT_OVER SOFT_Reset overwrite request 0x8 0x1 read-write HARD_OVER HARD_Reset overwrite request 0x9 0x1 read-write RBT_OVER Reboot Reset overwrite request 0xA 0x1 read-write SYS_SYSTEM_STAT SYSTEM_STAT System Status Register 0x1020 32 read-only DBG_SEC_ACT Debug Security active 0x3 0x1 read-only JTAG_SWD_LOCK_ACT Indicates if JTAG and SWD Lock is active 0x4 0x1 read-only IP_PROT_ACT Indicates if IP protection is active 0x5 0x1 read-only