Texas Instruments ti.com MSPM0L130X This preliminary header file does not have a version number - build date: 2023-02-21 16:43:37 ARM Device Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8 32 32 read-write 0x00000000 0xFFFFFFFF CM0 r0p1 little true false 3 false UART0 1.0 PERIPHERALREGION 0x40108000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG Peripheral Clock Configuration Register 0x808 32 read-write 0x00000000 CLKCFG_KEY KEY to Allow State Change -- 0xA9 0x18 0x8 write-only CLKCFG_KEY_UNLOCK _UNLOCK_W_ 169 CLKCFG_BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write CLKCFG_BLOCKASYNC_DISABLE DISABLE 0 CLKCFG_BLOCKASYNC_ENABLE ENABLE 1 GPRCM_STAT Status Register 0x814 32 read-only GPRCM_STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only GPRCM_STAT_RESETSTKY_NORES NORES 0 GPRCM_STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 INT_EVENT0_IIDX Interrupt index 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_RTFG RTFG 1 INT_EVENT0_IIDX_STAT_FEFG FEFG 2 INT_EVENT0_IIDX_STAT_PEFG PEFG 3 INT_EVENT0_IIDX_STAT_BEFG BEFG 4 INT_EVENT0_IIDX_STAT_OEFG OEFG 5 INT_EVENT0_IIDX_STAT_RXNE RXNE 6 INT_EVENT0_IIDX_STAT_RXPE RXPE 7 INT_EVENT0_IIDX_STAT_LINC0 LINC0 8 INT_EVENT0_IIDX_STAT_LINC1 LINC1 9 INT_EVENT0_IIDX_STAT_LINOVF LINOVF 10 INT_EVENT0_IIDX_STAT_RXIFG RXIFG 11 INT_EVENT0_IIDX_STAT_TXIFG TXIFG 12 INT_EVENT0_IIDX_STAT_EOT EOT 13 INT_EVENT0_IIDX_STAT_MODE_9B MODE_9B 14 INT_EVENT0_IIDX_STAT_CTS CTS 15 INT_EVENT0_IIDX_STAT_DMA_DONE_RX DMA_DONE_RX 16 INT_EVENT0_IIDX_STAT_DMA_DONE_TX DMA_DONE_TX 17 INT_EVENT0_IIDX_STAT_NERR_EVT NERR_EVT 18 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_IMASK_FRMERR_CLR CLR 0 INT_EVENT0_IMASK_FRMERR_SET SET 1 INT_EVENT0_IMASK_PARERR Enable UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_IMASK_PARERR_CLR CLR 0 INT_EVENT0_IMASK_PARERR_SET SET 1 INT_EVENT0_IMASK_BRKERR Enable UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_IMASK_BRKERR_CLR CLR 0 INT_EVENT0_IMASK_BRKERR_SET SET 1 INT_EVENT0_IMASK_OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_IMASK_OVRERR_CLR CLR 0 INT_EVENT0_IMASK_OVRERR_SET SET 1 INT_EVENT0_IMASK_RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_IMASK_RXNE_CLR CLR 0 INT_EVENT0_IMASK_RXNE_SET SET 1 INT_EVENT0_IMASK_RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_IMASK_RXPE_CLR CLR 0 INT_EVENT0_IMASK_RXPE_SET SET 1 INT_EVENT0_IMASK_LINOVF Enable LIN Hardware Counter Overflow Interrupt. 0x9 0x1 INT_EVENT0_IMASK_LINOVF_CLR CLR 0 INT_EVENT0_IMASK_LINOVF_SET SET 1 INT_EVENT0_IMASK_RXINT Enable UART Receive Interrupt. 0xA 0x1 INT_EVENT0_IMASK_RXINT_CLR CLR 0 INT_EVENT0_IMASK_RXINT_SET SET 1 INT_EVENT0_IMASK_TXINT Enable UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_IMASK_TXINT_CLR CLR 0 INT_EVENT0_IMASK_TXINT_SET SET 1 INT_EVENT0_IMASK_EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_IMASK_EOT_CLR CLR 0 INT_EVENT0_IMASK_EOT_SET SET 1 INT_EVENT0_IMASK_ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 INT_EVENT0_IMASK_ADDR_MATCH_CLR CLR 0 INT_EVENT0_IMASK_ADDR_MATCH_SET SET 1 INT_EVENT0_IMASK_CTS Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_IMASK_CTS_CLR CLR 0 INT_EVENT0_IMASK_CTS_SET SET 1 INT_EVENT0_IMASK_DMA_DONE_RX Enable DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_IMASK_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_IMASK_DMA_DONE_RX_SET SET 1 INT_EVENT0_IMASK_DMA_DONE_TX Enable DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_IMASK_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_IMASK_DMA_DONE_TX_SET SET 1 INT_EVENT0_IMASK_RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_IMASK_RTOUT_CLR CLR 0 INT_EVENT0_IMASK_RTOUT_SET SET 1 INT_EVENT0_IMASK_LINC0 Enable LIN Capture 0 / Match Interrupt . 0x7 0x1 INT_EVENT0_IMASK_LINC0_CLR CLR 0 INT_EVENT0_IMASK_LINC0_SET SET 1 INT_EVENT0_IMASK_LINC1 Enable LIN Capture 1 Interrupt. 0x8 0x1 INT_EVENT0_IMASK_LINC1_CLR CLR 0 INT_EVENT0_IMASK_LINC1_SET SET 1 INT_EVENT0_IMASK_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_IMASK_NERR_CLR CLR 0 INT_EVENT0_IMASK_NERR_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only INT_EVENT0_RIS_RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_RIS_RTOUT_CLR CLR 0 INT_EVENT0_RIS_RTOUT_SET SET 1 INT_EVENT0_RIS_FRMERR UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_RIS_FRMERR_CLR CLR 0 INT_EVENT0_RIS_FRMERR_SET SET 1 INT_EVENT0_RIS_PARERR UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_RIS_PARERR_CLR CLR 0 INT_EVENT0_RIS_PARERR_SET SET 1 INT_EVENT0_RIS_BRKERR UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_RIS_BRKERR_CLR CLR 0 INT_EVENT0_RIS_BRKERR_SET SET 1 INT_EVENT0_RIS_OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_RIS_OVRERR_CLR CLR 0 INT_EVENT0_RIS_OVRERR_SET SET 1 INT_EVENT0_RIS_RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_RIS_RXNE_CLR CLR 0 INT_EVENT0_RIS_RXNE_SET SET 1 INT_EVENT0_RIS_RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_RIS_RXPE_CLR CLR 0 INT_EVENT0_RIS_RXPE_SET SET 1 INT_EVENT0_RIS_LINC0 LIN Capture 0 / Match Interrupt . 0x7 0x1 INT_EVENT0_RIS_LINC0_CLR CLR 0 INT_EVENT0_RIS_LINC0_SET SET 1 INT_EVENT0_RIS_LINC1 LIN Capture 1 Interrupt. 0x8 0x1 INT_EVENT0_RIS_LINC1_CLR CLR 0 INT_EVENT0_RIS_LINC1_SET SET 1 INT_EVENT0_RIS_LINOVF LIN Hardware Counter Overflow Interrupt. 0x9 0x1 INT_EVENT0_RIS_LINOVF_CLR CLR 0 INT_EVENT0_RIS_LINOVF_SET SET 1 INT_EVENT0_RIS_RXINT UART Receive Interrupt. 0xA 0x1 INT_EVENT0_RIS_RXINT_CLR CLR 0 INT_EVENT0_RIS_RXINT_SET SET 1 INT_EVENT0_RIS_TXINT UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_RIS_TXINT_CLR CLR 0 INT_EVENT0_RIS_TXINT_SET SET 1 INT_EVENT0_RIS_EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_RIS_EOT_CLR CLR 0 INT_EVENT0_RIS_EOT_SET SET 1 INT_EVENT0_RIS_ADDR_MATCH Address Match Interrupt. 0xD 0x1 INT_EVENT0_RIS_ADDR_MATCH_CLR CLR 0 INT_EVENT0_RIS_ADDR_MATCH_SET SET 1 INT_EVENT0_RIS_CTS UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_RIS_CTS_CLR CLR 0 INT_EVENT0_RIS_CTS_SET SET 1 INT_EVENT0_RIS_DMA_DONE_RX DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_RIS_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_RIS_DMA_DONE_RX_SET SET 1 INT_EVENT0_RIS_DMA_DONE_TX DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_RIS_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_RIS_DMA_DONE_TX_SET SET 1 INT_EVENT0_RIS_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_RIS_NERR_CLR CLR 0 INT_EVENT0_RIS_NERR_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_MIS_RTOUT_CLR CLR 0 INT_EVENT0_MIS_RTOUT_SET SET 1 INT_EVENT0_MIS_FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_MIS_FRMERR_CLR CLR 0 INT_EVENT0_MIS_FRMERR_SET SET 1 INT_EVENT0_MIS_PARERR Masked UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_MIS_PARERR_CLR CLR 0 INT_EVENT0_MIS_PARERR_SET SET 1 INT_EVENT0_MIS_BRKERR Masked UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_MIS_BRKERR_CLR CLR 0 INT_EVENT0_MIS_BRKERR_SET SET 1 INT_EVENT0_MIS_OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_MIS_OVRERR_CLR CLR 0 INT_EVENT0_MIS_OVRERR_SET SET 1 INT_EVENT0_MIS_RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_MIS_RXNE_CLR CLR 0 INT_EVENT0_MIS_RXNE_SET SET 1 INT_EVENT0_MIS_RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_MIS_RXPE_CLR CLR 0 INT_EVENT0_MIS_RXPE_SET SET 1 INT_EVENT0_MIS_LINC0 Masked LIN Capture 0 / Match Interrupt . 0x7 0x1 INT_EVENT0_MIS_LINC0_CLR CLR 0 INT_EVENT0_MIS_LINC0_SET SET 1 INT_EVENT0_MIS_LINC1 Masked LIN Capture 1 Interrupt. 0x8 0x1 INT_EVENT0_MIS_LINC1_CLR CLR 0 INT_EVENT0_MIS_LINC1_SET SET 1 INT_EVENT0_MIS_LINOVF Masked LIN Hardware Counter Overflow Interrupt. 0x9 0x1 INT_EVENT0_MIS_LINOVF_CLR CLR 0 INT_EVENT0_MIS_LINOVF_SET SET 1 INT_EVENT0_MIS_RXINT Masked UART Receive Interrupt. 0xA 0x1 INT_EVENT0_MIS_RXINT_CLR CLR 0 INT_EVENT0_MIS_RXINT_SET SET 1 INT_EVENT0_MIS_TXINT Masked UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_MIS_TXINT_CLR CLR 0 INT_EVENT0_MIS_TXINT_SET SET 1 INT_EVENT0_MIS_EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_MIS_EOT_CLR CLR 0 INT_EVENT0_MIS_EOT_SET SET 1 INT_EVENT0_MIS_ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 INT_EVENT0_MIS_ADDR_MATCH_CLR CLR 0 INT_EVENT0_MIS_ADDR_MATCH_SET SET 1 INT_EVENT0_MIS_CTS Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_MIS_CTS_CLR CLR 0 INT_EVENT0_MIS_CTS_SET SET 1 INT_EVENT0_MIS_DMA_DONE_RX Masked DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_MIS_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_MIS_DMA_DONE_RX_SET SET 1 INT_EVENT0_MIS_DMA_DONE_TX Masked DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_MIS_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_MIS_DMA_DONE_TX_SET SET 1 INT_EVENT0_MIS_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_MIS_NERR_CLR CLR 0 INT_EVENT0_MIS_NERR_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_FRMERR Set UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_ISET_FRMERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_FRMERR_SET SET 1 INT_EVENT0_ISET_PARERR Set UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_ISET_PARERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_PARERR_SET SET 1 INT_EVENT0_ISET_BRKERR Set UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_ISET_BRKERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_BRKERR_SET SET 1 INT_EVENT0_ISET_OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_ISET_OVRERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_OVRERR_SET SET 1 INT_EVENT0_ISET_RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_ISET_RXNE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXNE_SET SET 1 INT_EVENT0_ISET_RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_ISET_RXPE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXPE_SET SET 1 INT_EVENT0_ISET_LINC0 Set LIN Capture 0 / Match Interrupt . 0x7 0x1 INT_EVENT0_ISET_LINC0_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_LINC0_SET SET 1 INT_EVENT0_ISET_LINC1 Set LIN Capture 1 Interrupt. 0x8 0x1 INT_EVENT0_ISET_LINC1_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_LINC1_SET SET 1 INT_EVENT0_ISET_LINOVF Set LIN Hardware Counter Overflow Interrupt. 0x9 0x1 INT_EVENT0_ISET_LINOVF_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_LINOVF_SET SET 1 INT_EVENT0_ISET_RXINT Set UART Receive Interrupt. 0xA 0x1 INT_EVENT0_ISET_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXINT_SET SET 1 INT_EVENT0_ISET_TXINT Set UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_ISET_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TXINT_SET SET 1 INT_EVENT0_ISET_EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_ISET_EOT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_EOT_SET SET 1 INT_EVENT0_ISET_ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_ADDR_MATCH_SET SET 1 INT_EVENT0_ISET_CTS Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_ISET_CTS_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_CTS_SET SET 1 INT_EVENT0_ISET_DMA_DONE_RX Set DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMA_DONE_RX_SET SET 1 INT_EVENT0_ISET_DMA_DONE_TX Set DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMA_DONE_TX_SET SET 1 INT_EVENT0_ISET_RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_ISET_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RTOUT_SET SET 1 INT_EVENT0_ISET_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_ISET_NERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_NERR_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_ICLR_FRMERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_FRMERR_CLR CLR 1 INT_EVENT0_ICLR_PARERR Clear UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_ICLR_PARERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_PARERR_CLR CLR 1 INT_EVENT0_ICLR_BRKERR Clear UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_ICLR_BRKERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_BRKERR_CLR CLR 1 INT_EVENT0_ICLR_OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_ICLR_OVRERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_OVRERR_CLR CLR 1 INT_EVENT0_ICLR_RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_ICLR_RXNE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXNE_CLR CLR 1 INT_EVENT0_ICLR_RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_ICLR_RXPE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXPE_CLR CLR 1 INT_EVENT0_ICLR_LINC0 Clear LIN Capture 0 / Match Interrupt . 0x7 0x1 INT_EVENT0_ICLR_LINC0_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_LINC0_CLR CLR 1 INT_EVENT0_ICLR_LINC1 Clear LIN Capture 1 Interrupt. 0x8 0x1 INT_EVENT0_ICLR_LINC1_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_LINC1_CLR CLR 1 INT_EVENT0_ICLR_LINOVF Clear LIN Hardware Counter Overflow Interrupt. 0x9 0x1 INT_EVENT0_ICLR_LINOVF_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_LINOVF_CLR CLR 1 INT_EVENT0_ICLR_RXINT Clear UART Receive Interrupt. 0xA 0x1 INT_EVENT0_ICLR_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXINT_CLR CLR 1 INT_EVENT0_ICLR_TXINT Clear UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_ICLR_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TXINT_CLR CLR 1 INT_EVENT0_ICLR_EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_ICLR_EOT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_EOT_CLR CLR 1 INT_EVENT0_ICLR_ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_ADDR_MATCH_CLR CLR 1 INT_EVENT0_ICLR_CTS Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_ICLR_CTS_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_CTS_CLR CLR 1 INT_EVENT0_ICLR_DMA_DONE_RX Clear DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMA_DONE_RX_CLR CLR 1 INT_EVENT0_ICLR_DMA_DONE_TX Clear DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMA_DONE_TX_CLR CLR 1 INT_EVENT0_ICLR_RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_ICLR_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RTOUT_CLR CLR 1 INT_EVENT0_ICLR_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_ICLR_NERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_NERR_CLR CLR 1 INT_EVENT1_IIDX Interrupt index 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_RTFG RTFG 1 INT_EVENT1_IIDX_STAT_RXIFG RXIFG 11 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_IMASK_RTOUT_CLR CLR 0 INT_EVENT1_IMASK_RTOUT_SET SET 1 INT_EVENT1_IMASK_RXINT Enable UART Receive Interrupt. 0xA 0x1 INT_EVENT1_IMASK_RXINT_CLR CLR 0 INT_EVENT1_IMASK_RXINT_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only INT_EVENT1_RIS_RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_RIS_RTOUT_CLR CLR 0 INT_EVENT1_RIS_RTOUT_SET SET 1 INT_EVENT1_RIS_RXINT UART Receive Interrupt. 0xA 0x1 INT_EVENT1_RIS_RXINT_CLR CLR 0 INT_EVENT1_RIS_RXINT_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_MIS_RTOUT_CLR CLR 0 INT_EVENT1_MIS_RTOUT_SET SET 1 INT_EVENT1_MIS_RXINT Masked UART Receive Interrupt. 0xA 0x1 INT_EVENT1_MIS_RXINT_CLR CLR 0 INT_EVENT1_MIS_RXINT_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_ISET_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_RTOUT_SET SET 1 INT_EVENT1_ISET_RXINT Set UART Receive Interrupt. 0xA 0x1 INT_EVENT1_ISET_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_RXINT_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_ICLR_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_RTOUT_CLR CLR 1 INT_EVENT1_ICLR_RXINT Clear UART Receive Interrupt. 0xA 0x1 INT_EVENT1_ICLR_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_RXINT_CLR CLR 1 INT_EVENT2_IIDX Interrupt index 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_TXIFG TXIFG 12 INT_EVENT2_IMASK Interrupt mask 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_TXINT Enable UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_IMASK_TXINT_CLR CLR 0 INT_EVENT2_IMASK_TXINT_SET SET 1 INT_EVENT2_RIS Raw interrupt status 0x1090 32 read-only INT_EVENT2_RIS_TXINT UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_RIS_TXINT_CLR CLR 0 INT_EVENT2_RIS_TXINT_SET SET 1 INT_EVENT2_MIS Masked interrupt status 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_TXINT Masked UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_MIS_TXINT_CLR CLR 0 INT_EVENT2_MIS_TXINT_SET SET 1 INT_EVENT2_ISET Interrupt set 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_TXINT Set UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_ISET_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_TXINT_SET SET 1 INT_EVENT2_ICLR Interrupt clear 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_TXINT Clear UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_ICLR_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_TXINT_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff CTL0_ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write CTL0_ENABLE_DISABLE DISABLE 0 CTL0_ENABLE_ENABLE ENABLE 1 CTL0_HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write CTL0_HSE_OVS16 OVS16 0 CTL0_HSE_OVS8 OVS8 1 CTL0_HSE_OVS3 OVS3 2 CTL0_LBE UART Loop Back Enable 0x2 0x1 read-write CTL0_LBE_DISABLE DISABLE 0 CTL0_LBE_ENABLE ENABLE 1 CTL0_RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write CTL0_RXE_DISABLE DISABLE 0 CTL0_RXE_ENABLE ENABLE 1 CTL0_TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write CTL0_TXE_DISABLE DISABLE 0 CTL0_TXE_ENABLE ENABLE 1 CTL0_RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CTL0_RTS_CLR CLR 0 CTL0_RTS_SET SET 1 CTL0_RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write CTL0_RTSEN_DISABLE DISABLE 0 CTL0_RTSEN_ENABLE ENABLE 1 CTL0_CTSEN Enable Clear To Send 0xE 0x1 read-write CTL0_CTSEN_DISABLE DISABLE 0 CTL0_CTSEN_ENABLE ENABLE 1 CTL0_MENC Manchester Encode enable 0x7 0x1 read-write CTL0_MENC_DISABLE DISABLE 0 CTL0_MENC_ENABLE ENABLE 1 CTL0_MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write CTL0_MODE_UART UART 0 CTL0_MODE_RS485 RS485 1 CTL0_MODE_IDLELINE IDLELINE 2 CTL0_MODE_ADDR9BIT ADDR9BIT 3 CTL0_MODE_SMART SMART 4 CTL0_MODE_DALI DALI 5 CTL0_FEN UART Enable FIFOs 0x11 0x1 read-write CTL0_FEN_DISABLE DISABLE 0 CTL0_FEN_ENABLE ENABLE 1 CTL0_TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write CTL0_TXD_OUT_LOW LOW 0 CTL0_TXD_OUT_HIGH HIGH 1 CTL0_TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0 0x5 0x1 read-write CTL0_TXD_OUT_EN_DISABLE DISABLE 0 CTL0_TXD_OUT_EN_ENABLE ENABLE 1 CTL0_MAJVOTE When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken. 0x12 0x1 read-write CTL0_MAJVOTE_DISABLE DISABLE 0 CTL0_MAJVOTE_ENABLE ENABLE 1 CTL0_MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write CTL0_MSBFIRST_DISABLE DISABLE 0 CTL0_MSBFIRST_ENABLE ENABLE 1 LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff LCRH_BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write LCRH_BRK_DISABLE DISABLE 0 LCRH_BRK_ENABLE ENABLE 1 LCRH_PEN UART Parity Enable 0x1 0x1 read-write LCRH_PEN_DISABLE DISABLE 0 LCRH_PEN_ENABLE ENABLE 1 LCRH_EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write LCRH_EPS_ODD ODD 0 LCRH_EPS_EVEN EVEN 1 LCRH_STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write LCRH_STP2_DISABLE DISABLE 0 LCRH_STP2_ENABLE ENABLE 1 LCRH_WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write LCRH_WLEN_DATABIT5 DATABIT5 0 LCRH_WLEN_DATABIT6 DATABIT6 1 LCRH_WLEN_DATABIT7 DATABIT7 2 LCRH_WLEN_DATABIT8 DATABIT8 3 LCRH_SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write LCRH_SPS_DISABLE DISABLE 0 LCRH_SPS_ENABLE ENABLE 1 LCRH_SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write LCRH_SENDIDLE_DISABLE DISABLE 0 LCRH_SENDIDLE_ENABLE ENABLE 1 LCRH_EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write LCRH_EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write STAT UART Status Register 0x1108 32 read-only STAT_BUSY UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only STAT_BUSY_CLEARED CLEARED 0 STAT_BUSY_SET SET 1 STAT_TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only STAT_TXFF_CLEARED CLEARED 0 STAT_TXFF_SET SET 1 STAT_RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only STAT_RXFF_CLEARED CLEARED 0 STAT_RXFF_SET SET 1 STAT_TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only STAT_TXFE_CLEARED CLEARED 0 STAT_TXFE_SET SET 1 STAT_CTS Clear To Send 0x8 0x1 read-only STAT_CTS_CLEARED CLEARED 0 STAT_CTS_SET SET 1 STAT_IDLE IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only STAT_IDLE_CLEARED CLEARED 0 STAT_IDLE_SET SET 1 STAT_RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only STAT_RXFE_CLEARED CLEARED 0 STAT_RXFE_SET SET 1 IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff IFLS_TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write IFLS_RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write IFLS_RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff IBRD_DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff FBRD_DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb GFCTL_AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only) 0x9 0x2 read-write GFCTL_AGFSEL_AGLIT_5 AGLIT_5 0 GFCTL_AGFSEL_AGLIT_10 AGLIT_10 1 GFCTL_AGFSEL_AGLIT_25 AGLIT_25 2 GFCTL_AGFSEL_AGLIT_50 AGLIT_50 3 GFCTL_AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write GFCTL_AGFEN_DISABLE DISABLE 0 GFCTL_AGFEN_ENABLE ENABLE 1 GFCTL_DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK) 0x0 0x6 read-write GFCTL_DGFSEL_DISABLED DISABLED 0 GFCTL_CHAIN Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0xB 0x1 read-write GFCTL_CHAIN_DISABLED DISABLED 0 GFCTL_CHAIN_ENABLED ENABLED 1 TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff TXDATA_DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff RXDATA_DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only RXDATA_FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only RXDATA_FRMERR_CLR CLR 0 RXDATA_FRMERR_SET SET 1 RXDATA_PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only RXDATA_PARERR_CLR CLR 0 RXDATA_PARERR_SET SET 1 RXDATA_BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only RXDATA_BRKERR_CLR CLR 0 RXDATA_BRKERR_SET SET 1 RXDATA_OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only RXDATA_OVRERR_CLR CLR 0 RXDATA_OVRERR_SET SET 1 RXDATA_NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only RXDATA_NERR_CLR CLR 0 RXDATA_NERR_SET SET 1 LINCNT UART LIN Mode Counter Register 0x1130 32 read-write 0x00000000 0xffffffff LINCNT_VALUE 16 bit up counter clocked by the module clock of the UART. 0x0 0x10 read-write LINCTL UART LIN Mode Control Register 0x1134 32 read-write 0x00000000 0xffffffff LINCTL_CTRENA LIN Counter Enable. LIN counter will only count when enabled. 0x0 0x1 read-write LINCTL_CTRENA_DISABLE DISABLE 0 LINCTL_CTRENA_ENABLE ENABLE 1 LINCTL_ZERONE Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD 0x1 0x1 read-write LINCTL_ZERONE_DISABLE DISABLE 0 LINCTL_ZERONE_ENABLE ENABLE 1 LINCTL_CNTRXLOW Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments. 0x2 0x1 read-write LINCTL_CNTRXLOW_DISABLE DISABLE 0 LINCTL_CNTRXLOW_ENABLE ENABLE 1 LINCTL_LINC0CAP Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled. 0x4 0x1 read-write LINCTL_LINC0CAP_DISABLE DISABLE 0 LINCTL_LINC0CAP_ENABLE ENABLE 1 LINCTL_LINC1CAP Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled. 0x5 0x1 read-write LINCTL_LINC1CAP_DISABLE DISABLE 0 LINCTL_LINC1CAP_ENABLE ENABLE 1 LINCTL_LINC0_MATCH Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled. 0x6 0x1 read-write LINCTL_LINC0_MATCH_DISABLE DISABLE 0 LINCTL_LINC0_MATCH_ENABLE ENABLE 1 LINC0 UART LIN Mode Capture 0 Register 0x1138 32 read-write 0x00000000 0xffffffff LINC0_DATA 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt. 0x0 0x10 read-write LINC1 UART LIN Mode Capture 1 Register 0x113C 32 read-write 0x00000000 0xffffffff LINC1_DATA 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture. 0x0 0x10 read-write IRCTL eUSCI_Ax IrDA Control Word Register 0x1140 32 read-write 0x00000000 0x0000ffff IRCTL_IRTXPL Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / [2 * f(IRTXCLK)] (IRTXCLK = functional clock of the UART) 0x2 0x6 read-write IRCTL_IRRXPL IrDA receive input UCAxRXD polarity 0x9 0x1 read-write IRCTL_IRRXPL_HIGH HIGHPULSE 0 IRCTL_IRRXPL_LOW LOWPULSE 1 IRCTL_IREN IrDA encoder/decoder enable 0x0 0x1 read-write IRCTL_IREN_DISABLE DISABLE 0 IRCTL_IREN_ENABLE ENABLE 1 IRCTL_IRTXCLK IrDA transmit pulse clock select 0x1 0x1 read-write IRCTL_IRTXCLK_BITCLK BITCLK 0 IRCTL_IRTXCLK_BRCLK BRCLK 1 AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff AMASK_VALUE Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match. 0x0 0x8 read-write ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR_VALUE Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh. 0x0 0x8 read-write CLKDIV2 Clock Divider 0x1160 32 read-write 0x00000000 CLKDIV2_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV2_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV2_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV2_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV2_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV2_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV2_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV2_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV2_RATIO_DIV_BY_8 DIV_BY_8 7 FLASHCTL 1.0 F65NW 0x400CD000 0x0 0x2000 registers IIDX Interrupt Index Register 0x1020 32 read-only 0x00000000 IIDX_STAT Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt. 0x0 0x1 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_DONE DONE 1 IMASK Interrupt Mask Register 0x1028 32 read-write IMASK_DONE Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register 0x0 0x1 read-write IMASK_DONE_DISABLED DISABLED 0 IMASK_DONE_ENABLED ENABLED 1 RIS Raw Interrupt Status Register 0x1030 32 read-only RIS_DONE NoWrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority. 0x0 0x1 read-only RIS_DONE_CLR CLR 0 RIS_DONE_SET SET 1 MIS Masked Interrupt Status Register 0x1038 32 read-only MIS_DONE NoWrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits. 0x0 0x1 read-only MIS_DONE_CLR CLR 0 MIS_DONE_SET SET 1 ISET Interrupt Set Register 0x1040 32 write-only ISET_DONE 0: No effect 1: Set the DONE interrupt in the RIS register 0x0 0x1 write-only ISET_DONE_NO_EFFECT NO_EFFECT 0 ISET_DONE_SET SET 1 ICLR Interrupt Clear Register 0x1048 32 write-only ICLR_DONE 0: No effect 1: Clear the DONE interrupt in the RIS register 0x0 0x1 write-only ICLR_DONE_NO_EFFECT NO_EFFECT 0 ICLR_DONE_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-only EVT_MODE_INT0_CFG Event line mode select for peripheral event 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 DESC Hardware Version Description Register 0x10FC 32 read-only DESC_MINREV Minor Revision 0x0 0x4 read-only DESC_MAJREV Major Revision 0x4 0x4 read-only DESC_INSTNUM Instance number 0x8 0x4 read-only DESC_FEATUREVER Feature set 0xC 0x4 read-only DESC_MODULEID Module ID 0x10 0x10 read-only CMDEXEC Command Execute Register 0x1100 32 read-write CMDEXEC_VAL Command Execute value Initiates execution of the command specified in the CMDTYPE register. 0x0 0x1 read-write CMDEXEC_VAL_NOEXECUTE NOEXECUTE 0 CMDEXEC_VAL_EXECUTE EXECUTE 1 CMDTYPE Command Type Register 0x1104 32 read-write CMDTYPE_COMMAND Command type 0x0 0x3 read-write CMDTYPE_COMMAND_NOOP NOOP 0 CMDTYPE_COMMAND_PROGRAM PROGRAM 1 CMDTYPE_COMMAND_ERASE ERASE 2 CMDTYPE_COMMAND_READVERIFY READVERIFY 3 CMDTYPE_COMMAND_MODECHANGE MODECHANGE 4 CMDTYPE_COMMAND_CLEARSTATUS CLEARSTATUS 5 CMDTYPE_COMMAND_BLANKVERIFY BLANKVERIFY 6 CMDTYPE_SIZE Command size 0x4 0x3 read-write CMDTYPE_SIZE_ONEWORD ONEWORD 0 CMDTYPE_SIZE_TWOWORD TWOWORD 1 CMDTYPE_SIZE_FOURWORD FOURWORD 2 CMDTYPE_SIZE_EIGHTWORD EIGHTWORD 3 CMDTYPE_SIZE_SECTOR SECTOR 4 CMDTYPE_SIZE_BANK BANK 5 CMDCTL Command Control Register 0x1108 32 read-write CMDCTL_MODESEL Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware. 0x0 0x4 read-write CMDCTL_MODESEL_READ READ 0 CMDCTL_MODESEL_RDMARG0 RDMARG0 2 CMDCTL_MODESEL_RDMARG1 RDMARG1 4 CMDCTL_MODESEL_RDMARG0B RDMARG0B 6 CMDCTL_MODESEL_RDMARG1B RDMARG1B 7 CMDCTL_MODESEL_PGMVER PGMVER 9 CMDCTL_MODESEL_PGMSW PGMSW 10 CMDCTL_MODESEL_ERASEVER ERASEVER 11 CMDCTL_MODESEL_ERASESECT ERASESECT 12 CMDCTL_MODESEL_PGMMW PGMMW 14 CMDCTL_MODESEL_ERASEBNK ERASEBNK 15 CMDCTL_REGIONSEL Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set. 0x9 0x4 read-write CMDCTL_REGIONSEL_MAIN MAIN 1 CMDCTL_REGIONSEL_NONMAIN NONMAIN 2 CMDCTL_REGIONSEL_TRIM TRIM 4 CMDCTL_REGIONSEL_ENGR ENGR 8 CMDCTL_ADDRXLATEOVR Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID. 0x10 0x1 read-write CMDCTL_ADDRXLATEOVR_NOOVERRIDE NOOVERRIDE 0 CMDCTL_ADDRXLATEOVR_OVERRIDE OVERRIDE 1 CMDCTL_SSERASEDIS Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired. 0x14 0x1 read-write CMDCTL_SSERASEDIS_ENABLE ENABLE 0 CMDCTL_SSERASEDIS_DISABLE DISABLE 1 CMDCTL_DATAVEREN Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming. 0x15 0x1 read-write CMDCTL_DATAVEREN_DISABLE DISABLE 0 CMDCTL_DATAVEREN_ENABLE ENABLE 1 CMDADDR Command Address Register 0x1120 32 read-write CMDADDR_VAL Address value 0x0 0x20 read-write CMDBYTEN Command Program Byte Enable Register 0x1124 32 read-write CMDBYTEN_VAL Command Byte Enable value. A 1-bit per flash word byte value is placed in this register. 0x0 0x8 read-write CMDDATA0 Command Data Register 0 0x1130 32 read-write CMDDATA0_VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write CMDDATA1 Command Data Register 1 0x1134 32 read-write CMDDATA1_VAL A 32-bit data value is placed in this field. 0x0 0x20 read-write CMDWEPROTA Command Write Erase Protect A Register 0x11D0 32 read-write CMDWEPROTA_VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase. 0x0 0x20 read-write CMDWEPROTB Command Write Erase Protect B Register 0x11D4 32 read-write CMDWEPROTB_VAL Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register. 0x0 0x4 read-write CMDWEPROTNM Command Write Erase Protect Non-Main Register 0x1210 32 read-write CMDWEPROTNM_VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase. 0x0 0x1 read-write CMDWEPROTTR Command Write Erase Protect Trim Register 0x1214 32 read-write CMDWEPROTTR_VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase. 0x0 0x1 read-write CMDWEPROTEN Command Write Erase Protect Engr Register 0x1218 32 read-write CMDWEPROTEN_VAL Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase. 0x0 0x2 read-write CFGCMD Command Configuration Register 0x13B0 32 read-write CFGCMD_WAITSTATE Wait State setting for program verify, erase verify and read verify 0x0 0x4 read-write CFGPCNT Pulse Counter Configuration Register 0x13B4 32 read-write CFGPCNT_MAXPCNTOVR Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used. 0x0 0x1 read-write CFGPCNT_MAXPCNTOVR_DEFAULT DEFAULT 0 CFGPCNT_MAXPCNTOVR_OVERRIDE OVERRIDE 1 CFGPCNT_MAXPCNTVAL Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}. 0x4 0x8 read-write STATCMD Command Status Register 0x13D0 32 read-only STATCMD_CMDDONE Command Done 0x0 0x1 read-only STATCMD_CMDDONE_STATNOTDONE STATNOTDONE 0 STATCMD_CMDDONE_STATDONE STATDONE 1 STATCMD_CMDPASS Command Pass - valid when CMD_DONE field is 1 0x1 0x1 read-only STATCMD_CMDPASS_STATFAIL STATFAIL 0 STATCMD_CMDPASS_STATPASS STATPASS 1 STATCMD_CMDINPROGRESS Command In Progress 0x2 0x1 read-only STATCMD_CMDINPROGRESS_STATCOMPLETE STATCOMPLETE 0 STATCMD_CMDINPROGRESS_STATINPROGRESS STATINPROGRESS 1 STATCMD_FAILWEPROT Command failed due to Write/Erase Protect Sector Violation 0x4 0x1 read-only STATCMD_FAILWEPROT_STATNOFAIL STATNOFAIL 0 STATCMD_FAILWEPROT_STATFAIL STATFAIL 1 STATCMD_FAILVERIFY Command failed due to verify error 0x5 0x1 read-only STATCMD_FAILVERIFY_STATNOFAIL STATNOFAIL 0 STATCMD_FAILVERIFY_STATFAIL STATFAIL 1 STATCMD_FAILMISC Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit. 0xC 0x1 read-only STATCMD_FAILMISC_STATNOFAIL STATNOFAIL 0 STATCMD_FAILMISC_STATFAIL STATFAIL 1 STATCMD_FAILILLADDR Command failed due to the use of an illegal address 0x6 0x1 read-only STATCMD_FAILILLADDR_STATNOFAIL STATNOFAIL 0 STATCMD_FAILILLADDR_STATFAIL STATFAIL 1 STATCMD_FAILMODE Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode. 0x7 0x1 read-only STATCMD_FAILMODE_STATNOFAIL STATNOFAIL 0 STATCMD_FAILMODE_STATFAIL STATFAIL 1 STATCMD_FAILINVDATA Program command failed because an attempt was made to program a stored 0 value to a 1. 0x8 0x1 read-only STATCMD_FAILINVDATA_STATNOFAIL STATNOFAIL 0 STATCMD_FAILINVDATA_STATFAIL STATFAIL 1 STATADDR Address Status Register 0x13D4 32 read-only STATADDR_BANKADDR Current Bank Address A bank offset address is stored in this register. 0x0 0x10 read-only STATADDR_BANKID Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank. 0x15 0x5 read-only STATADDR_BANKID_BANK0 BANK0 1 STATADDR_BANKID_BANK1 BANK1 2 STATADDR_BANKID_BANK2 BANK2 4 STATADDR_BANKID_BANK3 BANK3 8 STATADDR_BANKID_BANK4 BANK4 16 STATADDR_REGIONID Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating. 0x10 0x5 read-only STATADDR_REGIONID_MAIN MAIN 1 STATADDR_REGIONID_NONMAIN NONMAIN 2 STATADDR_REGIONID_TRIM TRIM 4 STATADDR_REGIONID_ENGR ENGR 8 STATPCNT Pulse Count Status Register 0x13D8 32 read-only STATPCNT_PULSECNT Current Pulse Counter Value 0x0 0xC read-only STATMODE Mode Status Register 0x13DC 32 read-only STATMODE_BANKNOTINRD Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank. 0x0 0x1 read-only STATMODE_BANKNOTINRD_BANK0 BANK0 1 STATMODE_BANKMODE Indicates mode of bank(s) that are not in READ mode 0x8 0x4 read-only STATMODE_BANKMODE_READ READ 0 STATMODE_BANKMODE_RDMARG0 RDMARG0 2 STATMODE_BANKMODE_RDMARG1 RDMARG1 4 STATMODE_BANKMODE_RDMARG0B RDMARG0B 6 STATMODE_BANKMODE_RDMARG1B RDMARG1B 7 STATMODE_BANKMODE_PGMVER PGMVER 9 STATMODE_BANKMODE_PGMSW PGMSW 10 STATMODE_BANKMODE_ERASEVER ERASEVER 11 STATMODE_BANKMODE_ERASESECT ERASESECT 12 STATMODE_BANKMODE_PGMMW PGMMW 14 STATMODE_BANKMODE_ERASEBNK ERASEBNK 15 STATMODE_BANK2TRDY Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s). 0x10 0x1 read-only STATMODE_BANK2TRDY_FALSE FALSE 0 STATMODE_BANK2TRDY_TRUE TRUE 1 STATMODE_BANK1TRDY Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed. 0x11 0x1 read-only STATMODE_BANK1TRDY_FALSE FALSE 0 STATMODE_BANK1TRDY_TRUE TRUE 1 GBLINFO0 Global Information Register 0 0x13F0 32 read-only GBLINFO0_SECTORSIZE Sector size in bytes 0x0 0x10 read-only GBLINFO0_SECTORSIZE_ONEKB ONEKB 1024 GBLINFO0_SECTORSIZE_TWOKB TWOKB 2048 GBLINFO0_NUMBANKS Number of banks instantiated Minimum: 1 Maximum: 5 0x10 0x3 read-only GBLINFO1 Global Information Register 1 0x13F4 32 read-only GBLINFO1_DATAWIDTH Data width in bits 0x0 0x8 read-only GBLINFO1_DATAWIDTH_W64BIT W64BIT 64 GBLINFO1_DATAWIDTH_W128BIT W128BIT 128 GBLINFO1_ECCWIDTH ECC data width in bits 0x8 0x5 read-only GBLINFO1_ECCWIDTH_W0BIT W0BIT 0 GBLINFO1_ECCWIDTH_W8BIT W8BIT 8 GBLINFO1_ECCWIDTH_W16BIT W16BIT 16 GBLINFO1_REDWIDTH Redundant data width in bits 0x10 0x3 read-only GBLINFO1_REDWIDTH_W0BIT W0BIT 0 GBLINFO1_REDWIDTH_W2BIT W2BIT 2 GBLINFO1_REDWIDTH_W4BIT W4BIT 4 GBLINFO2 Global Information Register 2 0x13F8 32 read-only GBLINFO2_DATAREGISTERS Number of data registers present. 0x0 0x4 read-only BANK0INFO0 Bank Information Register 0 for Bank 0 0x1400 32 read-only BANK0INFO0_MAINSIZE Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512) 0x0 0xC read-only BANK0INFO0_MAINSIZE_MINSECTORS MINSECTORS 8 BANK0INFO0_MAINSIZE_MAXSECTORS MAXSECTORS 512 BANK0INFO1 Bank Information Register 1 for Bank 0 0x1404 32 read-only BANK0INFO1_NONMAINSIZE Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x0 0x8 read-only BANK0INFO1_NONMAINSIZE_MINSECTORS MINSECTORS 0 BANK0INFO1_NONMAINSIZE_MAXSECTORS MAXSECTORS 32 BANK0INFO1_TRIMSIZE Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x8 0x8 read-only BANK0INFO1_TRIMSIZE_MINSECTORS MINSECTORS 0 BANK0INFO1_TRIMSIZE_MAXSECTORS MAXSECTORS 32 BANK0INFO1_ENGRSIZE Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0x10 0x8 read-only BANK0INFO1_ENGRSIZE_MINSECTORS MINSECTORS 0 BANK0INFO1_ENGRSIZE_MAXSECTORS MAXSECTORS 32 SPI0 1.0 PERIPHERALREGION 0x40468000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG Peripheral Clock Configuration Register 0x808 32 read-write 0x00000000 CLKCFG_KEY KEY to Allow State Change -- 0xA9 0x18 0x8 write-only CLKCFG_KEY_UNLOCK _UNLOCK_W_ 169 CLKCFG_BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write CLKCFG_BLOCKASYNC_DISABLE DISABLE 0 CLKCFG_BLOCKASYNC_ENABLE ENABLE 1 GPRCM_STAT Status Register 0x814 32 read-only GPRCM_STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only GPRCM_STAT_RESETSTKY_NORES NORES 0 GPRCM_STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_SYSCLK_SEL Selects SYSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_SYSCLK_SEL_DISABLE DISABLE 0 CLKSEL_SYSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 INT_EVENT0_IIDX Interrupt Index Register 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_RXFIFO_OFV_EVT RXFIFO_OFV_EVT 1 INT_EVENT0_IIDX_STAT_PER_EVT PER_EVT 2 INT_EVENT0_IIDX_STAT_RTOUT_EVT RTOUT_EVT 3 INT_EVENT0_IIDX_STAT_RX_EVT RX_EVT 4 INT_EVENT0_IIDX_STAT_TX_EVT TX_EVT 5 INT_EVENT0_IIDX_STAT_TX_EMPTY TX_EMPTY 6 INT_EVENT0_IIDX_STAT_IDLE_EVT IDLE_EVT 7 INT_EVENT0_IIDX_STAT_DMA_DONE_RX_EVT DMA_DONE_RX_EVT 8 INT_EVENT0_IIDX_STAT_DMA_DONE_TX_EVT DMA_DONE_TX_EVT 9 INT_EVENT0_IIDX_STAT_TXFIFO_UNF_EVT TXFIFO_UNF_EVT 10 INT_EVENT0_IIDX_STAT_RXFULL_EVT RXFULL_EVT 11 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 INT_EVENT0_IMASK_RX_CLR CLR 0 INT_EVENT0_IMASK_RX_SET SET 1 INT_EVENT0_IMASK_TX Transmit FIFO event mask. 0x4 0x1 INT_EVENT0_IMASK_TX_CLR CLR 0 INT_EVENT0_IMASK_TX_SET SET 1 INT_EVENT0_IMASK_TXEMPTY Transmit FIFO Empty event mask. 0x5 0x1 INT_EVENT0_IMASK_TXEMPTY_CLR CLR 0 INT_EVENT0_IMASK_TXEMPTY_SET SET 1 INT_EVENT0_IMASK_PER Parity error event mask. 0x1 0x1 INT_EVENT0_IMASK_PER_CLR CLR 0 INT_EVENT0_IMASK_PER_SET SET 1 INT_EVENT0_IMASK_DMA_DONE_RX DMA Done 1 event for RX event mask. 0x7 0x1 INT_EVENT0_IMASK_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_IMASK_DMA_DONE_RX_SET SET 1 INT_EVENT0_IMASK_RXFIFO_OVF RXFIFO overflow event mask. 0x0 0x1 INT_EVENT0_IMASK_RXFIFO_OVF_CLR CLR 0 INT_EVENT0_IMASK_RXFIFO_OVF_SET SET 1 INT_EVENT0_IMASK_DMA_DONE_TX DMA Done 1 event for TX event mask. 0x8 0x1 INT_EVENT0_IMASK_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_IMASK_DMA_DONE_TX_SET SET 1 INT_EVENT0_IMASK_IDLE SPI Idle event mask. 0x6 0x1 INT_EVENT0_IMASK_IDLE_CLR CLR 0 INT_EVENT0_IMASK_IDLE_SET SET 1 INT_EVENT0_IMASK_RTOUT Enable SPI Receive Time-Out event mask. 0x2 0x1 INT_EVENT0_IMASK_RTOUT_CLR CLR 0 INT_EVENT0_IMASK_RTOUT_SET SET 1 INT_EVENT0_IMASK_RXFULL RX FIFO Full Interrupt Mask 0xA 0x1 read-write INT_EVENT0_IMASK_RXFULL_CLR CLR 0 INT_EVENT0_IMASK_RXFULL_SET SET 1 INT_EVENT0_IMASK_TXFIFO_UNF TX FIFO underflow interrupt mask 0x9 0x1 read-write INT_EVENT0_IMASK_TXFIFO_UNF_CLR CLR 0 INT_EVENT0_IMASK_TXFIFO_UNF_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only 0x00000000 INT_EVENT0_RIS_RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 INT_EVENT0_RIS_RX_CLR CLR 0 INT_EVENT0_RIS_RX_SET SET 1 INT_EVENT0_RIS_TX Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 INT_EVENT0_RIS_TX_CLR CLR 0 INT_EVENT0_RIS_TX_SET SET 1 INT_EVENT0_RIS_TXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register. 0x5 0x1 INT_EVENT0_RIS_TXEMPTY_CLR CLR 0 INT_EVENT0_RIS_TXEMPTY_SET SET 1 INT_EVENT0_RIS_PER Parity error event: this bit is set if a Parity error has been detected 0x1 0x1 INT_EVENT0_RIS_PER_CLR CLR 0 INT_EVENT0_RIS_PER_SET SET 1 INT_EVENT0_RIS_DMA_DONE_RX DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x7 0x1 INT_EVENT0_RIS_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_RIS_DMA_DONE_RX_SET SET 1 INT_EVENT0_RIS_RXFIFO_OVF RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 INT_EVENT0_RIS_RXFIFO_OVF_CLR CLR 0 INT_EVENT0_RIS_RXFIFO_OVF_SET SET 1 INT_EVENT0_RIS_DMA_DONE_TX DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0x8 0x1 INT_EVENT0_RIS_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_RIS_DMA_DONE_TX_SET SET 1 INT_EVENT0_RIS_IDLE SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low. 0x6 0x1 INT_EVENT0_RIS_IDLE_CLR CLR 0 INT_EVENT0_RIS_IDLE_SET SET 1 INT_EVENT0_RIS_RTOUT SPI Receive Time-Out event. 0x2 0x1 INT_EVENT0_RIS_RTOUT_CLR CLR 0 INT_EVENT0_RIS_RTOUT_SET SET 1 INT_EVENT0_RIS_TXFIFO_UNF TX FIFO Underflow Interrupt 0x9 0x1 INT_EVENT0_RIS_TXFIFO_UNF_CLR CLR 0 INT_EVENT0_RIS_TXFIFO_UNF_SET SET 1 INT_EVENT0_RIS_RXFULL RX FIFO Full Interrupt 0xA 0x1 INT_EVENT0_RIS_RXFULL_CLR CLR 0 INT_EVENT0_RIS_RXFULL_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_RX Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 INT_EVENT0_MIS_RX_CLR CLR 0 INT_EVENT0_MIS_RX_SET SET 1 INT_EVENT0_MIS_TX Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached. 0x4 0x1 INT_EVENT0_MIS_TX_CLR CLR 0 INT_EVENT0_MIS_TX_SET SET 1 INT_EVENT0_MIS_TXEMPTY Masked Transmit FIFO Empty event. 0x5 0x1 INT_EVENT0_MIS_TXEMPTY_CLR CLR 0 INT_EVENT0_MIS_TXEMPTY_SET SET 1 INT_EVENT0_MIS_PER Masked Parity error event: this bit if a Parity error has been detected 0x1 0x1 INT_EVENT0_MIS_PER_CLR CLR 0 INT_EVENT0_MIS_PER_SET SET 1 INT_EVENT0_MIS_DMA_DONE_RX Masked DMA Done 1 event for RX. 0x7 0x1 INT_EVENT0_MIS_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_MIS_DMA_DONE_RX_SET SET 1 INT_EVENT0_MIS_RXFIFO_OVF Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0x0 0x1 INT_EVENT0_MIS_RXFIFO_OVF_CLR CLR 0 INT_EVENT0_MIS_RXFIFO_OVF_SET SET 1 INT_EVENT0_MIS_DMA_DONE_TX Masked DMA Done 1 event for TX. 0x8 0x1 INT_EVENT0_MIS_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_MIS_DMA_DONE_TX_SET SET 1 INT_EVENT0_MIS_IDLE Masked SPI IDLE mode event. 0x6 0x1 INT_EVENT0_MIS_IDLE_CLR CLR 0 INT_EVENT0_MIS_IDLE_SET SET 1 INT_EVENT0_MIS_RTOUT Masked SPI Receive Time-Out Interrupt. 0x2 0x1 INT_EVENT0_MIS_RTOUT_CLR CLR 0 INT_EVENT0_MIS_RTOUT_SET SET 1 INT_EVENT0_MIS_RXFULL RX FIFO Full Interrupt 0xA 0x1 INT_EVENT0_MIS_RXFULL_CLR CLR 0 INT_EVENT0_MIS_RXFULL_SET SET 1 INT_EVENT0_MIS_TXFIFO_UNF TX FIFO underflow interrupt 0x9 0x1 INT_EVENT0_MIS_TXFIFO_UNF_CLR CLR 0 INT_EVENT0_MIS_TXFIFO_UNF_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_RX Set Receive FIFO event. 0x3 0x1 INT_EVENT0_ISET_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RX_SET SET 1 INT_EVENT0_ISET_TX Set Transmit FIFO event. 0x4 0x1 INT_EVENT0_ISET_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TX_SET SET 1 INT_EVENT0_ISET_TXEMPTY Set Transmit FIFO Empty event. 0x5 0x1 INT_EVENT0_ISET_TXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TXEMPTY_SET SET 1 INT_EVENT0_ISET_PER Set Parity error event. 0x1 0x1 INT_EVENT0_ISET_PER_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_PER_SET SET 1 INT_EVENT0_ISET_DMA_DONE_RX Set DMA Done 1 event for RX. 0x7 0x1 INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMA_DONE_RX_SET SET 1 INT_EVENT0_ISET_RXFIFO_OVF Set RXFIFO overflow event. 0x0 0x1 INT_EVENT0_ISET_RXFIFO_OVF_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXFIFO_OVF_SET SET 1 INT_EVENT0_ISET_DMA_DONE_TX Set DMA Done 1 event for TX. 0x8 0x1 INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMA_DONE_TX_SET SET 1 INT_EVENT0_ISET_IDLE Set SPI IDLE mode event. 0x6 0x1 INT_EVENT0_ISET_IDLE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_IDLE_SET SET 1 INT_EVENT0_ISET_RTOUT Set SPI Receive Time-Out Event. 0x2 0x1 INT_EVENT0_ISET_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RTOUT_SET SET 1 INT_EVENT0_ISET_TXFIFO_UNF Set TX FIFO Underflow Event 0x9 0x1 INT_EVENT0_ISET_TXFIFO_UNF_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TXFIFO_UNF_SET SET 1 INT_EVENT0_ISET_RXFULL Set RX FIFO Full Event 0xA 0x1 INT_EVENT0_ISET_RXFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXFULL_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_RX Clear Receive FIFO event. 0x3 0x1 INT_EVENT0_ICLR_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RX_CLR CLR 1 INT_EVENT0_ICLR_TX Clear Transmit FIFO event. 0x4 0x1 INT_EVENT0_ICLR_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TX_CLR CLR 1 INT_EVENT0_ICLR_TXEMPTY Clear Transmit FIFO Empty event. 0x5 0x1 INT_EVENT0_ICLR_TXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TXEMPTY_CLR CLR 1 INT_EVENT0_ICLR_PER Clear Parity error event. 0x1 0x1 INT_EVENT0_ICLR_PER_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_PER_CLR CLR 1 INT_EVENT0_ICLR_DMA_DONE_RX Clear DMA Done 1 event for RX. 0x7 0x1 INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMA_DONE_RX_CLR CLR 1 INT_EVENT0_ICLR_RXFIFO_OVF Clear RXFIFO overflow event. 0x0 0x1 INT_EVENT0_ICLR_RXFIFO_OVF_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXFIFO_OVF_CLR CLR 1 INT_EVENT0_ICLR_DMA_DONE_TX Clear DMA Done 1 event for TX. 0x8 0x1 INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMA_DONE_TX_CLR CLR 1 INT_EVENT0_ICLR_IDLE Clear SPI IDLE mode event. 0x6 0x1 INT_EVENT0_ICLR_IDLE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_IDLE_CLR CLR 1 INT_EVENT0_ICLR_RTOUT Clear SPI Receive Time-Out Event. 0x2 0x1 INT_EVENT0_ICLR_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RTOUT_CLR CLR 1 INT_EVENT0_ICLR_TXFIFO_UNF Clear TXFIFO underflow event 0x9 0x1 INT_EVENT0_ICLR_TXFIFO_UNF_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TXFIFO_UNF_CLR CLR 1 INT_EVENT0_ICLR_RXFULL Clear RX FIFO underflow event 0xA 0x1 INT_EVENT0_ICLR_RXFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXFULL_CLR CLR 1 INT_EVENT1_IIDX Interrupt Index Register 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_RTOUT_EVT RTOUT_EVT 3 INT_EVENT1_IIDX_STAT_RX_EVT RX_EVT 4 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_RX Receive FIFO event mask. 0x3 0x1 INT_EVENT1_IMASK_RX_CLR CLR 0 INT_EVENT1_IMASK_RX_SET SET 1 INT_EVENT1_IMASK_RTOUT SPI Receive Time-Out event mask. 0x2 0x1 INT_EVENT1_IMASK_RTOUT_CLR CLR 0 INT_EVENT1_IMASK_RTOUT_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only INT_EVENT1_RIS_RX Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached 0x3 0x1 INT_EVENT1_RIS_RX_CLR CLR 0 INT_EVENT1_RIS_RX_SET SET 1 INT_EVENT1_RIS_RTOUT SPI Receive Time-Out Event. 0x2 0x1 INT_EVENT1_RIS_RTOUT_CLR CLR 0 INT_EVENT1_RIS_RTOUT_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_RX Receive FIFO event mask. 0x3 0x1 INT_EVENT1_MIS_RX_CLR CLR 0 INT_EVENT1_MIS_RX_SET SET 1 INT_EVENT1_MIS_RTOUT SPI Receive Time-Out event mask. 0x2 0x1 INT_EVENT1_MIS_RTOUT_CLR CLR 0 INT_EVENT1_MIS_RTOUT_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_RX Set Receive FIFO event. 0x3 0x1 INT_EVENT1_ISET_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_RX_SET SET 1 INT_EVENT1_ISET_RTOUT Set SPI Receive Time-Out event. 0x2 0x1 INT_EVENT1_ISET_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_RTOUT_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_RX Clear Receive FIFO event. 0x3 0x1 INT_EVENT1_ICLR_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_RX_CLR CLR 1 INT_EVENT1_ICLR_RTOUT Clear SPI Receive Time-Out event. 0x2 0x1 INT_EVENT1_ICLR_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_RTOUT_CLR CLR 1 INT_EVENT2_IIDX Interrupt Index Register 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_TX_EVT TX_EVT 5 INT_EVENT2_IMASK Interrupt mask 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_TX Transmit FIFO event mask. 0x4 0x1 INT_EVENT2_IMASK_TX_CLR CLR 0 INT_EVENT2_IMASK_TX_SET SET 1 INT_EVENT2_RIS Raw interrupt status 0x1090 32 read-only INT_EVENT2_RIS_TX Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 0x4 0x1 INT_EVENT2_RIS_TX_CLR CLR 0 INT_EVENT2_RIS_TX_SET SET 1 INT_EVENT2_MIS Masked interrupt status 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_TX Masked Transmit FIFO event 0x4 0x1 INT_EVENT2_MIS_TX_CLR CLR 0 INT_EVENT2_MIS_TX_SET SET 1 INT_EVENT2_ISET Interrupt set 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_TX Set Transmit FIFO event. 0x4 0x1 INT_EVENT2_ISET_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_TX_SET SET 1 INT_EVENT2_ICLR Interrupt clear 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_TX Clear Transmit FIFO event. 0x4 0x1 INT_EVENT2_ICLR_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_TX_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only EVT_MODE_INT1_CFG_DISABLE DISABLE 0 EVT_MODE_INT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_INT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only EVT_MODE_INT2_CFG_DISABLE DISABLE 0 EVT_MODE_INT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT2_CFG_HARDWARE HARDWARE 2 CTL0 SPI control register 0 0x1100 32 read-write 0x00000000 CTL0_DSS Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit 0x0 0x5 read-write CTL0_DSS_DSS_4 DSS_4 3 CTL0_DSS_DSS_5 DSS_5 4 CTL0_DSS_DSS_6 DSS_6 5 CTL0_DSS_DSS_7 DSS_7 6 CTL0_DSS_DSS_8 DSS_8 7 CTL0_DSS_DSS_9 DSS_9 8 CTL0_DSS_DSS_10 DSS_10 9 CTL0_DSS_DSS_11 DSS_11 10 CTL0_DSS_DSS_12 DSS_12 11 CTL0_DSS_DSS_13 DSS_13 12 CTL0_DSS_DSS_14 DSS_14 13 CTL0_DSS_DSS_15 DSS_15 14 CTL0_DSS_DSS_16 DSS_16 15 CTL0_DSS_DSS_32 DSS_32 31 CTL0_FRF Frame format Select 0x5 0x2 read-write CTL0_FRF_MOTOROLA_3WIRE MOTOROLA_3WIRE 0 CTL0_FRF_MOTOROLA_4WIRE MOTOROLA_4WIRE 1 CTL0_FRF_TI_SYNC TI_SYNC 2 CTL0_FRF_MIRCOWIRE MIRCOWIRE 3 CTL0_SPO CLKOUT polarity (Motorola SPI frame format only) 0x8 0x1 read-write CTL0_SPO_LOW LOW 0 CTL0_SPO_HIGH HIGH 1 CTL0_SPH CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0x9 0x1 read-write CTL0_SPH_FIRST FIRST 0 CTL0_SPH_SECOND SECOND 1 CTL0_CSSEL Select the CS line to control on data transfer This bit is for controller mode only. 0xC 0x2 read-write CTL0_CSSEL_CSSEL_0 CSSEL_0 0 CTL0_CSSEL_CSSEL_1 CSSEL_1 1 CTL0_CSSEL_CSSEL_2 CSSEL_2 2 CTL0_CSSEL_CSSEL_3 CSSEL_3 3 CTL0_CSCLR Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0. 0xE 0x1 read-write CTL0_CSCLR_DISABLE DISABLE 0 CTL0_CSCLR_ENABLE ENABLE 1 CTL0_PACKEN Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP 0x7 0x1 read-write CTL0_PACKEN_DISABLED DISABLED 0 CTL0_PACKEN_ENABLED ENABLED 1 CTL1 SPI control register 1 0x1104 32 read-write 0x00000004 CTL1_LBM Loop back mode 0x1 0x1 read-write CTL1_LBM_DISABLE DISABLE 0 CTL1_LBM_ENABLE ENABLE 1 CTL1_MS Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. 0x2 0x1 read-write CTL1_MS_DISABLE DISABLE 0 CTL1_MS_ENABLE ENABLE 1 CTL1_SOD Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line: 0x3 0x1 read-write CTL1_SOD_DISABLE DISABLE 0 CTL1_SOD_ENABLE ENABLE 1 CTL1_MSB MSB first select. Controls the direction of the receive and transmit shift register. 0x4 0x1 read-write CTL1_MSB_DISABLE DISABLE 0 CTL1_MSB_ENABLE ENABLE 1 CTL1_PREN Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set. 0x5 0x1 read-write CTL1_PREN_DISABLE DISABLE 0 CTL1_PREN_ENABLE ENABLE 1 CTL1_REPEATTX Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral. 0x10 0x8 read-write CTL1_REPEATTX_DISABLE DISABLE 0 CTL1_PES Even Parity Select 0x6 0x1 read-write CTL1_PES_DISABLE DISABLE 0 CTL1_PES_ENABLE ENABLE 1 CTL1_PBS Parity Bit Select 0x7 0x1 read-write CTL1_PBS_DISABLE DISABLE 0 CTL1_PBS_ENABLE ENABLE 1 CTL1_CDMODE Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low. 0xC 0x4 read-write CTL1_CDMODE_DATA DATA 0 CTL1_CDMODE_COMMAND COMMAND 15 CTL1_ENABLE SPI enable 0x0 0x1 read-write CTL1_ENABLE_DISABLE DISABLE 0 CTL1_ENABLE_ENABLE ENABLE 1 CTL1_RXTIMEOUT Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function. 0x18 0x6 read-write CTL1_CDENABLE Command/Data Mode enable 0xB 0x1 read-write CTL1_CDENABLE_DISABLE DISABLE 0 CTL1_CDENABLE_ENABLE ENABLE 1 CTL1_PTEN Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes. 0x8 0x1 read-write CTL1_PTEN_DISABLE DISABLE 0 CTL1_PTEN_ENABLE ENABLE 1 CLKCTL Clock prescaler and divider register. 0x1108 32 read-write 0x00000000 CLKCTL_SCR Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023. 0x0 0xA read-write CLKCTL_DSAMPLE Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations. 0x1C 0x4 read-write IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000012 0xffffffff IFLS_TXIFLSEL SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0x0 0x3 read-write IFLS_TXIFLSEL_LVL_OFF LVL_OFF 0 IFLS_TXIFLSEL_LVL_3_4 LVL_3_4 1 IFLS_TXIFLSEL_LVL_1_2 LVL_1_2 2 IFLS_TXIFLSEL_LVL_1_4 LVL_1_4 3 IFLS_TXIFLSEL_LVL_RES4 LVL_RES4 4 IFLS_TXIFLSEL_LVL_EMPTY LVL_EMPTY 5 IFLS_TXIFLSEL_LVL_RES6 LVL_RES6 6 IFLS_TXIFLSEL_LEVEL_1 LEVEL_1 7 IFLS_RXIFLSEL SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 0x3 0x3 read-write IFLS_RXIFLSEL_LVL_OFF LVL_OFF 0 IFLS_RXIFLSEL_LVL_1_4 LVL_1_4 1 IFLS_RXIFLSEL_LVL_1_2 LVL_1_2 2 IFLS_RXIFLSEL_LVL_3_4 LVL_3_4 3 IFLS_RXIFLSEL_LVL_RES4 LVL_RES4 4 IFLS_RXIFLSEL_LVL_FULL LVL_FULL 5 IFLS_RXIFLSEL_LVL_RES6 LVL_RES6 6 IFLS_RXIFLSEL_LEVEL_1 LEVEL_1 7 STAT Status Register 0x1110 32 read-only STAT_TFE Transmit FIFO empty. 0x0 0x1 STAT_TFE_NOT_EMPTY NOT_EMPTY 0 STAT_TFE_EMPTY EMPTY 1 STAT_TNF Transmit FIFO not full 0x1 0x1 STAT_TNF_FULL FULL 0 STAT_TNF_NOT_FULL NOT_FULL 1 STAT_RFE Receive FIFO empty. 0x2 0x1 STAT_RFE_NOT_EMPTY NOT_EMPTY 0 STAT_RFE_EMPTY EMPTY 1 STAT_RNF Receive FIFO not full 0x3 0x1 STAT_RNF_FULL FULL 0 STAT_RNF_NOT_FULL NOT_FULL 1 STAT_BUSY Busy 0x4 0x1 STAT_BUSY_IDLE IDLE 0 STAT_BUSY_ACTIVE ACTIVE 1 RXDATA RXDATA Register 0x1130 32 read-only 0x00000000 RXDATA_DATA Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer. 0x0 0x10 read-only TXDATA TXDATA Register 0x1140 32 read-write 0x00000000 TXDATA_DATA Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. 0x0 0x10 read-write I2C0 1.0 PERIPHERALREGION 0x400F0000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG Peripheral Clock Configuration Register 0x808 32 read-write 0x00000000 CLKCFG_KEY KEY to Allow State Change -- 0xA9 0x18 0x8 write-only CLKCFG_KEY_UNLOCK _UNLOCK_W_ 169 CLKCFG_BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write CLKCFG_BLOCKASYNC_DISABLE DISABLE 0 CLKCFG_BLOCKASYNC_ENABLE ENABLE 1 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 INT_EVENT0_IIDX Interrupt index 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_MRXDONEFG MRXDONEFG 1 INT_EVENT0_IIDX_STAT_MTXDONEFG MTXDONEFG 2 INT_EVENT0_IIDX_STAT_MRXFIFOTRG MRXFIFOTRG 3 INT_EVENT0_IIDX_STAT_MTXFIFOTRG MTXFIFOTRG 4 INT_EVENT0_IIDX_STAT_MRXFIFOFULL MRXFIFOFULL 5 INT_EVENT0_IIDX_STAT_MTX_EMPTY MTX_EMPTY 6 INT_EVENT0_IIDX_STAT_MNACKFG MNACKFG 8 INT_EVENT0_IIDX_STAT_MSTARTFG MSTARTFG 9 INT_EVENT0_IIDX_STAT_MSTOPFG MSTOPFG 10 INT_EVENT0_IIDX_STAT_MARBLOSTFG MARBLOSTFG 11 INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2 MDMA_DONE1_CH2 12 INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3 MDMA_DONE1_CH3 13 INT_EVENT0_IIDX_STAT_MPEC_RX_ERR MPEC_RX_ERR 14 INT_EVENT0_IIDX_STAT_TIMEOUTA TIMEOUTA 15 INT_EVENT0_IIDX_STAT_TIMEOUTB TIMEOUTB 16 INT_EVENT0_IIDX_STAT_SRXDONEFG SRXDONEFG 17 INT_EVENT0_IIDX_STAT_STXDONEFG STXDONEFG 18 INT_EVENT0_IIDX_STAT_SRXFIFOTRG SRXFIFOTRG 19 INT_EVENT0_IIDX_STAT_STXFIFOTRG STXFIFOTRG 20 INT_EVENT0_IIDX_STAT_SRXFIFOFULL SRXFIFOFULL 21 INT_EVENT0_IIDX_STAT_STXEMPTY STXEMPTY 22 INT_EVENT0_IIDX_STAT_SSTARTFG SSTARTFG 23 INT_EVENT0_IIDX_STAT_SSTOPFG SSTOPFG 24 INT_EVENT0_IIDX_STAT_SGENCALL SGENCALL 25 INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2 SDMA_DONE1_CH2 26 INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3 SDMA_DONE1_CH3 27 INT_EVENT0_IIDX_STAT_SPEC_RX_ERR SPEC_RX_ERR 28 INT_EVENT0_IIDX_STAT_STX_UNFL STX_UNFL 29 INT_EVENT0_IIDX_STAT_SRX_OVFL SRX_OVFL 30 INT_EVENT0_IIDX_STAT_SARBLOST SARBLOST 31 INT_EVENT0_IIDX_STAT_INTR_OVFL INTR_OVFL 32 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_MRXDONE Master Receive Transaction completed Interrupt 0x0 0x1 INT_EVENT0_IMASK_MRXDONE_CLR CLR 0 INT_EVENT0_IMASK_MRXDONE_SET SET 1 INT_EVENT0_IMASK_TIMEOUTA Timeout A Interrupt 0xE 0x1 INT_EVENT0_IMASK_TIMEOUTA_CLR CLR 0 INT_EVENT0_IMASK_TIMEOUTA_SET SET 1 INT_EVENT0_IMASK_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_IMASK_MNACK_CLR CLR 0 INT_EVENT0_IMASK_MNACK_SET SET 1 INT_EVENT0_IMASK_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_IMASK_MSTART_CLR CLR 0 INT_EVENT0_IMASK_MSTART_SET SET 1 INT_EVENT0_IMASK_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_IMASK_MSTOP_CLR CLR 0 INT_EVENT0_IMASK_MSTOP_SET SET 1 INT_EVENT0_IMASK_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_IMASK_MARBLOST_CLR CLR 0 INT_EVENT0_IMASK_MARBLOST_SET SET 1 INT_EVENT0_IMASK_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_IMASK_MTXDONE_CLR CLR 0 INT_EVENT0_IMASK_MTXDONE_SET SET 1 INT_EVENT0_IMASK_MRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 INT_EVENT0_IMASK_MRXFIFOFULL_CLR CLR 0 INT_EVENT0_IMASK_MRXFIFOFULL_SET SET 1 INT_EVENT0_IMASK_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_IMASK_MTXEMPTY_CLR CLR 0 INT_EVENT0_IMASK_MTXEMPTY_SET SET 1 INT_EVENT0_IMASK_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_IMASK_MRXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_MRXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_IMASK_MTXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_MTXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_IMASK_MDMA_DONE1_2_CLR CLR 0 INT_EVENT0_IMASK_MDMA_DONE1_2_SET SET 1 INT_EVENT0_IMASK_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_IMASK_MDMA_DONE1_3_CLR CLR 0 INT_EVENT0_IMASK_MDMA_DONE1_3_SET SET 1 INT_EVENT0_IMASK_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_IMASK_SRXDONE_CLR CLR 0 INT_EVENT0_IMASK_SRXDONE_SET SET 1 INT_EVENT0_IMASK_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_IMASK_STXDONE_CLR CLR 0 INT_EVENT0_IMASK_STXDONE_SET SET 1 INT_EVENT0_IMASK_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_IMASK_SGENCALL_CLR CLR 0 INT_EVENT0_IMASK_SGENCALL_SET SET 1 INT_EVENT0_IMASK_STXEMPTY Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_IMASK_STXEMPTY_CLR CLR 0 INT_EVENT0_IMASK_STXEMPTY_SET SET 1 INT_EVENT0_IMASK_SRXFIFOFULL RXFIFO full event. This interrupt is set if an Slave RX FIFO is full. 0x14 0x1 INT_EVENT0_IMASK_SRXFIFOFULL_CLR CLR 0 INT_EVENT0_IMASK_SRXFIFOFULL_SET SET 1 INT_EVENT0_IMASK_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_IMASK_SRXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_SRXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_IMASK_STXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_STXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_SSTART Start Condition Interrupt 0x16 0x1 INT_EVENT0_IMASK_SSTART_CLR CLR 0 INT_EVENT0_IMASK_SSTART_SET SET 1 INT_EVENT0_IMASK_SSTOP Stop Condition Interrupt 0x17 0x1 INT_EVENT0_IMASK_SSTOP_CLR CLR 0 INT_EVENT0_IMASK_SSTOP_SET SET 1 INT_EVENT0_IMASK_SDMA_DONE1_2 Slave DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_IMASK_SDMA_DONE1_2_CLR CLR 0 INT_EVENT0_IMASK_SDMA_DONE1_2_SET SET 1 INT_EVENT0_IMASK_SDMA_DONE1_3 Slave DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_IMASK_SDMA_DONE1_3_CLR CLR 0 INT_EVENT0_IMASK_SDMA_DONE1_3_SET SET 1 INT_EVENT0_IMASK_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_IMASK_MPEC_RX_ERR_CLR CLR 0 INT_EVENT0_IMASK_MPEC_RX_ERR_SET SET 1 INT_EVENT0_IMASK_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_IMASK_TIMEOUTB_CLR CLR 0 INT_EVENT0_IMASK_TIMEOUTB_SET SET 1 INT_EVENT0_IMASK_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_IMASK_SPEC_RX_ERR_CLR CLR 0 INT_EVENT0_IMASK_SPEC_RX_ERR_SET SET 1 INT_EVENT0_IMASK_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_IMASK_STX_UNFL_CLR CLR 0 INT_EVENT0_IMASK_STX_UNFL_SET SET 1 INT_EVENT0_IMASK_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_IMASK_SRX_OVFL_CLR CLR 0 INT_EVENT0_IMASK_SRX_OVFL_SET SET 1 INT_EVENT0_IMASK_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_IMASK_SARBLOST_CLR CLR 0 INT_EVENT0_IMASK_SARBLOST_SET SET 1 INT_EVENT0_IMASK_INTR_OVFL Interrupt Overflow Interrupt Mask 0x1F 0x1 INT_EVENT0_IMASK_INTR_OVFL_CLR CLR 0 INT_EVENT0_IMASK_INTR_OVFL_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only INT_EVENT0_RIS_MRXDONE Master Receive Transaction completed Interrupt 0x0 0x1 INT_EVENT0_RIS_MRXDONE_CLR CLR 0 INT_EVENT0_RIS_MRXDONE_SET SET 1 INT_EVENT0_RIS_TIMEOUTA Timeout A Interrupt 0xE 0x1 INT_EVENT0_RIS_TIMEOUTA_CLR CLR 0 INT_EVENT0_RIS_TIMEOUTA_SET SET 1 INT_EVENT0_RIS_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_RIS_MNACK_CLR CLR 0 INT_EVENT0_RIS_MNACK_SET SET 1 INT_EVENT0_RIS_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_RIS_MSTART_CLR CLR 0 INT_EVENT0_RIS_MSTART_SET SET 1 INT_EVENT0_RIS_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_RIS_MSTOP_CLR CLR 0 INT_EVENT0_RIS_MSTOP_SET SET 1 INT_EVENT0_RIS_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_RIS_MARBLOST_CLR CLR 0 INT_EVENT0_RIS_MARBLOST_SET SET 1 INT_EVENT0_RIS_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_RIS_MTXDONE_CLR CLR 0 INT_EVENT0_RIS_MTXDONE_SET SET 1 INT_EVENT0_RIS_MRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 INT_EVENT0_RIS_MRXFIFOFULL_CLR CLR 0 INT_EVENT0_RIS_MRXFIFOFULL_SET SET 1 INT_EVENT0_RIS_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_RIS_MTXEMPTY_CLR CLR 0 INT_EVENT0_RIS_MTXEMPTY_SET SET 1 INT_EVENT0_RIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_RIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_MRXFIFOTRG_SET SET 1 INT_EVENT0_RIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_RIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_MTXFIFOTRG_SET SET 1 INT_EVENT0_RIS_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_RIS_MDMA_DONE1_2_CLR CLR 0 INT_EVENT0_RIS_MDMA_DONE1_2_SET SET 1 INT_EVENT0_RIS_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_RIS_MDMA_DONE1_3_CLR CLR 0 INT_EVENT0_RIS_MDMA_DONE1_3_SET SET 1 INT_EVENT0_RIS_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_RIS_SRXDONE_CLR CLR 0 INT_EVENT0_RIS_SRXDONE_SET SET 1 INT_EVENT0_RIS_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_RIS_STXDONE_CLR CLR 0 INT_EVENT0_RIS_STXDONE_SET SET 1 INT_EVENT0_RIS_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_RIS_SGENCALL_CLR CLR 0 INT_EVENT0_RIS_SGENCALL_SET SET 1 INT_EVENT0_RIS_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_RIS_STXEMPTY_CLR CLR 0 INT_EVENT0_RIS_STXEMPTY_SET SET 1 INT_EVENT0_RIS_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_RIS_SRXFIFOFULL_CLR CLR 0 INT_EVENT0_RIS_SRXFIFOFULL_SET SET 1 INT_EVENT0_RIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_RIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_SRXFIFOTRG_SET SET 1 INT_EVENT0_RIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_RIS_STXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_STXFIFOTRG_SET SET 1 INT_EVENT0_RIS_SSTART Start Condition Interrupt 0x16 0x1 INT_EVENT0_RIS_SSTART_CLR CLR 0 INT_EVENT0_RIS_SSTART_SET SET 1 INT_EVENT0_RIS_SSTOP Stop Condition Interrupt 0x17 0x1 INT_EVENT0_RIS_SSTOP_CLR CLR 0 INT_EVENT0_RIS_SSTOP_SET SET 1 INT_EVENT0_RIS_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_RIS_SDMA_DONE1_2_CLR CLR 0 INT_EVENT0_RIS_SDMA_DONE1_2_SET SET 1 INT_EVENT0_RIS_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_RIS_SDMA_DONE1_3_CLR CLR 0 INT_EVENT0_RIS_SDMA_DONE1_3_SET SET 1 INT_EVENT0_RIS_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_RIS_MPEC_RX_ERR_CLR CLR 0 INT_EVENT0_RIS_MPEC_RX_ERR_SET SET 1 INT_EVENT0_RIS_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_RIS_TIMEOUTB_CLR CLR 0 INT_EVENT0_RIS_TIMEOUTB_SET SET 1 INT_EVENT0_RIS_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_RIS_SPEC_RX_ERR_CLR CLR 0 INT_EVENT0_RIS_SPEC_RX_ERR_SET SET 1 INT_EVENT0_RIS_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_RIS_STX_UNFL_CLR CLR 0 INT_EVENT0_RIS_STX_UNFL_SET SET 1 INT_EVENT0_RIS_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_RIS_SRX_OVFL_CLR CLR 0 INT_EVENT0_RIS_SRX_OVFL_SET SET 1 INT_EVENT0_RIS_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_RIS_SARBLOST_CLR CLR 0 INT_EVENT0_RIS_SARBLOST_SET SET 1 INT_EVENT0_RIS_INTR_OVFL Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced 0x1F 0x1 INT_EVENT0_RIS_INTR_OVFL_CLR CLR 0 INT_EVENT0_RIS_INTR_OVFL_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_MRXDONE Master Receive Data Interrupt 0x0 0x1 INT_EVENT0_MIS_MRXDONE_CLR CLR 0 INT_EVENT0_MIS_MRXDONE_SET SET 1 INT_EVENT0_MIS_TIMEOUTA Timeout A Interrupt 0xE 0x1 INT_EVENT0_MIS_TIMEOUTA_CLR CLR 0 INT_EVENT0_MIS_TIMEOUTA_SET SET 1 INT_EVENT0_MIS_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_MIS_MNACK_CLR CLR 0 INT_EVENT0_MIS_MNACK_SET SET 1 INT_EVENT0_MIS_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_MIS_MSTART_CLR CLR 0 INT_EVENT0_MIS_MSTART_SET SET 1 INT_EVENT0_MIS_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_MIS_MSTOP_CLR CLR 0 INT_EVENT0_MIS_MSTOP_SET SET 1 INT_EVENT0_MIS_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_MIS_MARBLOST_CLR CLR 0 INT_EVENT0_MIS_MARBLOST_SET SET 1 INT_EVENT0_MIS_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_MIS_MTXDONE_CLR CLR 0 INT_EVENT0_MIS_MTXDONE_SET SET 1 INT_EVENT0_MIS_MRXFIFOFULL RXFIFO full event. This interrupt is set if the RX FIFO is full. 0x4 0x1 INT_EVENT0_MIS_MRXFIFOFULL_CLR CLR 0 INT_EVENT0_MIS_MRXFIFOFULL_SET SET 1 INT_EVENT0_MIS_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_MIS_MTXEMPTY_CLR CLR 0 INT_EVENT0_MIS_MTXEMPTY_SET SET 1 INT_EVENT0_MIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_MIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_MRXFIFOTRG_SET SET 1 INT_EVENT0_MIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_MIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_MTXFIFOTRG_SET SET 1 INT_EVENT0_MIS_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_MIS_MDMA_DONE1_2_CLR CLR 0 INT_EVENT0_MIS_MDMA_DONE1_2_SET SET 1 INT_EVENT0_MIS_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_MIS_MDMA_DONE1_3_CLR CLR 0 INT_EVENT0_MIS_MDMA_DONE1_3_SET SET 1 INT_EVENT0_MIS_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_MIS_SRXDONE_CLR CLR 0 INT_EVENT0_MIS_SRXDONE_SET SET 1 INT_EVENT0_MIS_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_MIS_STXDONE_CLR CLR 0 INT_EVENT0_MIS_STXDONE_SET SET 1 INT_EVENT0_MIS_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_MIS_SGENCALL_CLR CLR 0 INT_EVENT0_MIS_SGENCALL_SET SET 1 INT_EVENT0_MIS_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_MIS_STXEMPTY_CLR CLR 0 INT_EVENT0_MIS_STXEMPTY_SET SET 1 INT_EVENT0_MIS_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_MIS_SRXFIFOFULL_CLR CLR 0 INT_EVENT0_MIS_SRXFIFOFULL_SET SET 1 INT_EVENT0_MIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_MIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_SRXFIFOTRG_SET SET 1 INT_EVENT0_MIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_MIS_STXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_STXFIFOTRG_SET SET 1 INT_EVENT0_MIS_SSTART Slave START Detection Interrupt 0x16 0x1 INT_EVENT0_MIS_SSTART_CLR CLR 0 INT_EVENT0_MIS_SSTART_SET SET 1 INT_EVENT0_MIS_SSTOP Slave STOP Detection Interrupt 0x17 0x1 INT_EVENT0_MIS_SSTOP_CLR CLR 0 INT_EVENT0_MIS_SSTOP_SET SET 1 INT_EVENT0_MIS_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_MIS_SDMA_DONE1_2_CLR CLR 0 INT_EVENT0_MIS_SDMA_DONE1_2_SET SET 1 INT_EVENT0_MIS_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_MIS_SDMA_DONE1_3_CLR CLR 0 INT_EVENT0_MIS_SDMA_DONE1_3_SET SET 1 INT_EVENT0_MIS_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_MIS_MPEC_RX_ERR_CLR CLR 0 INT_EVENT0_MIS_MPEC_RX_ERR_SET SET 1 INT_EVENT0_MIS_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_MIS_TIMEOUTB_CLR CLR 0 INT_EVENT0_MIS_TIMEOUTB_SET SET 1 INT_EVENT0_MIS_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_MIS_SPEC_RX_ERR_CLR CLR 0 INT_EVENT0_MIS_SPEC_RX_ERR_SET SET 1 INT_EVENT0_MIS_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_MIS_STX_UNFL_CLR CLR 0 INT_EVENT0_MIS_STX_UNFL_SET SET 1 INT_EVENT0_MIS_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_MIS_SRX_OVFL_CLR CLR 0 INT_EVENT0_MIS_SRX_OVFL_SET SET 1 INT_EVENT0_MIS_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_MIS_SARBLOST_CLR CLR 0 INT_EVENT0_MIS_SARBLOST_SET SET 1 INT_EVENT0_MIS_INTR_OVFL Interrupt overflow 0x1F 0x1 INT_EVENT0_MIS_INTR_OVFL_CLR CLR 0 INT_EVENT0_MIS_INTR_OVFL_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_MRXDONE Master Receive Data Interrupt Signals that a byte has been received 0x0 0x1 INT_EVENT0_ISET_MRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MRXDONE_SET SET 1 INT_EVENT0_ISET_TIMEOUTA Timeout A interrupt 0xE 0x1 INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TIMEOUTA_SET SET 1 INT_EVENT0_ISET_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_ISET_MNACK_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MNACK_SET SET 1 INT_EVENT0_ISET_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_ISET_MSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MSTART_SET SET 1 INT_EVENT0_ISET_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_ISET_MSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MSTOP_SET SET 1 INT_EVENT0_ISET_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_ISET_MARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MARBLOST_SET SET 1 INT_EVENT0_ISET_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_ISET_MTXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MTXDONE_SET SET 1 INT_EVENT0_ISET_MRXFIFOFULL RXFIFO full event. 0x4 0x1 INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MRXFIFOFULL_SET SET 1 INT_EVENT0_ISET_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MTXEMPTY_SET SET 1 INT_EVENT0_ISET_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MRXFIFOTRG_SET SET 1 INT_EVENT0_ISET_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MTXFIFOTRG_SET SET 1 INT_EVENT0_ISET_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MDMA_DONE1_2_SET SET 1 INT_EVENT0_ISET_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MDMA_DONE1_3_SET SET 1 INT_EVENT0_ISET_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_ISET_SRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRXDONE_SET SET 1 INT_EVENT0_ISET_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_ISET_STXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STXDONE_SET SET 1 INT_EVENT0_ISET_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_ISET_SGENCALL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SGENCALL_SET SET 1 INT_EVENT0_ISET_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_ISET_STXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STXEMPTY_SET SET 1 INT_EVENT0_ISET_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRXFIFOFULL_SET SET 1 INT_EVENT0_ISET_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRXFIFOTRG_SET SET 1 INT_EVENT0_ISET_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STXFIFOTRG_SET SET 1 INT_EVENT0_ISET_SSTART Start Condition Interrupt 0x16 0x1 INT_EVENT0_ISET_SSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SSTART_SET SET 1 INT_EVENT0_ISET_SSTOP Stop Condition Interrupt 0x17 0x1 INT_EVENT0_ISET_SSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SSTOP_SET SET 1 INT_EVENT0_ISET_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SDMA_DONE1_2_SET SET 1 INT_EVENT0_ISET_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SDMA_DONE1_3_SET SET 1 INT_EVENT0_ISET_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MPEC_RX_ERR_SET SET 1 INT_EVENT0_ISET_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TIMEOUTB_SET SET 1 INT_EVENT0_ISET_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SPEC_RX_ERR_SET SET 1 INT_EVENT0_ISET_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_ISET_STX_UNFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STX_UNFL_SET SET 1 INT_EVENT0_ISET_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRX_OVFL_SET SET 1 INT_EVENT0_ISET_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_ISET_SARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SARBLOST_SET SET 1 INT_EVENT0_ISET_INTR_OVFL Interrupt overflow 0x1F 0x1 INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_INTR_OVFL_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_MRXDONE Master Receive Data Interrupt Signals that a byte has been received 0x0 0x1 INT_EVENT0_ICLR_MRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MRXDONE_CLR CLR 1 INT_EVENT0_ICLR_TIMEOUTA Timeout A interrupt 0xE 0x1 INT_EVENT0_ICLR_TIMEOUTA_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TIMEOUTA_CLR CLR 1 INT_EVENT0_ICLR_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_ICLR_MNACK_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MNACK_CLR CLR 1 INT_EVENT0_ICLR_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_ICLR_MSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MSTART_CLR CLR 1 INT_EVENT0_ICLR_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_ICLR_MSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MSTOP_CLR CLR 1 INT_EVENT0_ICLR_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_ICLR_MARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MARBLOST_CLR CLR 1 INT_EVENT0_ICLR_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_ICLR_MTXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MTXDONE_CLR CLR 1 INT_EVENT0_ICLR_MRXFIFOFULL RXFIFO full event. 0x4 0x1 INT_EVENT0_ICLR_MRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MRXFIFOFULL_CLR CLR 1 INT_EVENT0_ICLR_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_ICLR_MTXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MTXEMPTY_CLR CLR 1 INT_EVENT0_ICLR_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_ICLR_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MRXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_ICLR_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MTXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_ICLR_MDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MDMA_DONE1_2_CLR CLR 1 INT_EVENT0_ICLR_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_ICLR_MDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MDMA_DONE1_3_CLR CLR 1 INT_EVENT0_ICLR_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_ICLR_SRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRXDONE_CLR CLR 1 INT_EVENT0_ICLR_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_ICLR_STXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STXDONE_CLR CLR 1 INT_EVENT0_ICLR_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_ICLR_SGENCALL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SGENCALL_CLR CLR 1 INT_EVENT0_ICLR_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_ICLR_STXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STXEMPTY_CLR CLR 1 INT_EVENT0_ICLR_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_ICLR_SRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRXFIFOFULL_CLR CLR 1 INT_EVENT0_ICLR_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_ICLR_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_ICLR_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_SSTART Slave START Detection Interrupt 0x16 0x1 INT_EVENT0_ICLR_SSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SSTART_CLR CLR 1 INT_EVENT0_ICLR_SSTOP Slave STOP Detection Interrupt 0x17 0x1 INT_EVENT0_ICLR_SSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SSTOP_CLR CLR 1 INT_EVENT0_ICLR_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_ICLR_SDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SDMA_DONE1_2_CLR CLR 1 INT_EVENT0_ICLR_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_ICLR_SDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SDMA_DONE1_3_CLR CLR 1 INT_EVENT0_ICLR_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_ICLR_MPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MPEC_RX_ERR_CLR CLR 1 INT_EVENT0_ICLR_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_ICLR_TIMEOUTB_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TIMEOUTB_CLR CLR 1 INT_EVENT0_ICLR_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_ICLR_SPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SPEC_RX_ERR_CLR CLR 1 INT_EVENT0_ICLR_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_ICLR_STX_UNFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STX_UNFL_CLR CLR 1 INT_EVENT0_ICLR_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_ICLR_SRX_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRX_OVFL_CLR CLR 1 INT_EVENT0_ICLR_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_ICLR_SARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SARBLOST_CLR CLR 1 INT_EVENT0_ICLR_INTR_OVFL Interrupt overflow 0x1F 0x1 INT_EVENT0_ICLR_INTR_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_INTR_OVFL_CLR CLR 1 INT_EVENT1_IIDX Interrupt index 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_MRXFIFOTRG MRXFIFOTRG 1 INT_EVENT1_IIDX_STAT_MTXFIFOTRG MTXFIFOTRG 2 INT_EVENT1_IIDX_STAT_SRXFIFOTRG SRXFIFOTRG 3 INT_EVENT1_IIDX_STAT_STXFIFOTRG STXFIFOTRG 4 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_IMASK_MRXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_MRXFIFOTRG_SET SET 1 INT_EVENT1_IMASK_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_IMASK_MTXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_MTXFIFOTRG_SET SET 1 INT_EVENT1_IMASK_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_IMASK_SRXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_SRXFIFOTRG_SET SET 1 INT_EVENT1_IMASK_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_IMASK_STXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_STXFIFOTRG_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only 0x00000000 INT_EVENT1_RIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_RIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_MRXFIFOTRG_SET SET 1 INT_EVENT1_RIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_RIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_MTXFIFOTRG_SET SET 1 INT_EVENT1_RIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_RIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_SRXFIFOTRG_SET SET 1 INT_EVENT1_RIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_RIS_STXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_STXFIFOTRG_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_MIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_MRXFIFOTRG_SET SET 1 INT_EVENT1_MIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_MIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_MTXFIFOTRG_SET SET 1 INT_EVENT1_MIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_MIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_SRXFIFOTRG_SET SET 1 INT_EVENT1_MIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_MIS_STXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_STXFIFOTRG_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_MRXFIFOTRG_SET SET 1 INT_EVENT1_ISET_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_MTXFIFOTRG_SET SET 1 INT_EVENT1_ISET_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_SRXFIFOTRG_SET SET 1 INT_EVENT1_ISET_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_STXFIFOTRG_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_MRXFIFOTRG_CLR CLR 1 INT_EVENT1_ICLR_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_MTXFIFOTRG_CLR CLR 1 INT_EVENT1_ICLR_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_SRXFIFOTRG_CLR CLR 1 INT_EVENT1_ICLR_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_STXFIFOTRG_CLR CLR 1 INT_EVENT2_IIDX Interrupt index 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_MRXFIFOTRG MRXFIFOTRG 1 INT_EVENT2_IIDX_STAT_MTXFIFOTRG MTXFIFOTRG 2 INT_EVENT2_IIDX_STAT_SRXFIFOTRG SRXFIFOTRG 3 INT_EVENT2_IIDX_STAT_STXFIFOTRG STXFIFOTRG 4 INT_EVENT2_IMASK Interrupt mask 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_IMASK_MRXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_MRXFIFOTRG_SET SET 1 INT_EVENT2_IMASK_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_IMASK_MTXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_MTXFIFOTRG_SET SET 1 INT_EVENT2_IMASK_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_IMASK_SRXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_SRXFIFOTRG_SET SET 1 INT_EVENT2_IMASK_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_IMASK_STXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_STXFIFOTRG_SET SET 1 INT_EVENT2_RIS Raw interrupt status 0x1090 32 read-only 0x00000000 INT_EVENT2_RIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_RIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_MRXFIFOTRG_SET SET 1 INT_EVENT2_RIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_RIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_MTXFIFOTRG_SET SET 1 INT_EVENT2_RIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_RIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_SRXFIFOTRG_SET SET 1 INT_EVENT2_RIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_RIS_STXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_STXFIFOTRG_SET SET 1 INT_EVENT2_MIS Masked interrupt status 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_MIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_MRXFIFOTRG_SET SET 1 INT_EVENT2_MIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_MIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_MTXFIFOTRG_SET SET 1 INT_EVENT2_MIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_MIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_SRXFIFOTRG_SET SET 1 INT_EVENT2_MIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_MIS_STXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_STXFIFOTRG_SET SET 1 INT_EVENT2_ISET Interrupt set 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MRXFIFOTRG_SET SET 1 INT_EVENT2_ISET_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MTXFIFOTRG_SET SET 1 INT_EVENT2_ISET_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_SRXFIFOTRG_SET SET 1 INT_EVENT2_ISET_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_STXFIFOTRG_SET SET 1 INT_EVENT2_ICLR Interrupt clear 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_ICLR_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MRXFIFOTRG_CLR CLR 1 INT_EVENT2_ICLR_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_ICLR_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MTXFIFOTRG_CLR CLR 1 INT_EVENT2_ICLR_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_ICLR_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_SRXFIFOTRG_CLR CLR 1 INT_EVENT2_ICLR_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_ICLR_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_STXFIFOTRG_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only EVT_MODE_INT1_CFG_DISABLE DISABLE 0 EVT_MODE_INT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 GFCTL I2C Glitch Filter Control 0x1200 32 read-write GFCTL_AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0x9 0x2 read-write GFCTL_AGFSEL_AGLIT_5 AGLIT_5 0 GFCTL_AGFSEL_AGLIT_10 AGLIT_10 1 GFCTL_AGFSEL_AGLIT_25 AGLIT_25 2 GFCTL_AGFSEL_AGLIT_50 AGLIT_50 3 GFCTL_DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0x0 0x3 read-write GFCTL_DGFSEL_DISABLED DISABLED 0 GFCTL_DGFSEL_CLK_1 CLK_1 1 GFCTL_DGFSEL_CLK_2 CLK_2 2 GFCTL_DGFSEL_CLK_3 CLK_3 3 GFCTL_DGFSEL_CLK_4 CLK_4 4 GFCTL_DGFSEL_CLK_8 CLK_8 5 GFCTL_DGFSEL_CLK_16 CLK_16 6 GFCTL_DGFSEL_CLK_31 CLK_31 7 GFCTL_AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write GFCTL_AGFEN_DISABLE DISABLE 0 GFCTL_AGFEN_ENABLE ENABLE 1 GFCTL_CHAIN Analog and digital noise filters chaining enable. 0xB 0x1 GFCTL_CHAIN_DISABLE DISABLE 0 GFCTL_CHAIN_ENABLE ENABLE 1 TIMEOUT_CTL I2C Timeout Count Control Register 0x1204 32 read-write 0x00020002 0xffffffff TIMEOUT_CTL_TCNTLA Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0x0 0x8 read-write TIMEOUT_CTL_TCNTAEN Timeout Counter A Enable 0xF 0x1 read-write TIMEOUT_CTL_TCNTAEN_DISABLE DISABLE 0 TIMEOUT_CTL_TCNTAEN_ENABLE ENABLE 1 TIMEOUT_CTL_TCNTLB Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0x10 0x8 read-write TIMEOUT_CTL_TCNTBEN Timeout Counter B Enable 0x1F 0x1 read-write TIMEOUT_CTL_TCNTBEN_DISABLE DISABLE 0 TIMEOUT_CTL_TCNTBEN_ENABLE ENABLE 1 TIMEOUT_CNT I2C Timeout Count Register 0x1208 32 read-only 0x00020002 0xffffffff TIMEOUT_CNT_TCNTA Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0x0 0x8 read-only TIMEOUT_CNT_TCNTB Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0x10 0x8 MSA I2C Master Slave Address Register 0x1210 32 read-write 0x00000000 MSA_DIR Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0x0 0x1 MSA_DIR_TRANSMIT TRANSMIT 0 MSA_DIR_RECEIVE RECEIVE 1 MSA_SADDR I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0x1 0xA MSA_MMODE This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MSA_MMODE_MODE7 MODE7 0 MSA_MMODE_MODE10 MODE10 1 MCTR I2C Master Control Register 0x1214 32 read-write 0x00000000 0xffffffff MCTR_BURSTRUN I2C Master Enable and start transaction 0x0 0x1 read-write MCTR_BURSTRUN_DISABLE DISABLE 0 MCTR_BURSTRUN_ENABLE ENABLE 1 MCTR_START Generate START 0x1 0x1 read-write MCTR_START_DISABLE DISABLE 0 MCTR_START_ENABLE ENABLE 1 MCTR_STOP Generate STOP 0x2 0x1 read-write MCTR_STOP_DISABLE DISABLE 0 MCTR_STOP_ENABLE ENABLE 1 MCTR_ACK Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding. 0x3 0x1 read-write MCTR_ACK_DISABLE DISABLE 0 MCTR_ACK_ENABLE ENABLE 1 MCTR_MBLEN I2C transaction length This field contains the programmed length of bytes of the Transaction. 0x10 0xC read-write MCTR_MACKOEN Master ACK overrride Enable 0x4 0x1 MCTR_MACKOEN_DISABLE DISABLE 0 MCTR_MACKOEN_ENABLE ENABLE 1 MCTR_RD_ON_TXEMPTY Read on TX Empty 0x5 0x1 MCTR_RD_ON_TXEMPTY_DISABLE DISABLE 0 MCTR_RD_ON_TXEMPTY_ENABLE ENABLE 1 MSR I2C Master Status Register 0x1218 32 read-only MSR_BUSY I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0x0 0x1 read-only MSR_BUSY_CLEARED CLEARED 0 MSR_BUSY_SET SET 1 MSR_ERR Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0x1 0x1 read-only MSR_ERR_CLEARED CLEARED 0 MSR_ERR_SET SET 1 MSR_ADRACK Acknowledge Address 0x2 0x1 read-only MSR_ADRACK_CLEARED CLEARED 0 MSR_ADRACK_SET SET 1 MSR_DATACK Acknowledge Data 0x3 0x1 read-only MSR_DATACK_CLEARED CLEARED 0 MSR_DATACK_SET SET 1 MSR_ARBLST Arbitration Lost 0x4 0x1 read-only MSR_ARBLST_CLEARED CLEARED 0 MSR_ARBLST_SET SET 1 MSR_IDLE I2C Idle 0x5 0x1 read-only MSR_IDLE_CLEARED CLEARED 0 MSR_IDLE_SET SET 1 MSR_BUSBSY I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x6 0x1 read-only MSR_BUSBSY_CLEARED CLEARED 0 MSR_BUSBSY_SET SET 1 MSR_MBCNT I2C Master Transaction Count This field contains the current count-down value of the transaction. 0x10 0xC read-only MRXDATA I2C Master RXData 0x121C 32 read-only 0x00000000 0xffffffff MRXDATA_VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only MTXDATA I2C Master TXData 0x1220 32 read-write 0x00000000 0xffffffff MTXDATA_VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write MTPR I2C Master Timer Period 0x1224 32 read-write 0x00000001 0xffffffff MTPR_TPR Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0x0 0x7 read-write MCR I2C Master Configuration 0x1228 32 read-write 0x00000000 0xffffffff MCR_LPBK I2C Loopback 0x8 0x1 read-write MCR_LPBK_DISABLE DISABLE 0 MCR_LPBK_ENABLE ENABLE 1 MCR_MMST Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller. 0x1 0x1 read-write MCR_MMST_DISABLE DISABLE 0 MCR_MMST_ENABLE ENABLE 1 MCR_ACTIVE Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0x0 0x1 read-write MCR_ACTIVE_DISABLE DISABLE 0 MCR_ACTIVE_ENABLE ENABLE 1 MCR_CLKSTRETCH Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0x2 0x1 read-write MCR_CLKSTRETCH_DISABLE DISABLE 0 MCR_CLKSTRETCH_ENABLE ENABLE 1 MBMON I2C Master Bus Monitor 0x1234 32 read-only 0x00000003 0xffffffff MBMON_SCL I2C SCL Status 0x0 0x1 read-only MBMON_SCL_CLEARED CLEARED 0 MBMON_SCL_SET SET 1 MBMON_SDA I2C SDA Status 0x1 0x1 read-only MBMON_SDA_CLEARED CLEARED 0 MBMON_SDA_SET SET 1 MFIFOCTL I2C Master FIFO Control 0x1238 32 read-write 0x00000000 MFIFOCTL_TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 MFIFOCTL_TXTRIG_LEVEL_4 LEVEL_4 4 MFIFOCTL_TXTRIG_LEVEL_5 LEVEL_5 5 MFIFOCTL_TXTRIG_LEVEL_6 LEVEL_6 6 MFIFOCTL_TXTRIG_LEVEL_7 LEVEL_7 7 MFIFOCTL_TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 MFIFOCTL_TXFLUSH_NOFLUSH NOFLUSH 0 MFIFOCTL_TXFLUSH_FLUSH FLUSH 1 MFIFOCTL_RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 MFIFOCTL_RXTRIG_LEVEL_5 LEVEL_5 4 MFIFOCTL_RXTRIG_LEVEL_6 LEVEL_6 5 MFIFOCTL_RXTRIG_LEVEL_7 LEVEL_7 6 MFIFOCTL_RXTRIG_LEVEL_8 LEVEL_8 7 MFIFOCTL_RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 MFIFOCTL_RXFLUSH_NOFLUSH NOFLUSH 0 MFIFOCTL_RXFLUSH_FLUSH FLUSH 1 MFIFOSR I2C Master FIFO Status Register 0x123C 32 read-only 0x00000800 MFIFOSR_RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only MFIFOSR_TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only MFIFOSR_RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 MFIFOSR_RXFLUSH_INACTIVE INACTIVE 0 MFIFOSR_RXFLUSH_ACTIVE ACTIVE 1 MFIFOSR_TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 MFIFOSR_TXFLUSH_INACTIVE INACTIVE 0 MFIFOSR_TXFLUSH_ACTIVE ACTIVE 1 MASTER_I2CPECCTL I2C master PEC control register 0x1240 32 read-write 0x00000000 0xffffffff MASTER_I2CPECCTL_PECCNT PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine. 0x0 0x9 MASTER_I2CPECCTL_PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 MASTER_I2CPECCTL_PECEN_DISABLE DISABLE 0 MASTER_I2CPECCTL_PECEN_ENABLE ENABLE 1 MASTER_PECSR I2C master PEC status register 0x1244 32 read-only 0x00000000 0xffffffff MASTER_PECSR_PECBYTECNT PEC Byte Count This is the current PEC Byte Count of the Master State Machine. 0x0 0x9 MASTER_PECSR_PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 MASTER_PECSR_PECSTS_CHECK_CLEARED CLEARED 0 MASTER_PECSR_PECSTS_CHECK_SET SET 1 MASTER_PECSR_PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 MASTER_PECSR_PECSTS_ERROR_CLEARED CLEARED 0 MASTER_PECSR_PECSTS_ERROR_SET SET 1 SOAR I2C Slave Own Address 0x1250 32 read-write 0x00004000 0xffffffff SOAR_OAR I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0x0 0xA read-write SOAR_OAREN I2C Slave Own Address Enable 0xE 0x1 SOAR_OAREN_DISABLE DISABLE 0 SOAR_OAREN_ENABLE ENABLE 1 SOAR_SMODE This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 SOAR_SMODE_MODE7 MODE7 0 SOAR_SMODE_MODE10 MODE10 1 SOAR2 I2C Slave Own Address 2 0x1254 32 read-write 0x00000000 0xffffffff SOAR2_OAR2 I2C Slave Own Address 2 This field specifies the alternate OAR2 address. 0x0 0x7 read-write SOAR2_OAR2EN I2C Slave Own Address 2 Enable 0x7 0x1 read-write SOAR2_OAR2EN_DISABLE DISABLE 0 SOAR2_OAR2EN_ENABLE ENABLE 1 SOAR2_OAR2_MASK I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care. 0x10 0x7 SCTR I2C Slave Control Register 0x1258 32 read-write 0x00000404 0xffffffff SCTR_ACTIVE Device Active. Setting this bit enables the slave functionality. 0x0 0x1 read-write SCTR_ACTIVE_DISABLE DISABLE 0 SCTR_ACTIVE_ENABLE ENABLE 1 SCTR_GENCALL General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0x1 0x1 read-write SCTR_GENCALL_DISABLE DISABLE 0 SCTR_GENCALL_ENABLE ENABLE 1 SCTR_SCLKSTRETCH Slave Clock Stretch Enable 0x2 0x1 SCTR_SCLKSTRETCH_DISABLE DISABLE 0 SCTR_SCLKSTRETCH_ENABLE ENABLE 1 SCTR_TXEMPTY_ON_TREQ Tx Empty Interrupt on TREQ 0x3 0x1 SCTR_TXEMPTY_ON_TREQ_DISABLE DISABLE 0 SCTR_TXEMPTY_ON_TREQ_ENABLE ENABLE 1 SCTR_TXTRIG_TXMODE Tx Trigger when slave FSM is in Tx Mode 0x4 0x1 SCTR_TXTRIG_TXMODE_DISABLE DISABLE 0 SCTR_TXTRIG_TXMODE_ENABLE ENABLE 1 SCTR_TXWAIT_STALE_TXFIFO Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0x5 0x1 SCTR_TXWAIT_STALE_TXFIFO_DISABLE DISABLE 0 SCTR_TXWAIT_STALE_TXFIFO_ENABLE ENABLE 1 SCTR_RXFULL_ON_RREQ Rx full interrupt generated on RREQ condition as indicated in SSR 0x6 0x1 SCTR_RXFULL_ON_RREQ_DISABLE DISABLE 0 SCTR_RXFULL_ON_RREQ_ENABLE ENABLE 1 SCTR_EN_DEFHOSTADR Enable Default Host Address 0x7 0x1 SCTR_EN_DEFHOSTADR_DISABLE DISABLE 0 SCTR_EN_DEFHOSTADR_ENABLE ENABLE 1 SCTR_EN_ALRESPADR Enable Alert Response Address 0x8 0x1 SCTR_EN_ALRESPADR_DISABLE DISABLE 0 SCTR_EN_ALRESPADR_ENABLE ENABLE 1 SCTR_EN_DEFDEVADR Enable Deault device address 0x9 0x1 SCTR_EN_DEFDEVADR_DISABLE DISABLE 0 SCTR_EN_DEFDEVADR_ENABLE ENABLE 1 SCTR_SWUEN Slave Wakeup Enable 0xA 0x1 SCTR_SWUEN_DISABLE DISABLE 0 SCTR_SWUEN_ENABLE ENABLE 1 SSR I2C Slave Status Register 0x125C 32 read-only 0x00000000 0xffffffff SSR_RREQ Receive Request 0x0 0x1 read-only SSR_RREQ_CLEARED CLEARED 0 SSR_RREQ_SET SET 1 SSR_TREQ Transmit Request 0x1 0x1 read-only SSR_TREQ_CLEARED CLEARED 0 SSR_TREQ_SET SET 1 SSR_OAR2SEL OAR2 Address Matched This bit gets reevaluated after every address comparison. 0x3 0x1 read-only SSR_OAR2SEL_CLEARED CLEARED 0 SSR_OAR2SEL_SET SET 1 SSR_QCMDST Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0x4 0x1 read-only SSR_QCMDST_CLEARED CLEARED 0 SSR_QCMDST_SET SET 1 SSR_QCMDRW Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0x5 0x1 read-only SSR_QCMDRW_CLEARED CLEARED 0 SSR_QCMDRW_SET SET 1 SSR_RXMODE Slave FSM is in Rx MODE 0x2 0x1 SSR_RXMODE_CLEARED CLEARED 0 SSR_RXMODE_SET SET 1 SSR_BUSBSY I2C bus is busy 0x6 0x1 SSR_BUSBSY_CLEARED CLEARED 0 SSR_BUSBSY_SET SET 1 SSR_TXMODE Slave FSM is in TX MODE 0x7 0x1 SSR_TXMODE_CLEARED CLEARED 0 SSR_TXMODE_SET SET 1 SSR_STALE_TXFIFO Stale Tx FIFO 0x8 0x1 SSR_STALE_TXFIFO_CLEARED CLEARED 0 SSR_STALE_TXFIFO_SET SET 1 SSR_ADDRMATCH Indicates the address for which slave address match happened 0x9 0xA SRXDATA I2C Slave RXData 0x1260 32 read-only 0x00000000 0xffffffff SRXDATA_VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only STXDATA I2C Slave TXData 0x1264 32 read-write 0x00000000 0xffffffff STXDATA_VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write SACKCTL I2C Slave ACK Control 0x1268 32 read-write 0x00000000 0xffffffff SACKCTL_ACKOEN I2C Slave ACK Override Enable 0x0 0x1 read-write SACKCTL_ACKOEN_DISABLE DISABLE 0 SACKCTL_ACKOEN_ENABLE ENABLE 1 SACKCTL_ACKOVAL I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data. 0x1 0x1 read-write SACKCTL_ACKOVAL_DISABLE DISABLE 0 SACKCTL_ACKOVAL_ENABLE ENABLE 1 SACKCTL_ACKOEN_ON_START When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition. 0x2 0x1 SACKCTL_ACKOEN_ON_START_DISABLE DISABLE 0 SACKCTL_ACKOEN_ON_START_ENABLE ENABLE 1 SACKCTL_ACKOEN_ON_PECNEXT When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL. 0x3 0x1 SACKCTL_ACKOEN_ON_PECNEXT_DISABLE DISABLE 0 SACKCTL_ACKOEN_ON_PECNEXT_ENABLE ENABLE 1 SACKCTL_ACKOEN_ON_PECDONE When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte. 0x4 0x1 SACKCTL_ACKOEN_ON_PECDONE_DISABLE DISABLE 0 SACKCTL_ACKOEN_ON_PECDONE_ENABLE ENABLE 1 SFIFOCTL I2C Slave FIFO Control 0x126C 32 read-write 0x00000000 SFIFOCTL_TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 SFIFOCTL_TXTRIG_LEVEL_4 LEVEL_4 4 SFIFOCTL_TXTRIG_LEVEL_5 LEVEL_5 5 SFIFOCTL_TXTRIG_LEVEL_6 LEVEL_6 6 SFIFOCTL_TXTRIG_LEVEL_7 LEVEL_7 7 SFIFOCTL_TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 SFIFOCTL_TXFLUSH_NOFLUSH NOFLUSH 0 SFIFOCTL_TXFLUSH_FLUSH FLUSH 1 SFIFOCTL_RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 SFIFOCTL_RXFLUSH_NOFLUSH NOFLUSH 0 SFIFOCTL_RXFLUSH_FLUSH FLUSH 1 SFIFOCTL_RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 SFIFOCTL_RXTRIG_LEVEL_5 LEVEL_5 4 SFIFOCTL_RXTRIG_LEVEL_6 LEVEL_6 5 SFIFOCTL_RXTRIG_LEVEL_7 LEVEL_7 6 SFIFOCTL_RXTRIG_LEVEL_8 LEVEL_8 7 SFIFOSR I2C Slave FIFO Status Register 0x1270 32 read-only 0x00000800 SFIFOSR_RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only SFIFOSR_TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only SFIFOSR_TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 SFIFOSR_TXFLUSH_INACTIVE INACTIVE 0 SFIFOSR_TXFLUSH_ACTIVE ACTIVE 1 SFIFOSR_RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 SFIFOSR_RXFLUSH_INACTIVE INACTIVE 0 SFIFOSR_RXFLUSH_ACTIVE ACTIVE 1 SLAVE_PECCTL I2C Slave PEC control register 0x1274 32 read-write 0x00000000 0xffffffff SLAVE_PECCTL_PECCNT When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction 0x0 0x9 SLAVE_PECCTL_PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 SLAVE_PECCTL_PECEN_DISABLE DISABLE 0 SLAVE_PECCTL_PECEN_ENABLE ENABLE 1 SLAVE_PECSR I2C slave PEC status register 0x1278 32 read-only 0x00000000 0xffffffff SLAVE_PECSR_PECBYTECNT This is the current PEC Byte Count of the Slave State Machine. 0x0 0x9 SLAVE_PECSR_PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 SLAVE_PECSR_PECSTS_CHECK_CLEARED CLEARED 0 SLAVE_PECSR_PECSTS_CHECK_SET SET 1 SLAVE_PECSR_PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 SLAVE_PECSR_PECSTS_ERROR_CLEARED CLEARED 0 SLAVE_PECSR_PECSTS_ERROR_SET SET 1 CPUSS 1.0 CPUSSMMR 0x40400000 0x0 0x1F00 registers EVT_MODE Event Mode 0x10E0 32 read-only EVT_MODE_INT_CFG Event line mode select 0x0 0x2 read-only EVT_MODE_INT_CFG_DISABLE DISABLE 0 EVT_MODE_INT_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 read-only DESC_MAJREV Major rev of the IP 0x4 0x4 read-only DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only INT_GROUP0_IIDX Interrupt index 0x1100 32 read-only 0x00000000 INT_GROUP0_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_GROUP0_IIDX_STAT_NO_INTR NO_INTR 0 INT_GROUP0_IIDX_STAT_INT0 INT0 1 INT_GROUP0_IIDX_STAT_INT1 INT1 2 INT_GROUP0_IIDX_STAT_INT2 INT2 3 INT_GROUP0_IIDX_STAT_INT3 INT3 4 INT_GROUP0_IIDX_STAT_INT4 INT4 5 INT_GROUP0_IIDX_STAT_INT5 INT5 6 INT_GROUP0_IIDX_STAT_INT6 INT6 7 INT_GROUP0_IIDX_STAT_INT7 INT7 8 INT_GROUP0_IMASK Interrupt mask 0x1108 32 read-only 0x000000ff INT_GROUP0_IMASK_INT Masks the corresponding interrupt 0x0 0x8 read-only INT_GROUP0_IMASK_INT_CLR CLR 0 INT_GROUP0_IMASK_INT_SET SET 1 INT_GROUP0_RIS Raw interrupt status 0x1110 32 read-only 0x00000000 INT_GROUP0_RIS_INT Raw interrupt status for INT 0x0 0x8 INT_GROUP0_RIS_INT_CLR CLR 0 INT_GROUP0_RIS_INT_SET SET 1 INT_GROUP0_MIS Masked interrupt status 0x1118 32 read-only 0x00000000 INT_GROUP0_MIS_INT Masked interrupt status for INT0 0x0 0x1 INT_GROUP0_MIS_INT_CLR CLR 0 INT_GROUP0_MIS_INT_SET SET 1 INT_GROUP0_ISET Interrupt set 0x1120 32 write-only 0x00000000 INT_GROUP0_ISET_INT Sets INT in RIS register 0x0 0x1 INT_GROUP0_ISET_INT_NO_EFFECT NO_EFFECT 0 INT_GROUP0_ISET_INT_SET SET 1 INT_GROUP0_ICLR Interrupt clear 0x1128 32 write-only 0x00000000 INT_GROUP0_ICLR_INT Clears INT in RIS register 0x0 0x1 INT_GROUP0_ICLR_INT_NO_EFFECT NO_EFFECT 0 INT_GROUP0_ICLR_INT_CLR CLR 1 INT_GROUP1_IIDX Interrupt index 0x1130 32 read-only 0x00000000 INT_GROUP1_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_GROUP1_IIDX_STAT_NO_INTR NO_INTR 0 INT_GROUP1_IIDX_STAT_INT0 INT0 1 INT_GROUP1_IIDX_STAT_INT1 INT1 2 INT_GROUP1_IIDX_STAT_INT2 INT2 3 INT_GROUP1_IIDX_STAT_INT3 INT3 4 INT_GROUP1_IIDX_STAT_INT4 INT4 5 INT_GROUP1_IIDX_STAT_INT5 INT5 6 INT_GROUP1_IIDX_STAT_INT6 INT6 7 INT_GROUP1_IIDX_STAT_INT7 INT7 8 INT_GROUP1_IMASK Interrupt mask 0x1138 32 read-only 0x000000ff INT_GROUP1_IMASK_INT Masks the corresponding interrupt 0x0 0x8 read-only INT_GROUP1_IMASK_INT_CLR CLR 0 INT_GROUP1_IMASK_INT_SET SET 1 INT_GROUP1_RIS Raw interrupt status 0x1140 32 read-only 0x00000000 INT_GROUP1_RIS_INT Raw interrupt status for INT 0x0 0x1 INT_GROUP1_RIS_INT_CLR CLR 0 INT_GROUP1_RIS_INT_SET SET 1 INT_GROUP1_MIS Masked interrupt status 0x1148 32 read-only 0x00000000 INT_GROUP1_MIS_INT Masked interrupt status for INT0 0x0 0x1 INT_GROUP1_MIS_INT_CLR CLR 0 INT_GROUP1_MIS_INT_SET SET 1 INT_GROUP1_ISET Interrupt set 0x1150 32 write-only 0x00000000 INT_GROUP1_ISET_INT Sets INT in RIS register 0x0 0x1 INT_GROUP1_ISET_INT_NO_EFFECT NO_EFFECT 0 INT_GROUP1_ISET_INT_SET SET 1 INT_GROUP1_ICLR Interrupt clear 0x1158 32 write-only 0x00000000 INT_GROUP1_ICLR_INT Clears INT in RIS register 0x0 0x1 INT_GROUP1_ICLR_INT_NO_EFFECT NO_EFFECT 0 INT_GROUP1_ICLR_INT_CLR CLR 1 CTL Prefetch/Cache control 0x1300 32 read-write 0x00000007 CTL_PREFETCH Used to enable/disable instruction prefetch to Flash. 0x0 0x1 read-write CTL_PREFETCH_DISABLE DISABLE 0 CTL_PREFETCH_ENABLE ENABLE 1 CTL_ICACHE Used to enable/disable Instruction caching on flash access. 0x1 0x1 read-write CTL_ICACHE_DISABLE DISABLE 0 CTL_ICACHE_ENABLE ENABLE 1 CTL_LITEN Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals 0x2 0x1 read-write CTL_LITEN_DISABLE DISABLE 0 CTL_LITEN_ENABLE ENABLE 1 GPIOA 1.0 PERIPHERALREGION 0x400A0000 0x0 0x1F00 registers FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 FPUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKOVR Clock Override 0x1010 32 read-write 0x00000000 CLKOVR_OVERRIDE Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request 0x0 0x1 read-write CLKOVR_OVERRIDE_DISABLED DISABLED 0 CLKOVR_OVERRIDE_ENABLED ENABLED 1 CLKOVR_RUN_STOP If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system 0x1 0x1 read-write CLKOVR_RUN_STOP_RUN RUN 0 CLKOVR_RUN_STOP_STOP STOP 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000001 PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 INT_EVENT0_IIDX Interrupt index 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_DIO0 DIO0 1 INT_EVENT0_IIDX_STAT_DIO1 DIO1 2 INT_EVENT0_IIDX_STAT_DIO2 DIO2 3 INT_EVENT0_IIDX_STAT_DIO3 DIO3 4 INT_EVENT0_IIDX_STAT_DIO4 DIO4 5 INT_EVENT0_IIDX_STAT_DIO5 DIO5 6 INT_EVENT0_IIDX_STAT_DIO6 DIO6 7 INT_EVENT0_IIDX_STAT_DIO7 DIO7 8 INT_EVENT0_IIDX_STAT_DIO8 DIO8 9 INT_EVENT0_IIDX_STAT_DIO9 DIO9 10 INT_EVENT0_IIDX_STAT_DIO10 DIO10 11 INT_EVENT0_IIDX_STAT_DIO11 DIO11 12 INT_EVENT0_IIDX_STAT_DIO12 DIO12 13 INT_EVENT0_IIDX_STAT_DIO13 DIO13 14 INT_EVENT0_IIDX_STAT_DIO14 DIO14 15 INT_EVENT0_IIDX_STAT_DIO15 DIO15 16 INT_EVENT0_IIDX_STAT_DIO16 DIO16 17 INT_EVENT0_IIDX_STAT_DIO17 DIO17 18 INT_EVENT0_IIDX_STAT_DIO18 DIO18 19 INT_EVENT0_IIDX_STAT_DIO19 DIO19 20 INT_EVENT0_IIDX_STAT_DIO20 DIO20 21 INT_EVENT0_IIDX_STAT_DIO21 DIO21 22 INT_EVENT0_IIDX_STAT_DIO22 DIO22 23 INT_EVENT0_IIDX_STAT_DIO23 DIO23 24 INT_EVENT0_IIDX_STAT_DIO24 DIO24 25 INT_EVENT0_IIDX_STAT_DIO25 DIO25 26 INT_EVENT0_IIDX_STAT_DIO26 DIO26 27 INT_EVENT0_IIDX_STAT_DIO27 DIO27 28 INT_EVENT0_IIDX_STAT_DIO28 DIO28 29 INT_EVENT0_IIDX_STAT_DIO29 DIO29 30 INT_EVENT0_IIDX_STAT_DIO30 DIO30 31 INT_EVENT0_IIDX_STAT_DIO31 DIO31 32 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_DIO0 DIO0 event mask 0x0 0x1 INT_EVENT0_IMASK_DIO0_CLR CLR 0 INT_EVENT0_IMASK_DIO0_SET SET 1 INT_EVENT0_IMASK_DIO1 DIO1 event mask 0x1 0x1 INT_EVENT0_IMASK_DIO1_CLR CLR 0 INT_EVENT0_IMASK_DIO1_SET SET 1 INT_EVENT0_IMASK_DIO2 DIO2 event mask 0x2 0x1 INT_EVENT0_IMASK_DIO2_CLR CLR 0 INT_EVENT0_IMASK_DIO2_SET SET 1 INT_EVENT0_IMASK_DIO3 DIO3 event mask 0x3 0x1 INT_EVENT0_IMASK_DIO3_CLR CLR 0 INT_EVENT0_IMASK_DIO3_SET SET 1 INT_EVENT0_IMASK_DIO4 DIO4 event mask 0x4 0x1 INT_EVENT0_IMASK_DIO4_CLR CLR 0 INT_EVENT0_IMASK_DIO4_SET SET 1 INT_EVENT0_IMASK_DIO5 DIO5 event mask 0x5 0x1 INT_EVENT0_IMASK_DIO5_CLR CLR 0 INT_EVENT0_IMASK_DIO5_SET SET 1 INT_EVENT0_IMASK_DIO6 DIO6 event mask 0x6 0x1 INT_EVENT0_IMASK_DIO6_CLR CLR 0 INT_EVENT0_IMASK_DIO6_SET SET 1 INT_EVENT0_IMASK_DIO7 DIO7 event mask 0x7 0x1 INT_EVENT0_IMASK_DIO7_CLR CLR 0 INT_EVENT0_IMASK_DIO7_SET SET 1 INT_EVENT0_IMASK_DIO8 DIO8 event mask 0x8 0x1 INT_EVENT0_IMASK_DIO8_CLR CLR 0 INT_EVENT0_IMASK_DIO8_SET SET 1 INT_EVENT0_IMASK_DIO9 DIO9 event mask 0x9 0x1 INT_EVENT0_IMASK_DIO9_CLR CLR 0 INT_EVENT0_IMASK_DIO9_SET SET 1 INT_EVENT0_IMASK_DIO10 DIO10 event mask 0xA 0x1 INT_EVENT0_IMASK_DIO10_CLR CLR 0 INT_EVENT0_IMASK_DIO10_SET SET 1 INT_EVENT0_IMASK_DIO11 DIO11 event mask 0xB 0x1 INT_EVENT0_IMASK_DIO11_CLR CLR 0 INT_EVENT0_IMASK_DIO11_SET SET 1 INT_EVENT0_IMASK_DIO12 DIO12 event mask 0xC 0x1 INT_EVENT0_IMASK_DIO12_CLR CLR 0 INT_EVENT0_IMASK_DIO12_SET SET 1 INT_EVENT0_IMASK_DIO13 DIO13 event mask 0xD 0x1 INT_EVENT0_IMASK_DIO13_CLR CLR 0 INT_EVENT0_IMASK_DIO13_SET SET 1 INT_EVENT0_IMASK_DIO14 DIO14 event mask 0xE 0x1 INT_EVENT0_IMASK_DIO14_CLR CLR 0 INT_EVENT0_IMASK_DIO14_SET SET 1 INT_EVENT0_IMASK_DIO15 DIO15 event mask 0xF 0x1 INT_EVENT0_IMASK_DIO15_CLR CLR 0 INT_EVENT0_IMASK_DIO15_SET SET 1 INT_EVENT0_IMASK_DIO16 DIO16 event mask 0x10 0x1 INT_EVENT0_IMASK_DIO16_CLR CLR 0 INT_EVENT0_IMASK_DIO16_SET SET 1 INT_EVENT0_IMASK_DIO17 DIO17 event mask 0x11 0x1 INT_EVENT0_IMASK_DIO17_CLR CLR 0 INT_EVENT0_IMASK_DIO17_SET SET 1 INT_EVENT0_IMASK_DIO18 DIO18 event mask 0x12 0x1 INT_EVENT0_IMASK_DIO18_CLR CLR 0 INT_EVENT0_IMASK_DIO18_SET SET 1 INT_EVENT0_IMASK_DIO19 DIO19 event mask 0x13 0x1 INT_EVENT0_IMASK_DIO19_CLR CLR 0 INT_EVENT0_IMASK_DIO19_SET SET 1 INT_EVENT0_IMASK_DIO20 DIO20 event mask 0x14 0x1 INT_EVENT0_IMASK_DIO20_CLR CLR 0 INT_EVENT0_IMASK_DIO20_SET SET 1 INT_EVENT0_IMASK_DIO21 DIO21 event mask 0x15 0x1 INT_EVENT0_IMASK_DIO21_CLR CLR 0 INT_EVENT0_IMASK_DIO21_SET SET 1 INT_EVENT0_IMASK_DIO22 DIO22 event mask 0x16 0x1 INT_EVENT0_IMASK_DIO22_CLR CLR 0 INT_EVENT0_IMASK_DIO22_SET SET 1 INT_EVENT0_IMASK_DIO23 DIO23 event mask 0x17 0x1 INT_EVENT0_IMASK_DIO23_CLR CLR 0 INT_EVENT0_IMASK_DIO23_SET SET 1 INT_EVENT0_IMASK_DIO24 DIO24 event mask 0x18 0x1 INT_EVENT0_IMASK_DIO24_CLR CLR 0 INT_EVENT0_IMASK_DIO24_SET SET 1 INT_EVENT0_IMASK_DIO25 DIO25 event mask 0x19 0x1 INT_EVENT0_IMASK_DIO25_CLR CLR 0 INT_EVENT0_IMASK_DIO25_SET SET 1 INT_EVENT0_IMASK_DIO26 DIO26 event mask 0x1A 0x1 INT_EVENT0_IMASK_DIO26_CLR CLR 0 INT_EVENT0_IMASK_DIO26_SET SET 1 INT_EVENT0_IMASK_DIO27 DIO27 event mask 0x1B 0x1 INT_EVENT0_IMASK_DIO27_CLR CLR 0 INT_EVENT0_IMASK_DIO27_SET SET 1 INT_EVENT0_IMASK_DIO28 DIO28 event mask 0x1C 0x1 INT_EVENT0_IMASK_DIO28_CLR CLR 0 INT_EVENT0_IMASK_DIO28_SET SET 1 INT_EVENT0_IMASK_DIO29 DIO29 event mask 0x1D 0x1 INT_EVENT0_IMASK_DIO29_CLR CLR 0 INT_EVENT0_IMASK_DIO29_SET SET 1 INT_EVENT0_IMASK_DIO30 DIO30 event mask 0x1E 0x1 INT_EVENT0_IMASK_DIO30_CLR CLR 0 INT_EVENT0_IMASK_DIO30_SET SET 1 INT_EVENT0_IMASK_DIO31 DIO31 event mask 0x1F 0x1 INT_EVENT0_IMASK_DIO31_CLR CLR 0 INT_EVENT0_IMASK_DIO31_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only 0x00000000 INT_EVENT0_RIS_DIO0 DIO0 event 0x0 0x1 INT_EVENT0_RIS_DIO0_CLR CLR 0 INT_EVENT0_RIS_DIO0_SET SET 1 INT_EVENT0_RIS_DIO1 DIO1 event 0x1 0x1 INT_EVENT0_RIS_DIO1_CLR CLR 0 INT_EVENT0_RIS_DIO1_SET SET 1 INT_EVENT0_RIS_DIO2 DIO2 event 0x2 0x1 INT_EVENT0_RIS_DIO2_CLR CLR 0 INT_EVENT0_RIS_DIO2_SET SET 1 INT_EVENT0_RIS_DIO3 DIO3 event 0x3 0x1 INT_EVENT0_RIS_DIO3_CLR CLR 0 INT_EVENT0_RIS_DIO3_SET SET 1 INT_EVENT0_RIS_DIO4 DIO4 event 0x4 0x1 INT_EVENT0_RIS_DIO4_CLR CLR 0 INT_EVENT0_RIS_DIO4_SET SET 1 INT_EVENT0_RIS_DIO5 DIO5 event 0x5 0x1 INT_EVENT0_RIS_DIO5_CLR CLR 0 INT_EVENT0_RIS_DIO5_SET SET 1 INT_EVENT0_RIS_DIO6 DIO6 event 0x6 0x1 INT_EVENT0_RIS_DIO6_CLR CLR 0 INT_EVENT0_RIS_DIO6_SET SET 1 INT_EVENT0_RIS_DIO7 DIO7 event 0x7 0x1 INT_EVENT0_RIS_DIO7_CLR CLR 0 INT_EVENT0_RIS_DIO7_SET SET 1 INT_EVENT0_RIS_DIO8 DIO8 event 0x8 0x1 INT_EVENT0_RIS_DIO8_CLR CLR 0 INT_EVENT0_RIS_DIO8_SET SET 1 INT_EVENT0_RIS_DIO9 DIO9 event 0x9 0x1 INT_EVENT0_RIS_DIO9_CLR CLR 0 INT_EVENT0_RIS_DIO9_SET SET 1 INT_EVENT0_RIS_DIO10 DIO10 event 0xA 0x1 INT_EVENT0_RIS_DIO10_CLR CLR 0 INT_EVENT0_RIS_DIO10_SET SET 1 INT_EVENT0_RIS_DIO11 DIO11 event 0xB 0x1 INT_EVENT0_RIS_DIO11_CLR CLR 0 INT_EVENT0_RIS_DIO11_SET SET 1 INT_EVENT0_RIS_DIO12 DIO12 event 0xC 0x1 INT_EVENT0_RIS_DIO12_CLR CLR 0 INT_EVENT0_RIS_DIO12_SET SET 1 INT_EVENT0_RIS_DIO13 DIO13 event 0xD 0x1 INT_EVENT0_RIS_DIO13_CLR CLR 0 INT_EVENT0_RIS_DIO13_SET SET 1 INT_EVENT0_RIS_DIO14 DIO14 event 0xE 0x1 INT_EVENT0_RIS_DIO14_CLR CLR 0 INT_EVENT0_RIS_DIO14_SET SET 1 INT_EVENT0_RIS_DIO15 DIO15 event 0xF 0x1 INT_EVENT0_RIS_DIO15_CLR CLR 0 INT_EVENT0_RIS_DIO15_SET SET 1 INT_EVENT0_RIS_DIO16 DIO16 event 0x10 0x1 INT_EVENT0_RIS_DIO16_CLR CLR 0 INT_EVENT0_RIS_DIO16_SET SET 1 INT_EVENT0_RIS_DIO17 DIO17 event 0x11 0x1 INT_EVENT0_RIS_DIO17_CLR CLR 0 INT_EVENT0_RIS_DIO17_SET SET 1 INT_EVENT0_RIS_DIO18 DIO18 event 0x12 0x1 INT_EVENT0_RIS_DIO18_CLR CLR 0 INT_EVENT0_RIS_DIO18_SET SET 1 INT_EVENT0_RIS_DIO19 DIO19 event 0x13 0x1 INT_EVENT0_RIS_DIO19_CLR CLR 0 INT_EVENT0_RIS_DIO19_SET SET 1 INT_EVENT0_RIS_DIO20 DIO20 event 0x14 0x1 INT_EVENT0_RIS_DIO20_CLR CLR 0 INT_EVENT0_RIS_DIO20_SET SET 1 INT_EVENT0_RIS_DIO21 DIO21 event 0x15 0x1 INT_EVENT0_RIS_DIO21_CLR CLR 0 INT_EVENT0_RIS_DIO21_SET SET 1 INT_EVENT0_RIS_DIO22 DIO22 event 0x16 0x1 INT_EVENT0_RIS_DIO22_CLR CLR 0 INT_EVENT0_RIS_DIO22_SET SET 1 INT_EVENT0_RIS_DIO23 DIO23 event 0x17 0x1 INT_EVENT0_RIS_DIO23_CLR CLR 0 INT_EVENT0_RIS_DIO23_SET SET 1 INT_EVENT0_RIS_DIO24 DIO24 event 0x18 0x1 INT_EVENT0_RIS_DIO24_CLR CLR 0 INT_EVENT0_RIS_DIO24_SET SET 1 INT_EVENT0_RIS_DIO25 DIO25 event 0x19 0x1 INT_EVENT0_RIS_DIO25_CLR CLR 0 INT_EVENT0_RIS_DIO25_SET SET 1 INT_EVENT0_RIS_DIO26 DIO26 event 0x1A 0x1 INT_EVENT0_RIS_DIO26_CLR CLR 0 INT_EVENT0_RIS_DIO26_SET SET 1 INT_EVENT0_RIS_DIO27 DIO27 event 0x1B 0x1 INT_EVENT0_RIS_DIO27_CLR CLR 0 INT_EVENT0_RIS_DIO27_SET SET 1 INT_EVENT0_RIS_DIO28 DIO28 event 0x1C 0x1 INT_EVENT0_RIS_DIO28_CLR CLR 0 INT_EVENT0_RIS_DIO28_SET SET 1 INT_EVENT0_RIS_DIO29 DIO29 event 0x1D 0x1 INT_EVENT0_RIS_DIO29_CLR CLR 0 INT_EVENT0_RIS_DIO29_SET SET 1 INT_EVENT0_RIS_DIO30 DIO30 event 0x1E 0x1 INT_EVENT0_RIS_DIO30_CLR CLR 0 INT_EVENT0_RIS_DIO30_SET SET 1 INT_EVENT0_RIS_DIO31 DIO31 event 0x1F 0x1 INT_EVENT0_RIS_DIO31_CLR CLR 0 INT_EVENT0_RIS_DIO31_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_DIO0 DIO0 event 0x0 0x1 INT_EVENT0_MIS_DIO0_CLR CLR 0 INT_EVENT0_MIS_DIO0_SET SET 1 INT_EVENT0_MIS_DIO1 DIO1 event 0x1 0x1 INT_EVENT0_MIS_DIO1_CLR CLR 0 INT_EVENT0_MIS_DIO1_SET SET 1 INT_EVENT0_MIS_DIO2 DIO2 event 0x2 0x1 INT_EVENT0_MIS_DIO2_CLR CLR 0 INT_EVENT0_MIS_DIO2_SET SET 1 INT_EVENT0_MIS_DIO3 DIO3 event 0x3 0x1 INT_EVENT0_MIS_DIO3_CLR CLR 0 INT_EVENT0_MIS_DIO3_SET SET 1 INT_EVENT0_MIS_DIO4 DIO4 event 0x4 0x1 INT_EVENT0_MIS_DIO4_CLR CLR 0 INT_EVENT0_MIS_DIO4_SET SET 1 INT_EVENT0_MIS_DIO5 DIO5 event 0x5 0x1 INT_EVENT0_MIS_DIO5_CLR CLR 0 INT_EVENT0_MIS_DIO5_SET SET 1 INT_EVENT0_MIS_DIO6 DIO6 event 0x6 0x1 INT_EVENT0_MIS_DIO6_CLR CLR 0 INT_EVENT0_MIS_DIO6_SET SET 1 INT_EVENT0_MIS_DIO7 DIO7 event 0x7 0x1 INT_EVENT0_MIS_DIO7_CLR CLR 0 INT_EVENT0_MIS_DIO7_SET SET 1 INT_EVENT0_MIS_DIO8 DIO8 event 0x8 0x1 INT_EVENT0_MIS_DIO8_CLR CLR 0 INT_EVENT0_MIS_DIO8_SET SET 1 INT_EVENT0_MIS_DIO9 DIO9 event 0x9 0x1 INT_EVENT0_MIS_DIO9_CLR CLR 0 INT_EVENT0_MIS_DIO9_SET SET 1 INT_EVENT0_MIS_DIO10 DIO10 event 0xA 0x1 INT_EVENT0_MIS_DIO10_CLR CLR 0 INT_EVENT0_MIS_DIO10_SET SET 1 INT_EVENT0_MIS_DIO11 DIO11 event 0xB 0x1 INT_EVENT0_MIS_DIO11_CLR CLR 0 INT_EVENT0_MIS_DIO11_SET SET 1 INT_EVENT0_MIS_DIO12 DIO12 event 0xC 0x1 INT_EVENT0_MIS_DIO12_CLR CLR 0 INT_EVENT0_MIS_DIO12_SET SET 1 INT_EVENT0_MIS_DIO13 DIO13 event 0xD 0x1 INT_EVENT0_MIS_DIO13_CLR CLR 0 INT_EVENT0_MIS_DIO13_SET SET 1 INT_EVENT0_MIS_DIO14 DIO14 event 0xE 0x1 INT_EVENT0_MIS_DIO14_CLR CLR 0 INT_EVENT0_MIS_DIO14_SET SET 1 INT_EVENT0_MIS_DIO15 DIO15 event 0xF 0x1 INT_EVENT0_MIS_DIO15_CLR CLR 0 INT_EVENT0_MIS_DIO15_SET SET 1 INT_EVENT0_MIS_DIO16 DIO16 event 0x10 0x1 INT_EVENT0_MIS_DIO16_CLR CLR 0 INT_EVENT0_MIS_DIO16_SET SET 1 INT_EVENT0_MIS_DIO17 DIO17 event 0x11 0x1 INT_EVENT0_MIS_DIO17_CLR CLR 0 INT_EVENT0_MIS_DIO17_SET SET 1 INT_EVENT0_MIS_DIO18 DIO18 event 0x12 0x1 INT_EVENT0_MIS_DIO18_CLR CLR 0 INT_EVENT0_MIS_DIO18_SET SET 1 INT_EVENT0_MIS_DIO19 DIO19 event 0x13 0x1 INT_EVENT0_MIS_DIO19_CLR CLR 0 INT_EVENT0_MIS_DIO19_SET SET 1 INT_EVENT0_MIS_DIO20 DIO20 event 0x14 0x1 INT_EVENT0_MIS_DIO20_CLR CLR 0 INT_EVENT0_MIS_DIO20_SET SET 1 INT_EVENT0_MIS_DIO21 DIO21 event 0x15 0x1 INT_EVENT0_MIS_DIO21_CLR CLR 0 INT_EVENT0_MIS_DIO21_SET SET 1 INT_EVENT0_MIS_DIO22 DIO22 event 0x16 0x1 INT_EVENT0_MIS_DIO22_CLR CLR 0 INT_EVENT0_MIS_DIO22_SET SET 1 INT_EVENT0_MIS_DIO23 DIO23 event 0x17 0x1 INT_EVENT0_MIS_DIO23_CLR CLR 0 INT_EVENT0_MIS_DIO23_SET SET 1 INT_EVENT0_MIS_DIO24 DIO24 event 0x18 0x1 INT_EVENT0_MIS_DIO24_CLR CLR 0 INT_EVENT0_MIS_DIO24_SET SET 1 INT_EVENT0_MIS_DIO25 DIO25 event 0x19 0x1 INT_EVENT0_MIS_DIO25_CLR CLR 0 INT_EVENT0_MIS_DIO25_SET SET 1 INT_EVENT0_MIS_DIO26 DIO26 event 0x1A 0x1 INT_EVENT0_MIS_DIO26_CLR CLR 0 INT_EVENT0_MIS_DIO26_SET SET 1 INT_EVENT0_MIS_DIO27 DIO27 event 0x1B 0x1 INT_EVENT0_MIS_DIO27_CLR CLR 0 INT_EVENT0_MIS_DIO27_SET SET 1 INT_EVENT0_MIS_DIO28 DIO28 event 0x1C 0x1 INT_EVENT0_MIS_DIO28_CLR CLR 0 INT_EVENT0_MIS_DIO28_SET SET 1 INT_EVENT0_MIS_DIO29 DIO29 event 0x1D 0x1 INT_EVENT0_MIS_DIO29_CLR CLR 0 INT_EVENT0_MIS_DIO29_SET SET 1 INT_EVENT0_MIS_DIO30 DIO30 event 0x1E 0x1 INT_EVENT0_MIS_DIO30_CLR CLR 0 INT_EVENT0_MIS_DIO30_SET SET 1 INT_EVENT0_MIS_DIO31 DIO31 event 0x1F 0x1 INT_EVENT0_MIS_DIO31_CLR CLR 0 INT_EVENT0_MIS_DIO31_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_DIO0 DIO0 event 0x0 0x1 INT_EVENT0_ISET_DIO0_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO0_SET SET 1 INT_EVENT0_ISET_DIO1 DIO1 event 0x1 0x1 INT_EVENT0_ISET_DIO1_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO1_SET SET 1 INT_EVENT0_ISET_DIO2 DIO2 event 0x2 0x1 INT_EVENT0_ISET_DIO2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO2_SET SET 1 INT_EVENT0_ISET_DIO3 DIO3 event 0x3 0x1 INT_EVENT0_ISET_DIO3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO3_SET SET 1 INT_EVENT0_ISET_DIO4 DIO4 event 0x4 0x1 INT_EVENT0_ISET_DIO4_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO4_SET SET 1 INT_EVENT0_ISET_DIO5 DIO5 event 0x5 0x1 INT_EVENT0_ISET_DIO5_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO5_SET SET 1 INT_EVENT0_ISET_DIO6 DIO6 event 0x6 0x1 INT_EVENT0_ISET_DIO6_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO6_SET SET 1 INT_EVENT0_ISET_DIO7 DIO7 event 0x7 0x1 INT_EVENT0_ISET_DIO7_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO7_SET SET 1 INT_EVENT0_ISET_DIO8 DIO8 event 0x8 0x1 INT_EVENT0_ISET_DIO8_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO8_SET SET 1 INT_EVENT0_ISET_DIO9 DIO9 event 0x9 0x1 INT_EVENT0_ISET_DIO9_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO9_SET SET 1 INT_EVENT0_ISET_DIO10 DIO10 event 0xA 0x1 INT_EVENT0_ISET_DIO10_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO10_SET SET 1 INT_EVENT0_ISET_DIO11 DIO11 event 0xB 0x1 INT_EVENT0_ISET_DIO11_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO11_SET SET 1 INT_EVENT0_ISET_DIO12 DIO12 event 0xC 0x1 INT_EVENT0_ISET_DIO12_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO12_SET SET 1 INT_EVENT0_ISET_DIO13 DIO13 event 0xD 0x1 INT_EVENT0_ISET_DIO13_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO13_SET SET 1 INT_EVENT0_ISET_DIO14 DIO14 event 0xE 0x1 INT_EVENT0_ISET_DIO14_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO14_SET SET 1 INT_EVENT0_ISET_DIO15 DIO15 event 0xF 0x1 INT_EVENT0_ISET_DIO15_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO15_SET SET 1 INT_EVENT0_ISET_DIO16 DIO16 event 0x10 0x1 INT_EVENT0_ISET_DIO16_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO16_SET SET 1 INT_EVENT0_ISET_DIO17 DIO17 event 0x11 0x1 INT_EVENT0_ISET_DIO17_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO17_SET SET 1 INT_EVENT0_ISET_DIO18 DIO18 event 0x12 0x1 INT_EVENT0_ISET_DIO18_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO18_SET SET 1 INT_EVENT0_ISET_DIO19 DIO19 event 0x13 0x1 INT_EVENT0_ISET_DIO19_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO19_SET SET 1 INT_EVENT0_ISET_DIO20 DIO20 event 0x14 0x1 INT_EVENT0_ISET_DIO20_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO20_SET SET 1 INT_EVENT0_ISET_DIO21 DIO21 event 0x15 0x1 INT_EVENT0_ISET_DIO21_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO21_SET SET 1 INT_EVENT0_ISET_DIO22 DIO22 event 0x16 0x1 INT_EVENT0_ISET_DIO22_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO22_SET SET 1 INT_EVENT0_ISET_DIO23 DIO23 event 0x17 0x1 INT_EVENT0_ISET_DIO23_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO23_SET SET 1 INT_EVENT0_ISET_DIO24 DIO24 event 0x18 0x1 INT_EVENT0_ISET_DIO24_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO24_SET SET 1 INT_EVENT0_ISET_DIO25 DIO25 event 0x19 0x1 INT_EVENT0_ISET_DIO25_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO25_SET SET 1 INT_EVENT0_ISET_DIO26 DIO26 event 0x1A 0x1 INT_EVENT0_ISET_DIO26_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO26_SET SET 1 INT_EVENT0_ISET_DIO27 DIO27 event 0x1B 0x1 INT_EVENT0_ISET_DIO27_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO27_SET SET 1 INT_EVENT0_ISET_DIO28 DIO28 event 0x1C 0x1 INT_EVENT0_ISET_DIO28_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO28_SET SET 1 INT_EVENT0_ISET_DIO29 DIO29 event 0x1D 0x1 INT_EVENT0_ISET_DIO29_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO29_SET SET 1 INT_EVENT0_ISET_DIO30 DIO30 event 0x1E 0x1 INT_EVENT0_ISET_DIO30_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO30_SET SET 1 INT_EVENT0_ISET_DIO31 DIO31 event 0x1F 0x1 INT_EVENT0_ISET_DIO31_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DIO31_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_DIO0 DIO0 event 0x0 0x1 INT_EVENT0_ICLR_DIO0_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO0_CLR CLR 1 INT_EVENT0_ICLR_DIO1 DIO1 event 0x1 0x1 INT_EVENT0_ICLR_DIO1_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO1_CLR CLR 1 INT_EVENT0_ICLR_DIO2 DIO2 event 0x2 0x1 INT_EVENT0_ICLR_DIO2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO2_CLR CLR 1 INT_EVENT0_ICLR_DIO3 DIO3 event 0x3 0x1 INT_EVENT0_ICLR_DIO3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO3_CLR CLR 1 INT_EVENT0_ICLR_DIO4 DIO4 event 0x4 0x1 INT_EVENT0_ICLR_DIO4_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO4_CLR CLR 1 INT_EVENT0_ICLR_DIO5 DIO5 event 0x5 0x1 INT_EVENT0_ICLR_DIO5_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO5_CLR CLR 1 INT_EVENT0_ICLR_DIO6 DIO6 event 0x6 0x1 INT_EVENT0_ICLR_DIO6_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO6_CLR CLR 1 INT_EVENT0_ICLR_DIO7 DIO7 event 0x7 0x1 INT_EVENT0_ICLR_DIO7_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO7_CLR CLR 1 INT_EVENT0_ICLR_DIO8 DIO8 event 0x8 0x1 INT_EVENT0_ICLR_DIO8_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO8_CLR CLR 1 INT_EVENT0_ICLR_DIO9 DIO9 event 0x9 0x1 INT_EVENT0_ICLR_DIO9_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO9_CLR CLR 1 INT_EVENT0_ICLR_DIO10 DIO10 event 0xA 0x1 INT_EVENT0_ICLR_DIO10_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO10_CLR CLR 1 INT_EVENT0_ICLR_DIO11 DIO11 event 0xB 0x1 INT_EVENT0_ICLR_DIO11_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO11_CLR CLR 1 INT_EVENT0_ICLR_DIO12 DIO12 event 0xC 0x1 INT_EVENT0_ICLR_DIO12_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO12_CLR CLR 1 INT_EVENT0_ICLR_DIO13 DIO13 event 0xD 0x1 INT_EVENT0_ICLR_DIO13_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO13_CLR CLR 1 INT_EVENT0_ICLR_DIO14 DIO14 event 0xE 0x1 INT_EVENT0_ICLR_DIO14_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO14_CLR CLR 1 INT_EVENT0_ICLR_DIO15 DIO15 event 0xF 0x1 INT_EVENT0_ICLR_DIO15_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO15_CLR CLR 1 INT_EVENT0_ICLR_DIO16 DIO16 event 0x10 0x1 INT_EVENT0_ICLR_DIO16_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO16_CLR CLR 1 INT_EVENT0_ICLR_DIO17 DIO17 event 0x11 0x1 INT_EVENT0_ICLR_DIO17_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO17_CLR CLR 1 INT_EVENT0_ICLR_DIO18 DIO18 event 0x12 0x1 INT_EVENT0_ICLR_DIO18_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO18_CLR CLR 1 INT_EVENT0_ICLR_DIO19 DIO19 event 0x13 0x1 INT_EVENT0_ICLR_DIO19_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO19_CLR CLR 1 INT_EVENT0_ICLR_DIO20 DIO20 event 0x14 0x1 INT_EVENT0_ICLR_DIO20_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO20_CLR CLR 1 INT_EVENT0_ICLR_DIO21 DIO21 event 0x15 0x1 INT_EVENT0_ICLR_DIO21_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO21_CLR CLR 1 INT_EVENT0_ICLR_DIO22 DIO22 event 0x16 0x1 INT_EVENT0_ICLR_DIO22_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO22_CLR CLR 1 INT_EVENT0_ICLR_DIO23 DIO23 event 0x17 0x1 INT_EVENT0_ICLR_DIO23_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO23_CLR CLR 1 INT_EVENT0_ICLR_DIO24 DIO24 event 0x18 0x1 INT_EVENT0_ICLR_DIO24_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO24_CLR CLR 1 INT_EVENT0_ICLR_DIO25 DIO25 event 0x19 0x1 INT_EVENT0_ICLR_DIO25_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO25_CLR CLR 1 INT_EVENT0_ICLR_DIO26 DIO26 event 0x1A 0x1 INT_EVENT0_ICLR_DIO26_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO26_CLR CLR 1 INT_EVENT0_ICLR_DIO27 DIO27 event 0x1B 0x1 INT_EVENT0_ICLR_DIO27_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO27_CLR CLR 1 INT_EVENT0_ICLR_DIO28 DIO28 event 0x1C 0x1 INT_EVENT0_ICLR_DIO28_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO28_CLR CLR 1 INT_EVENT0_ICLR_DIO29 DIO29 event 0x1D 0x1 INT_EVENT0_ICLR_DIO29_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO29_CLR CLR 1 INT_EVENT0_ICLR_DIO30 DIO30 event 0x1E 0x1 INT_EVENT0_ICLR_DIO30_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO30_CLR CLR 1 INT_EVENT0_ICLR_DIO31 DIO31 event 0x1F 0x1 INT_EVENT0_ICLR_DIO31_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DIO31_CLR CLR 1 INT_EVENT1_IIDX Interrupt index 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_DIO0 DIO0 1 INT_EVENT1_IIDX_STAT_DIO1 DIO1 2 INT_EVENT1_IIDX_STAT_DIO2 DIO2 3 INT_EVENT1_IIDX_STAT_DIO3 DIO3 4 INT_EVENT1_IIDX_STAT_DIO4 DIO4 5 INT_EVENT1_IIDX_STAT_DIO5 DIO5 6 INT_EVENT1_IIDX_STAT_DIO6 DIO6 7 INT_EVENT1_IIDX_STAT_DIO7 DIO7 8 INT_EVENT1_IIDX_STAT_DIO8 DIO8 9 INT_EVENT1_IIDX_STAT_DIO9 DIO9 10 INT_EVENT1_IIDX_STAT_DIO10 DIO10 11 INT_EVENT1_IIDX_STAT_DIO11 DIO11 12 INT_EVENT1_IIDX_STAT_DIO12 DIO12 13 INT_EVENT1_IIDX_STAT_DIO13 DIO13 14 INT_EVENT1_IIDX_STAT_DIO14 DIO14 15 INT_EVENT1_IIDX_STAT_DIO15 DIO15 16 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_DIO0 DIO0 event mask 0x0 0x1 INT_EVENT1_IMASK_DIO0_CLR CLR 0 INT_EVENT1_IMASK_DIO0_SET SET 1 INT_EVENT1_IMASK_DIO1 DIO1 event mask 0x1 0x1 INT_EVENT1_IMASK_DIO1_CLR CLR 0 INT_EVENT1_IMASK_DIO1_SET SET 1 INT_EVENT1_IMASK_DIO2 DIO2 event mask 0x2 0x1 INT_EVENT1_IMASK_DIO2_CLR CLR 0 INT_EVENT1_IMASK_DIO2_SET SET 1 INT_EVENT1_IMASK_DIO3 DIO3 event mask 0x3 0x1 INT_EVENT1_IMASK_DIO3_CLR CLR 0 INT_EVENT1_IMASK_DIO3_SET SET 1 INT_EVENT1_IMASK_DIO4 DIO4 event mask 0x4 0x1 INT_EVENT1_IMASK_DIO4_CLR CLR 0 INT_EVENT1_IMASK_DIO4_SET SET 1 INT_EVENT1_IMASK_DIO5 DIO5 event mask 0x5 0x1 INT_EVENT1_IMASK_DIO5_CLR CLR 0 INT_EVENT1_IMASK_DIO5_SET SET 1 INT_EVENT1_IMASK_DIO6 DIO6 event mask 0x6 0x1 INT_EVENT1_IMASK_DIO6_CLR CLR 0 INT_EVENT1_IMASK_DIO6_SET SET 1 INT_EVENT1_IMASK_DIO7 DIO7 event mask 0x7 0x1 INT_EVENT1_IMASK_DIO7_CLR CLR 0 INT_EVENT1_IMASK_DIO7_SET SET 1 INT_EVENT1_IMASK_DIO8 DIO8 event mask 0x8 0x1 INT_EVENT1_IMASK_DIO8_CLR CLR 0 INT_EVENT1_IMASK_DIO8_SET SET 1 INT_EVENT1_IMASK_DIO9 DIO9 event mask 0x9 0x1 INT_EVENT1_IMASK_DIO9_CLR CLR 0 INT_EVENT1_IMASK_DIO9_SET SET 1 INT_EVENT1_IMASK_DIO10 DIO10 event mask 0xA 0x1 INT_EVENT1_IMASK_DIO10_CLR CLR 0 INT_EVENT1_IMASK_DIO10_SET SET 1 INT_EVENT1_IMASK_DIO11 DIO11 event mask 0xB 0x1 INT_EVENT1_IMASK_DIO11_CLR CLR 0 INT_EVENT1_IMASK_DIO11_SET SET 1 INT_EVENT1_IMASK_DIO12 DIO12 event mask 0xC 0x1 INT_EVENT1_IMASK_DIO12_CLR CLR 0 INT_EVENT1_IMASK_DIO12_SET SET 1 INT_EVENT1_IMASK_DIO13 DIO13 event mask 0xD 0x1 INT_EVENT1_IMASK_DIO13_CLR CLR 0 INT_EVENT1_IMASK_DIO13_SET SET 1 INT_EVENT1_IMASK_DIO14 DIO14 event mask 0xE 0x1 INT_EVENT1_IMASK_DIO14_CLR CLR 0 INT_EVENT1_IMASK_DIO14_SET SET 1 INT_EVENT1_IMASK_DIO15 DIO15 event mask 0xF 0x1 INT_EVENT1_IMASK_DIO15_CLR CLR 0 INT_EVENT1_IMASK_DIO15_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only 0x00000000 INT_EVENT1_RIS_DIO0 DIO0 event 0x0 0x1 INT_EVENT1_RIS_DIO0_CLR CLR 0 INT_EVENT1_RIS_DIO0_SET SET 1 INT_EVENT1_RIS_DIO1 DIO1 event 0x1 0x1 INT_EVENT1_RIS_DIO1_CLR CLR 0 INT_EVENT1_RIS_DIO1_SET SET 1 INT_EVENT1_RIS_DIO2 DIO2 event 0x2 0x1 INT_EVENT1_RIS_DIO2_CLR CLR 0 INT_EVENT1_RIS_DIO2_SET SET 1 INT_EVENT1_RIS_DIO3 DIO3 event 0x3 0x1 INT_EVENT1_RIS_DIO3_CLR CLR 0 INT_EVENT1_RIS_DIO3_SET SET 1 INT_EVENT1_RIS_DIO4 DIO4 event 0x4 0x1 INT_EVENT1_RIS_DIO4_CLR CLR 0 INT_EVENT1_RIS_DIO4_SET SET 1 INT_EVENT1_RIS_DIO5 DIO5 event 0x5 0x1 INT_EVENT1_RIS_DIO5_CLR CLR 0 INT_EVENT1_RIS_DIO5_SET SET 1 INT_EVENT1_RIS_DIO6 DIO6 event 0x6 0x1 INT_EVENT1_RIS_DIO6_CLR CLR 0 INT_EVENT1_RIS_DIO6_SET SET 1 INT_EVENT1_RIS_DIO7 DIO7 event 0x7 0x1 INT_EVENT1_RIS_DIO7_CLR CLR 0 INT_EVENT1_RIS_DIO7_SET SET 1 INT_EVENT1_RIS_DIO8 DIO8 event 0x8 0x1 INT_EVENT1_RIS_DIO8_CLR CLR 0 INT_EVENT1_RIS_DIO8_SET SET 1 INT_EVENT1_RIS_DIO9 DIO9 event 0x9 0x1 INT_EVENT1_RIS_DIO9_CLR CLR 0 INT_EVENT1_RIS_DIO9_SET SET 1 INT_EVENT1_RIS_DIO10 DIO10 event 0xA 0x1 INT_EVENT1_RIS_DIO10_CLR CLR 0 INT_EVENT1_RIS_DIO10_SET SET 1 INT_EVENT1_RIS_DIO11 DIO11 event 0xB 0x1 INT_EVENT1_RIS_DIO11_CLR CLR 0 INT_EVENT1_RIS_DIO11_SET SET 1 INT_EVENT1_RIS_DIO12 DIO12 event 0xC 0x1 INT_EVENT1_RIS_DIO12_CLR CLR 0 INT_EVENT1_RIS_DIO12_SET SET 1 INT_EVENT1_RIS_DIO13 DIO13 event 0xD 0x1 INT_EVENT1_RIS_DIO13_CLR CLR 0 INT_EVENT1_RIS_DIO13_SET SET 1 INT_EVENT1_RIS_DIO14 DIO14 event 0xE 0x1 INT_EVENT1_RIS_DIO14_CLR CLR 0 INT_EVENT1_RIS_DIO14_SET SET 1 INT_EVENT1_RIS_DIO15 DIO15 event 0xF 0x1 INT_EVENT1_RIS_DIO15_CLR CLR 0 INT_EVENT1_RIS_DIO15_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_DIO0 DIO0 event 0x0 0x1 INT_EVENT1_MIS_DIO0_CLR CLR 0 INT_EVENT1_MIS_DIO0_SET SET 1 INT_EVENT1_MIS_DIO1 DIO1 event 0x1 0x1 INT_EVENT1_MIS_DIO1_CLR CLR 0 INT_EVENT1_MIS_DIO1_SET SET 1 INT_EVENT1_MIS_DIO2 DIO2 event 0x2 0x1 INT_EVENT1_MIS_DIO2_CLR CLR 0 INT_EVENT1_MIS_DIO2_SET SET 1 INT_EVENT1_MIS_DIO3 DIO3 event 0x3 0x1 INT_EVENT1_MIS_DIO3_CLR CLR 0 INT_EVENT1_MIS_DIO3_SET SET 1 INT_EVENT1_MIS_DIO4 DIO4 event 0x4 0x1 INT_EVENT1_MIS_DIO4_CLR CLR 0 INT_EVENT1_MIS_DIO4_SET SET 1 INT_EVENT1_MIS_DIO5 DIO5 event 0x5 0x1 INT_EVENT1_MIS_DIO5_CLR CLR 0 INT_EVENT1_MIS_DIO5_SET SET 1 INT_EVENT1_MIS_DIO6 DIO6 event 0x6 0x1 INT_EVENT1_MIS_DIO6_CLR CLR 0 INT_EVENT1_MIS_DIO6_SET SET 1 INT_EVENT1_MIS_DIO7 DIO7 event 0x7 0x1 INT_EVENT1_MIS_DIO7_CLR CLR 0 INT_EVENT1_MIS_DIO7_SET SET 1 INT_EVENT1_MIS_DIO8 DIO8 event 0x8 0x1 INT_EVENT1_MIS_DIO8_CLR CLR 0 INT_EVENT1_MIS_DIO8_SET SET 1 INT_EVENT1_MIS_DIO9 DIO9 event 0x9 0x1 INT_EVENT1_MIS_DIO9_CLR CLR 0 INT_EVENT1_MIS_DIO9_SET SET 1 INT_EVENT1_MIS_DIO10 DIO10 event 0xA 0x1 INT_EVENT1_MIS_DIO10_CLR CLR 0 INT_EVENT1_MIS_DIO10_SET SET 1 INT_EVENT1_MIS_DIO11 DIO11 event 0xB 0x1 INT_EVENT1_MIS_DIO11_CLR CLR 0 INT_EVENT1_MIS_DIO11_SET SET 1 INT_EVENT1_MIS_DIO12 DIO12 event 0xC 0x1 INT_EVENT1_MIS_DIO12_CLR CLR 0 INT_EVENT1_MIS_DIO12_SET SET 1 INT_EVENT1_MIS_DIO13 DIO13 event 0xD 0x1 INT_EVENT1_MIS_DIO13_CLR CLR 0 INT_EVENT1_MIS_DIO13_SET SET 1 INT_EVENT1_MIS_DIO14 DIO14 event 0xE 0x1 INT_EVENT1_MIS_DIO14_CLR CLR 0 INT_EVENT1_MIS_DIO14_SET SET 1 INT_EVENT1_MIS_DIO15 DIO15 event 0xF 0x1 INT_EVENT1_MIS_DIO15_CLR CLR 0 INT_EVENT1_MIS_DIO15_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_DIO0 DIO0 event 0x0 0x1 INT_EVENT1_ISET_DIO0_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO0_SET SET 1 INT_EVENT1_ISET_DIO1 DIO1 event 0x1 0x1 INT_EVENT1_ISET_DIO1_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO1_SET SET 1 INT_EVENT1_ISET_DIO2 DIO2 event 0x2 0x1 INT_EVENT1_ISET_DIO2_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO2_SET SET 1 INT_EVENT1_ISET_DIO3 DIO3 event 0x3 0x1 INT_EVENT1_ISET_DIO3_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO3_SET SET 1 INT_EVENT1_ISET_DIO4 DIO4 event 0x4 0x1 INT_EVENT1_ISET_DIO4_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO4_SET SET 1 INT_EVENT1_ISET_DIO5 DIO5 event 0x5 0x1 INT_EVENT1_ISET_DIO5_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO5_SET SET 1 INT_EVENT1_ISET_DIO6 DIO6 event 0x6 0x1 INT_EVENT1_ISET_DIO6_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO6_SET SET 1 INT_EVENT1_ISET_DIO7 DIO7 event 0x7 0x1 INT_EVENT1_ISET_DIO7_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO7_SET SET 1 INT_EVENT1_ISET_DIO8 DIO8 event 0x8 0x1 INT_EVENT1_ISET_DIO8_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO8_SET SET 1 INT_EVENT1_ISET_DIO9 DIO9 event 0x9 0x1 INT_EVENT1_ISET_DIO9_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO9_SET SET 1 INT_EVENT1_ISET_DIO10 DIO10 event 0xA 0x1 INT_EVENT1_ISET_DIO10_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO10_SET SET 1 INT_EVENT1_ISET_DIO11 DIO11 event 0xB 0x1 INT_EVENT1_ISET_DIO11_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO11_SET SET 1 INT_EVENT1_ISET_DIO12 DIO12 event 0xC 0x1 INT_EVENT1_ISET_DIO12_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO12_SET SET 1 INT_EVENT1_ISET_DIO13 DIO13 event 0xD 0x1 INT_EVENT1_ISET_DIO13_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO13_SET SET 1 INT_EVENT1_ISET_DIO14 DIO14 event 0xE 0x1 INT_EVENT1_ISET_DIO14_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO14_SET SET 1 INT_EVENT1_ISET_DIO15 DIO15 event 0xF 0x1 INT_EVENT1_ISET_DIO15_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_DIO15_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_DIO0 DIO0 event 0x0 0x1 INT_EVENT1_ICLR_DIO0_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO0_CLR CLR 1 INT_EVENT1_ICLR_DIO1 DIO1 event 0x1 0x1 INT_EVENT1_ICLR_DIO1_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO1_CLR CLR 1 INT_EVENT1_ICLR_DIO2 DIO2 event 0x2 0x1 INT_EVENT1_ICLR_DIO2_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO2_CLR CLR 1 INT_EVENT1_ICLR_DIO3 DIO3 event 0x3 0x1 INT_EVENT1_ICLR_DIO3_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO3_CLR CLR 1 INT_EVENT1_ICLR_DIO4 DIO4 event 0x4 0x1 INT_EVENT1_ICLR_DIO4_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO4_CLR CLR 1 INT_EVENT1_ICLR_DIO5 DIO5 event 0x5 0x1 INT_EVENT1_ICLR_DIO5_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO5_CLR CLR 1 INT_EVENT1_ICLR_DIO6 DIO6 event 0x6 0x1 INT_EVENT1_ICLR_DIO6_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO6_CLR CLR 1 INT_EVENT1_ICLR_DIO7 DIO7 event 0x7 0x1 INT_EVENT1_ICLR_DIO7_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO7_CLR CLR 1 INT_EVENT1_ICLR_DIO8 DIO8 event 0x8 0x1 INT_EVENT1_ICLR_DIO8_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO8_CLR CLR 1 INT_EVENT1_ICLR_DIO9 DIO9 event 0x9 0x1 INT_EVENT1_ICLR_DIO9_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO9_CLR CLR 1 INT_EVENT1_ICLR_DIO10 DIO10 event 0xA 0x1 INT_EVENT1_ICLR_DIO10_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO10_CLR CLR 1 INT_EVENT1_ICLR_DIO11 DIO11 event 0xB 0x1 INT_EVENT1_ICLR_DIO11_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO11_CLR CLR 1 INT_EVENT1_ICLR_DIO12 DIO12 event 0xC 0x1 INT_EVENT1_ICLR_DIO12_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO12_CLR CLR 1 INT_EVENT1_ICLR_DIO13 DIO13 event 0xD 0x1 INT_EVENT1_ICLR_DIO13_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO13_CLR CLR 1 INT_EVENT1_ICLR_DIO14 DIO14 event 0xE 0x1 INT_EVENT1_ICLR_DIO14_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO14_CLR CLR 1 INT_EVENT1_ICLR_DIO15 DIO15 event 0xF 0x1 INT_EVENT1_ICLR_DIO15_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_DIO15_CLR CLR 1 INT_EVENT2_IIDX Interrupt index 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT Interrupt index status 0x0 0x8 read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_DIO16 DIO16 1 INT_EVENT2_IIDX_STAT_DIO17 DIO17 2 INT_EVENT2_IIDX_STAT_DIO18 DIO18 3 INT_EVENT2_IIDX_STAT_DIO19 DIO19 4 INT_EVENT2_IIDX_STAT_DIO20 DIO20 5 INT_EVENT2_IIDX_STAT_DIO21 DIO21 6 INT_EVENT2_IIDX_STAT_DIO22 DIO22 7 INT_EVENT2_IIDX_STAT_DIO23 DIO23 8 INT_EVENT2_IIDX_STAT_DIO24 DIO24 9 INT_EVENT2_IIDX_STAT_DIO25 DIO25 10 INT_EVENT2_IIDX_STAT_DIO26 DIO26 11 INT_EVENT2_IIDX_STAT_DIO27 DIO27 12 INT_EVENT2_IIDX_STAT_DIO28 DIO28 13 INT_EVENT2_IIDX_STAT_DIO29 DIO29 14 INT_EVENT2_IIDX_STAT_DIO30 DIO30 15 INT_EVENT2_IIDX_STAT_DIO31 DIO31 16 INT_EVENT2_IMASK Interrupt mask 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_DIO16 DIO16 event mask 0x10 0x1 INT_EVENT2_IMASK_DIO16_CLR CLR 0 INT_EVENT2_IMASK_DIO16_SET SET 1 INT_EVENT2_IMASK_DIO17 DIO17 event mask 0x11 0x1 INT_EVENT2_IMASK_DIO17_CLR CLR 0 INT_EVENT2_IMASK_DIO17_SET SET 1 INT_EVENT2_IMASK_DIO18 DIO18 event mask 0x12 0x1 INT_EVENT2_IMASK_DIO18_CLR CLR 0 INT_EVENT2_IMASK_DIO18_SET SET 1 INT_EVENT2_IMASK_DIO19 DIO19 event mask 0x13 0x1 INT_EVENT2_IMASK_DIO19_CLR CLR 0 INT_EVENT2_IMASK_DIO19_SET SET 1 INT_EVENT2_IMASK_DIO20 DIO20 event mask 0x14 0x1 INT_EVENT2_IMASK_DIO20_CLR CLR 0 INT_EVENT2_IMASK_DIO20_SET SET 1 INT_EVENT2_IMASK_DIO21 DIO21 event mask 0x15 0x1 INT_EVENT2_IMASK_DIO21_CLR CLR 0 INT_EVENT2_IMASK_DIO21_SET SET 1 INT_EVENT2_IMASK_DIO22 DIO22 event mask 0x16 0x1 INT_EVENT2_IMASK_DIO22_CLR CLR 0 INT_EVENT2_IMASK_DIO22_SET SET 1 INT_EVENT2_IMASK_DIO23 DIO23 event mask 0x17 0x1 INT_EVENT2_IMASK_DIO23_CLR CLR 0 INT_EVENT2_IMASK_DIO23_SET SET 1 INT_EVENT2_IMASK_DIO24 DIO24 event mask 0x18 0x1 INT_EVENT2_IMASK_DIO24_CLR CLR 0 INT_EVENT2_IMASK_DIO24_SET SET 1 INT_EVENT2_IMASK_DIO25 DIO25 event mask 0x19 0x1 INT_EVENT2_IMASK_DIO25_CLR CLR 0 INT_EVENT2_IMASK_DIO25_SET SET 1 INT_EVENT2_IMASK_DIO26 DIO26 event mask 0x1A 0x1 INT_EVENT2_IMASK_DIO26_CLR CLR 0 INT_EVENT2_IMASK_DIO26_SET SET 1 INT_EVENT2_IMASK_DIO27 DIO27 event mask 0x1B 0x1 INT_EVENT2_IMASK_DIO27_CLR CLR 0 INT_EVENT2_IMASK_DIO27_SET SET 1 INT_EVENT2_IMASK_DIO28 DIO28 event mask 0x1C 0x1 INT_EVENT2_IMASK_DIO28_CLR CLR 0 INT_EVENT2_IMASK_DIO28_SET SET 1 INT_EVENT2_IMASK_DIO29 DIO29 event mask 0x1D 0x1 INT_EVENT2_IMASK_DIO29_CLR CLR 0 INT_EVENT2_IMASK_DIO29_SET SET 1 INT_EVENT2_IMASK_DIO30 DIO30 event mask 0x1E 0x1 INT_EVENT2_IMASK_DIO30_CLR CLR 0 INT_EVENT2_IMASK_DIO30_SET SET 1 INT_EVENT2_IMASK_DIO31 DIO31 event mask 0x1F 0x1 INT_EVENT2_IMASK_DIO31_CLR CLR 0 INT_EVENT2_IMASK_DIO31_SET SET 1 INT_EVENT2_RIS Raw interrupt status 0x1090 32 read-only 0x00000000 INT_EVENT2_RIS_DIO16 DIO16 event 0x10 0x1 INT_EVENT2_RIS_DIO16_CLR CLR 0 INT_EVENT2_RIS_DIO16_SET SET 1 INT_EVENT2_RIS_DIO17 DIO17 event 0x11 0x1 INT_EVENT2_RIS_DIO17_CLR CLR 0 INT_EVENT2_RIS_DIO17_SET SET 1 INT_EVENT2_RIS_DIO18 DIO18 event 0x12 0x1 INT_EVENT2_RIS_DIO18_CLR CLR 0 INT_EVENT2_RIS_DIO18_SET SET 1 INT_EVENT2_RIS_DIO19 DIO19 event 0x13 0x1 INT_EVENT2_RIS_DIO19_CLR CLR 0 INT_EVENT2_RIS_DIO19_SET SET 1 INT_EVENT2_RIS_DIO20 DIO20 event 0x14 0x1 INT_EVENT2_RIS_DIO20_CLR CLR 0 INT_EVENT2_RIS_DIO20_SET SET 1 INT_EVENT2_RIS_DIO21 DIO21 event 0x15 0x1 INT_EVENT2_RIS_DIO21_CLR CLR 0 INT_EVENT2_RIS_DIO21_SET SET 1 INT_EVENT2_RIS_DIO22 DIO22 event 0x16 0x1 INT_EVENT2_RIS_DIO22_CLR CLR 0 INT_EVENT2_RIS_DIO22_SET SET 1 INT_EVENT2_RIS_DIO23 DIO23 event 0x17 0x1 INT_EVENT2_RIS_DIO23_CLR CLR 0 INT_EVENT2_RIS_DIO23_SET SET 1 INT_EVENT2_RIS_DIO24 DIO24 event 0x18 0x1 INT_EVENT2_RIS_DIO24_CLR CLR 0 INT_EVENT2_RIS_DIO24_SET SET 1 INT_EVENT2_RIS_DIO25 DIO25 event 0x19 0x1 INT_EVENT2_RIS_DIO25_CLR CLR 0 INT_EVENT2_RIS_DIO25_SET SET 1 INT_EVENT2_RIS_DIO26 DIO26 event 0x1A 0x1 INT_EVENT2_RIS_DIO26_CLR CLR 0 INT_EVENT2_RIS_DIO26_SET SET 1 INT_EVENT2_RIS_DIO27 DIO27 event 0x1B 0x1 INT_EVENT2_RIS_DIO27_CLR CLR 0 INT_EVENT2_RIS_DIO27_SET SET 1 INT_EVENT2_RIS_DIO28 DIO28 event 0x1C 0x1 INT_EVENT2_RIS_DIO28_CLR CLR 0 INT_EVENT2_RIS_DIO28_SET SET 1 INT_EVENT2_RIS_DIO29 DIO29 event 0x1D 0x1 INT_EVENT2_RIS_DIO29_CLR CLR 0 INT_EVENT2_RIS_DIO29_SET SET 1 INT_EVENT2_RIS_DIO30 DIO30 event 0x1E 0x1 INT_EVENT2_RIS_DIO30_CLR CLR 0 INT_EVENT2_RIS_DIO30_SET SET 1 INT_EVENT2_RIS_DIO31 DIO31 event 0x1F 0x1 INT_EVENT2_RIS_DIO31_CLR CLR 0 INT_EVENT2_RIS_DIO31_SET SET 1 INT_EVENT2_MIS Masked interrupt status 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_DIO16 DIO16 event 0x10 0x1 INT_EVENT2_MIS_DIO16_CLR CLR 0 INT_EVENT2_MIS_DIO16_SET SET 1 INT_EVENT2_MIS_DIO17 DIO17 event 0x11 0x1 INT_EVENT2_MIS_DIO17_CLR CLR 0 INT_EVENT2_MIS_DIO17_SET SET 1 INT_EVENT2_MIS_DIO18 DIO18 event 0x12 0x1 INT_EVENT2_MIS_DIO18_CLR CLR 0 INT_EVENT2_MIS_DIO18_SET SET 1 INT_EVENT2_MIS_DIO19 DIO19 event 0x13 0x1 INT_EVENT2_MIS_DIO19_CLR CLR 0 INT_EVENT2_MIS_DIO19_SET SET 1 INT_EVENT2_MIS_DIO20 DIO20 event 0x14 0x1 INT_EVENT2_MIS_DIO20_CLR CLR 0 INT_EVENT2_MIS_DIO20_SET SET 1 INT_EVENT2_MIS_DIO21 DIO21 event 0x15 0x1 INT_EVENT2_MIS_DIO21_CLR CLR 0 INT_EVENT2_MIS_DIO21_SET SET 1 INT_EVENT2_MIS_DIO22 DIO22 event 0x16 0x1 INT_EVENT2_MIS_DIO22_CLR CLR 0 INT_EVENT2_MIS_DIO22_SET SET 1 INT_EVENT2_MIS_DIO23 DIO23 event 0x17 0x1 INT_EVENT2_MIS_DIO23_CLR CLR 0 INT_EVENT2_MIS_DIO23_SET SET 1 INT_EVENT2_MIS_DIO24 DIO24 event 0x18 0x1 INT_EVENT2_MIS_DIO24_CLR CLR 0 INT_EVENT2_MIS_DIO24_SET SET 1 INT_EVENT2_MIS_DIO25 DIO25 event 0x19 0x1 INT_EVENT2_MIS_DIO25_CLR CLR 0 INT_EVENT2_MIS_DIO25_SET SET 1 INT_EVENT2_MIS_DIO26 DIO26 event 0x1A 0x1 INT_EVENT2_MIS_DIO26_CLR CLR 0 INT_EVENT2_MIS_DIO26_SET SET 1 INT_EVENT2_MIS_DIO27 DIO27 event 0x1B 0x1 INT_EVENT2_MIS_DIO27_CLR CLR 0 INT_EVENT2_MIS_DIO27_SET SET 1 INT_EVENT2_MIS_DIO28 DIO28 event 0x1C 0x1 INT_EVENT2_MIS_DIO28_CLR CLR 0 INT_EVENT2_MIS_DIO28_SET SET 1 INT_EVENT2_MIS_DIO29 DIO29 event 0x1D 0x1 INT_EVENT2_MIS_DIO29_CLR CLR 0 INT_EVENT2_MIS_DIO29_SET SET 1 INT_EVENT2_MIS_DIO30 DIO30 event 0x1E 0x1 INT_EVENT2_MIS_DIO30_CLR CLR 0 INT_EVENT2_MIS_DIO30_SET SET 1 INT_EVENT2_MIS_DIO31 DIO31 event 0x1F 0x1 INT_EVENT2_MIS_DIO31_CLR CLR 0 INT_EVENT2_MIS_DIO31_SET SET 1 INT_EVENT2_ISET Interrupt set 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_DIO16 DIO16 event 0x10 0x1 INT_EVENT2_ISET_DIO16_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO16_SET SET 1 INT_EVENT2_ISET_DIO17 DIO17 event 0x11 0x1 INT_EVENT2_ISET_DIO17_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO17_SET SET 1 INT_EVENT2_ISET_DIO18 DIO18 event 0x12 0x1 INT_EVENT2_ISET_DIO18_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO18_SET SET 1 INT_EVENT2_ISET_DIO19 DIO19 event 0x13 0x1 INT_EVENT2_ISET_DIO19_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO19_SET SET 1 INT_EVENT2_ISET_DIO20 DIO20 event 0x14 0x1 INT_EVENT2_ISET_DIO20_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO20_SET SET 1 INT_EVENT2_ISET_DIO21 DIO21 event 0x15 0x1 INT_EVENT2_ISET_DIO21_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO21_SET SET 1 INT_EVENT2_ISET_DIO22 DIO22 event 0x16 0x1 INT_EVENT2_ISET_DIO22_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO22_SET SET 1 INT_EVENT2_ISET_DIO23 DIO23 event 0x17 0x1 INT_EVENT2_ISET_DIO23_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO23_SET SET 1 INT_EVENT2_ISET_DIO24 DIO24 event 0x18 0x1 INT_EVENT2_ISET_DIO24_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO24_SET SET 1 INT_EVENT2_ISET_DIO25 DIO25 event 0x19 0x1 INT_EVENT2_ISET_DIO25_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO25_SET SET 1 INT_EVENT2_ISET_DIO26 DIO26 event 0x1A 0x1 INT_EVENT2_ISET_DIO26_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO26_SET SET 1 INT_EVENT2_ISET_DIO27 DIO27 event 0x1B 0x1 INT_EVENT2_ISET_DIO27_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO27_SET SET 1 INT_EVENT2_ISET_DIO28 DIO28 event 0x1C 0x1 INT_EVENT2_ISET_DIO28_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO28_SET SET 1 INT_EVENT2_ISET_DIO29 DIO29 event 0x1D 0x1 INT_EVENT2_ISET_DIO29_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO29_SET SET 1 INT_EVENT2_ISET_DIO30 DIO30 event 0x1E 0x1 INT_EVENT2_ISET_DIO30_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO30_SET SET 1 INT_EVENT2_ISET_DIO31 DIO31 event 0x1F 0x1 INT_EVENT2_ISET_DIO31_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_DIO31_SET SET 1 INT_EVENT2_ICLR Interrupt clear 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_DIO16 DIO16 event 0x10 0x1 INT_EVENT2_ICLR_DIO16_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO16_CLR CLR 1 INT_EVENT2_ICLR_DIO17 DIO17 event 0x11 0x1 INT_EVENT2_ICLR_DIO17_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO17_CLR CLR 1 INT_EVENT2_ICLR_DIO18 DIO18 event 0x12 0x1 INT_EVENT2_ICLR_DIO18_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO18_CLR CLR 1 INT_EVENT2_ICLR_DIO19 DIO19 event 0x13 0x1 INT_EVENT2_ICLR_DIO19_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO19_CLR CLR 1 INT_EVENT2_ICLR_DIO20 DIO20 event 0x14 0x1 INT_EVENT2_ICLR_DIO20_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO20_CLR CLR 1 INT_EVENT2_ICLR_DIO21 DIO21 event 0x15 0x1 INT_EVENT2_ICLR_DIO21_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO21_CLR CLR 1 INT_EVENT2_ICLR_DIO22 DIO22 event 0x16 0x1 INT_EVENT2_ICLR_DIO22_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO22_CLR CLR 1 INT_EVENT2_ICLR_DIO23 DIO23 event 0x17 0x1 INT_EVENT2_ICLR_DIO23_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO23_CLR CLR 1 INT_EVENT2_ICLR_DIO24 DIO24 event 0x18 0x1 INT_EVENT2_ICLR_DIO24_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO24_CLR CLR 1 INT_EVENT2_ICLR_DIO25 DIO25 event 0x19 0x1 INT_EVENT2_ICLR_DIO25_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO25_CLR CLR 1 INT_EVENT2_ICLR_DIO26 DIO26 event 0x1A 0x1 INT_EVENT2_ICLR_DIO26_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO26_CLR CLR 1 INT_EVENT2_ICLR_DIO27 DIO27 event 0x1B 0x1 INT_EVENT2_ICLR_DIO27_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO27_CLR CLR 1 INT_EVENT2_ICLR_DIO28 DIO28 event 0x1C 0x1 INT_EVENT2_ICLR_DIO28_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO28_CLR CLR 1 INT_EVENT2_ICLR_DIO29 DIO29 event 0x1D 0x1 INT_EVENT2_ICLR_DIO29_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO29_CLR CLR 1 INT_EVENT2_ICLR_DIO30 DIO30 event 0x1E 0x1 INT_EVENT2_ICLR_DIO30_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO30_CLR CLR 1 INT_EVENT2_ICLR_DIO31 DIO31 event 0x1F 0x1 INT_EVENT2_ICLR_DIO31_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_DIO31_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 DOUT3_0 Data output 3 to 0 0x1200 32 write-only 0x00000000 DOUT3_0_DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT3_0_DIO0_ZERO ZERO 0 DOUT3_0_DIO0_ONE ONE 1 DOUT3_0_DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT3_0_DIO1_ZERO ZERO 0 DOUT3_0_DIO1_ONE ONE 1 DOUT3_0_DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT3_0_DIO2_ZERO ZERO 0 DOUT3_0_DIO2_ONE ONE 1 DOUT3_0_DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT3_0_DIO3_ZERO ZERO 0 DOUT3_0_DIO3_ONE ONE 1 DOUT7_4 Data output 7 to 4 0x1204 32 write-only 0x00000000 DOUT7_4_DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT7_4_DIO4_ZERO ZERO 0 DOUT7_4_DIO4_ONE ONE 1 DOUT7_4_DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT7_4_DIO5_ZERO ZERO 0 DOUT7_4_DIO5_ONE ONE 1 DOUT7_4_DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT7_4_DIO6_ZERO ZERO 0 DOUT7_4_DIO6_ONE ONE 1 DOUT7_4_DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT7_4_DIO7_ZERO ZERO 0 DOUT7_4_DIO7_ONE ONE 1 DOUT11_8 Data output 11 to 8 0x1208 32 write-only 0x00000000 DOUT11_8_DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT11_8_DIO8_ZERO ZERO 0 DOUT11_8_DIO8_ONE ONE 1 DOUT11_8_DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT11_8_DIO9_ZERO ZERO 0 DOUT11_8_DIO9_ONE ONE 1 DOUT11_8_DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT11_8_DIO10_ZERO ZERO 0 DOUT11_8_DIO10_ONE ONE 1 DOUT11_8_DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT11_8_DIO11_ZERO ZERO 0 DOUT11_8_DIO11_ONE ONE 1 DOUT15_12 Data output 15 to 12 0x120C 32 write-only 0x00000000 DOUT15_12_DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT15_12_DIO12_ZERO ZERO 0 DOUT15_12_DIO12_ONE ONE 1 DOUT15_12_DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT15_12_DIO13_ZERO ZERO 0 DOUT15_12_DIO13_ONE ONE 1 DOUT15_12_DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT15_12_DIO14_ZERO ZERO 0 DOUT15_12_DIO14_ONE ONE 1 DOUT15_12_DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT15_12_DIO15_ZERO ZERO 0 DOUT15_12_DIO15_ONE ONE 1 DOUT19_16 Data output 19 to 16 0x1210 32 write-only 0x00000000 DOUT19_16_DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT19_16_DIO16_ZERO ZERO 0 DOUT19_16_DIO16_ONE ONE 1 DOUT19_16_DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT19_16_DIO17_ZERO ZERO 0 DOUT19_16_DIO17_ONE ONE 1 DOUT19_16_DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT19_16_DIO18_ZERO ZERO 0 DOUT19_16_DIO18_ONE ONE 1 DOUT19_16_DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT19_16_DIO19_ZERO ZERO 0 DOUT19_16_DIO19_ONE ONE 1 DOUT23_20 Data output 23 to 20 0x1214 32 write-only 0x00000000 DOUT23_20_DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT23_20_DIO20_ZERO ZERO 0 DOUT23_20_DIO20_ONE ONE 1 DOUT23_20_DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT23_20_DIO21_ZERO ZERO 0 DOUT23_20_DIO21_ONE ONE 1 DOUT23_20_DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT23_20_DIO22_ZERO ZERO 0 DOUT23_20_DIO22_ONE ONE 1 DOUT23_20_DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT23_20_DIO23_ZERO ZERO 0 DOUT23_20_DIO23_ONE ONE 1 DOUT27_24 Data output 27 to 24 0x1218 32 write-only 0x00000000 DOUT27_24_DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT27_24_DIO24_ZERO ZERO 0 DOUT27_24_DIO24_ONE ONE 1 DOUT27_24_DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT27_24_DIO25_ZERO ZERO 0 DOUT27_24_DIO25_ONE ONE 1 DOUT27_24_DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT27_24_DIO26_ZERO ZERO 0 DOUT27_24_DIO26_ONE ONE 1 DOUT27_24_DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT27_24_DIO27_ZERO ZERO 0 DOUT27_24_DIO27_ONE ONE 1 DOUT31_28 Data output 31 to 28 0x121C 32 write-only 0x00000000 DOUT31_28_DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x0 0x1 write-only DOUT31_28_DIO28_ZERO ZERO 0 DOUT31_28_DIO28_ONE ONE 1 DOUT31_28_DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x8 0x1 write-only DOUT31_28_DIO29_ZERO ZERO 0 DOUT31_28_DIO29_ONE ONE 1 DOUT31_28_DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x10 0x1 write-only DOUT31_28_DIO30_ZERO ZERO 0 DOUT31_28_DIO30_ONE ONE 1 DOUT31_28_DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x18 0x1 write-only DOUT31_28_DIO31_ZERO ZERO 0 DOUT31_28_DIO31_ONE ONE 1 DOUT31_0 Data output 31 to 0 0x1280 32 read-write 0x00000000 DOUT31_0_DIO0 This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register. 0x0 0x1 read-write DOUT31_0_DIO0_ZERO ZERO 0 DOUT31_0_DIO0_ONE ONE 1 DOUT31_0_DIO1 This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register. 0x1 0x1 read-write DOUT31_0_DIO1_ZERO ZERO 0 DOUT31_0_DIO1_ONE ONE 1 DOUT31_0_DIO2 This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register. 0x2 0x1 read-write DOUT31_0_DIO2_ZERO ZERO 0 DOUT31_0_DIO2_ONE ONE 1 DOUT31_0_DIO3 This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register. 0x3 0x1 read-write DOUT31_0_DIO3_ZERO ZERO 0 DOUT31_0_DIO3_ONE ONE 1 DOUT31_0_DIO4 This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register. 0x4 0x1 read-write DOUT31_0_DIO4_ZERO ZERO 0 DOUT31_0_DIO4_ONE ONE 1 DOUT31_0_DIO5 This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register. 0x5 0x1 read-write DOUT31_0_DIO5_ZERO ZERO 0 DOUT31_0_DIO5_ONE ONE 1 DOUT31_0_DIO6 This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register. 0x6 0x1 read-write DOUT31_0_DIO6_ZERO ZERO 0 DOUT31_0_DIO6_ONE ONE 1 DOUT31_0_DIO7 This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register. 0x7 0x1 read-write DOUT31_0_DIO7_ZERO ZERO 0 DOUT31_0_DIO7_ONE ONE 1 DOUT31_0_DIO8 This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register. 0x8 0x1 read-write DOUT31_0_DIO8_ZERO ZERO 0 DOUT31_0_DIO8_ONE ONE 1 DOUT31_0_DIO9 This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register. 0x9 0x1 read-write DOUT31_0_DIO9_ZERO ZERO 0 DOUT31_0_DIO9_ONE ONE 1 DOUT31_0_DIO10 This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register. 0xA 0x1 read-write DOUT31_0_DIO10_ZERO ZERO 0 DOUT31_0_DIO10_ONE ONE 1 DOUT31_0_DIO11 This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register. 0xB 0x1 read-write DOUT31_0_DIO11_ZERO ZERO 0 DOUT31_0_DIO11_ONE ONE 1 DOUT31_0_DIO12 This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register. 0xC 0x1 read-write DOUT31_0_DIO12_ZERO ZERO 0 DOUT31_0_DIO12_ONE ONE 1 DOUT31_0_DIO13 This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register. 0xD 0x1 read-write DOUT31_0_DIO13_ZERO ZERO 0 DOUT31_0_DIO13_ONE ONE 1 DOUT31_0_DIO14 This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register. 0xE 0x1 read-write DOUT31_0_DIO14_ZERO ZERO 0 DOUT31_0_DIO14_ONE ONE 1 DOUT31_0_DIO15 This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register. 0xF 0x1 read-write DOUT31_0_DIO15_ZERO ZERO 0 DOUT31_0_DIO15_ONE ONE 1 DOUT31_0_DIO16 This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register. 0x10 0x1 read-write DOUT31_0_DIO16_ZERO ZERO 0 DOUT31_0_DIO16_ONE ONE 1 DOUT31_0_DIO17 This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register. 0x11 0x1 read-write DOUT31_0_DIO17_ZERO ZERO 0 DOUT31_0_DIO17_ONE ONE 1 DOUT31_0_DIO18 This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register. 0x12 0x1 read-write DOUT31_0_DIO18_ZERO ZERO 0 DOUT31_0_DIO18_ONE ONE 1 DOUT31_0_DIO19 This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register. 0x13 0x1 read-write DOUT31_0_DIO19_ZERO ZERO 0 DOUT31_0_DIO19_ONE ONE 1 DOUT31_0_DIO20 This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register. 0x14 0x1 read-write DOUT31_0_DIO20_ZERO ZERO 0 DOUT31_0_DIO20_ONE ONE 1 DOUT31_0_DIO21 This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register. 0x15 0x1 read-write DOUT31_0_DIO21_ZERO ZERO 0 DOUT31_0_DIO21_ONE ONE 1 DOUT31_0_DIO22 This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register. 0x16 0x1 read-write DOUT31_0_DIO22_ZERO ZERO 0 DOUT31_0_DIO22_ONE ONE 1 DOUT31_0_DIO23 This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register. 0x17 0x1 read-write DOUT31_0_DIO23_ZERO ZERO 0 DOUT31_0_DIO23_ONE ONE 1 DOUT31_0_DIO24 This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register. 0x18 0x1 read-write DOUT31_0_DIO24_ZERO ZERO 0 DOUT31_0_DIO24_ONE ONE 1 DOUT31_0_DIO25 This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register. 0x19 0x1 read-write DOUT31_0_DIO25_ZERO ZERO 0 DOUT31_0_DIO25_ONE ONE 1 DOUT31_0_DIO26 This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register. 0x1A 0x1 read-write DOUT31_0_DIO26_ZERO ZERO 0 DOUT31_0_DIO26_ONE ONE 1 DOUT31_0_DIO27 This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register. 0x1B 0x1 read-write DOUT31_0_DIO27_ZERO ZERO 0 DOUT31_0_DIO27_ONE ONE 1 DOUT31_0_DIO28 This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register. 0x1C 0x1 read-write DOUT31_0_DIO28_ZERO ZERO 0 DOUT31_0_DIO28_ONE ONE 1 DOUT31_0_DIO29 This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register. 0x1D 0x1 read-write DOUT31_0_DIO29_ZERO ZERO 0 DOUT31_0_DIO29_ONE ONE 1 DOUT31_0_DIO30 This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register. 0x1E 0x1 read-write DOUT31_0_DIO30_ZERO ZERO 0 DOUT31_0_DIO30_ONE ONE 1 DOUT31_0_DIO31 This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register. 0x1F 0x1 read-write DOUT31_0_DIO31_ZERO ZERO 0 DOUT31_0_DIO31_ONE ONE 1 DOUTSET31_0 Data output set 31 to 0 0x1290 32 write-only 0x00000000 DOUTSET31_0_DIO0 Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only DOUTSET31_0_DIO0_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO0_SET SET 1 DOUTSET31_0_DIO1 Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only DOUTSET31_0_DIO1_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO1_SET SET 1 DOUTSET31_0_DIO2 Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only DOUTSET31_0_DIO2_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO2_SET SET 1 DOUTSET31_0_DIO3 Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only DOUTSET31_0_DIO3_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO3_SET SET 1 DOUTSET31_0_DIO4 Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only DOUTSET31_0_DIO4_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO4_SET SET 1 DOUTSET31_0_DIO5 Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only DOUTSET31_0_DIO5_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO5_SET SET 1 DOUTSET31_0_DIO6 Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only DOUTSET31_0_DIO6_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO6_SET SET 1 DOUTSET31_0_DIO7 Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only DOUTSET31_0_DIO7_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO7_SET SET 1 DOUTSET31_0_DIO8 Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only DOUTSET31_0_DIO8_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO8_SET SET 1 DOUTSET31_0_DIO9 Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only DOUTSET31_0_DIO9_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO9_SET SET 1 DOUTSET31_0_DIO10 Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only DOUTSET31_0_DIO10_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO10_SET SET 1 DOUTSET31_0_DIO11 Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only DOUTSET31_0_DIO11_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO11_SET SET 1 DOUTSET31_0_DIO12 Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only DOUTSET31_0_DIO12_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO12_SET SET 1 DOUTSET31_0_DIO13 Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only DOUTSET31_0_DIO13_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO13_SET SET 1 DOUTSET31_0_DIO14 Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only DOUTSET31_0_DIO14_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO14_SET SET 1 DOUTSET31_0_DIO15 Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only DOUTSET31_0_DIO15_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO15_SET SET 1 DOUTSET31_0_DIO16 Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only DOUTSET31_0_DIO16_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO16_SET SET 1 DOUTSET31_0_DIO17 Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only DOUTSET31_0_DIO17_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO17_SET SET 1 DOUTSET31_0_DIO18 Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only DOUTSET31_0_DIO18_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO18_SET SET 1 DOUTSET31_0_DIO19 Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only DOUTSET31_0_DIO19_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO19_SET SET 1 DOUTSET31_0_DIO20 Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only DOUTSET31_0_DIO20_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO20_SET SET 1 DOUTSET31_0_DIO21 Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only DOUTSET31_0_DIO21_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO21_SET SET 1 DOUTSET31_0_DIO22 Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only DOUTSET31_0_DIO22_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO22_SET SET 1 DOUTSET31_0_DIO23 Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only DOUTSET31_0_DIO23_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO23_SET SET 1 DOUTSET31_0_DIO24 Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only DOUTSET31_0_DIO24_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO24_SET SET 1 DOUTSET31_0_DIO25 Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only DOUTSET31_0_DIO25_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO25_SET SET 1 DOUTSET31_0_DIO26 Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only DOUTSET31_0_DIO26_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO26_SET SET 1 DOUTSET31_0_DIO27 Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only DOUTSET31_0_DIO27_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO27_SET SET 1 DOUTSET31_0_DIO28 Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only DOUTSET31_0_DIO28_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO28_SET SET 1 DOUTSET31_0_DIO29 Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only DOUTSET31_0_DIO29_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO29_SET SET 1 DOUTSET31_0_DIO30 Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only DOUTSET31_0_DIO30_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO30_SET SET 1 DOUTSET31_0_DIO31 Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only DOUTSET31_0_DIO31_NO_EFFECT NO_EFFECT 0 DOUTSET31_0_DIO31_SET SET 1 DOUTCLR31_0 Data output clear 31 to 0 0x12A0 32 write-only 0x00000000 DOUTCLR31_0_DIO0 Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect. 0x0 0x1 write-only DOUTCLR31_0_DIO0_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO0_CLR CLR 1 DOUTCLR31_0_DIO1 Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1 0x1 write-only DOUTCLR31_0_DIO1_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO1_CLR CLR 1 DOUTCLR31_0_DIO2 Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect. 0x2 0x1 write-only DOUTCLR31_0_DIO2_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO2_CLR CLR 1 DOUTCLR31_0_DIO3 Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect. 0x3 0x1 write-only DOUTCLR31_0_DIO3_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO3_CLR CLR 1 DOUTCLR31_0_DIO4 Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect. 0x4 0x1 write-only DOUTCLR31_0_DIO4_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO4_CLR CLR 1 DOUTCLR31_0_DIO5 Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect. 0x5 0x1 write-only DOUTCLR31_0_DIO5_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO5_CLR CLR 1 DOUTCLR31_0_DIO6 Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect. 0x6 0x1 write-only DOUTCLR31_0_DIO6_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO6_CLR CLR 1 DOUTCLR31_0_DIO7 Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect. 0x7 0x1 write-only DOUTCLR31_0_DIO7_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO7_CLR CLR 1 DOUTCLR31_0_DIO8 Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect. 0x8 0x1 write-only DOUTCLR31_0_DIO8_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO8_CLR CLR 1 DOUTCLR31_0_DIO9 Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect. 0x9 0x1 write-only DOUTCLR31_0_DIO9_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO9_CLR CLR 1 DOUTCLR31_0_DIO10 Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect. 0xA 0x1 write-only DOUTCLR31_0_DIO10_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO10_CLR CLR 1 DOUTCLR31_0_DIO11 Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect. 0xB 0x1 write-only DOUTCLR31_0_DIO11_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO11_CLR CLR 1 DOUTCLR31_0_DIO12 Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect. 0xC 0x1 write-only DOUTCLR31_0_DIO12_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO12_CLR CLR 1 DOUTCLR31_0_DIO13 Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect. 0xD 0x1 write-only DOUTCLR31_0_DIO13_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO13_CLR CLR 1 DOUTCLR31_0_DIO14 Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect. 0xE 0x1 write-only DOUTCLR31_0_DIO14_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO14_CLR CLR 1 DOUTCLR31_0_DIO15 Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect. 0xF 0x1 write-only DOUTCLR31_0_DIO15_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO15_CLR CLR 1 DOUTCLR31_0_DIO16 Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect. 0x10 0x1 write-only DOUTCLR31_0_DIO16_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO16_CLR CLR 1 DOUTCLR31_0_DIO17 Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect. 0x11 0x1 write-only DOUTCLR31_0_DIO17_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO17_CLR CLR 1 DOUTCLR31_0_DIO18 Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect. 0x12 0x1 write-only DOUTCLR31_0_DIO18_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO18_CLR CLR 1 DOUTCLR31_0_DIO19 Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect. 0x13 0x1 write-only DOUTCLR31_0_DIO19_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO19_CLR CLR 1 DOUTCLR31_0_DIO20 Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect. 0x14 0x1 write-only DOUTCLR31_0_DIO20_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO20_CLR CLR 1 DOUTCLR31_0_DIO21 Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect. 0x15 0x1 write-only DOUTCLR31_0_DIO21_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO21_CLR CLR 1 DOUTCLR31_0_DIO22 Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect. 0x16 0x1 write-only DOUTCLR31_0_DIO22_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO22_CLR CLR 1 DOUTCLR31_0_DIO23 Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect. 0x17 0x1 write-only DOUTCLR31_0_DIO23_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO23_CLR CLR 1 DOUTCLR31_0_DIO24 Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect. 0x18 0x1 write-only DOUTCLR31_0_DIO24_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO24_CLR CLR 1 DOUTCLR31_0_DIO25 Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect. 0x19 0x1 write-only DOUTCLR31_0_DIO25_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO25_CLR CLR 1 DOUTCLR31_0_DIO26 Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only DOUTCLR31_0_DIO26_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO26_CLR CLR 1 DOUTCLR31_0_DIO27 Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only DOUTCLR31_0_DIO27_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO27_CLR CLR 1 DOUTCLR31_0_DIO28 Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only DOUTCLR31_0_DIO28_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO28_CLR CLR 1 DOUTCLR31_0_DIO29 Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only DOUTCLR31_0_DIO29_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO29_CLR CLR 1 DOUTCLR31_0_DIO30 Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only DOUTCLR31_0_DIO30_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO30_CLR CLR 1 DOUTCLR31_0_DIO31 Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only DOUTCLR31_0_DIO31_NO_EFFECT NO_EFFECT 0 DOUTCLR31_0_DIO31_CLR CLR 1 DOUTTGL31_0 Data output toggle 31 to 0 0x12B0 32 write-only 0x00000000 DOUTTGL31_0_DIO0 This bit is used to toggle DIO0 output. 0x0 0x1 write-only DOUTTGL31_0_DIO0_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO0_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO1 This bit is used to toggle DIO1 output. 0x1 0x1 write-only DOUTTGL31_0_DIO1_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO1_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO2 This bit is used to toggle DIO2 output. 0x2 0x1 write-only DOUTTGL31_0_DIO2_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO2_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO3 This bit is used to toggle DIO3 output. 0x3 0x1 write-only DOUTTGL31_0_DIO3_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO3_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO4 This bit is used to toggle DIO4 output. 0x4 0x1 write-only DOUTTGL31_0_DIO4_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO4_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO5 This bit is used to toggle DIO5 output. 0x5 0x1 write-only DOUTTGL31_0_DIO5_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO5_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO6 This bit is used to toggle DIO6 output. 0x6 0x1 write-only DOUTTGL31_0_DIO6_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO6_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO7 This bit is used to toggle DIO7 output. 0x7 0x1 write-only DOUTTGL31_0_DIO7_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO7_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO8 This bit is used to toggle DIO8 output. 0x8 0x1 write-only DOUTTGL31_0_DIO8_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO8_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO9 This bit is used to toggle DIO9 output. 0x9 0x1 write-only DOUTTGL31_0_DIO9_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO9_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO10 This bit is used to toggle DIO10 output. 0xA 0x1 write-only DOUTTGL31_0_DIO10_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO10_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO11 This bit is used to toggle DIO11 output. 0xB 0x1 write-only DOUTTGL31_0_DIO11_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO11_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO12 This bit is used to toggle DIO12 output. 0xC 0x1 write-only DOUTTGL31_0_DIO12_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO12_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO13 This bit is used to toggle DIO13 output. 0xD 0x1 write-only DOUTTGL31_0_DIO13_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO13_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO14 This bit is used to toggle DIO14 output. 0xE 0x1 write-only DOUTTGL31_0_DIO14_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO14_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO15 This bit is used to toggle DIO15 output. 0xF 0x1 write-only DOUTTGL31_0_DIO15_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO15_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO16 This bit is used to toggle DIO16 output. 0x10 0x1 write-only DOUTTGL31_0_DIO16_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO16_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO17 This bit is used to toggle DIO17 output. 0x11 0x1 write-only DOUTTGL31_0_DIO17_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO17_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO18 This bit is used to toggle DIO18 output. 0x12 0x1 write-only DOUTTGL31_0_DIO18_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO18_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO19 This bit is used to toggle DIO19 output. 0x13 0x1 write-only DOUTTGL31_0_DIO19_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO19_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO20 This bit is used to toggle DIO20 output. 0x14 0x1 write-only DOUTTGL31_0_DIO20_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO20_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO21 This bit is used to toggle DIO21 output. 0x15 0x1 write-only DOUTTGL31_0_DIO21_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO21_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO22 This bit is used to toggle DIO22 output. 0x16 0x1 write-only DOUTTGL31_0_DIO22_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO22_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO23 This bit is used to toggle DIO23 output. 0x17 0x1 write-only DOUTTGL31_0_DIO23_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO23_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO24 This bit is used to toggle DIO24 output. 0x18 0x1 write-only DOUTTGL31_0_DIO24_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO24_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO25 This bit is used to toggle DIO25 output. 0x19 0x1 write-only DOUTTGL31_0_DIO25_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO25_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO26 This bit is used to toggle DIO26 output. 0x1A 0x1 write-only DOUTTGL31_0_DIO26_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO26_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO27 This bit is used to toggle DIO27 output. 0x1B 0x1 write-only DOUTTGL31_0_DIO27_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO27_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO28 This bit is used to toggle DIO28 output. 0x1C 0x1 write-only DOUTTGL31_0_DIO28_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO28_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO29 This bit is used to toggle DIO29 output. 0x1D 0x1 write-only DOUTTGL31_0_DIO29_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO29_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO30 This bit is used to toggle DIO30 output. 0x1E 0x1 write-only DOUTTGL31_0_DIO30_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO30_TOGGLE TOGGLE 1 DOUTTGL31_0_DIO31 This bit is used to toggle DIO31 output. 0x1F 0x1 write-only DOUTTGL31_0_DIO31_NO_EFFECT NO_EFFECT 0 DOUTTGL31_0_DIO31_TOGGLE TOGGLE 1 DOE31_0 Data output enable 31 to 0 0x12C0 32 read-write 0x00000000 DOE31_0_DIO0 Enables data output for DIO0. 0x0 0x1 read-write DOE31_0_DIO0_DISABLE DISABLE 0 DOE31_0_DIO0_ENABLE ENABLE 1 DOE31_0_DIO1 Enables data output for DIO1. 0x1 0x1 read-write DOE31_0_DIO1_DISABLE DISABLE 0 DOE31_0_DIO1_ENABLE ENABLE 1 DOE31_0_DIO2 Enables data output for DIO2. 0x2 0x1 read-write DOE31_0_DIO2_DISABLE DISABLE 0 DOE31_0_DIO2_ENABLE ENABLE 1 DOE31_0_DIO3 Enables data output for DIO3. 0x3 0x1 read-write DOE31_0_DIO3_DISABLE DISABLE 0 DOE31_0_DIO3_ENABLE ENABLE 1 DOE31_0_DIO4 Enables data output for DIO4. 0x4 0x1 read-write DOE31_0_DIO4_DISABLE DISABLE 0 DOE31_0_DIO4_ENABLE ENABLE 1 DOE31_0_DIO5 Enables data output for DIO5. 0x5 0x1 read-write DOE31_0_DIO5_DISABLE DISABLE 0 DOE31_0_DIO5_ENABLE ENABLE 1 DOE31_0_DIO6 Enables data output for DIO6. 0x6 0x1 read-write DOE31_0_DIO6_DISABLE DISABLE 0 DOE31_0_DIO6_ENABLE ENABLE 1 DOE31_0_DIO7 Enables data output for DIO7. 0x7 0x1 read-write DOE31_0_DIO7_DISABLE DISABLE 0 DOE31_0_DIO7_ENABLE ENABLE 1 DOE31_0_DIO8 Enables data output for DIO8. 0x8 0x1 read-write DOE31_0_DIO8_DISABLE DISABLE 0 DOE31_0_DIO8_ENABLE ENABLE 1 DOE31_0_DIO9 Enables data output for DIO9. 0x9 0x1 read-write DOE31_0_DIO9_DISABLE DISABLE 0 DOE31_0_DIO9_ENABLE ENABLE 1 DOE31_0_DIO10 Enables data output for DIO10. 0xA 0x1 read-write DOE31_0_DIO10_DISABLE DISABLE 0 DOE31_0_DIO10_ENABLE ENABLE 1 DOE31_0_DIO11 Enables data output for DIO11. 0xB 0x1 read-write DOE31_0_DIO11_DISABLE DISABLE 0 DOE31_0_DIO11_ENABLE ENABLE 1 DOE31_0_DIO12 Enables data output for DIO12. 0xC 0x1 read-write DOE31_0_DIO12_DISABLE DISABLE 0 DOE31_0_DIO12_ENABLE ENABLE 1 DOE31_0_DIO13 Enables data output for DIO13. 0xD 0x1 read-write DOE31_0_DIO13_DISABLE DISABLE 0 DOE31_0_DIO13_ENABLE ENABLE 1 DOE31_0_DIO14 Enables data output for DIO14. 0xE 0x1 read-write DOE31_0_DIO14_DISABLE DISABLE 0 DOE31_0_DIO14_ENABLE ENABLE 1 DOE31_0_DIO15 Enables data output for DIO15. 0xF 0x1 read-write DOE31_0_DIO15_DISABLE DISABLE 0 DOE31_0_DIO15_ENABLE ENABLE 1 DOE31_0_DIO16 Enables data output for DIO16. 0x10 0x1 read-write DOE31_0_DIO16_DISABLE DISABLE 0 DOE31_0_DIO16_ENABLE ENABLE 1 DOE31_0_DIO17 Enables data output for DIO17. 0x11 0x1 read-write DOE31_0_DIO17_DISABLE DISABLE 0 DOE31_0_DIO17_ENABLE ENABLE 1 DOE31_0_DIO18 Enables data output for DIO18. 0x12 0x1 read-write DOE31_0_DIO18_DISABLE DISABLE 0 DOE31_0_DIO18_ENABLE ENABLE 1 DOE31_0_DIO19 Enables data output for DIO19. 0x13 0x1 read-write DOE31_0_DIO19_DISABLE DISABLE 0 DOE31_0_DIO19_ENABLE ENABLE 1 DOE31_0_DIO20 Enables data output for DIO20. 0x14 0x1 read-write DOE31_0_DIO20_DISABLE DISABLE 0 DOE31_0_DIO20_ENABLE ENABLE 1 DOE31_0_DIO21 Enables data output for DIO21. 0x15 0x1 read-write DOE31_0_DIO21_DISABLE DISABLE 0 DOE31_0_DIO21_ENABLE ENABLE 1 DOE31_0_DIO22 Enables data output for DIO22. 0x16 0x1 read-write DOE31_0_DIO22_DISABLE DISABLE 0 DOE31_0_DIO22_ENABLE ENABLE 1 DOE31_0_DIO23 Enables data output for DIO23. 0x17 0x1 read-write DOE31_0_DIO23_DISABLE DISABLE 0 DOE31_0_DIO23_ENABLE ENABLE 1 DOE31_0_DIO24 Enables data output for DIO24. 0x18 0x1 read-write DOE31_0_DIO24_DISABLE DISABLE 0 DOE31_0_DIO24_ENABLE ENABLE 1 DOE31_0_DIO25 Enables data output for DIO25. 0x19 0x1 read-write DOE31_0_DIO25_DISABLE DISABLE 0 DOE31_0_DIO25_ENABLE ENABLE 1 DOE31_0_DIO26 Enables data output for DIO26. 0x1A 0x1 read-write DOE31_0_DIO26_DISABLE DISABLE 0 DOE31_0_DIO26_ENABLE ENABLE 1 DOE31_0_DIO27 Enables data output for DIO27. 0x1B 0x1 read-write DOE31_0_DIO27_DISABLE DISABLE 0 DOE31_0_DIO27_ENABLE ENABLE 1 DOE31_0_DIO28 Enables data output for DIO28. 0x1C 0x1 read-write DOE31_0_DIO28_DISABLE DISABLE 0 DOE31_0_DIO28_ENABLE ENABLE 1 DOE31_0_DIO29 Enables data output for DIO29. 0x1D 0x1 read-write DOE31_0_DIO29_DISABLE DISABLE 0 DOE31_0_DIO29_ENABLE ENABLE 1 DOE31_0_DIO30 Enables data output for DIO30. 0x1E 0x1 read-write DOE31_0_DIO30_DISABLE DISABLE 0 DOE31_0_DIO30_ENABLE ENABLE 1 DOE31_0_DIO31 Enables data output for DIO31. 0x1F 0x1 read-write DOE31_0_DIO31_DISABLE DISABLE 0 DOE31_0_DIO31_ENABLE ENABLE 1 DOESET31_0 Data output enable set 31 to 0 0x12D0 32 write-only 0x00000000 DOESET31_0_DIO0 Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only DOESET31_0_DIO0_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO0_SET SET 1 DOESET31_0_DIO1 Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only DOESET31_0_DIO1_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO1_SET SET 1 DOESET31_0_DIO2 Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only DOESET31_0_DIO2_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO2_SET SET 1 DOESET31_0_DIO3 Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only DOESET31_0_DIO3_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO3_SET SET 1 DOESET31_0_DIO4 Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only DOESET31_0_DIO4_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO4_SET SET 1 DOESET31_0_DIO5 Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only DOESET31_0_DIO5_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO5_SET SET 1 DOESET31_0_DIO6 Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only DOESET31_0_DIO6_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO6_SET SET 1 DOESET31_0_DIO7 Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only DOESET31_0_DIO7_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO7_SET SET 1 DOESET31_0_DIO8 Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only DOESET31_0_DIO8_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO8_SET SET 1 DOESET31_0_DIO9 Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only DOESET31_0_DIO9_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO9_SET SET 1 DOESET31_0_DIO10 Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only DOESET31_0_DIO10_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO10_SET SET 1 DOESET31_0_DIO11 Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only DOESET31_0_DIO11_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO11_SET SET 1 DOESET31_0_DIO12 Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only DOESET31_0_DIO12_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO12_SET SET 1 DOESET31_0_DIO13 Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only DOESET31_0_DIO13_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO13_SET SET 1 DOESET31_0_DIO14 Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only DOESET31_0_DIO14_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO14_SET SET 1 DOESET31_0_DIO15 Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only DOESET31_0_DIO15_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO15_SET SET 1 DOESET31_0_DIO16 Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only DOESET31_0_DIO16_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO16_SET SET 1 DOESET31_0_DIO17 Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only DOESET31_0_DIO17_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO17_SET SET 1 DOESET31_0_DIO18 Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only DOESET31_0_DIO18_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO18_SET SET 1 DOESET31_0_DIO19 Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only DOESET31_0_DIO19_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO19_SET SET 1 DOESET31_0_DIO20 Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only DOESET31_0_DIO20_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO20_SET SET 1 DOESET31_0_DIO21 Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only DOESET31_0_DIO21_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO21_SET SET 1 DOESET31_0_DIO22 Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only DOESET31_0_DIO22_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO22_SET SET 1 DOESET31_0_DIO23 Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only DOESET31_0_DIO23_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO23_SET SET 1 DOESET31_0_DIO24 Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only DOESET31_0_DIO24_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO24_SET SET 1 DOESET31_0_DIO25 Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only DOESET31_0_DIO25_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO25_SET SET 1 DOESET31_0_DIO26 Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only DOESET31_0_DIO26_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO26_SET SET 1 DOESET31_0_DIO27 Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only DOESET31_0_DIO27_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO27_SET SET 1 DOESET31_0_DIO28 Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only DOESET31_0_DIO28_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO28_SET SET 1 DOESET31_0_DIO29 Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only DOESET31_0_DIO29_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO29_SET SET 1 DOESET31_0_DIO30 Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only DOESET31_0_DIO30_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO30_SET SET 1 DOESET31_0_DIO31 Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only DOESET31_0_DIO31_NO_EFFECT NO_EFFECT 0 DOESET31_0_DIO31_SET SET 1 DOECLR31_0 Data output enable clear 31 to 0 0x12E0 32 write-only 0x00000000 DOECLR31_0_DIO0 Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect. 0x0 0x1 write-only DOECLR31_0_DIO0_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO0_CLR CLR 1 DOECLR31_0_DIO1 Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect. 0x1 0x1 write-only DOECLR31_0_DIO1_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO1_CLR CLR 1 DOECLR31_0_DIO2 Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect. 0x2 0x1 write-only DOECLR31_0_DIO2_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO2_CLR CLR 1 DOECLR31_0_DIO3 Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect. 0x3 0x1 write-only DOECLR31_0_DIO3_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO3_CLR CLR 1 DOECLR31_0_DIO4 Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect. 0x4 0x1 write-only DOECLR31_0_DIO4_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO4_CLR CLR 1 DOECLR31_0_DIO5 Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect. 0x5 0x1 write-only DOECLR31_0_DIO5_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO5_CLR CLR 1 DOECLR31_0_DIO6 Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect. 0x6 0x1 write-only DOECLR31_0_DIO6_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO6_CLR CLR 1 DOECLR31_0_DIO7 Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect. 0x7 0x1 write-only DOECLR31_0_DIO7_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO7_CLR CLR 1 DOECLR31_0_DIO8 Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect. 0x8 0x1 write-only DOECLR31_0_DIO8_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO8_CLR CLR 1 DOECLR31_0_DIO9 Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect. 0x9 0x1 write-only DOECLR31_0_DIO9_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO9_CLR CLR 1 DOECLR31_0_DIO10 Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect. 0xA 0x1 write-only DOECLR31_0_DIO10_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO10_CLR CLR 1 DOECLR31_0_DIO11 Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect. 0xB 0x1 write-only DOECLR31_0_DIO11_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO11_CLR CLR 1 DOECLR31_0_DIO12 Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect. 0xC 0x1 write-only DOECLR31_0_DIO12_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO12_CLR CLR 1 DOECLR31_0_DIO13 Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect. 0xD 0x1 write-only DOECLR31_0_DIO13_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO13_CLR CLR 1 DOECLR31_0_DIO14 Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect. 0xE 0x1 write-only DOECLR31_0_DIO14_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO14_CLR CLR 1 DOECLR31_0_DIO15 Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect. 0xF 0x1 write-only DOECLR31_0_DIO15_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO15_CLR CLR 1 DOECLR31_0_DIO16 Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect. 0x10 0x1 write-only DOECLR31_0_DIO16_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO16_CLR CLR 1 DOECLR31_0_DIO17 Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect. 0x11 0x1 write-only DOECLR31_0_DIO17_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO17_CLR CLR 1 DOECLR31_0_DIO18 Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect. 0x12 0x1 write-only DOECLR31_0_DIO18_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO18_CLR CLR 1 DOECLR31_0_DIO19 Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect. 0x13 0x1 write-only DOECLR31_0_DIO19_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO19_CLR CLR 1 DOECLR31_0_DIO20 Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect. 0x14 0x1 write-only DOECLR31_0_DIO20_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO20_CLR CLR 1 DOECLR31_0_DIO21 Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect. 0x15 0x1 write-only DOECLR31_0_DIO21_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO21_CLR CLR 1 DOECLR31_0_DIO22 Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect. 0x16 0x1 write-only DOECLR31_0_DIO22_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO22_CLR CLR 1 DOECLR31_0_DIO23 Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect. 0x17 0x1 write-only DOECLR31_0_DIO23_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO23_CLR CLR 1 DOECLR31_0_DIO24 Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect. 0x18 0x1 write-only DOECLR31_0_DIO24_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO24_CLR CLR 1 DOECLR31_0_DIO25 Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect. 0x19 0x1 write-only DOECLR31_0_DIO25_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO25_CLR CLR 1 DOECLR31_0_DIO26 Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect. 0x1A 0x1 write-only DOECLR31_0_DIO26_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO26_CLR CLR 1 DOECLR31_0_DIO27 Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect. 0x1B 0x1 write-only DOECLR31_0_DIO27_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO27_CLR CLR 1 DOECLR31_0_DIO28 Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect. 0x1C 0x1 write-only DOECLR31_0_DIO28_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO28_CLR CLR 1 DOECLR31_0_DIO29 Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect. 0x1D 0x1 write-only DOECLR31_0_DIO29_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO29_CLR CLR 1 DOECLR31_0_DIO30 Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect. 0x1E 0x1 write-only DOECLR31_0_DIO30_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO30_CLR CLR 1 DOECLR31_0_DIO31 Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect. 0x1F 0x1 write-only DOECLR31_0_DIO31_NO_EFFECT NO_EFFECT 0 DOECLR31_0_DIO31_CLR CLR 1 DIN3_0 Data input 3 to 0 0x1300 32 read-only 0x00000000 DIN3_0_DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only DIN3_0_DIO0_ZERO ZERO 0 DIN3_0_DIO0_ONE ONE 1 DIN3_0_DIO1 This bit reads the data input value of DIO1. 0x8 0x1 read-only DIN3_0_DIO1_ZERO ZERO 0 DIN3_0_DIO1_ONE ONE 1 DIN3_0_DIO2 This bit reads the data input value of DIO2. 0x10 0x1 read-only DIN3_0_DIO2_ZERO ZERO 0 DIN3_0_DIO2_ONE ONE 1 DIN3_0_DIO3 This bit reads the data input value of DIO3. 0x18 0x1 read-only DIN3_0_DIO3_ZERO ZERO 0 DIN3_0_DIO3_ONE ONE 1 DIN7_4 Data input 7 to 4 0x1304 32 read-only 0x00000000 DIN7_4_DIO4 This bit reads the data input value of DIO4. 0x0 0x1 read-only DIN7_4_DIO4_ZERO ZERO 0 DIN7_4_DIO4_ONE ONE 1 DIN7_4_DIO5 This bit reads the data input value of DIO5. 0x8 0x1 read-only DIN7_4_DIO5_ZERO ZERO 0 DIN7_4_DIO5_ONE ONE 1 DIN7_4_DIO6 This bit reads the data input value of DIO6. 0x10 0x1 read-only DIN7_4_DIO6_ZERO ZERO 0 DIN7_4_DIO6_ONE ONE 1 DIN7_4_DIO7 This bit reads the data input value of DIO7. 0x18 0x1 read-only DIN7_4_DIO7_ZERO ZERO 0 DIN7_4_DIO7_ONE ONE 1 DIN11_8 Data input 11 to 8 0x1308 32 read-only 0x00000000 DIN11_8_DIO8 This bit reads the data input value of DIO8. 0x0 0x1 read-only DIN11_8_DIO8_ZERO ZERO 0 DIN11_8_DIO8_ONE ONE 1 DIN11_8_DIO9 This bit reads the data input value of DIO9. 0x8 0x1 read-only DIN11_8_DIO9_ZERO ZERO 0 DIN11_8_DIO9_ONE ONE 1 DIN11_8_DIO10 This bit reads the data input value of DIO10. 0x10 0x1 read-only DIN11_8_DIO10_ZERO ZERO 0 DIN11_8_DIO10_ONE ONE 1 DIN11_8_DIO11 This bit reads the data input value of DIO11. 0x18 0x1 read-only DIN11_8_DIO11_ZERO ZERO 0 DIN11_8_DIO11_ONE ONE 1 DIN15_12 Data input 15 to 12 0x130C 32 read-only 0x00000000 DIN15_12_DIO12 This bit reads the data input value of DIO12. 0x0 0x1 read-only DIN15_12_DIO12_ZERO ZERO 0 DIN15_12_DIO12_ONE ONE 1 DIN15_12_DIO13 This bit reads the data input value of DIO13. 0x8 0x1 read-only DIN15_12_DIO13_ZERO ZERO 0 DIN15_12_DIO13_ONE ONE 1 DIN15_12_DIO14 This bit reads the data input value of DIO14. 0x10 0x1 read-only DIN15_12_DIO14_ZERO ZERO 0 DIN15_12_DIO14_ONE ONE 1 DIN15_12_DIO15 This bit reads the data input value of DIO15. 0x18 0x1 read-only DIN15_12_DIO15_ZERO ZERO 0 DIN15_12_DIO15_ONE ONE 1 DIN19_16 Data input 19 to 16 0x1310 32 read-only 0x00000000 DIN19_16_DIO16 This bit reads the data input value of DIO16. 0x0 0x1 read-only DIN19_16_DIO16_ZERO ZERO 0 DIN19_16_DIO16_ONE ONE 1 DIN19_16_DIO17 This bit reads the data input value of DIO17. 0x8 0x1 read-only DIN19_16_DIO17_ZERO ZERO 0 DIN19_16_DIO17_ONE ONE 1 DIN19_16_DIO18 This bit reads the data input value of DIO18. 0x10 0x1 read-only DIN19_16_DIO18_ZERO ZERO 0 DIN19_16_DIO18_ONE ONE 1 DIN19_16_DIO19 This bit reads the data input value of DIO19. 0x18 0x1 read-only DIN19_16_DIO19_ZERO ZERO 0 DIN19_16_DIO19_ONE ONE 1 DIN23_20 Data input 23 to 20 0x1314 32 read-only 0x00000000 DIN23_20_DIO20 This bit reads the data input value of DIO20. 0x0 0x1 read-only DIN23_20_DIO20_ZERO ZERO 0 DIN23_20_DIO20_ONE ONE 1 DIN23_20_DIO21 This bit reads the data input value of DIO21. 0x8 0x1 read-only DIN23_20_DIO21_ZERO ZERO 0 DIN23_20_DIO21_ONE ONE 1 DIN23_20_DIO22 This bit reads the data input value of DIO22. 0x10 0x1 read-only DIN23_20_DIO22_ZERO ZERO 0 DIN23_20_DIO22_ONE ONE 1 DIN23_20_DIO23 This bit reads the data input value of DIO23. 0x18 0x1 read-only DIN23_20_DIO23_ZERO ZERO 0 DIN23_20_DIO23_ONE ONE 1 DIN27_24 Data input 27 to 24 0x1318 32 read-only 0x00000000 DIN27_24_DIO24 This bit reads the data input value of DIO24. 0x0 0x1 read-only DIN27_24_DIO24_ZERO ZERO 0 DIN27_24_DIO24_ONE ONE 1 DIN27_24_DIO25 This bit reads the data input value of DIO25. 0x8 0x1 read-only DIN27_24_DIO25_ZERO ZERO 0 DIN27_24_DIO25_ONE ONE 1 DIN27_24_DIO26 This bit reads the data input value of DIO26. 0x10 0x1 read-only DIN27_24_DIO26_ZERO ZERO 0 DIN27_24_DIO26_ONE ONE 1 DIN27_24_DIO27 This bit reads the data input value of DIO27. 0x18 0x1 read-only DIN27_24_DIO27_ZERO ZERO 0 DIN27_24_DIO27_ONE ONE 1 DIN31_28 Data input 31 to 28 0x131C 32 read-only 0x00000000 DIN31_28_DIO28 This bit reads the data input value of DIO28. 0x0 0x1 read-only DIN31_28_DIO28_ZERO ZERO 0 DIN31_28_DIO28_ONE ONE 1 DIN31_28_DIO29 This bit reads the data input value of DIO29. 0x8 0x1 read-only DIN31_28_DIO29_ZERO ZERO 0 DIN31_28_DIO29_ONE ONE 1 DIN31_28_DIO30 This bit reads the data input value of DIO30. 0x10 0x1 read-only DIN31_28_DIO30_ZERO ZERO 0 DIN31_28_DIO30_ONE ONE 1 DIN31_28_DIO31 This bit reads the data input value of DIO31. 0x18 0x1 read-only DIN31_28_DIO31_ZERO ZERO 0 DIN31_28_DIO31_ONE ONE 1 DIN31_0 Data input 31 to 0 0x1380 32 read-only 0x00000000 DIN31_0_DIO0 This bit reads the data input value of DIO0. 0x0 0x1 read-only DIN31_0_DIO0_ZERO ZERO 0 DIN31_0_DIO0_ONE ONE 1 DIN31_0_DIO1 This bit reads the data input value of DIO1. 0x1 0x1 read-only DIN31_0_DIO1_ZERO ZERO 0 DIN31_0_DIO1_ONE ONE 1 DIN31_0_DIO2 This bit reads the data input value of DIO2. 0x2 0x1 read-only DIN31_0_DIO2_ZERO ZERO 0 DIN31_0_DIO2_ONE ONE 1 DIN31_0_DIO3 This bit reads the data input value of DIO3. 0x3 0x1 read-only DIN31_0_DIO3_ZERO ZERO 0 DIN31_0_DIO3_ONE ONE 1 DIN31_0_DIO4 This bit reads the data input value of DIO4. 0x4 0x1 read-only DIN31_0_DIO4_ZERO ZERO 0 DIN31_0_DIO4_ONE ONE 1 DIN31_0_DIO5 This bit reads the data input value of DIO5. 0x5 0x1 read-only DIN31_0_DIO5_ZERO ZERO 0 DIN31_0_DIO5_ONE ONE 1 DIN31_0_DIO6 This bit reads the data input value of DIO6. 0x6 0x1 read-only DIN31_0_DIO6_ZERO ZERO 0 DIN31_0_DIO6_ONE ONE 1 DIN31_0_DIO7 This bit reads the data input value of DIO7. 0x7 0x1 read-only DIN31_0_DIO7_ZERO ZERO 0 DIN31_0_DIO7_ONE ONE 1 DIN31_0_DIO8 This bit reads the data input value of DIO8. 0x8 0x1 read-only DIN31_0_DIO8_ZERO ZERO 0 DIN31_0_DIO8_ONE ONE 1 DIN31_0_DIO9 This bit reads the data input value of DIO9. 0x9 0x1 read-only DIN31_0_DIO9_ZERO ZERO 0 DIN31_0_DIO9_ONE ONE 1 DIN31_0_DIO10 This bit reads the data input value of DIO10. 0xA 0x1 read-only DIN31_0_DIO10_ZERO ZERO 0 DIN31_0_DIO10_ONE ONE 1 DIN31_0_DIO11 This bit reads the data input value of DIO11. 0xB 0x1 read-only DIN31_0_DIO11_ZERO ZERO 0 DIN31_0_DIO11_ONE ONE 1 DIN31_0_DIO12 This bit reads the data input value of DIO12. 0xC 0x1 read-only DIN31_0_DIO12_ZERO ZERO 0 DIN31_0_DIO12_ONE ONE 1 DIN31_0_DIO13 This bit reads the data input value of DIO13. 0xD 0x1 read-only DIN31_0_DIO13_ZERO ZERO 0 DIN31_0_DIO13_ONE ONE 1 DIN31_0_DIO14 This bit reads the data input value of DIO14. 0xE 0x1 read-only DIN31_0_DIO14_ZERO ZERO 0 DIN31_0_DIO14_ONE ONE 1 DIN31_0_DIO15 This bit reads the data input value of DIO15. 0xF 0x1 read-only DIN31_0_DIO15_ZERO ZERO 0 DIN31_0_DIO15_ONE ONE 1 DIN31_0_DIO16 This bit reads the data input value of DIO16. 0x10 0x1 read-only DIN31_0_DIO16_ZERO ZERO 0 DIN31_0_DIO16_ONE ONE 1 DIN31_0_DIO17 This bit reads the data input value of DIO17. 0x11 0x1 read-only DIN31_0_DIO17_ZERO ZERO 0 DIN31_0_DIO17_ONE ONE 1 DIN31_0_DIO18 This bit reads the data input value of DIO18. 0x12 0x1 read-only DIN31_0_DIO18_ZERO ZERO 0 DIN31_0_DIO18_ONE ONE 1 DIN31_0_DIO19 This bit reads the data input value of DIO19. 0x13 0x1 read-only DIN31_0_DIO19_ZERO ZERO 0 DIN31_0_DIO19_ONE ONE 1 DIN31_0_DIO20 This bit reads the data input value of DIO20. 0x14 0x1 read-only DIN31_0_DIO20_ZERO ZERO 0 DIN31_0_DIO20_ONE ONE 1 DIN31_0_DIO21 This bit reads the data input value of DIO21. 0x15 0x1 read-only DIN31_0_DIO21_ZERO ZERO 0 DIN31_0_DIO21_ONE ONE 1 DIN31_0_DIO22 This bit reads the data input value of DIO22. 0x16 0x1 read-only DIN31_0_DIO22_ZERO ZERO 0 DIN31_0_DIO22_ONE ONE 1 DIN31_0_DIO23 This bit reads the data input value of DIO23. 0x17 0x1 read-only DIN31_0_DIO23_ZERO ZERO 0 DIN31_0_DIO23_ONE ONE 1 DIN31_0_DIO24 This bit reads the data input value of DIO24. 0x18 0x1 read-only DIN31_0_DIO24_ZERO ZERO 0 DIN31_0_DIO24_ONE ONE 1 DIN31_0_DIO25 This bit reads the data input value of DIO25. 0x19 0x1 read-only DIN31_0_DIO25_ZERO ZERO 0 DIN31_0_DIO25_ONE ONE 1 DIN31_0_DIO26 This bit reads the data input value of DIO26. 0x1A 0x1 read-only DIN31_0_DIO26_ZERO ZERO 0 DIN31_0_DIO26_ONE ONE 1 DIN31_0_DIO27 This bit reads the data input value of DIO27. 0x1B 0x1 read-only DIN31_0_DIO27_ZERO ZERO 0 DIN31_0_DIO27_ONE ONE 1 DIN31_0_DIO28 This bit reads the data input value of DIO28. 0x1C 0x1 read-only DIN31_0_DIO28_ZERO ZERO 0 DIN31_0_DIO28_ONE ONE 1 DIN31_0_DIO29 This bit reads the data input value of DIO29. 0x1D 0x1 read-only DIN31_0_DIO29_ZERO ZERO 0 DIN31_0_DIO29_ONE ONE 1 DIN31_0_DIO30 This bit reads the data input value of DIO30. 0x1E 0x1 read-only DIN31_0_DIO30_ZERO ZERO 0 DIN31_0_DIO30_ONE ONE 1 DIN31_0_DIO31 This bit reads the data input value of DIO31. 0x1F 0x1 read-only DIN31_0_DIO31_ZERO ZERO 0 DIN31_0_DIO31_ONE ONE 1 POLARITY15_0 Polarity 15 to 0 0x1390 32 read-write 0x00000000 POLARITY15_0_DIO0 Enables and configures edge detection polarity for DIO0. 0x0 0x2 read-write POLARITY15_0_DIO0_DISABLE DISABLE 0 POLARITY15_0_DIO0_RISE RISE 1 POLARITY15_0_DIO0_FALL FALL 2 POLARITY15_0_DIO0_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO1 Enables and configures edge detection polarity for DIO1. 0x2 0x2 read-write POLARITY15_0_DIO1_DISABLE DISABLE 0 POLARITY15_0_DIO1_RISE RISE 1 POLARITY15_0_DIO1_FALL FALL 2 POLARITY15_0_DIO1_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO2 Enables and configures edge detection polarity for DIO2. 0x4 0x2 read-write POLARITY15_0_DIO2_DISABLE DISABLE 0 POLARITY15_0_DIO2_RISE RISE 1 POLARITY15_0_DIO2_FALL FALL 2 POLARITY15_0_DIO2_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO3 Enables and configures edge detection polarity for DIO3. 0x6 0x2 read-write POLARITY15_0_DIO3_DISABLE DISABLE 0 POLARITY15_0_DIO3_RISE RISE 1 POLARITY15_0_DIO3_FALL FALL 2 POLARITY15_0_DIO3_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO4 Enables and configures edge detection polarity for DIO4. 0x8 0x2 read-write POLARITY15_0_DIO4_DISABLE DISABLE 0 POLARITY15_0_DIO4_RISE RISE 1 POLARITY15_0_DIO4_FALL FALL 2 POLARITY15_0_DIO4_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO5 Enables and configures edge detection polarity for DIO5. 0xA 0x2 read-write POLARITY15_0_DIO5_DISABLE DISABLE 0 POLARITY15_0_DIO5_RISE RISE 1 POLARITY15_0_DIO5_FALL FALL 2 POLARITY15_0_DIO5_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO6 Enables and configures edge detection polarity for DIO6. 0xC 0x2 read-write POLARITY15_0_DIO6_DISABLE DISABLE 0 POLARITY15_0_DIO6_RISE RISE 1 POLARITY15_0_DIO6_FALL FALL 2 POLARITY15_0_DIO6_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO7 Enables and configures edge detection polarity for DIO7. 0xE 0x2 read-write POLARITY15_0_DIO7_DISABLE DISABLE 0 POLARITY15_0_DIO7_RISE RISE 1 POLARITY15_0_DIO7_FALL FALL 2 POLARITY15_0_DIO7_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO8 Enables and configures edge detection polarity for DIO8. 0x10 0x2 read-write POLARITY15_0_DIO8_DISABLE DISABLE 0 POLARITY15_0_DIO8_RISE RISE 1 POLARITY15_0_DIO8_FALL FALL 2 POLARITY15_0_DIO8_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO9 Enables and configures edge detection polarity for DIO9. 0x12 0x2 read-write POLARITY15_0_DIO9_DISABLE DISABLE 0 POLARITY15_0_DIO9_RISE RISE 1 POLARITY15_0_DIO9_FALL FALL 2 POLARITY15_0_DIO9_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO10 Enables and configures edge detection polarity for DIO10. 0x14 0x2 read-write POLARITY15_0_DIO10_DISABLE DISABLE 0 POLARITY15_0_DIO10_RISE RISE 1 POLARITY15_0_DIO10_FALL FALL 2 POLARITY15_0_DIO10_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO11 Enables and configures edge detection polarity for DIO11. 0x16 0x2 read-write POLARITY15_0_DIO11_DISABLE DISABLE 0 POLARITY15_0_DIO11_RISE RISE 1 POLARITY15_0_DIO11_FALL FALL 2 POLARITY15_0_DIO11_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO12 Enables and configures edge detection polarity for DIO12. 0x18 0x2 read-write POLARITY15_0_DIO12_DISABLE DISABLE 0 POLARITY15_0_DIO12_RISE RISE 1 POLARITY15_0_DIO12_FALL FALL 2 POLARITY15_0_DIO12_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO13 Enables and configures edge detection polarity for DIO13. 0x1A 0x2 read-write POLARITY15_0_DIO13_DISABLE DISABLE 0 POLARITY15_0_DIO13_RISE RISE 1 POLARITY15_0_DIO13_FALL FALL 2 POLARITY15_0_DIO13_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO14 Enables and configures edge detection polarity for DIO14. 0x1C 0x2 read-write POLARITY15_0_DIO14_DISABLE DISABLE 0 POLARITY15_0_DIO14_RISE RISE 1 POLARITY15_0_DIO14_FALL FALL 2 POLARITY15_0_DIO14_RISE_FALL RISE_FALL 3 POLARITY15_0_DIO15 Enables and configures edge detection polarity for DIO15. 0x1E 0x2 read-write POLARITY15_0_DIO15_DISABLE DISABLE 0 POLARITY15_0_DIO15_RISE RISE 1 POLARITY15_0_DIO15_FALL FALL 2 POLARITY15_0_DIO15_RISE_FALL RISE_FALL 3 POLARITY31_16 Polarity 31 to 16 0x13A0 32 read-write 0x00000000 POLARITY31_16_DIO16 Enables and configures edge detection polarity for DIO16. 0x0 0x2 read-write POLARITY31_16_DIO16_DISABLE DISABLE 0 POLARITY31_16_DIO16_RISE RISE 1 POLARITY31_16_DIO16_FALL FALL 2 POLARITY31_16_DIO16_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO17 Enables and configures edge detection polarity for DIO17. 0x2 0x2 read-write POLARITY31_16_DIO17_DISABLE DISABLE 0 POLARITY31_16_DIO17_RISE RISE 1 POLARITY31_16_DIO17_FALL FALL 2 POLARITY31_16_DIO17_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO18 Enables and configures edge detection polarity for DIO18. 0x4 0x2 read-write POLARITY31_16_DIO18_DISABLE DISABLE 0 POLARITY31_16_DIO18_RISE RISE 1 POLARITY31_16_DIO18_FALL FALL 2 POLARITY31_16_DIO18_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO19 Enables and configures edge detection polarity for DIO19. 0x6 0x2 read-write POLARITY31_16_DIO19_DISABLE DISABLE 0 POLARITY31_16_DIO19_RISE RISE 1 POLARITY31_16_DIO19_FALL FALL 2 POLARITY31_16_DIO19_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO20 Enables and configures edge detection polarity for DIO20. 0x8 0x2 read-write POLARITY31_16_DIO20_DISABLE DISABLE 0 POLARITY31_16_DIO20_RISE RISE 1 POLARITY31_16_DIO20_FALL FALL 2 POLARITY31_16_DIO20_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO21 Enables and configures edge detection polarity for DIO21. 0xA 0x2 read-write POLARITY31_16_DIO21_DISABLE DISABLE 0 POLARITY31_16_DIO21_RISE RISE 1 POLARITY31_16_DIO21_FALL FALL 2 POLARITY31_16_DIO21_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO22 Enables and configures edge detection polarity for DIO22. 0xC 0x2 read-write POLARITY31_16_DIO22_DISABLE DISABLE 0 POLARITY31_16_DIO22_RISE RISE 1 POLARITY31_16_DIO22_FALL FALL 2 POLARITY31_16_DIO22_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO23 Enables and configures edge detection polarity for DIO23. 0xE 0x2 read-write POLARITY31_16_DIO23_DISABLE DISABLE 0 POLARITY31_16_DIO23_RISE RISE 1 POLARITY31_16_DIO23_FALL FALL 2 POLARITY31_16_DIO23_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO24 Enables and configures edge detection polarity for DIO24. 0x10 0x2 read-write POLARITY31_16_DIO24_DISABLE DISABLE 0 POLARITY31_16_DIO24_RISE RISE 1 POLARITY31_16_DIO24_FALL FALL 2 POLARITY31_16_DIO24_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO25 Enables and configures edge detection polarity for DIO25. 0x12 0x2 read-write POLARITY31_16_DIO25_DISABLE DISABLE 0 POLARITY31_16_DIO25_RISE RISE 1 POLARITY31_16_DIO25_FALL FALL 2 POLARITY31_16_DIO25_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO26 Enables and configures edge detection polarity for DIO26. 0x14 0x2 read-write POLARITY31_16_DIO26_DISABLE DISABLE 0 POLARITY31_16_DIO26_RISE RISE 1 POLARITY31_16_DIO26_FALL FALL 2 POLARITY31_16_DIO26_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO27 Enables and configures edge detection polarity for DIO27. 0x16 0x2 read-write POLARITY31_16_DIO27_DISABLE DISABLE 0 POLARITY31_16_DIO27_RISE RISE 1 POLARITY31_16_DIO27_FALL FALL 2 POLARITY31_16_DIO27_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO28 Enables and configures edge detection polarity for DIO28. 0x18 0x2 read-write POLARITY31_16_DIO28_DISABLE DISABLE 0 POLARITY31_16_DIO28_RISE RISE 1 POLARITY31_16_DIO28_FALL FALL 2 POLARITY31_16_DIO28_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO29 Enables and configures edge detection polarity for DIO29. 0x1A 0x2 read-write POLARITY31_16_DIO29_DISABLE DISABLE 0 POLARITY31_16_DIO29_RISE RISE 1 POLARITY31_16_DIO29_FALL FALL 2 POLARITY31_16_DIO29_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO30 Enables and configures edge detection polarity for DIO30. 0x1C 0x2 read-write POLARITY31_16_DIO30_DISABLE DISABLE 0 POLARITY31_16_DIO30_RISE RISE 1 POLARITY31_16_DIO30_FALL FALL 2 POLARITY31_16_DIO30_RISE_FALL RISE_FALL 3 POLARITY31_16_DIO31 Enables and configures edge detection polarity for DIO31. 0x1E 0x2 read-write POLARITY31_16_DIO31_DISABLE DISABLE 0 POLARITY31_16_DIO31_RISE RISE 1 POLARITY31_16_DIO31_FALL FALL 2 POLARITY31_16_DIO31_RISE_FALL RISE_FALL 3 CTL FAST WAKE GLOBAL EN 0x1400 32 read-write 0x00000000 CTL_FASTWAKEONLY FASTWAKEONLY for the global control of fastwake 0x0 0x1 read-write CTL_FASTWAKEONLY_NOT_GLOBAL_EN NOT_GLOBAL_EN 0 CTL_FASTWAKEONLY_GLOBAL_EN GLOBAL_EN 1 FASTWAKE FAST WAKE ENABLE 0x1404 32 read-write 0x00000000 FASTWAKE_DIN0 Enable fastwake feature for DIN0 0x0 0x1 FASTWAKE_DIN0_DISABLE DISABLE 0 FASTWAKE_DIN0_ENABLE ENABLE 1 FASTWAKE_DIN1 Enable fastwake feature for DIN1 0x1 0x1 FASTWAKE_DIN1_DISABLE DISABLE 0 FASTWAKE_DIN1_ENABLE ENABLE 1 FASTWAKE_DIN2 Enable fastwake feature for DIN2 0x2 0x1 FASTWAKE_DIN2_DISABLE DISABLE 0 FASTWAKE_DIN2_ENABLE ENABLE 1 FASTWAKE_DIN3 Enable fastwake feature for DIN3 0x3 0x1 FASTWAKE_DIN3_DISABLE DISABLE 0 FASTWAKE_DIN3_ENABLE ENABLE 1 FASTWAKE_DIN4 Enable fastwake feature for DIN4 0x4 0x1 FASTWAKE_DIN4_DISABLE DISABLE 0 FASTWAKE_DIN4_ENABLE ENABLE 1 FASTWAKE_DIN5 Enable fastwake feature for DIN5 0x5 0x1 FASTWAKE_DIN5_DISABLE DISABLE 0 FASTWAKE_DIN5_ENABLE ENABLE 1 FASTWAKE_DIN6 Enable fastwake feature for DIN6 0x6 0x1 FASTWAKE_DIN6_DISABLE DISABLE 0 FASTWAKE_DIN6_ENABLE ENABLE 1 FASTWAKE_DIN7 Enable fastwake feature for DIN7 0x7 0x1 FASTWAKE_DIN7_DISABLE DISABLE 0 FASTWAKE_DIN7_ENABLE ENABLE 1 FASTWAKE_DIN8 Enable fastwake feature for DIN8 0x8 0x1 FASTWAKE_DIN8_DISABLE DISABLE 0 FASTWAKE_DIN8_ENABLE ENABLE 1 FASTWAKE_DIN9 Enable fastwake feature for DIN9 0x9 0x1 FASTWAKE_DIN9_DISABLE DISABLE 0 FASTWAKE_DIN9_ENABLE ENABLE 1 FASTWAKE_DIN10 Enable fastwake feature for DIN10 0xA 0x1 FASTWAKE_DIN10_DISABLE DISABLE 0 FASTWAKE_DIN10_ENABLE ENABLE 1 FASTWAKE_DIN11 Enable fastwake feature for DIN11 0xB 0x1 FASTWAKE_DIN11_DISABLE DISABLE 0 FASTWAKE_DIN11_ENABLE ENABLE 1 FASTWAKE_DIN12 Enable fastwake feature for DIN12 0xC 0x1 FASTWAKE_DIN12_DISABLE DISABLE 0 FASTWAKE_DIN12_ENABLE ENABLE 1 FASTWAKE_DIN13 Enable fastwake feature for DIN13 0xD 0x1 FASTWAKE_DIN13_DISABLE DISABLE 0 FASTWAKE_DIN13_ENABLE ENABLE 1 FASTWAKE_DIN14 Enable fastwake feature for DIN14 0xE 0x1 FASTWAKE_DIN14_DISABLE DISABLE 0 FASTWAKE_DIN14_ENABLE ENABLE 1 FASTWAKE_DIN15 Enable fastwake feature for DIN15 0xF 0x1 FASTWAKE_DIN15_DISABLE DISABLE 0 FASTWAKE_DIN15_ENABLE ENABLE 1 FASTWAKE_DIN16 Enable fastwake feature for DIN16 0x10 0x1 FASTWAKE_DIN16_DISABLE DISABLE 0 FASTWAKE_DIN16_ENABLE ENABLE 1 FASTWAKE_DIN17 Enable fastwake feature for DIN17 0x11 0x1 FASTWAKE_DIN17_DISABLE DISABLE 0 FASTWAKE_DIN17_ENABLE ENABLE 1 FASTWAKE_DIN18 Enable fastwake feature for DIN18 0x12 0x1 FASTWAKE_DIN18_DISABLE DISABLE 0 FASTWAKE_DIN18_ENABLE ENABLE 1 FASTWAKE_DIN19 Enable fastwake feature for DIN19 0x13 0x1 FASTWAKE_DIN19_DISABLE DISABLE 0 FASTWAKE_DIN19_ENABLE ENABLE 1 FASTWAKE_DIN20 Enable fastwake feature for DIN20 0x14 0x1 FASTWAKE_DIN20_DISABLE DISABLE 0 FASTWAKE_DIN20_ENABLE ENABLE 1 FASTWAKE_DIN21 Enable fastwake feature for DIN21 0x15 0x1 FASTWAKE_DIN21_DISABLE DISABLE 0 FASTWAKE_DIN21_ENABLE ENABLE 1 FASTWAKE_DIN22 Enable fastwake feature for DIN22 0x16 0x1 FASTWAKE_DIN22_DISABLE DISABLE 0 FASTWAKE_DIN22_ENABLE ENABLE 1 FASTWAKE_DIN23 Enable fastwake feature for DIN23 0x17 0x1 FASTWAKE_DIN23_DISABLE DISABLE 0 FASTWAKE_DIN23_ENABLE ENABLE 1 FASTWAKE_DIN24 Enable fastwake feature for DIN24 0x18 0x1 FASTWAKE_DIN24_DISABLE DISABLE 0 FASTWAKE_DIN24_ENABLE ENABLE 1 FASTWAKE_DIN25 Enable fastwake feature for DIN25 0x19 0x1 FASTWAKE_DIN25_DISABLE DISABLE 0 FASTWAKE_DIN25_ENABLE ENABLE 1 FASTWAKE_DIN26 Enable fastwake feature for DIN26 0x1A 0x1 FASTWAKE_DIN26_DISABLE DISABLE 0 FASTWAKE_DIN26_ENABLE ENABLE 1 FASTWAKE_DIN27 Enable fastwake feature for DIN27 0x1B 0x1 FASTWAKE_DIN27_DISABLE DISABLE 0 FASTWAKE_DIN27_ENABLE ENABLE 1 FASTWAKE_DIN28 Enable fastwake feature for DIN29 0x1C 0x1 FASTWAKE_DIN28_DISABLE DISABLE 0 FASTWAKE_DIN28_ENABLE ENABLE 1 FASTWAKE_DIN29 Enable fastwake feature for DIN29 0x1D 0x1 FASTWAKE_DIN29_DISABLE DISABLE 0 FASTWAKE_DIN29_ENABLE ENABLE 1 FASTWAKE_DIN30 Enable fastwake feature for DIN30 0x1E 0x1 FASTWAKE_DIN30_DISABLE DISABLE 0 FASTWAKE_DIN30_ENABLE ENABLE 1 FASTWAKE_DIN31 Enable fastwake feature for DIN31 0x1F 0x1 FASTWAKE_DIN31_DISABLE DISABLE 0 FASTWAKE_DIN31_ENABLE ENABLE 1 SUB0CFG Subscriber 0 configuration 0x1500 32 read-write 0x00000000 SUB0CFG_ENABLE This bit is used to enable subscriber 0 event. 0x0 0x1 read-write SUB0CFG_ENABLE_CLR CLR 0 SUB0CFG_ENABLE_SET SET 1 SUB0CFG_OUTPOLICY These bits configure the output policy for subscriber 0 event. 0x8 0x2 read-write SUB0CFG_OUTPOLICY_SET SET 0 SUB0CFG_OUTPOLICY_CLR CLR 1 SUB0CFG_OUTPOLICY_TOGGLE TOGGLE 2 SUB0CFG_INDEX Indicates the specific bit among lower 16 bits that is targeted by the subscriber action 0x10 0x4 read-write SUB0CFG_INDEX_MIN MIN 0 SUB0CFG_INDEX_MAX MAX 15 FILTEREN15_0 Filter Enable 15 to 0 0x1508 32 read-write 0x00000000 FILTEREN15_0_DIN0 Programmable counter length of digital glitch filter for DIN0 0x0 0x2 FILTEREN15_0_DIN0_DISABLE DISABLE 0 FILTEREN15_0_DIN0_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN0_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN0_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN1 Programmable counter length of digital glitch filter for DIN1 0x2 0x2 FILTEREN15_0_DIN1_DISABLE DISABLE 0 FILTEREN15_0_DIN1_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN1_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN1_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN2 Programmable counter length of digital glitch filter for DIN2 0x4 0x2 FILTEREN15_0_DIN2_DISABLE DISABLE 0 FILTEREN15_0_DIN2_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN2_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN2_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN3 Programmable counter length of digital glitch filter for DIN3 0x6 0x2 FILTEREN15_0_DIN3_DISABLE DISABLE 0 FILTEREN15_0_DIN3_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN3_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN3_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN4 Programmable counter length of digital glitch filter for DIN4 0x8 0x2 FILTEREN15_0_DIN4_DISABLE DISABLE 0 FILTEREN15_0_DIN4_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN4_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN4_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN5 Programmable counter length of digital glitch filter for DIN5 0xA 0x2 FILTEREN15_0_DIN5_DISABLE DISABLE 0 FILTEREN15_0_DIN5_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN5_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN5_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN6 Programmable counter length of digital glitch filter for DIN6 0xC 0x2 FILTEREN15_0_DIN6_DISABLE DISABLE 0 FILTEREN15_0_DIN6_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN6_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN6_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN7 Programmable counter length of digital glitch filter for DIN7 0xE 0x2 FILTEREN15_0_DIN7_DISABLE DISABLE 0 FILTEREN15_0_DIN7_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN7_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN7_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN8 Programmable counter length of digital glitch filter for DIN8 0x10 0x2 FILTEREN15_0_DIN8_DISABLE DISABLE 0 FILTEREN15_0_DIN8_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN8_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN8_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN9 Programmable counter length of digital glitch filter for DIN9 0x12 0x2 FILTEREN15_0_DIN9_DISABLE DISABLE 0 FILTEREN15_0_DIN9_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN9_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN9_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN10 Programmable counter length of digital glitch filter for DIN10 0x14 0x2 FILTEREN15_0_DIN10_DISABLE DISABLE 0 FILTEREN15_0_DIN10_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN10_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN10_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN11 Programmable counter length of digital glitch filter for DIN11 0x16 0x2 FILTEREN15_0_DIN11_DISABLE DISABLE 0 FILTEREN15_0_DIN11_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN11_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN11_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN12 Programmable counter length of digital glitch filter for DIN12 0x18 0x2 FILTEREN15_0_DIN12_DISABLE DISABLE 0 FILTEREN15_0_DIN12_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN12_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN12_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN13 Programmable counter length of digital glitch filter for DIN13 0x1A 0x2 FILTEREN15_0_DIN13_DISABLE DISABLE 0 FILTEREN15_0_DIN13_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN13_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN13_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN14 Programmable counter length of digital glitch filter for DIN14 0x1C 0x2 FILTEREN15_0_DIN14_DISABLE DISABLE 0 FILTEREN15_0_DIN14_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN14_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN14_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN15_0_DIN15 Programmable counter length of digital glitch filter for DIN15 0x1E 0x2 FILTEREN15_0_DIN15_DISABLE DISABLE 0 FILTEREN15_0_DIN15_ONE_CYCLE ONE_CYCLE 1 FILTEREN15_0_DIN15_THREE_CYCLE THREE_CYCLE 2 FILTEREN15_0_DIN15_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16 Filter Enable 31 to 16 0x150C 32 read-write 0x00000000 FILTEREN31_16_DIN16 Programmable counter length of digital glitch filter for DIN16 0x0 0x2 FILTEREN31_16_DIN16_DISABLE DISABLE 0 FILTEREN31_16_DIN16_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN16_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN16_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN17 Programmable counter length of digital glitch filter for DIN17 0x2 0x2 FILTEREN31_16_DIN17_DISABLE DISABLE 0 FILTEREN31_16_DIN17_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN17_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN17_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN18 Programmable counter length of digital glitch filter for DIN18 0x4 0x2 FILTEREN31_16_DIN18_DISABLE DISABLE 0 FILTEREN31_16_DIN18_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN18_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN18_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN19 Programmable counter length of digital glitch filter for DIN19 0x6 0x2 FILTEREN31_16_DIN19_DISABLE DISABLE 0 FILTEREN31_16_DIN19_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN19_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN19_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN20 Programmable counter length of digital glitch filter for DIN20 0x8 0x2 FILTEREN31_16_DIN20_DISABLE DISABLE 0 FILTEREN31_16_DIN20_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN20_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN20_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN21 Programmable counter length of digital glitch filter for DIN21 0xA 0x2 FILTEREN31_16_DIN21_DISABLE DISABLE 0 FILTEREN31_16_DIN21_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN21_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN21_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN22 Programmable counter length of digital glitch filter for DIN22 0xC 0x2 FILTEREN31_16_DIN22_DISABLE DISABLE 0 FILTEREN31_16_DIN22_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN22_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN22_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN23 Programmable counter length of digital glitch filter for DIN23 0xE 0x2 FILTEREN31_16_DIN23_DISABLE DISABLE 0 FILTEREN31_16_DIN23_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN23_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN23_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN24 Programmable counter length of digital glitch filter for DIN24 0x10 0x2 FILTEREN31_16_DIN24_DISABLE DISABLE 0 FILTEREN31_16_DIN24_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN24_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN24_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN25 Programmable counter length of digital glitch filter for DIN25 0x12 0x2 FILTEREN31_16_DIN25_DISABLE DISABLE 0 FILTEREN31_16_DIN25_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN25_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN25_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN26 Programmable counter length of digital glitch filter for DIN26 0x14 0x2 FILTEREN31_16_DIN26_DISABLE DISABLE 0 FILTEREN31_16_DIN26_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN26_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN26_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN27 Programmable counter length of digital glitch filter for DIN27 0x16 0x2 FILTEREN31_16_DIN27_DISABLE DISABLE 0 FILTEREN31_16_DIN27_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN27_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN27_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN28 Programmable counter length of digital glitch filter for DIN28 0x18 0x2 FILTEREN31_16_DIN28_DISABLE DISABLE 0 FILTEREN31_16_DIN28_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN28_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN28_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN29 Programmable counter length of digital glitch filter for DIN29 0x1A 0x2 FILTEREN31_16_DIN29_DISABLE DISABLE 0 FILTEREN31_16_DIN29_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN29_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN29_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN30 Programmable counter length of digital glitch filter for DIN30 0x1C 0x2 FILTEREN31_16_DIN30_DISABLE DISABLE 0 FILTEREN31_16_DIN30_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN30_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN30_EIGHT_CYCLE EIGHT_CYCLE 3 FILTEREN31_16_DIN31 Programmable counter length of digital glitch filter for DIN31 0x1E 0x2 FILTEREN31_16_DIN31_DISABLE DISABLE 0 FILTEREN31_16_DIN31_ONE_CYCLE ONE_CYCLE 1 FILTEREN31_16_DIN31_THREE_CYCLE THREE_CYCLE 2 FILTEREN31_16_DIN31_EIGHT_CYCLE EIGHT_CYCLE 3 DMAMASK DMA Write MASK 0x1510 32 read-write 0x00000000 DMAMASK_DOUT0 DMA is allowed to modify DOUT0 0x0 0x1 DMAMASK_DOUT0_DISABLE DISABLE 0 DMAMASK_DOUT0_ENABLE ENABLE 1 DMAMASK_DOUT1 DMA is allowed to modify DOUT1 0x1 0x1 DMAMASK_DOUT1_DISABLE DISABLE 0 DMAMASK_DOUT1_ENABLE ENABLE 1 DMAMASK_DOUT2 DMA is allowed to modify DOUT2 0x2 0x1 DMAMASK_DOUT2_DISABLE DISABLE 0 DMAMASK_DOUT2_ENABLE ENABLE 1 DMAMASK_DOUT3 DMA is allowed to modify DOUT3 0x3 0x1 DMAMASK_DOUT3_DISABLE DISABLE 0 DMAMASK_DOUT3_ENABLE ENABLE 1 DMAMASK_DOUT4 DMA is allowed to modify DOUT4 0x4 0x1 DMAMASK_DOUT4_DISABLE DISABLE 0 DMAMASK_DOUT4_ENABLE ENABLE 1 DMAMASK_DOUT5 DMA is allowed to modify DOUT5 0x5 0x1 DMAMASK_DOUT5_DISABLE DISABLE 0 DMAMASK_DOUT5_ENABLE ENABLE 1 DMAMASK_DOUT6 DMA is allowed to modify DOUT6 0x6 0x1 DMAMASK_DOUT6_DISABLE DISABLE 0 DMAMASK_DOUT6_ENABLE ENABLE 1 DMAMASK_DOUT7 DMA is allowed to modify DOUT7 0x7 0x1 DMAMASK_DOUT7_DISABLE DISABLE 0 DMAMASK_DOUT7_ENABLE ENABLE 1 DMAMASK_DOUT8 DMA is allowed to modify DOUT8 0x8 0x1 DMAMASK_DOUT8_DISABLE DISABLE 0 DMAMASK_DOUT8_ENABLE ENABLE 1 DMAMASK_DOUT9 DMA is allowed to modify DOUT9 0x9 0x1 DMAMASK_DOUT9_DISABLE DISABLE 0 DMAMASK_DOUT9_ENABLE ENABLE 1 DMAMASK_DOUT10 DMA is allowed to modify DOUT10 0xA 0x1 DMAMASK_DOUT10_DISABLE DISABLE 0 DMAMASK_DOUT10_ENABLE ENABLE 1 DMAMASK_DOUT11 DMA is allowed to modify DOUT11 0xB 0x1 DMAMASK_DOUT11_DISABLE DISABLE 0 DMAMASK_DOUT11_ENABLE ENABLE 1 DMAMASK_DOUT12 DMA is allowed to modify DOUT12 0xC 0x1 DMAMASK_DOUT12_DISABLE DISABLE 0 DMAMASK_DOUT12_ENABLE ENABLE 1 DMAMASK_DOUT13 DMA is allowed to modify DOUT13 0xD 0x1 DMAMASK_DOUT13_DISABLE DISABLE 0 DMAMASK_DOUT13_ENABLE ENABLE 1 DMAMASK_DOUT14 DMA is allowed to modify DOUT14 0xE 0x1 DMAMASK_DOUT14_DISABLE DISABLE 0 DMAMASK_DOUT14_ENABLE ENABLE 1 DMAMASK_DOUT15 DMA is allowed to modify DOUT15 0xF 0x1 DMAMASK_DOUT15_DISABLE DISABLE 0 DMAMASK_DOUT15_ENABLE ENABLE 1 DMAMASK_DOUT16 DMA is allowed to modify DOUT16 0x10 0x1 DMAMASK_DOUT16_DISABLE DISABLE 0 DMAMASK_DOUT16_ENABLE ENABLE 1 DMAMASK_DOUT17 DMA is allowed to modify DOUT17 0x11 0x1 DMAMASK_DOUT17_DISABLE DISABLE 0 DMAMASK_DOUT17_ENABLE ENABLE 1 DMAMASK_DOUT18 DMA is allowed to modify DOUT18 0x12 0x1 DMAMASK_DOUT18_DISABLE DISABLE 0 DMAMASK_DOUT18_ENABLE ENABLE 1 DMAMASK_DOUT19 DMA is allowed to modify DOUT19 0x13 0x1 DMAMASK_DOUT19_DISABLE DISABLE 0 DMAMASK_DOUT19_ENABLE ENABLE 1 DMAMASK_DOUT20 DMA is allowed to modify DOUT20 0x14 0x1 DMAMASK_DOUT20_DISABLE DISABLE 0 DMAMASK_DOUT20_ENABLE ENABLE 1 DMAMASK_DOUT21 DMA is allowed to modify DOUT21 0x15 0x1 DMAMASK_DOUT21_DISABLE DISABLE 0 DMAMASK_DOUT21_ENABLE ENABLE 1 DMAMASK_DOUT22 DMA is allowed to modify DOUT22 0x16 0x1 DMAMASK_DOUT22_DISABLE DISABLE 0 DMAMASK_DOUT22_ENABLE ENABLE 1 DMAMASK_DOUT23 DMA is allowed to modify DOUT23 0x17 0x1 DMAMASK_DOUT23_DISABLE DISABLE 0 DMAMASK_DOUT23_ENABLE ENABLE 1 DMAMASK_DOUT24 DMA is allowed to modify DOUT24 0x18 0x1 DMAMASK_DOUT24_DISABLE DISABLE 0 DMAMASK_DOUT24_ENABLE ENABLE 1 DMAMASK_DOUT25 DMA is allowed to modify DOUT25 0x19 0x1 DMAMASK_DOUT25_DISABLE DISABLE 0 DMAMASK_DOUT25_ENABLE ENABLE 1 DMAMASK_DOUT26 DMA is allowed to modify DOUT26 0x1A 0x1 DMAMASK_DOUT26_DISABLE DISABLE 0 DMAMASK_DOUT26_ENABLE ENABLE 1 DMAMASK_DOUT27 DMA is allowed to modify DOUT27 0x1B 0x1 DMAMASK_DOUT27_DISABLE DISABLE 0 DMAMASK_DOUT27_ENABLE ENABLE 1 DMAMASK_DOUT28 DMA is allowed to modify DOUT28 0x1C 0x1 DMAMASK_DOUT28_DISABLE DISABLE 0 DMAMASK_DOUT28_ENABLE ENABLE 1 DMAMASK_DOUT29 DMA is allowed to modify DOUT29 0x1D 0x1 DMAMASK_DOUT29_DISABLE DISABLE 0 DMAMASK_DOUT29_ENABLE ENABLE 1 DMAMASK_DOUT30 DMA is allowed to modify DOUT30 0x1E 0x1 DMAMASK_DOUT30_DISABLE DISABLE 0 DMAMASK_DOUT30_ENABLE ENABLE 1 DMAMASK_DOUT31 DMA is allowed to modify DOUT31 0x1F 0x1 DMAMASK_DOUT31_DISABLE DISABLE 0 DMAMASK_DOUT31_ENABLE ENABLE 1 SUB1CFG Subscriber 1 configuration 0x1520 32 read-write 0x00000000 SUB1CFG_ENABLE This bit is used to enable subscriber 1 event. 0x0 0x1 read-write SUB1CFG_ENABLE_CLR CLR 0 SUB1CFG_ENABLE_SET SET 1 SUB1CFG_OUTPOLICY These bits configure the output policy for subscriber 1 event. 0x8 0x2 read-write SUB1CFG_OUTPOLICY_SET SET 0 SUB1CFG_OUTPOLICY_CLR CLR 1 SUB1CFG_OUTPOLICY_TOGGLE TOGGLE 2 SUB1CFG_INDEX indicates the specific bit in the upper 16 bits that is targeted by the subscriber action 0x10 0x4 read-write SUB1CFG_INDEX_MIN MIN 0 SUB1CFG_INDEX_MAX MAX 15 UART1 1.0 PERIPHERALREGION 0x40100000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG Peripheral Clock Configuration Register 0x808 32 read-write 0x00000000 CLKCFG_KEY KEY to Allow State Change -- 0xA9 0x18 0x8 write-only CLKCFG_KEY_UNLOCK _UNLOCK_W_ 169 CLKCFG_BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write CLKCFG_BLOCKASYNC_DISABLE DISABLE 0 CLKCFG_BLOCKASYNC_ENABLE ENABLE 1 GPRCM_STAT Status Register 0x814 32 read-only GPRCM_STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only GPRCM_STAT_RESETSTKY_NORES NORES 0 GPRCM_STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUS CLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 INT_EVENT0_IIDX Interrupt index 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_RTFG RTFG 1 INT_EVENT0_IIDX_STAT_FEFG FEFG 2 INT_EVENT0_IIDX_STAT_PEFG PEFG 3 INT_EVENT0_IIDX_STAT_BEFG BEFG 4 INT_EVENT0_IIDX_STAT_OEFG OEFG 5 INT_EVENT0_IIDX_STAT_RXNE RXNE 6 INT_EVENT0_IIDX_STAT_RXPE RXPE 7 INT_EVENT0_IIDX_STAT_LINC0 LINC0 8 INT_EVENT0_IIDX_STAT_LINC1 LINC1 9 INT_EVENT0_IIDX_STAT_LINOVF LINOVF 10 INT_EVENT0_IIDX_STAT_RXIFG RXIFG 11 INT_EVENT0_IIDX_STAT_TXIFG TXIFG 12 INT_EVENT0_IIDX_STAT_EOT EOT 13 INT_EVENT0_IIDX_STAT_MODE_9B MODE_9B 14 INT_EVENT0_IIDX_STAT_CTS CTS 15 INT_EVENT0_IIDX_STAT_DMA_DONE_RX DMA_DONE_RX 16 INT_EVENT0_IIDX_STAT_DMA_DONE_TX DMA_DONE_TX 17 INT_EVENT0_IIDX_STAT_NERR_EVT NERR_EVT 18 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_FRMERR Enable UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_IMASK_FRMERR_CLR CLR 0 INT_EVENT0_IMASK_FRMERR_SET SET 1 INT_EVENT0_IMASK_PARERR Enable UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_IMASK_PARERR_CLR CLR 0 INT_EVENT0_IMASK_PARERR_SET SET 1 INT_EVENT0_IMASK_BRKERR Enable UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_IMASK_BRKERR_CLR CLR 0 INT_EVENT0_IMASK_BRKERR_SET SET 1 INT_EVENT0_IMASK_OVRERR Enable UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_IMASK_OVRERR_CLR CLR 0 INT_EVENT0_IMASK_OVRERR_SET SET 1 INT_EVENT0_IMASK_RXNE Enable Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_IMASK_RXNE_CLR CLR 0 INT_EVENT0_IMASK_RXNE_SET SET 1 INT_EVENT0_IMASK_RXPE Enable Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_IMASK_RXPE_CLR CLR 0 INT_EVENT0_IMASK_RXPE_SET SET 1 INT_EVENT0_IMASK_RXINT Enable UART Receive Interrupt. 0xA 0x1 INT_EVENT0_IMASK_RXINT_CLR CLR 0 INT_EVENT0_IMASK_RXINT_SET SET 1 INT_EVENT0_IMASK_TXINT Enable UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_IMASK_TXINT_CLR CLR 0 INT_EVENT0_IMASK_TXINT_SET SET 1 INT_EVENT0_IMASK_EOT Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_IMASK_EOT_CLR CLR 0 INT_EVENT0_IMASK_EOT_SET SET 1 INT_EVENT0_IMASK_ADDR_MATCH Enable Address Match Interrupt. 0xD 0x1 INT_EVENT0_IMASK_ADDR_MATCH_CLR CLR 0 INT_EVENT0_IMASK_ADDR_MATCH_SET SET 1 INT_EVENT0_IMASK_CTS Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_IMASK_CTS_CLR CLR 0 INT_EVENT0_IMASK_CTS_SET SET 1 INT_EVENT0_IMASK_DMA_DONE_RX Enable DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_IMASK_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_IMASK_DMA_DONE_RX_SET SET 1 INT_EVENT0_IMASK_DMA_DONE_TX Enable DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_IMASK_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_IMASK_DMA_DONE_TX_SET SET 1 INT_EVENT0_IMASK_RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_IMASK_RTOUT_CLR CLR 0 INT_EVENT0_IMASK_RTOUT_SET SET 1 INT_EVENT0_IMASK_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_IMASK_NERR_CLR CLR 0 INT_EVENT0_IMASK_NERR_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only INT_EVENT0_RIS_RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_RIS_RTOUT_CLR CLR 0 INT_EVENT0_RIS_RTOUT_SET SET 1 INT_EVENT0_RIS_FRMERR UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_RIS_FRMERR_CLR CLR 0 INT_EVENT0_RIS_FRMERR_SET SET 1 INT_EVENT0_RIS_PARERR UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_RIS_PARERR_CLR CLR 0 INT_EVENT0_RIS_PARERR_SET SET 1 INT_EVENT0_RIS_BRKERR UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_RIS_BRKERR_CLR CLR 0 INT_EVENT0_RIS_BRKERR_SET SET 1 INT_EVENT0_RIS_OVRERR UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_RIS_OVRERR_CLR CLR 0 INT_EVENT0_RIS_OVRERR_SET SET 1 INT_EVENT0_RIS_RXNE Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_RIS_RXNE_CLR CLR 0 INT_EVENT0_RIS_RXNE_SET SET 1 INT_EVENT0_RIS_RXPE Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_RIS_RXPE_CLR CLR 0 INT_EVENT0_RIS_RXPE_SET SET 1 INT_EVENT0_RIS_RXINT UART Receive Interrupt. 0xA 0x1 INT_EVENT0_RIS_RXINT_CLR CLR 0 INT_EVENT0_RIS_RXINT_SET SET 1 INT_EVENT0_RIS_TXINT UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_RIS_TXINT_CLR CLR 0 INT_EVENT0_RIS_TXINT_SET SET 1 INT_EVENT0_RIS_EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_RIS_EOT_CLR CLR 0 INT_EVENT0_RIS_EOT_SET SET 1 INT_EVENT0_RIS_ADDR_MATCH Address Match Interrupt. 0xD 0x1 INT_EVENT0_RIS_ADDR_MATCH_CLR CLR 0 INT_EVENT0_RIS_ADDR_MATCH_SET SET 1 INT_EVENT0_RIS_CTS UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_RIS_CTS_CLR CLR 0 INT_EVENT0_RIS_CTS_SET SET 1 INT_EVENT0_RIS_DMA_DONE_RX DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_RIS_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_RIS_DMA_DONE_RX_SET SET 1 INT_EVENT0_RIS_DMA_DONE_TX DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_RIS_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_RIS_DMA_DONE_TX_SET SET 1 INT_EVENT0_RIS_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_RIS_NERR_CLR CLR 0 INT_EVENT0_RIS_NERR_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_MIS_RTOUT_CLR CLR 0 INT_EVENT0_MIS_RTOUT_SET SET 1 INT_EVENT0_MIS_FRMERR Masked UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_MIS_FRMERR_CLR CLR 0 INT_EVENT0_MIS_FRMERR_SET SET 1 INT_EVENT0_MIS_PARERR Masked UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_MIS_PARERR_CLR CLR 0 INT_EVENT0_MIS_PARERR_SET SET 1 INT_EVENT0_MIS_BRKERR Masked UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_MIS_BRKERR_CLR CLR 0 INT_EVENT0_MIS_BRKERR_SET SET 1 INT_EVENT0_MIS_OVRERR Masked UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_MIS_OVRERR_CLR CLR 0 INT_EVENT0_MIS_OVRERR_SET SET 1 INT_EVENT0_MIS_RXNE Masked Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_MIS_RXNE_CLR CLR 0 INT_EVENT0_MIS_RXNE_SET SET 1 INT_EVENT0_MIS_RXPE Masked Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_MIS_RXPE_CLR CLR 0 INT_EVENT0_MIS_RXPE_SET SET 1 INT_EVENT0_MIS_RXINT Masked UART Receive Interrupt. 0xA 0x1 INT_EVENT0_MIS_RXINT_CLR CLR 0 INT_EVENT0_MIS_RXINT_SET SET 1 INT_EVENT0_MIS_TXINT Masked UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_MIS_TXINT_CLR CLR 0 INT_EVENT0_MIS_TXINT_SET SET 1 INT_EVENT0_MIS_EOT UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_MIS_EOT_CLR CLR 0 INT_EVENT0_MIS_EOT_SET SET 1 INT_EVENT0_MIS_ADDR_MATCH Masked Address Match Interrupt. 0xD 0x1 INT_EVENT0_MIS_ADDR_MATCH_CLR CLR 0 INT_EVENT0_MIS_ADDR_MATCH_SET SET 1 INT_EVENT0_MIS_CTS Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_MIS_CTS_CLR CLR 0 INT_EVENT0_MIS_CTS_SET SET 1 INT_EVENT0_MIS_DMA_DONE_RX Masked DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_MIS_DMA_DONE_RX_CLR CLR 0 INT_EVENT0_MIS_DMA_DONE_RX_SET SET 1 INT_EVENT0_MIS_DMA_DONE_TX Masked DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_MIS_DMA_DONE_TX_CLR CLR 0 INT_EVENT0_MIS_DMA_DONE_TX_SET SET 1 INT_EVENT0_MIS_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_MIS_NERR_CLR CLR 0 INT_EVENT0_MIS_NERR_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_FRMERR Set UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_ISET_FRMERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_FRMERR_SET SET 1 INT_EVENT0_ISET_PARERR Set UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_ISET_PARERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_PARERR_SET SET 1 INT_EVENT0_ISET_BRKERR Set UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_ISET_BRKERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_BRKERR_SET SET 1 INT_EVENT0_ISET_OVRERR Set UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_ISET_OVRERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_OVRERR_SET SET 1 INT_EVENT0_ISET_RXNE Set Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_ISET_RXNE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXNE_SET SET 1 INT_EVENT0_ISET_RXPE Set Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_ISET_RXPE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXPE_SET SET 1 INT_EVENT0_ISET_RXINT Set UART Receive Interrupt. 0xA 0x1 INT_EVENT0_ISET_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RXINT_SET SET 1 INT_EVENT0_ISET_TXINT Set UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_ISET_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TXINT_SET SET 1 INT_EVENT0_ISET_EOT Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_ISET_EOT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_EOT_SET SET 1 INT_EVENT0_ISET_ADDR_MATCH Set Address Match Interrupt. 0xD 0x1 INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_ADDR_MATCH_SET SET 1 INT_EVENT0_ISET_CTS Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_ISET_CTS_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_CTS_SET SET 1 INT_EVENT0_ISET_DMA_DONE_RX Set DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMA_DONE_RX_SET SET 1 INT_EVENT0_ISET_DMA_DONE_TX Set DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMA_DONE_TX_SET SET 1 INT_EVENT0_ISET_RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_ISET_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_RTOUT_SET SET 1 INT_EVENT0_ISET_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_ISET_NERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_NERR_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_FRMERR Clear UART Framing Error Interrupt. 0x1 0x1 INT_EVENT0_ICLR_FRMERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_FRMERR_CLR CLR 1 INT_EVENT0_ICLR_PARERR Clear UART Parity Error Interrupt. 0x2 0x1 INT_EVENT0_ICLR_PARERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_PARERR_CLR CLR 1 INT_EVENT0_ICLR_BRKERR Clear UART Break Error Interrupt. 0x3 0x1 INT_EVENT0_ICLR_BRKERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_BRKERR_CLR CLR 1 INT_EVENT0_ICLR_OVRERR Clear UART Receive Overrun Error Interrupt. 0x4 0x1 INT_EVENT0_ICLR_OVRERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_OVRERR_CLR CLR 1 INT_EVENT0_ICLR_RXNE Clear Negative Edge on UARTxRXD Interrupt. 0x5 0x1 INT_EVENT0_ICLR_RXNE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXNE_CLR CLR 1 INT_EVENT0_ICLR_RXPE Clear Positive Edge on UARTxRXD Interrupt. 0x6 0x1 INT_EVENT0_ICLR_RXPE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXPE_CLR CLR 1 INT_EVENT0_ICLR_RXINT Clear UART Receive Interrupt. 0xA 0x1 INT_EVENT0_ICLR_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RXINT_CLR CLR 1 INT_EVENT0_ICLR_TXINT Clear UART Transmit Interrupt. 0xB 0x1 INT_EVENT0_ICLR_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TXINT_CLR CLR 1 INT_EVENT0_ICLR_EOT Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer. 0xC 0x1 INT_EVENT0_ICLR_EOT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_EOT_CLR CLR 1 INT_EVENT0_ICLR_ADDR_MATCH Clear Address Match Interrupt. 0xD 0x1 INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_ADDR_MATCH_CLR CLR 1 INT_EVENT0_ICLR_CTS Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled 0xE 0x1 INT_EVENT0_ICLR_CTS_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_CTS_CLR CLR 1 INT_EVENT0_ICLR_DMA_DONE_RX Clear DMA Done on RX Event Channel 0xF 0x1 INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMA_DONE_RX_CLR CLR 1 INT_EVENT0_ICLR_DMA_DONE_TX Clear DMA Done on TX Event Channel 0x10 0x1 INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMA_DONE_TX_CLR CLR 1 INT_EVENT0_ICLR_RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT0_ICLR_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_RTOUT_CLR CLR 1 INT_EVENT0_ICLR_NERR Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0x11 0x1 INT_EVENT0_ICLR_NERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_NERR_CLR CLR 1 INT_EVENT1_IIDX Interrupt index 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_RTFG RTFG 1 INT_EVENT1_IIDX_STAT_RXIFG RXIFG 11 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_RTOUT Enable UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_IMASK_RTOUT_CLR CLR 0 INT_EVENT1_IMASK_RTOUT_SET SET 1 INT_EVENT1_IMASK_RXINT Enable UART Receive Interrupt. 0xA 0x1 INT_EVENT1_IMASK_RXINT_CLR CLR 0 INT_EVENT1_IMASK_RXINT_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only INT_EVENT1_RIS_RTOUT UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_RIS_RTOUT_CLR CLR 0 INT_EVENT1_RIS_RTOUT_SET SET 1 INT_EVENT1_RIS_RXINT UART Receive Interrupt. 0xA 0x1 INT_EVENT1_RIS_RXINT_CLR CLR 0 INT_EVENT1_RIS_RXINT_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_RTOUT Masked UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_MIS_RTOUT_CLR CLR 0 INT_EVENT1_MIS_RTOUT_SET SET 1 INT_EVENT1_MIS_RXINT Masked UART Receive Interrupt. 0xA 0x1 INT_EVENT1_MIS_RXINT_CLR CLR 0 INT_EVENT1_MIS_RXINT_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_RTOUT Set UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_ISET_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_RTOUT_SET SET 1 INT_EVENT1_ISET_RXINT Set UART Receive Interrupt. 0xA 0x1 INT_EVENT1_ISET_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_RXINT_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_RTOUT Clear UARTOUT Receive Time-Out Interrupt. 0x0 0x1 INT_EVENT1_ICLR_RTOUT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_RTOUT_CLR CLR 1 INT_EVENT1_ICLR_RXINT Clear UART Receive Interrupt. 0xA 0x1 INT_EVENT1_ICLR_RXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_RXINT_CLR CLR 1 INT_EVENT2_IIDX Interrupt index 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_TXIFG TXIFG 12 INT_EVENT2_IMASK Interrupt mask 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_TXINT Enable UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_IMASK_TXINT_CLR CLR 0 INT_EVENT2_IMASK_TXINT_SET SET 1 INT_EVENT2_RIS Raw interrupt status 0x1090 32 read-only INT_EVENT2_RIS_TXINT UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_RIS_TXINT_CLR CLR 0 INT_EVENT2_RIS_TXINT_SET SET 1 INT_EVENT2_MIS Masked interrupt status 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_TXINT Masked UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_MIS_TXINT_CLR CLR 0 INT_EVENT2_MIS_TXINT_SET SET 1 INT_EVENT2_ISET Interrupt set 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_TXINT Set UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_ISET_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_TXINT_SET SET 1 INT_EVENT2_ICLR Interrupt clear 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_TXINT Clear UART Transmit Interrupt. 0xB 0x1 INT_EVENT2_ICLR_TXINT_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_TXINT_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CTL0 UART Control Register 0 0x1100 32 read-write 0x00000038 0xffffffff CTL0_ENABLE UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0x0 0x1 read-write CTL0_ENABLE_DISABLE DISABLE 0 CTL0_ENABLE_ENABLE ENABLE 1 CTL0_HSE High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set). 0xF 0x2 read-write CTL0_HSE_OVS16 OVS16 0 CTL0_HSE_OVS8 OVS8 1 CTL0_HSE_OVS3 OVS3 2 CTL0_LBE UART Loop Back Enable 0x2 0x1 read-write CTL0_LBE_DISABLE DISABLE 0 CTL0_LBE_ENABLE ENABLE 1 CTL0_RXE UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set. 0x3 0x1 read-write CTL0_RXE_DISABLE DISABLE 0 CTL0_RXE_ENABLE ENABLE 1 CTL0_TXE UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set. 0x4 0x1 read-write CTL0_TXE_DISABLE DISABLE 0 CTL0_TXE_ENABLE ENABLE 1 CTL0_RTS Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0xC 0x1 read-write CTL0_RTS_CLR CLR 0 CTL0_RTS_SET SET 1 CTL0_RTSEN Enable hardware controlled Request to Send 0xD 0x1 read-write CTL0_RTSEN_DISABLE DISABLE 0 CTL0_RTSEN_ENABLE ENABLE 1 CTL0_CTSEN Enable Clear To Send 0xE 0x1 read-write CTL0_CTSEN_DISABLE DISABLE 0 CTL0_CTSEN_ENABLE ENABLE 1 CTL0_MODE Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0x8 0x3 read-write CTL0_MODE_UART UART 0 CTL0_MODE_RS485 RS485 1 CTL0_MODE_IDLELINE IDLELINE 2 CTL0_MODE_ADDR9BIT ADDR9BIT 3 CTL0_MODE_SMART SMART 4 CTL0_MODE_DALI DALI 5 CTL0_FEN UART Enable FIFOs 0x11 0x1 read-write CTL0_FEN_DISABLE DISABLE 0 CTL0_FEN_ENABLE ENABLE 1 CTL0_TXD_OUT TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0x6 0x1 read-write CTL0_TXD_OUT_LOW LOW 0 CTL0_TXD_OUT_HIGH HIGH 1 CTL0_TXD_OUT_EN TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0 0x5 0x1 read-write CTL0_TXD_OUT_EN_DISABLE DISABLE 0 CTL0_TXD_OUT_EN_ENABLE ENABLE 1 CTL0_MAJVOTE When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken. 0x12 0x1 read-write CTL0_MAJVOTE_DISABLE DISABLE 0 CTL0_MAJVOTE_ENABLE ENABLE 1 CTL0_MSBFIRST Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0x13 0x1 read-write CTL0_MSBFIRST_DISABLE DISABLE 0 CTL0_MSBFIRST_ENABLE ENABLE 1 LCRH UART Line Control Register 0x1104 32 read-write 0x00000000 0xffffffff LCRH_BRK UART Send Break (for LIN Protocol) 0x0 0x1 read-write LCRH_BRK_DISABLE DISABLE 0 LCRH_BRK_ENABLE ENABLE 1 LCRH_PEN UART Parity Enable 0x1 0x1 read-write LCRH_PEN_DISABLE DISABLE 0 LCRH_PEN_ENABLE ENABLE 1 LCRH_EPS UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte 0x2 0x1 read-write LCRH_EPS_ODD ODD 0 LCRH_EPS_EVEN EVEN 1 LCRH_STP2 UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0x3 0x1 read-write LCRH_STP2_DISABLE DISABLE 0 LCRH_STP2_ENABLE ENABLE 1 LCRH_WLEN UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x4 0x2 read-write LCRH_WLEN_DATABIT5 DATABIT5 0 LCRH_WLEN_DATABIT6 DATABIT6 1 LCRH_WLEN_DATABIT7 DATABIT7 2 LCRH_WLEN_DATABIT8 DATABIT8 3 LCRH_SPS UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0x6 0x1 read-write LCRH_SPS_DISABLE DISABLE 0 LCRH_SPS_ENABLE ENABLE 1 LCRH_SENDIDLE UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards. 0x7 0x1 read-write LCRH_SENDIDLE_DISABLE DISABLE 0 LCRH_SENDIDLE_ENABLE ENABLE 1 LCRH_EXTDIR_SETUP Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0x10 0x5 read-write LCRH_EXTDIR_HOLD Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0x15 0x5 read-write STAT UART Status Register 0x1108 32 read-only STAT_BUSY UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0x0 0x1 read-only STAT_BUSY_CLEARED CLEARED 0 STAT_BUSY_SET SET 1 STAT_TXFF UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x7 0x1 read-only STAT_TXFF_CLEARED CLEARED 0 STAT_TXFF_SET SET 1 STAT_RXFF UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x3 0x1 read-only STAT_RXFF_CLEARED CLEARED 0 STAT_RXFF_SET SET 1 STAT_TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x6 0x1 read-only STAT_TXFE_CLEARED CLEARED 0 STAT_TXFE_SET SET 1 STAT_CTS Clear To Send 0x8 0x1 read-only STAT_CTS_CLEARED CLEARED 0 STAT_CTS_SET SET 1 STAT_IDLE IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0x9 0x1 read-only STAT_IDLE_CLEARED CLEARED 0 STAT_IDLE_SET SET 1 STAT_RXFE UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0x2 0x1 read-only STAT_RXFE_CLEARED CLEARED 0 STAT_RXFE_SET SET 1 IFLS UART Interrupt FIFO Level Select Register 0x110C 32 read-write 0x00000022 0xffffffff IFLS_TXIFLSEL UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 0x0 0x3 read-write IFLS_RXIFLSEL UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0x4 0x3 read-write IFLS_RXTOSEL UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function. 0x8 0x4 read-write IBRD UART Integer Baud-Rate Divisor Register 0x1110 32 read-write 0x00000000 0xffffffff IBRD_DIVINT Integer Baud-Rate Divisor 0x0 0x10 read-write FBRD UART Fractional Baud-Rate Divisor Register 0x1114 32 read-write 0x00000000 0xffffffff FBRD_DIVFRAC Fractional Baud-Rate Divisor 0x0 0x6 read-write GFCTL Glitch Filter Control 0x1118 32 read-write 0x00000000 0xfffffffb GFCTL_AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only) 0x9 0x2 read-write GFCTL_AGFSEL_AGLIT_5 AGLIT_5 0 GFCTL_AGFSEL_AGLIT_10 AGLIT_10 1 GFCTL_AGFSEL_AGLIT_25 AGLIT_25 2 GFCTL_AGFSEL_AGLIT_50 AGLIT_50 3 GFCTL_AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write GFCTL_AGFEN_DISABLE DISABLE 0 GFCTL_AGFEN_ENABLE ENABLE 1 TXDATA UART Transmit Data Register 0x1120 32 read-write 0x00000000 0xffffffff TXDATA_DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-write RXDATA UART Receive Data Register 0x1124 32 read-only 0x00000000 0xffffffff RXDATA_DATA Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0x0 0x8 read-only RXDATA_FRMERR UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0x8 0x1 read-only RXDATA_FRMERR_CLR CLR 0 RXDATA_FRMERR_SET SET 1 RXDATA_PARERR UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0x9 0x1 read-only RXDATA_PARERR_CLR CLR 0 RXDATA_PARERR_SET SET 1 RXDATA_BRKERR UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0xA 0x1 read-only RXDATA_BRKERR_CLR CLR 0 RXDATA_BRKERR_SET SET 1 RXDATA_OVRERR UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. 0xB 0x1 read-only RXDATA_OVRERR_CLR CLR 0 RXDATA_OVRERR_SET SET 1 RXDATA_NERR Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0xC 0x1 read-only RXDATA_NERR_CLR CLR 0 RXDATA_NERR_SET SET 1 AMASK Self Address Mask Register 0x1148 32 read-write 0x000000ff 0xffffffff AMASK_VALUE Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match. 0x0 0x8 read-write ADDR Self Address Register 0x114C 32 read-write 0x00000000 0xffffffff ADDR_VALUE Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh. 0x0 0x8 read-write WWDT0 1.0 WWDT 0x40080000 0x0 0x1500 registers PWREN Power enable 0x800 32 read-write PWREN_ENABLE Enable the power Note: For safety devices the power cannot be disabled once enabled. 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear [GPRCM.STAT.RESETSTKY] 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible. 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write 0x00000000 PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 0x0 0x5 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_INTTIM INTTIM 1 IMASK Interrupt mask 0x1028 32 read-write 0x00000000 IMASK_INTTIM Interval Timer Interrupt. 0x0 0x1 IMASK_INTTIM_CLR CLR 0 IMASK_INTTIM_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 RIS_INTTIM Interval Timer Interrupt. 0x0 0x1 RIS_INTTIM_CLR CLR 0 RIS_INTTIM_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_INTTIM Interval Timer Interrupt. 0x0 0x1 MIS_INTTIM_CLR CLR 0 MIS_INTTIM_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_INTTIM Interval Timer Interrupt. 0x0 0x1 ISET_INTTIM_NO_EFFECT NO_EFFECT 0 ISET_INTTIM_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_INTTIM Interval Timer Interrupt. 0x0 0x1 ICLR_INTTIM_NO_EFFECT NO_EFFECT 0 ICLR_INTTIM_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 WWDTCTL0 Window Watchdog Timer Control Register 0 0x1100 32 read-write 0x00000043 0xffffffff WWDTCTL0_PER Timer Period of the WWDT. These bits select the total watchdog timer count. 0x4 0x3 read-write WWDTCTL0_PER_EN_25 EN_25 0 WWDTCTL0_PER_EN_21 EN_21 1 WWDTCTL0_PER_EN_18 EN_18 2 WWDTCTL0_PER_EN_15 EN_15 3 WWDTCTL0_PER_EN_12 EN_12 4 WWDTCTL0_PER_EN_10 EN_10 5 WWDTCTL0_PER_EN_8 EN_8 6 WWDTCTL0_PER_EN_6 EN_6 7 WWDTCTL0_WINDOW0 Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1). 0x8 0x3 read-write WWDTCTL0_WINDOW0_SIZE_0 SIZE_0 0 WWDTCTL0_WINDOW0_SIZE_12 SIZE_12 1 WWDTCTL0_WINDOW0_SIZE_18 SIZE_18 2 WWDTCTL0_WINDOW0_SIZE_25 SIZE_25 3 WWDTCTL0_WINDOW0_SIZE_50 SIZE_50 4 WWDTCTL0_WINDOW0_SIZE_75 SIZE_75 5 WWDTCTL0_WINDOW0_SIZE_81 SIZE_81 6 WWDTCTL0_WINDOW0_SIZE_87 SIZE_87 7 WWDTCTL0_MODE Window Watchdog Timer Mode 0x10 0x1 read-write WWDTCTL0_MODE_WINDOW WINDOW 0 WWDTCTL0_MODE_INTERVAL INTERVAL 1 WWDTCTL0_STISM Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported. 0x11 0x1 read-write WWDTCTL0_STISM_CONT CONT 0 WWDTCTL0_STISM_STOP STOP 1 WWDTCTL0_KEY KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0. 0x18 0x8 read-write WWDTCTL0_KEY_UNLOCK_W _TO_UNLOCK_W_ 201 WWDTCTL0_CLKDIV Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0. 0x0 0x3 read-write WWDTCTL0_WINDOW1 Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1). 0xC 0x3 read-write WWDTCTL0_WINDOW1_SIZE_0 SIZE_0 0 WWDTCTL0_WINDOW1_SIZE_12 SIZE_12 1 WWDTCTL0_WINDOW1_SIZE_18 SIZE_18 2 WWDTCTL0_WINDOW1_SIZE_25 SIZE_25 3 WWDTCTL0_WINDOW1_SIZE_50 SIZE_50 4 WWDTCTL0_WINDOW1_SIZE_75 SIZE_75 5 WWDTCTL0_WINDOW1_SIZE_81 SIZE_81 6 WWDTCTL0_WINDOW1_SIZE_87 SIZE_87 7 WWDTCTL1 Window Watchdog Timer Control Register 0 0x1104 32 read-write 0x00000000 0xffffffff WWDTCTL1_KEY KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0. 0x18 0x8 write-only WWDTCTL1_KEY_UNLOCK_W _TO_UNLOCK_W_ 190 WWDTCTL1_WINSEL Close Window Select 0x0 0x1 read-write WWDTCTL1_WINSEL_WIN0 WIN0 0 WWDTCTL1_WINSEL_WIN1 WIN1 1 WWDTCNTRST Window Watchdog Timer Counter Reset Register 0x1108 32 read-write 0x00000000 0xffffffff WWDTCNTRST_RESTART Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0. 0x0 0x20 read-write WWDTSTAT Window Watchdog Timer Status Register 0x110C 32 read-only 0x00000000 0xffffffff WWDTSTAT_RUN Watchdog running status flag. 0x0 0x1 read-only WWDTSTAT_RUN_OFF OFF 0 WWDTSTAT_RUN_ON ON 1 DEBUGSS 1.0 DSSM 0x400C7000 0x0 0x1F00 registers IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x8 IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_TXIFG TXIFG 1 IIDX_STAT_RXIFG RXIFG 2 IIDX_STAT_PWRUP PWRUP 3 IIDX_STAT_PWRDWN PWRDWN 4 IMASK Interrupt mask 0x1028 32 read-write 0x00000000 IMASK_TXIFG Masks TXIFG in MIS register 0x0 0x1 IMASK_TXIFG_CLR CLR 0 IMASK_TXIFG_SET SET 1 IMASK_RXIFG Masks RXIFG in MIS register 0x1 0x1 IMASK_RXIFG_CLR CLR 0 IMASK_RXIFG_SET SET 1 IMASK_PWRUPIFG Masks PWRUPIFG in MIS register 0x2 0x1 IMASK_PWRUPIFG_CLR CLR 0 IMASK_PWRUPIFG_SET SET 1 IMASK_PWRDWNIFG Masks PWRDWNIFG in MIS register 0x3 0x1 IMASK_PWRDWNIFG_CLR CLR 0 IMASK_PWRDWNIFG_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 RIS_TXIFG Raw interrupt status for TXIFG 0x0 0x1 RIS_TXIFG_CLR CLR 0 RIS_TXIFG_SET SET 1 RIS_RXIFG Raw interrupt status for RXIFG 0x1 0x1 RIS_RXIFG_CLR CLR 0 RIS_RXIFG_SET SET 1 RIS_PWRUPIFG Raw interrupt status for PWRUPIFG 0x2 0x1 RIS_PWRUPIFG_CLR CLR 0 RIS_PWRUPIFG_SET SET 1 RIS_PWRDWNIFG Raw interrupt status for PWRDWNIFG 0x3 0x1 RIS_PWRDWNIFG_CLR CLR 0 RIS_PWRDWNIFG_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_TXIFG Masked interrupt status for TXIFG 0x0 0x1 MIS_TXIFG_CLR CLR 0 MIS_TXIFG_SET SET 1 MIS_RXIFG Masked interrupt status for RXIFG 0x1 0x1 MIS_RXIFG_CLR CLR 0 MIS_RXIFG_SET SET 1 MIS_PWRUPIFG Masked interrupt status for PWRUPIFG 0x2 0x1 MIS_PWRUPIFG_CLR CLR 0 MIS_PWRUPIFG_SET SET 1 MIS_PWRDWNIFG Masked interrupt status for PWRDWNIFG 0x3 0x1 MIS_PWRDWNIFG_CLR CLR 0 MIS_PWRDWNIFG_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_TXIFG Sets TXIFG in RIS register 0x0 0x1 ISET_TXIFG_NO_EFFECT NO_EFFECT 0 ISET_TXIFG_SET SET 1 ISET_RXIFG Sets RXIFG in RIS register 0x1 0x1 ISET_RXIFG_NO_EFFECT NO_EFFECT 0 ISET_RXIFG_SET SET 1 ISET_PWRUPIFG Sets PWRUPIFG in RIS register 0x2 0x1 ISET_PWRUPIFG_NO_EFFECT NO_EFFECT 0 ISET_PWRUPIFG_SET SET 1 ISET_PWRDWNIFG Sets PWRDWNIFG in RIS register 0x3 0x1 ISET_PWRDWNIFG_NO_EFFECT NO_EFFECT 0 ISET_PWRDWNIFG_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_TXIFG Clears TXIFG in RIS register 0x0 0x1 ICLR_TXIFG_NO_EFFECT NO_EFFECT 0 ICLR_TXIFG_CLR CLR 1 ICLR_RXIFG Clears RXIFG in RIS register 0x1 0x1 ICLR_RXIFG_NO_EFFECT NO_EFFECT 0 ICLR_RXIFG_CLR CLR 1 ICLR_PWRUPIFG Clears PWRUPIFG in RIS register 0x2 0x1 ICLR_PWRUPIFG_NO_EFFECT NO_EFFECT 0 ICLR_PWRUPIFG_CLR CLR 1 ICLR_PWRDWNIFG Clears PWRDWNIFG in RIS register 0x3 0x1 ICLR_PWRDWNIFG_NO_EFFECT NO_EFFECT 0 ICLR_PWRDWNIFG_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-only EVT_MODE_INT0_CFG Event line mode select for peripheral events 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 TXD Transmit data register 0x1100 32 read-only 0x00000000 TXD_TX_DATA Contains data written by an external debug tool to the SEC-AP TXDATA register 0x0 0x20 read-only TXCTL Transmit control register 0x1104 32 read-only 0x00000000 TXCTL_TRANSMIT Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field. 0x0 0x1 read-only TXCTL_TRANSMIT_EMPTY EMPTY 0 TXCTL_TRANSMIT_FULL FULL 1 TXCTL_TRANSMIT_FLAGS Generic TX flags that can be set by external debug tool. Functionality is defined by SW. 0x1 0x1F read-only RXD Receive data register 0x1108 32 read-write 0x00000000 RXD_RX_DATA Contains data written by SM/OW. 0x0 0x20 read-write RXCTL Receive control register 0x110C 32 read-write 0x00000000 RXCTL_RECEIVE Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field. 0x0 0x1 read-only RXCTL_RECEIVE_EMPTY EMPTY 0 RXCTL_RECEIVE_FULL FULL 1 RXCTL_RECEIVE_FLAGS Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW. 0x1 0x7 read-write SPECIAL_AUTH Special enable authorization register 0x1200 32 read-only 0x00000013 SPECIAL_AUTH_SECAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP. 0x0 0x1 read-only SPECIAL_AUTH_SECAPEN_DISABLE DISABLE 0 SPECIAL_AUTH_SECAPEN_ENABLE ENABLE 1 SPECIAL_AUTH_SWDPORTEN When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access. 0x1 0x1 read-only SPECIAL_AUTH_SWDPORTEN_DISABLE DISABLE 0 SPECIAL_AUTH_SWDPORTEN_ENABLE ENABLE 1 SPECIAL_AUTH_DFTAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. 0x2 0x1 read-only SPECIAL_AUTH_DFTAPEN_DISABLE DISABLE 0 SPECIAL_AUTH_DFTAPEN_ENABLE ENABLE 1 SPECIAL_AUTH_ETAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. 0x3 0x1 read-only SPECIAL_AUTH_ETAPEN_DISABLE DISABLE 0 SPECIAL_AUTH_ETAPEN_ENABLE ENABLE 1 SPECIAL_AUTH_CFGAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP. 0x4 0x1 read-only SPECIAL_AUTH_CFGAPEN_DISABLE DISABLE 0 SPECIAL_AUTH_CFGAPEN_ENABLE ENABLE 1 SPECIAL_AUTH_AHBAPEN Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation. 0x5 0x1 read-only SPECIAL_AUTH_AHBAPEN_DISABLE DISABLE 0 SPECIAL_AUTH_AHBAPEN_ENABLE ENABLE 1 SPECIAL_AUTH_PWRAPEN An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access. 0x6 0x1 read-only SPECIAL_AUTH_PWRAPEN_DISABLE DISABLE 0 SPECIAL_AUTH_PWRAPEN_ENABLE ENABLE 1 APP_AUTH Application CPU0 authorization register 0x1210 32 read-only 0x00000000 APP_AUTH_DBGEN Controls invasive debug enable. 0x0 0x1 read-only APP_AUTH_DBGEN_DISABLE DISABLE 0 APP_AUTH_DBGEN_ENABLE ENABLE 1 APP_AUTH_NIDEN Controls non-invasive debug enable. 0x1 0x1 read-only APP_AUTH_NIDEN_DISABLE DISABLE 0 APP_AUTH_NIDEN_ENABLE ENABLE 1 APP_AUTH_SPIDEN Secure invasive debug enable. 0x2 0x1 read-only APP_AUTH_SPIDEN_DISABLE DISABLE 0 APP_AUTH_SPIDEN_ENABLE ENABLE 1 APP_AUTH_SPNIDEN Secure non-invasive debug enable. 0x3 0x1 read-only APP_AUTH_SPNIDEN_DISABLE DISABLE 0 APP_AUTH_SPNIDEN_ENABLE ENABLE 1 VREF 1.0 PERIPHERALREGION 0x40030000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 read-write CLKSEL Clock Selection 0x1008 32 read-write 0x00000000 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 read-only DESC_MAJREV Major rev of the IP 0x4 0x4 read-only DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only CTL0 Control 0 0x1100 32 read-write 0x00000000 CTL0_ENABLE This bit enables the VREF module. 0x0 0x1 read-write CTL0_ENABLE_DISABLE DISABLE 0 CTL0_ENABLE_ENABLE ENABLE 1 CTL0_ENABLEBIAS This bit enables the VREF Bias. 0x1 0x1 read-write CTL0_ENABLEBIAS_DISABLE DISABLE 0 CTL0_ENABLEBIAS_ENABLE ENABLE 1 CTL0_IBPROG There bits configure current bias. 0x2 0x2 read-write CTL0_IBPROG_NOMIBIAS NOMIBIAS 0 CTL0_IBPROG_IBPROG01 IBPROG01 1 CTL0_IBPROG_IBPROG10 IBPROG10 2 CTL0_IBPROG_IBPROG11 IBPROG11 3 CTL0_BUFCONFIG These bits configure output buffer. 0x7 0x1 read-write CTL0_BUFCONFIG_OUTPUT2P5V HV 0 CTL0_BUFCONFIG_OUTPUT1P4V LV 1 CTL0_SPARE These bits are reserved 0x9 0x4 read-write CTL0_SHMODE This bit enable sample and hold mode 0x8 0x1 read-write CTL0_SHMODE_DISABLE DISABLE 0 CTL0_SHMODE_ENABLE ENABLE 1 CTL1 Control 1 0x1104 32 read-write 0x00000000 CTL1_READY These bits defines status of VREF 0x0 0x1 read-only CTL1_READY_NOTRDY NOTRDY 0 CTL1_READY_RDY RDY 1 CTL1_VREFLOSEL This bit select VREFLO pin 0x1 0x1 read-write CTL2 Control 2 0x1108 32 read-write 0x00000000 CTL2_SHCYCLE Sample and hold cycle count 0x0 0x10 read-write CTL2_HCYCLE Hold cycle count 0x10 0x10 read-write CRC 1.0 PERIPHERALREGION 0x40440000 0x0 0x2000 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CRCCTRL CRC Control Register 0x1100 32 read-write 0x00000000 0x00000007 CRCCTRL_POLYSIZE This bit indicates which CRC calculation is performed by the generator. 0x0 0x1 read-write CRCCTRL_POLYSIZE_CRC32 CRC32 0 CRCCTRL_POLYSIZE_CRC16 CRC16 1 CRCCTRL_BITREVERSE CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT. 0x1 0x1 read-write CRCCTRL_BITREVERSE_NOT_REVERSED NOT_REVERSED 0 CRCCTRL_BITREVERSE_REVERSED REVERSED 1 CRCCTRL_INPUT_ENDIANNESS CRC Endian. This bit indicates the byte order within a word or half word of input data. 0x2 0x1 read-write CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN LITTLE_ENDIAN 0 CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN BIG_ENDIAN 1 CRCCTRL_OUTPUT_BYTESWAP CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0 0x4 0x1 read-write CRCCTRL_OUTPUT_BYTESWAP_DISABLE DISABLE 0 CRCCTRL_OUTPUT_BYTESWAP_ENABLE ENABLE 1 CRCSEED CRC Seed Register 0x1104 32 write-only 0x00000000 0xffffffff CRCSEED_SEED Seed Data 0x0 0x20 write-only CRCIN CRC Input Data Register 0x1108 32 write-only 0x00000000 0xffffffff CRCIN_DATA Input Data 0x0 0x20 write-only CRCOUT CRC Output Result Register 0x110C 32 read-only 0x00000000 0xffffffff CRCOUT_RESULT Result 0x0 0x20 read-only 512 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511 CRCIN_IDX[%s] CRC Input Data Array Register 0x1800 32 write-only 0x00000000 0xffffffff CRCIN_IDX_DATA Input Data 0x0 0x20 write-only OPA0 1.0 PERIPHERALREGION 0x40020000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 GPRCM_STAT Status Register 0x814 32 read-only GPRCM_STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only GPRCM_STAT_RESETSTKY_NORES NORES 0 GPRCM_STAT_RESETSTKY_RESET RESET 1 CLKOVR Clock Override 0x1010 32 read-write 0x00000000 CLKOVR_OVERRIDE Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request 0x0 0x1 read-write CLKOVR_OVERRIDE_DISABLED DISABLED 0 CLKOVR_OVERRIDE_ENABLED ENABLED 1 CLKOVR_RUN_STOP If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system 0x1 0x1 read-write CLKOVR_RUN_STOP_RUN RUN 0 CLKOVR_RUN_STOP_STOP STOP 1 PWRCTL Power Control 0x101C 32 read-write PWRCTL_AUTO_OFF When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled. 0x0 0x1 read-write PWRCTL_AUTO_OFF_DISABLE DISABLE 0 PWRCTL_AUTO_OFF_ENABLE ENABLE 1 CTL Control Register 0x1100 32 read-write 0x00000000 0x0000ffff CTL_ENABLE OAxn Enable. 0x0 0x1 read-write CTL_ENABLE_OFF OFF 0 CTL_ENABLE_ON ON 1 CFGBASE Configuration Base Register 0x1104 32 read-write 0x00000000 0x0000ffff CFGBASE_GBW Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0. 0x0 0x1 read-write CFGBASE_GBW_LOWGAIN LOWGAIN 0 CFGBASE_GBW_HIGHGAIN HIGHGAIN 1 CFGBASE_RRI Rail-to-rail input enable. Can only be modified when STAT.BUSY=0 0x2 0x1 read-write CFGBASE_RRI_OFF OFF 0 CFGBASE_RRI_ON ON 1 CFG Configuration Register 0x1108 32 read-write 0x00000000 0xffffffff CFG_CHOP Chopping enable. 0x0 0x2 read-write CFG_CHOP_OFF OFF 0 CFG_CHOP_ON ON 1 CFG_CHOP_AVGON AVGON 2 CFG_OUTPIN Enable output pin 0x2 0x1 read-write CFG_OUTPIN_DISABLED DISABLED 0 CFG_OUTPIN_ENABLED ENABLED 1 CFG_PSEL Positive OA input selection. Please refer to the device specific datasheet for exact channels available. 0x3 0x4 read-write CFG_PSEL_NC NC 0 CFG_PSEL_EXTPIN0 EXTPIN0 1 CFG_PSEL_EXTPIN1 EXTPIN1 2 CFG_PSEL_DAC12OUT DAC12OUT 3 CFG_PSEL_DAC8OUT DAC8OUT 4 CFG_PSEL_VREF VREF 5 CFG_PSEL_OANM1RTOP OANM1RTOP 6 CFG_PSEL_GPAMP_OUT_INT GPAMP_OUT_INT 7 CFG_PSEL_VSS VSS 8 CFG_NSEL Negative OA input selection. Please refer to the device specific datasheet for exact channels available. 0x7 0x3 read-write CFG_NSEL_NC NC 0 CFG_NSEL_EXTPIN0 EXTPIN0 1 CFG_NSEL_EXTPIN1 EXTPIN1 2 CFG_NSEL_OANP1RBOT OANP1RBOT 3 CFG_NSEL_OANRTAP OANRTAP 4 CFG_NSEL_OANRTOP OANRTOP 5 CFG_NSEL_SPARE SPARE 6 CFG_MSEL MSEL Mux selection. Please refer to the device specific datasheet for exact channels available. 0xA 0x3 read-write CFG_MSEL_NC NC 0 CFG_MSEL_EXTNPIN1 EXTNPIN1 1 CFG_MSEL_VSS VSS 2 CFG_MSEL_DAC12OUT DAC12OUT 3 CFG_MSEL_OANM1RTOP OANM1RTOP 4 CFG_GAIN Gain setting. Refer to TRM for enumeration information. 0xD 0x3 read-write STAT Status Register 0x1118 32 read-only 0x00000000 0x0000ffff STAT_RDY OA ready status. 0x0 0x1 read-only STAT_RDY_FALSE FALSE 0 STAT_RDY_TRUE TRUE 1 TIMG1 1.0 PERIPHERALREGION 0x40086000 0x0 0x1F00 registers FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 FPUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x8 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_Z Z 1 IIDX_STAT_L L 2 IIDX_STAT_CCD0 CCD0 5 IIDX_STAT_CCD1 CCD1 6 IIDX_STAT_CCD2 CCD2 7 IIDX_STAT_CCD3 CCD3 8 IIDX_STAT_CCU0 CCU0 9 IIDX_STAT_CCU1 CCU1 10 IIDX_STAT_CCU2 CCU2 11 IIDX_STAT_CCU3 CCU3 12 IIDX_STAT_CCD4 CCD4 13 IIDX_STAT_CCD5 CCD5 14 IIDX_STAT_CCU4 CCU4 15 IIDX_STAT_CCU5 CCU5 16 IIDX_STAT_F F 25 IIDX_STAT_TOV TOV 26 IIDX_STAT_REPC REPC 27 IIDX_STAT_DC DC 28 IIDX_STAT_QEIERR QEIERR 29 IMASK Interrupt mask 0x1028 32 read-write IMASK_Z Zero Event mask 0x0 0x1 IMASK_Z_CLR CLR 0 IMASK_Z_SET SET 1 IMASK_L Load Event mask 0x1 0x1 IMASK_L_CLR CLR 0 IMASK_L_SET SET 1 IMASK_CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 IMASK_CCD0_CLR CLR 0 IMASK_CCD0_SET SET 1 IMASK_CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 IMASK_CCD1_CLR CLR 0 IMASK_CCD1_SET SET 1 IMASK_CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 IMASK_CCU0_CLR CLR 0 IMASK_CCU0_SET SET 1 IMASK_CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 IMASK_CCU1_CLR CLR 0 IMASK_CCU1_SET SET 1 IMASK_TOV Trigger Overflow Event mask 0x19 0x1 IMASK_TOV_CLR CLR 0 IMASK_TOV_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 0xffffffff RIS_Z Zero event generated an interrupt. 0x0 0x1 RIS_Z_CLR CLR 0 RIS_Z_SET SET 1 RIS_L Load event generated an interrupt. 0x1 0x1 RIS_L_CLR CLR 0 RIS_L_SET SET 1 RIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 RIS_CCD0_CLR CLR 0 RIS_CCD0_SET SET 1 RIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 RIS_CCD1_CLR CLR 0 RIS_CCD1_SET SET 1 RIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 RIS_CCU0_CLR CLR 0 RIS_CCU0_SET SET 1 RIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 RIS_CCU1_CLR CLR 0 RIS_CCU1_SET SET 1 RIS_TOV Trigger overflow 0x19 0x1 RIS_TOV_CLR CLR 0 RIS_TOV_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_Z Zero event generated an interrupt. 0x0 0x1 MIS_Z_CLR CLR 0 MIS_Z_SET SET 1 MIS_L Load event generated an interrupt. 0x1 0x1 MIS_L_CLR CLR 0 MIS_L_SET SET 1 MIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 MIS_CCD0_CLR CLR 0 MIS_CCD0_SET SET 1 MIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 MIS_CCD1_CLR CLR 0 MIS_CCD1_SET SET 1 MIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 MIS_CCU0_CLR CLR 0 MIS_CCU0_SET SET 1 MIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 MIS_CCU1_CLR CLR 0 MIS_CCU1_SET SET 1 MIS_TOV Trigger overflow 0x19 0x1 MIS_TOV_CLR CLR 0 MIS_TOV_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_Z Zero event SET 0x0 0x1 ISET_Z_NO_EFFECT NO_EFFECT 0 ISET_Z_SET SET 1 ISET_L Load event SET 0x1 0x1 ISET_L_NO_EFFECT NO_EFFECT 0 ISET_L_SET SET 1 ISET_CCD0 Capture or compare down event SET 0x4 0x1 ISET_CCD0_NO_EFFECT NO_EFFECT 0 ISET_CCD0_SET SET 1 ISET_CCD1 Capture or compare down event SET 0x5 0x1 ISET_CCD1_NO_EFFECT NO_EFFECT 0 ISET_CCD1_SET SET 1 ISET_CCU0 Capture or compare up event SET 0x8 0x1 ISET_CCU0_NO_EFFECT NO_EFFECT 0 ISET_CCU0_SET SET 1 ISET_CCU1 Capture or compare up event SET 0x9 0x1 ISET_CCU1_NO_EFFECT NO_EFFECT 0 ISET_CCU1_SET SET 1 ISET_TOV Trigger Overflow event SET 0x19 0x1 ISET_TOV_NO_EFFECT NO_EFFECT 0 ISET_TOV_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_Z Zero event CLEAR 0x0 0x1 ICLR_Z_NO_EFFECT NO_EFFECT 0 ICLR_Z_CLR CLR 1 ICLR_L Load event CLEAR 0x1 0x1 ICLR_L_NO_EFFECT NO_EFFECT 0 ICLR_L_CLR CLR 1 ICLR_CCD0 Capture or compare down event CLEAR 0x4 0x1 ICLR_CCD0_NO_EFFECT NO_EFFECT 0 ICLR_CCD0_CLR CLR 1 ICLR_CCD1 Capture or compare down event CLEAR 0x5 0x1 ICLR_CCD1_NO_EFFECT NO_EFFECT 0 ICLR_CCD1_CLR CLR 1 ICLR_CCU0 Capture or compare up event CLEAR 0x8 0x1 ICLR_CCU0_NO_EFFECT NO_EFFECT 0 ICLR_CCU0_CLR CLR 1 ICLR_CCU1 Capture or compare up event CLEAR 0x9 0x1 ICLR_CCU1_NO_EFFECT NO_EFFECT 0 ICLR_CCU1_CLR CLR 1 ICLR_TOV Trigger Overflow event CLEAR 0x19 0x1 ICLR_TOV_NO_EFFECT NO_EFFECT 0 ICLR_TOV_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT_MODE_EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only EVT_MODE_EVT0_CFG_DISABLE DISABLE 0 EVT_MODE_EVT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CCPD CCP Direction 0x1100 32 read-write CCPD_C0CCP0 Counter CCP0 0x0 0x1 CCPD_C0CCP0_INPUT INPUT 0 CCPD_C0CCP0_OUTPUT OUTPUT 1 CCPD_C0CCP1 Counter CCP1 0x1 0x1 CCPD_C0CCP1_INPUT INPUT 0 CCPD_C0CCP1_OUTPUT OUTPUT 1 ODIS Output Disable 0x1104 32 read-write ODIS_C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write ODIS_C0CCP0_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP0_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 ODIS_C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write ODIS_C0CCP1_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP1_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 CCLKCTL Counter Clock Control Register 0x1108 32 read-write CCLKCTL_CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write CCLKCTL_CLKEN_DISABLED DISABLED 0 CCLKCTL_CLKEN_ENABLED ENABLED 1 CPS Clock Prescale Register 0x110C 32 read-write CPS_PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write CPSV Clock prescale count status register 0x1110 32 read-only CPSV_CPSVAL Current Prescale Count Value 0x0 0x8 read-only CTTRIGCTL Timer Cross Trigger Control Register 0x1114 32 read-write CTTRIGCTL_CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write CTTRIGCTL_CTEN_DISABLED DISABLED 0 CTTRIGCTL_CTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write CTTRIGCTL_EVTCTEN_DISABLED DISABLED 0 CTTRIGCTL_EVTCTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write CTTRIGCTL_EVTCTTRIGSEL_FSUB0 FSUB0 0 CTTRIGCTL_EVTCTTRIGSEL_FSUB1 FSUB1 1 CTTRIGCTL_EVTCTTRIGSEL_Z Z 2 CTTRIGCTL_EVTCTTRIGSEL_L L 3 CTTRIGCTL_EVTCTTRIGSEL_CCD0 CCD0 4 CTTRIGCTL_EVTCTTRIGSEL_CCD1 CCD1 5 CTTRIGCTL_EVTCTTRIGSEL_CCD2 CCD2 6 CTTRIGCTL_EVTCTTRIGSEL_CCD3 CCD3 7 CTTRIGCTL_EVTCTTRIGSEL_CCU0 CCU0 8 CTTRIGCTL_EVTCTTRIGSEL_CCU1 CCU1 9 CTTRIGCTL_EVTCTTRIGSEL_CCU2 CCU2 10 CTTRIGCTL_EVTCTTRIGSEL_CCU3 CCU3 11 CTTRIG Timer Cross Trigger Register 0x111C 32 write-only CTTRIG_TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only CTTRIG_TRIG_DISABLED DISABLED 0 CTTRIG_TRIG_GENERATE GENERATE 1 CTR Counter Register 0x1800 32 read-write 0x00000000 0xffffffff CTR_CCTR Current Counter value 0x0 0x10 read-write CTRCTL Counter Control Register 0x1804 32 read-write 0x0000ff80 0xffffffff CTRCTL_EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write CTRCTL_EN_DISABLED DISABLED 0 CTRCTL_EN_ENABLED ENABLED 1 CTRCTL_REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write CTRCTL_REPEAT_REPEAT_0 REPEAT_0 0 CTRCTL_REPEAT_REPEAT_1 REPEAT_1 1 CTRCTL_REPEAT_REPEAT_2 REPEAT_2 2 CTRCTL_REPEAT_REPEAT_3 REPEAT_3 3 CTRCTL_REPEAT_REPEAT_4 REPEAT_4 4 CTRCTL_CM Count Mode 0x4 0x2 read-write CTRCTL_CM_DOWN DOWN 0 CTRCTL_CM_UP_DOWN UP_DOWN 1 CTRCTL_CM_UP UP 2 CTRCTL_CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write CTRCTL_CVAE_LDVAL LDVAL 0 CTRCTL_CVAE_NOCHANGE NOCHANGE 1 CTRCTL_CVAE_ZEROVAL ZEROVAL 2 CTRCTL_DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write CTRCTL_DRB_RESUME RESUME 0 CTRCTL_DRB_CVAE_ACTION CVAE_ACTION 1 CTRCTL_CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CTRCTL_CLC_CCCTL0_LCOND CCCTL0_LCOND 0 CTRCTL_CLC_CCCTL1_LCOND CCCTL1_LCOND 1 CTRCTL_CLC_CCCTL2_LCOND CCCTL2_LCOND 2 CTRCTL_CLC_CCCTL3_LCOND CCCTL3_LCOND 3 CTRCTL_CLC_QEI_2INP QEI_2INP 4 CTRCTL_CLC_QEI_3INP QEI_3INP 5 CTRCTL_CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CTRCTL_CAC_CCCTL0_ACOND CCCTL0_ACOND 0 CTRCTL_CAC_CCCTL1_ACOND CCCTL1_ACOND 1 CTRCTL_CAC_CCCTL2_ACOND CCCTL2_ACOND 2 CTRCTL_CAC_CCCTL3_ACOND CCCTL3_ACOND 3 CTRCTL_CAC_QEI_2INP QEI_2INP 4 CTRCTL_CAC_QEI_3INP QEI_3INP 5 CTRCTL_CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CTRCTL_CZC_CCCTL0_ZCOND CCCTL0_ZCOND 0 CTRCTL_CZC_CCCTL1_ZCOND CCCTL1_ZCOND 1 CTRCTL_CZC_CCCTL2_ZCOND CCCTL2_ZCOND 2 CTRCTL_CZC_CCCTL3_ZCOND CCCTL3_ZCOND 3 CTRCTL_CZC_QEI_2INP QEI_2INP 4 CTRCTL_CZC_QEI_3INP QEI_3INP 5 LOAD Load Register 0x1808 32 read-write 0x00000000 0xffffffff LOAD_LD Load Value 0x0 0x10 read-write 2 4 0,1 CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x1810 32 read-write 0x00000000 0xffffffff CC_01_CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 CCCTL_01[%s] Capture or Compare Control Registers 0x1830 32 read-write 0x00000000 0xffffffff CCCTL_01_CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write CCCTL_01_CCOND_NOCAPTURE NOCAPTURE 0 CCCTL_01_CCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_CCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_CCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write CCCTL_01_ACOND_TIMCLK TIMCLK 0 CCCTL_01_ACOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ACOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ACOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND_CC_TRIG_HIGH CC_TRIG_HIGH 5 CCCTL_01_LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CCCTL_01_LCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_LCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_LCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CCCTL_01_ZCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ZCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ZCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write CCCTL_01_COC_COMPARE COMPARE 0 CCCTL_01_COC_CAPTURE CAPTURE 1 CCCTL_01_CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write CCCTL_01_CCACTUPD_IMMEDIATELY IMMEDIATELY 0 CCCTL_01_CCACTUPD_ZERO_EVT ZERO_EVT 1 CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT COMPARE_DOWN_EVT 2 CCCTL_01_CCACTUPD_COMPARE_UP_EVT COMPARE_UP_EVT 3 CCCTL_01_CCACTUPD_ZERO_LOAD_EVT ZERO_LOAD_EVT 4 CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT ZERO_RC_ZERO_EVT 5 CCCTL_01_CCACTUPD_TRIG TRIG 6 CCCTL_01_CC2SELU Selects the source second CCU event. 0x16 0x3 CCCTL_01_CC2SELU_SEL_CCU0 SEL_CCU0 0 CCCTL_01_CC2SELU_SEL_CCU1 SEL_CCU1 1 CCCTL_01_CC2SELU_SEL_CCU2 SEL_CCU2 2 CCCTL_01_CC2SELU_SEL_CCU3 SEL_CCU3 3 CCCTL_01_CC2SELU_SEL_CCU4 SEL_CCU4 4 CCCTL_01_CC2SELU_SEL_CCU5 SEL_CCU5 5 CCCTL_01_CC2SELD Selects the source second CCD event. 0x1D 0x3 CCCTL_01_CC2SELD_SEL_CCD0 SEL_CCD0 0 CCCTL_01_CC2SELD_SEL_CCD1 SEL_CCD1 1 CCCTL_01_CC2SELD_SEL_CCD2 SEL_CCD2 2 CCCTL_01_CC2SELD_SEL_CCD3 SEL_CCD3 3 CCCTL_01_CC2SELD_SEL_CCD4 SEL_CCD4 4 CCCTL_01_CC2SELD_SEL_CCD5 SEL_CCD5 5 2 4 0,1 OCTL_01[%s] CCP Output Control Registers 0x1850 32 read-write 0x00000000 0xffffffff OCTL_01_CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write OCTL_01_CCPOINV_NOINV NOINV 0 OCTL_01_CCPOINV_INV INV 1 OCTL_01_CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write OCTL_01_CCPIV_LOW LOW 0 OCTL_01_CCPIV_HIGH HIGH 1 OCTL_01_CCPO CCP Output Source 0x0 0x4 read-write OCTL_01_CCPO_FUNCVAL FUNCVAL 0 OCTL_01_CCPO_LOAD LOAD 1 OCTL_01_CCPO_CMPVAL CMPVAL 2 OCTL_01_CCPO_ZERO ZERO 4 OCTL_01_CCPO_CAPCOND CAPCOND 5 OCTL_01_CCPO_FAULTCOND FAULTCOND 6 OCTL_01_CCPO_CC0_MIRROR_ALL CC0_MIRROR_ALL 8 OCTL_01_CCPO_CC1_MIRROR_ALL CC1_MIRROR_ALL 9 OCTL_01_CCPO_DEADBAND DEADBAND 12 OCTL_01_CCPO_CNTDIR CNTDIR 13 2 4 0,1 CCACT_01[%s] Capture or Compare Action Registers 0x1870 32 read-write 0x00000000 0xffffffff CCACT_01_ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write CCACT_01_ZACT_DISABLED DISABLED 0 CCACT_01_ZACT_CCP_HIGH CCP_HIGH 1 CCACT_01_ZACT_CCP_LOW CCP_LOW 2 CCACT_01_ZACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write CCACT_01_LACT_DISABLED DISABLED 0 CCACT_01_LACT_CCP_HIGH CCP_HIGH 1 CCACT_01_LACT_CCP_LOW CCP_LOW 2 CCACT_01_LACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write CCACT_01_CDACT_DISABLED DISABLED 0 CCACT_01_CDACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CDACT_CCP_LOW CCP_LOW 2 CCACT_01_CDACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write CCACT_01_CUACT_DISABLED DISABLED 0 CCACT_01_CUACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CUACT_CCP_LOW CCP_LOW 2 CCACT_01_CUACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write CCACT_01_CC2DACT_DISABLED DISABLED 0 CCACT_01_CC2DACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2DACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2DACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write CCACT_01_CC2UACT_DISABLED DISABLED 0 CCACT_01_CC2UACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2UACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2UACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_SWFRCACT CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write CCACT_01_SWFRCACT_DISABLED DISABLED 0 CCACT_01_SWFRCACT_CCP_HIGH CCP_HIGH 1 CCACT_01_SWFRCACT_CCP_LOW CCP_LOW 2 2 4 0,1 IFCTL_01[%s] Input Filter Control Register 0x1880 32 read-write 0x00000000 0xffffffff IFCTL_01_ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write IFCTL_01_ISEL_CCPX_INPUT CCPX_INPUT 0 IFCTL_01_ISEL_CCPX_INPUT_PAIR CCPX_INPUT_PAIR 1 IFCTL_01_ISEL_CCP0_INPUT CCP0_INPUT 2 IFCTL_01_ISEL_TRIG_INPUT TRIG_INPUT 3 IFCTL_01_ISEL_CCP_XOR CCP_XOR 4 IFCTL_01_ISEL_FSUB0 FSUB0 5 IFCTL_01_ISEL_FSUB1 FSUB1 6 IFCTL_01_ISEL_COMP0 COMP0 7 IFCTL_01_ISEL_COMP1 COMP1 8 IFCTL_01_ISEL_COMP2 COMP2 9 IFCTL_01_INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write IFCTL_01_INV_NOINVERT NOINVERT 0 IFCTL_01_INV_INVERT INVERT 1 IFCTL_01_FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write IFCTL_01_FP__3 _3 0 IFCTL_01_FP__5 _5 1 IFCTL_01_FP__8 _8 2 IFCTL_01_CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write IFCTL_01_CPV_CONSECUTIVE CONSECUTIVE 0 IFCTL_01_CPV_VOTING VOTING 1 IFCTL_01_FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write IFCTL_01_FE_DISABLED DISABLED 0 IFCTL_01_FE_ENABLED ENABLED 1 TSEL Trigger Select 0x18B0 32 read-write 0x00000000 0xffffffff TSEL_ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TSEL_ETSEL_TRIG0 TRIG0 0 TSEL_ETSEL_TRIG1 TRIG1 1 TSEL_ETSEL_TRIG2 TRIG2 2 TSEL_ETSEL_TRIG3 TRIG3 3 TSEL_ETSEL_TRIG4 TRIG4 4 TSEL_ETSEL_TRIG5 TRIG5 5 TSEL_ETSEL_TRIG6 TRIG6 6 TSEL_ETSEL_TRIG7 TRIG7 7 TSEL_ETSEL_TRIG8 TRIG8 8 TSEL_ETSEL_TRIG9 TRIG9 9 TSEL_ETSEL_TRIG10 TRIG10 10 TSEL_ETSEL_TRIG11 TRIG11 11 TSEL_ETSEL_TRIG12 TRIG12 12 TSEL_ETSEL_TRIG13 TRIG13 13 TSEL_ETSEL_TRIG14 TRIG14 14 TSEL_ETSEL_TRIG15 TRIG15 15 TSEL_ETSEL_TRIG_SUB0 TRIG_SUB0 16 TSEL_ETSEL_TRIG_SUB1 TRIG_SUB1 17 TSEL_TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write TSEL_TE_DISABLED DISABLED 0 TSEL_TE_ENABLED ENABLED 1 DMA 1.0 PERIPHERALREGION 0x4042A000 0x0 0x1F00 registers FSUB_0 Subscriber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-255 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-255 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Port 0 0x444 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-255 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x8 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_DMACH0 DMACH0 1 IIDX_STAT_DMACH1 DMACH1 2 IIDX_STAT_DMACH2 DMACH2 3 IIDX_STAT_DMACH3 DMACH3 4 IIDX_STAT_DMACH4 DMACH4 5 IIDX_STAT_DMACH5 DMACH5 6 IIDX_STAT_DMACH6 DMACH6 7 IIDX_STAT_DMACH7 DMACH7 8 IIDX_STAT_DMACH8 DMACH8 9 IIDX_STAT_DMACH9 DMACH9 10 IIDX_STAT_DMACH10 DMACH10 11 IIDX_STAT_DMACH11 DMACH11 12 IIDX_STAT_DMACH12 DMACH12 13 IIDX_STAT_DMACH13 DMACH13 14 IIDX_STAT_DMACH14 DMACH14 15 IIDX_STAT_DMACH15 DMACH15 16 IIDX_STAT_PREIRQCH0 PREIRQCH0 17 IIDX_STAT_PREIRQCH1 PREIRQCH1 18 IIDX_STAT_PREIRQCH2 PREIRQCH2 19 IIDX_STAT_PREIRQCH3 PREIRQCH3 20 IIDX_STAT_PREIRQCH4 PREIRQCH4 21 IIDX_STAT_PREIRQCH5 PREIRQCH5 22 IIDX_STAT_PREIRQCH6 PREIRQCH6 23 IIDX_STAT_PREIRQCH7 PREIRQCH7 24 IIDX_STAT_ADDRERR ADDRERR 25 IIDX_STAT_DATAERR DATAERR 26 IMASK Interrupt mask 0x1028 32 read-write 0x00000000 IMASK_DMACH0 DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0). 0x0 0x1 IMASK_DMACH0_CLR CLR 0 IMASK_DMACH0_SET SET 1 IMASK_DMACH1 DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0). 0x1 0x1 read-write IMASK_DMACH1_CLR CLR 0 IMASK_DMACH1_SET SET 1 IMASK_DMACH2 DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0). 0x2 0x1 IMASK_DMACH2_CLR CLR 0 IMASK_DMACH2_SET SET 1 IMASK_PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 IMASK_PREIRQCH0_CLR CLR 0 IMASK_PREIRQCH0_SET SET 1 IMASK_ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 IMASK_ADDRERR_CLR CLR 0 IMASK_ADDRERR_SET SET 1 IMASK_DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 IMASK_DATAERR_CLR CLR 0 IMASK_DATAERR_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 RIS_DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 RIS_DMACH0_CLR CLR 0 RIS_DMACH0_SET SET 1 RIS_DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 RIS_DMACH1_CLR CLR 0 RIS_DMACH1_SET SET 1 RIS_DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 RIS_DMACH2_CLR CLR 0 RIS_DMACH2_SET SET 1 RIS_PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 RIS_PREIRQCH0_CLR CLR 0 RIS_PREIRQCH0_SET SET 1 RIS_ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 RIS_ADDRERR_CLR CLR 0 RIS_ADDRERR_SET SET 1 RIS_DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 RIS_DATAERR_CLR CLR 0 RIS_DATAERR_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 MIS_DMACH0_CLR CLR 0 MIS_DMACH0_SET SET 1 MIS_DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 MIS_DMACH1_CLR CLR 0 MIS_DMACH1_SET SET 1 MIS_DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 MIS_DMACH2_CLR CLR 0 MIS_DMACH2_SET SET 1 MIS_PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 MIS_PREIRQCH0_CLR CLR 0 MIS_PREIRQCH0_SET SET 1 MIS_ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 MIS_ADDRERR_CLR CLR 0 MIS_ADDRERR_SET SET 1 MIS_DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 MIS_DATAERR_CLR CLR 0 MIS_DATAERR_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 ISET_DMACH0_NO_EFFECT NO_EFFECT 0 ISET_DMACH0_SET SET 1 ISET_DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 ISET_DMACH1_NO_EFFECT NO_EFFECT 0 ISET_DMACH1_SET SET 1 ISET_DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 ISET_DMACH2_NO_EFFECT NO_EFFECT 0 ISET_DMACH2_SET SET 1 ISET_PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 ISET_PREIRQCH0_CLR CLR 0 ISET_PREIRQCH0_SET SET 1 ISET_ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 ISET_ADDRERR_CLR CLR 0 ISET_ADDRERR_SET SET 1 ISET_DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 ISET_DATAERR_CLR CLR 0 ISET_DATAERR_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_DMACH0 DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0). 0x0 0x1 ICLR_DMACH0_NO_EFFECT NO_EFFECT 0 ICLR_DMACH0_CLR CLR 1 ICLR_DMACH1 DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0). 0x1 0x1 ICLR_DMACH1_NO_EFFECT NO_EFFECT 0 ICLR_DMACH1_CLR CLR 1 ICLR_DMACH2 DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0). 0x2 0x1 ICLR_DMACH2_NO_EFFECT NO_EFFECT 0 ICLR_DMACH2_CLR CLR 1 ICLR_PREIRQCH0 Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold. 0x10 0x1 ICLR_PREIRQCH0_CLR CLR 0 ICLR_PREIRQCH0_SET SET 1 ICLR_ADDRERR DMA address error, SRC address not reachable. 0x18 0x1 ICLR_ADDRERR_CLR CLR 0 ICLR_ADDRERR_SET SET 1 ICLR_DATAERR DMA data error, SRC data might be corrupted (PAR or ECC error). 0x19 0x1 ICLR_DATAERR_CLR CLR 0 ICLR_DATAERR_SET SET 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to interrupt event INT_EVENT[0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to generic event INT_EVENT[1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_FEATUREVER Feature Set for the DMA: number of DMA channel minus one (e.g. 0->1ch, 2->3ch, 15->16ch). 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 DMAPRIO DMA Channel Priority Control 0x1100 32 read-write DMAPRIO_ROUNDROBIN Round robin. This bit enables the round-robin DMA channel priorities. 0x0 0x1 DMAPRIO_ROUNDROBIN_DISABLE DISABLE 0 DMAPRIO_ROUNDROBIN_ENABLE ENABLE 1 DMAPRIO_BURSTSZ Define the burst size of a block transfer, before the priority is re-evaluated 0x10 0x2 DMAPRIO_BURSTSZ_INFINITI INFINITI 0 DMAPRIO_BURSTSZ_BURST_8 BURST_8 1 DMAPRIO_BURSTSZ_BUSRT_16 BUSRT_16 2 DMAPRIO_BURSTSZ_BURST_32 BURST_32 3 DMATCTL DMA Trigger Select 0x1110 32 read-write DMATCTL_DMATSEL DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping. 0x0 0x6 DMATCTL_DMATSEL_DMAREQ DMAREQ 0 DMATCTL_DMATINT DMA Trigger by Internal Channel 0x7 0x1 DMATCTL_DMATINT_EXTERNAL EXTERNAL 0 DMATCTL_DMATINT_INTERNAL INTERNAL 1 DMACTL DMA Channel Control 0x1200 32 read-write DMACTL_DMAREQ DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0x0 0x1 DMACTL_DMAREQ_IDLE IDLE 0 DMACTL_DMAREQ_REQUEST REQUEST 1 DMACTL_DMAEN DMA enable 0x1 0x1 DMACTL_DMAEN_DISABLE DISABLE 0 DMACTL_DMAEN_ENABLE ENABLE 1 DMACTL_DMASRCWDTH DMA source width. This bit selects the source data width as a byte, half word, word or long word. 0x8 0x2 DMACTL_DMASRCWDTH_BYTE BYTE 0 DMACTL_DMASRCWDTH_HALF HALF 1 DMACTL_DMASRCWDTH_WORD WORD 2 DMACTL_DMASRCWDTH_LONG LONG 3 DMACTL_DMADSTWDTH DMA destination width. This bit selects the destination as a byte, half word, word or long word. 0xC 0x2 DMACTL_DMADSTWDTH_BYTE BYTE 0 DMACTL_DMADSTWDTH_HALF HALF 1 DMACTL_DMADSTWDTH_WORD WORD 2 DMACTL_DMADSTWDTH_LONG LONG 3 DMACTL_DMASRCINCR DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4. 0x10 0x4 DMACTL_DMASRCINCR_UNCHANGED UNCHANGED 0 DMACTL_DMASRCINCR_DECREMENT DECREMENT 2 DMACTL_DMASRCINCR_INCREMENT INCREMENT 3 DMACTL_DMASRCINCR_STRIDE_2 STRIDE_2 8 DMACTL_DMASRCINCR_STRIDE_3 STRIDE_3 9 DMACTL_DMASRCINCR_STRIDE_4 STRIDE_4 10 DMACTL_DMASRCINCR_STRIDE_5 STRIDE_5 11 DMACTL_DMASRCINCR_STRIDE_6 STRIDE_6 12 DMACTL_DMASRCINCR_STRIDE_7 STRIDE_7 13 DMACTL_DMASRCINCR_STRIDE_8 STRIDE_8 14 DMACTL_DMASRCINCR_STRIDE_9 STRIDE_9 15 DMACTL_DMADSTINCR DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4. 0x14 0x4 DMACTL_DMADSTINCR_UNCHANGED UNCHANGED 0 DMACTL_DMADSTINCR_DECREMENT DECREMENT 2 DMACTL_DMADSTINCR_INCREMENT INCREMENT 3 DMACTL_DMADSTINCR_STRIDE_2 STRIDE_2 8 DMACTL_DMADSTINCR_STRIDE_3 STRIDE_3 9 DMACTL_DMADSTINCR_STRIDE_4 STRIDE_4 10 DMACTL_DMADSTINCR_STRIDE_5 STRIDE_5 11 DMACTL_DMADSTINCR_STRIDE_6 STRIDE_6 12 DMACTL_DMADSTINCR_STRIDE_7 STRIDE_7 13 DMACTL_DMADSTINCR_STRIDE_8 STRIDE_8 14 DMACTL_DMADSTINCR_STRIDE_9 STRIDE_9 15 DMACTL_DMATM DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set. 0x1C 0x2 DMACTL_DMATM_SINGLE SINGLE 0 DMACTL_DMATM_BLOCK BLOCK 1 DMACTL_DMATM_RPTSNGL RPTSNGL 2 DMACTL_DMATM_RPTBLCK RPTBLCK 3 DMACTL_DMAEM DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0. 0x18 0x2 DMACTL_DMAEM_NORMAL NORMAL 0 DMACTL_DMAEM_FILLMODE FILLMODE 2 DMACTL_DMAEM_TABLEMODE TABLEMODE 3 DMACTL_DMAPREIRQ Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0. 0x4 0x3 DMACTL_DMAPREIRQ_PREIRQ_DISABLE PREIRQ_DISABLE 0 DMACTL_DMAPREIRQ_PREIRQ_1 PREIRQ_1 1 DMACTL_DMAPREIRQ_PREIRQ_2 PREIRQ_2 2 DMACTL_DMAPREIRQ_PREIRQ_4 PREIRQ_4 3 DMACTL_DMAPREIRQ_PREIRQ_8 PREIRQ_8 4 DMACTL_DMAPREIRQ_PREIRQ_32 PREIRQ_32 5 DMACTL_DMAPREIRQ_PREIRQ_64 PREIRQ_64 6 DMACTL_DMAPREIRQ_PREIRQ_HALF PREIRQ_HALF 7 DMASA DMA Channel Source Address 0x1204 32 read-write DMASA_ADDR DMA Channel Source Address 0x0 0x20 DMADA DMA Channel Destination Address 0x1208 32 read-write DMADA_ADDR DMA Channel Destination Address 0x0 0x20 DMASZ DMA Channel Size 0x120C 32 read-write DMASZ_SIZE DMA Channel Size in number of transfers 0x0 0x10 COMP0 1.0 PERIPHERALREGION 0x40008000 0x0 0x1F00 registers FSUB_0 Subscriber Port 0 0x400 32 read-write FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher port 1 0x444 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG Peripheral Clock Configuration Register 0x808 32 read-write 0x00000000 CLKCFG_KEY KEY to Allow State Change -- 0xA9 0x18 0x8 write-only CLKCFG_KEY_UNLOCK _UNLOCK_W_ 169 CLKCFG_BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write CLKCFG_BLOCKASYNC_DISABLE DISABLE 0 CLKCFG_BLOCKASYNC_ENABLE ENABLE 1 GPRCM_STAT Status Register 0x814 32 read-only GPRCM_STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only GPRCM_STAT_RESETSTKY_NORES NORES 0 GPRCM_STAT_RESETSTKY_RESET RESET 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x2 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_OUTRDYIFG OUTRDYIFG 1 IIDX_STAT_COMPIFG COMPIFG 2 IIDX_STAT_COMPINVIFG COMPINVIFG 3 IMASK Interrupt mask 0x1028 32 read-write 0x00000000 IMASK_COMPIFG Masks COMPIFG 0x1 0x1 IMASK_COMPIFG_CLR CLR 0 IMASK_COMPIFG_SET SET 1 IMASK_COMPINVIFG Masks COMPINVIFG 0x2 0x1 IMASK_COMPINVIFG_CLR CLR 0 IMASK_COMPINVIFG_SET SET 1 IMASK_OUTRDYIFG Masks OUTRDYIFG 0x3 0x1 IMASK_OUTRDYIFG_CLR CLR 0 IMASK_OUTRDYIFG_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 RIS_COMPIFG Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x1 0x1 RIS_COMPIFG_CLR CLR 0 RIS_COMPIFG_SET SET 1 RIS_COMPINVIFG Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit. 0x2 0x1 RIS_COMPINVIFG_CLR CLR 0 RIS_COMPINVIFG_SET SET 1 RIS_OUTRDYIFG Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid. 0x3 0x1 RIS_OUTRDYIFG_CLR CLR 0 RIS_OUTRDYIFG_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_COMPIFG Masked interrupt status for COMPIFG 0x1 0x1 MIS_COMPIFG_CLR CLR 0 MIS_COMPIFG_SET SET 1 MIS_COMPINVIFG Masked interrupt status for COMPINVIFG 0x2 0x1 MIS_COMPINVIFG_CLR CLR 0 MIS_COMPINVIFG_SET SET 1 MIS_OUTRDYIFG Masked interrupt status for OUTRDYIFG 0x3 0x1 MIS_OUTRDYIFG_CLR CLR 0 MIS_OUTRDYIFG_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_COMPIFG Sets COMPIFG in RIS register 0x1 0x1 ISET_COMPIFG_NO_EFFECT NO_EFFECT 0 ISET_COMPIFG_SET SET 1 ISET_COMPINVIFG Sets COMPINVIFG in RIS register 0x2 0x1 ISET_COMPINVIFG_NO_EFFECT NO_EFFECT 0 ISET_COMPINVIFG_SET SET 1 ISET_OUTRDYIFG Sets OUTRDYIFG in RIS register 0x3 0x1 ISET_OUTRDYIFG_NO_EFFECT NO_EFFECT 0 ISET_OUTRDYIFG_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_COMPIFG Clears COMPIFG in RIS register 0x1 0x1 ICLR_COMPIFG_NO_EFFECT NO_EFFECT 0 ICLR_COMPIFG_CLR CLR 1 ICLR_COMPINVIFG Clears COMPINVIFG in RIS register 0x2 0x1 ICLR_COMPINVIFG_NO_EFFECT NO_EFFECT 0 ICLR_COMPINVIFG_CLR CLR 1 ICLR_OUTRDYIFG Clears OUTRDYIFG in RIS register 0x3 0x1 ICLR_OUTRDYIFG_NO_EFFECT NO_EFFECT 0 ICLR_OUTRDYIFG_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write 0x00000009 EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 read-only DESC_MAJREV Major rev of the IP 0x4 0x4 read-only DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only CTL0 Control 0 0x1100 32 read-write 0x00000000 CTL0_IPSEL Channel input selected for the positive terminal of the comparator if IPEN is set to 1. 0x0 0x3 read-write CTL0_IPSEL_CH_0 CH_0 0 CTL0_IPSEL_CH_1 CH_1 1 CTL0_IPSEL_CH_2 CH_2 2 CTL0_IPSEL_CH_3 CH_3 3 CTL0_IPSEL_CH_4 CH_4 4 CTL0_IPSEL_CH_5 CH_5 5 CTL0_IPSEL_CH_6 CH_6 6 CTL0_IPSEL_CH_7 CH_7 7 CTL0_IPEN Channel input enable for the positive terminal of the comparator. 0xF 0x1 read-write CTL0_IPEN_DISABLE DISABLE 0 CTL0_IPEN_ENABLE ENABLE 1 CTL0_IMEN Channel input enable for the negative terminal of the comparator. 0x1F 0x1 read-write CTL0_IMEN_DISABLE DISABLE 0 CTL0_IMEN_ENABLE ENABLE 1 CTL0_IMSEL Channel input selected for the negative terminal of the comparator if IMEN is set to 1. 0x10 0x3 read-write CTL0_IMSEL_CH_0 CH_0 0 CTL0_IMSEL_CH_1 CH_1 1 CTL0_IMSEL_CH_2 CH_2 2 CTL0_IMSEL_CH_3 CH_3 3 CTL0_IMSEL_CH_4 CH_4 4 CTL0_IMSEL_CH_5 CH_5 5 CTL0_IMSEL_CH_6 CH_6 6 CTL0_IMSEL_CH_7 CH_7 7 CTL1 Control 1 0x1104 32 read-write 0x00000000 CTL1_ENABLE This bit turns on the comparator. When the comparator is turned off it consumes no power. 0x0 0x1 read-write CTL1_ENABLE_OFF OFF 0 CTL1_ENABLE_ON ON 1 CTL1_MODE This bit selects the comparator operating mode. 0x1 0x1 read-write CTL1_MODE_FAST FAST 0 CTL1_MODE_ULP ULP 1 CTL1_EXCH This bit exchanges the comparator inputs and inverts the comparator output. 0x2 0x1 read-write CTL1_EXCH_NO_EXC NO_EXC 0 CTL1_EXCH_EXC EXC 1 CTL1_SHORT This bit shorts the positive and negative input terminals of the comparator. 0x3 0x1 read-write CTL1_SHORT_NO_SHT NO_SHT 0 CTL1_SHORT_SHT SHT 1 CTL1_IES This bit selected the interrupt edge for COMPIFG and COMPINVIFG. 0x4 0x1 read-write CTL1_IES_RISING RISING 0 CTL1_IES_FALLING FALLING 1 CTL1_HYST These bits select the hysteresis setting of the comparator. 0x5 0x2 read-write CTL1_HYST_NO_HYS NO_HYS 0 CTL1_HYST_LOW_HYS LOW_HYS 1 CTL1_HYST_MED_HYS MED_HYS 2 CTL1_HYST_HIGH_HYS HIGH_HYS 3 CTL1_OUTPOL This bit selects the comparator output polarity. 0x7 0x1 read-write CTL1_OUTPOL_NON_INV NON_INV 0 CTL1_OUTPOL_INV INV 1 CTL1_FLTEN This bit enables the analog filter at comparator output. 0x8 0x1 read-write CTL1_FLTEN_DISABLE DISABLE 0 CTL1_FLTEN_ENABLE ENABLE 1 CTL1_FLTDLY These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings. 0x9 0x2 read-write CTL1_FLTDLY_DLY_0 DLY_0 0 CTL1_FLTDLY_DLY_1 DLY_1 1 CTL1_FLTDLY_DLY_2 DLY_2 2 CTL1_FLTDLY_DLY_3 DLY_3 3 CTL1_WINCOMPEN This bit enables window comparator operation of comparator. 0xC 0x1 read-write CTL1_WINCOMPEN_OFF OFF 0 CTL1_WINCOMPEN_ON ON 1 CTL2 Control 2 0x1108 32 read-write 0x00000000 CTL2_REFMODE This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0. 0x0 0x1 read-write CTL2_REFMODE_STATIC STATIC 0 CTL2_REFMODE_SAMPLED SAMPLED 1 CTL2_REFSRC These bits select the reference source for the comparator. 0x3 0x2 read-write CTL2_REFSRC_OFF OFF 0 CTL2_REFSRC_VDDA_DAC VDDA_DAC 1 CTL2_REFSRC_VREF_DAC VREF_DAC 2 CTL2_REFSRC_VREF VREF 3 CTL2_REFSEL This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator. 0x7 0x1 read-write CTL2_REFSEL_POSITIVE POSITIVE 0 CTL2_REFSEL_NEGATIVE NEGATIVE 1 CTL2_DACCTL This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1. 0x10 0x1 read-write CTL2_DACCTL_COMPOUT_SEL COMPOUT_SEL 0 CTL2_DACCTL_DACSW_SEL DACSW_SEL 1 CTL2_DACSW This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1. 0x11 0x1 read-write CTL2_DACSW_DACCODE0_SEL DACCODE0_SEL 0 CTL2_DACSW_DACCODE1_SEL DACCODE1_SEL 1 CTL2_BLANKSRC These bits select the blanking source for the comparator. 0x8 0x3 read-write CTL2_BLANKSRC_DISABLE DISABLE 0 CTL2_BLANKSRC_BLANKSRC1 BLANKSRC1 1 CTL2_BLANKSRC_BLANKSRC2 BLANKSRC2 2 CTL2_BLANKSRC_BLANKSRC3 BLANKSRC3 3 CTL2_BLANKSRC_BLANKSRC4 BLANKSRC4 4 CTL2_BLANKSRC_BLANKSRC5 BLANKSRC5 5 CTL2_BLANKSRC_BLANKSRC6 BLANKSRC6 6 CTL2_SAMPMODE Enable sampled mode of comparator. 0x18 0x1 read-write CTL2_SAMPMODE_DISABLE DISABLE 0 CTL2_SAMPMODE_ENABLE ENABLE 1 CTL3 Control 3 0x110C 32 read-write 0x00000000 CTL3_DACCODE0 This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x0 0x8 read-write CTL3_DACCODE1 This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256. 0x10 0x8 read-write STAT Status 0x1120 32 read-only 0x00000000 STAT_OUT This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output. 0x0 0x1 read-only STAT_OUT_LOW LOW 0 STAT_OUT_HIGH HIGH 1 SYSCTL 1.0 mem_map 0x400AF000 0x0 0x2C64 registers IIDX SYSCTL interrupt index 0x1020 32 read-only 0x00000000 0x00000003 IIDX_STAT The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers. 0x0 0x2 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_LFOSCGOOD LFOSCGOOD 1 IIDX_STAT_ANACLKERR ANACLKERR 2 IMASK SYSCTL interrupt mask 0x1028 32 read-write 0x00000000 0x00000003 IMASK_LFOSCGOOD Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully. 0x0 0x1 read-write IMASK_LFOSCGOOD_DISABLE DISABLE 0 IMASK_LFOSCGOOD_ENABLE ENABLE 1 IMASK_ANACLKERR Analog Clocking Consistency Error 0x1 0x1 read-write IMASK_ANACLKERR_DISABLE DISABLE 0 IMASK_ANACLKERR_ENABLE ENABLE 1 RIS SYSCTL raw interrupt status 0x1030 32 read-only 0x00000000 0x00000003 RIS_LFOSCGOOD Raw status of the LFOSCGOOD interrupt. 0x0 0x1 read-only RIS_LFOSCGOOD_FALSE FALSE 0 RIS_LFOSCGOOD_TRUE TRUE 1 RIS_ANACLKERR Analog Clocking Consistency Error 0x1 0x1 read-only RIS_ANACLKERR_FALSE FALSE 0 RIS_ANACLKERR_TRUE TRUE 1 MIS SYSCTL masked interrupt status 0x1038 32 read-only 0x00000000 0x00000003 MIS_LFOSCGOOD Masked status of the LFOSCGOOD interrupt. 0x0 0x1 read-only MIS_LFOSCGOOD_FALSE FALSE 0 MIS_LFOSCGOOD_TRUE TRUE 1 MIS_ANACLKERR Analog Clocking Consistency Error 0x1 0x1 read-only MIS_ANACLKERR_FALSE FALSE 0 MIS_ANACLKERR_TRUE TRUE 1 ISET SYSCTL interrupt set 0x1040 32 write-only 0x00000000 0x00000003 ISET_LFOSCGOOD Set the LFOSCGOOD interrupt. 0x0 0x1 write-only ISET_LFOSCGOOD_NO_EFFECT NO_EFFECT 0 ISET_LFOSCGOOD_SET SET 1 ISET_ANACLKERR Analog Clocking Consistency Error 0x1 0x1 write-only ISET_ANACLKERR_NO_EFFECT NO_EFFECT 0 ISET_ANACLKERR_SET SET 1 ICLR SYSCTL interrupt clear 0x1048 32 write-only 0x00000000 0x00000003 ICLR_LFOSCGOOD Clear the LFOSCGOOD interrupt. 0x0 0x1 write-only ICLR_LFOSCGOOD_NO_EFFECT NO_EFFECT 0 ICLR_LFOSCGOOD_CLR CLR 1 ICLR_ANACLKERR Analog Clocking Consistency Error 0x1 0x1 write-only ICLR_ANACLKERR_NO_EFFECT NO_EFFECT 0 ICLR_ANACLKERR_CLR CLR 1 NMIIIDX NMI interrupt index 0x1050 32 read-only 0x00000000 0x00000003 NMIIIDX_STAT The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register. 0x0 0x2 read-only NMIIIDX_STAT_NO_INTR NO_INTR 0 NMIIIDX_STAT_BORLVL BORLVL 1 NMIIIDX_STAT_WWDT0 WWDT0 2 NMIRIS NMI raw interrupt status 0x1060 32 read-only 0x00000000 0x00000003 NMIRIS_BORLVL Raw status of the BORLVL NMI 0x0 0x1 read-only NMIRIS_BORLVL_FALSE FALSE 0 NMIRIS_BORLVL_TRUE TRUE 1 NMIRIS_WWDT0 Watch Dog 0 Fault 0x1 0x1 read-only NMIRIS_WWDT0_FALSE FALSE 0 NMIRIS_WWDT0_TRUE TRUE 1 NMIISET NMI interrupt set 0x1070 32 write-only 0x00000000 0x00000003 NMIISET_BORLVL Set the BORLVL NMI 0x0 0x1 write-only NMIISET_BORLVL_NO_EFFECT NO_EFFECT 0 NMIISET_BORLVL_SET SET 1 NMIISET_WWDT0 Watch Dog 0 Fault 0x1 0x1 write-only NMIISET_WWDT0_NO_EFFECT NO_EFFECT 0 NMIISET_WWDT0_SET SET 1 NMIICLR NMI interrupt clear 0x1078 32 write-only 0x00000000 0x00000003 NMIICLR_BORLVL Clr the BORLVL NMI 0x0 0x1 write-only NMIICLR_BORLVL_NO_EFFECT NO_EFFECT 0 NMIICLR_BORLVL_CLR CLR 1 NMIICLR_WWDT0 Watch Dog 0 Fault 0x1 0x1 write-only NMIICLR_WWDT0_NO_EFFECT NO_EFFECT 0 NMIICLR_WWDT0_CLR CLR 1 SYSOSCCFG SYSOSC configuration 0x1100 32 read-write 0x00020000 0x00030703 SYSOSCCFG_USE4MHZSTOP USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption. 0x8 0x1 read-write SYSOSCCFG_USE4MHZSTOP_DISABLE DISABLE 0 SYSOSCCFG_USE4MHZSTOP_ENABLE ENABLE 1 SYSOSCCFG_DISABLESTOP DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption. 0x9 0x1 read-write SYSOSCCFG_DISABLESTOP_DISABLE DISABLE 0 SYSOSCCFG_DISABLESTOP_ENABLE ENABLE 1 SYSOSCCFG_BLOCKASYNCALL BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode. 0x10 0x1 read-write SYSOSCCFG_BLOCKASYNCALL_DISABLE DISABLE 0 SYSOSCCFG_BLOCKASYNCALL_ENABLE ENABLE 1 SYSOSCCFG_DISABLE DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK. 0xA 0x1 read-write SYSOSCCFG_DISABLE_DISABLE DISABLE 0 SYSOSCCFG_DISABLE_ENABLE ENABLE 1 SYSOSCCFG_FASTCPUEVENT FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency. 0x11 0x1 read-write SYSOSCCFG_FASTCPUEVENT_DISABLE DISABLE 0 SYSOSCCFG_FASTCPUEVENT_ENABLE ENABLE 1 SYSOSCCFG_FREQ Target operating frequency for the system oscillator (SYSOSC) 0x0 0x2 read-write SYSOSCCFG_FREQ_SYSOSCBASE SYSOSCBASE 0 SYSOSCCFG_FREQ_SYSOSC4M SYSOSC4M 1 SYSOSCCFG_FREQ_SYSOSCUSER SYSOSCUSER 2 SYSOSCCFG_FREQ_SYSOSCTURBO SYSOSCTURBO 3 MCLKCFG Main clock (MCLK) configuration 0x1104 32 read-write 0x00000000 0x00000000 MCLKCFG_MDIV MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC 0x0 0x4 read-write MCLKCFG_FLASHWAIT FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK 0x8 0x4 read-write MCLKCFG_USEMFTICK USEMFTICK specifies whether the 4MHz constant-rate cloc20(MFCLK) to peripherals is enabled or disabled. 0xC 0x1 read-write MCLKCFG_USELFCLK USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source 0x14 0x1 read-write MCLKCFG_STOPCLKSTBY STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). 0x15 0x1 read-write MCLKCFG_MCLKDEADCHK MCLKDEADCHK enables or disables the continuous MCLK dead check monitor 0x16 0x1 read-write GENCLKCFG General clock configuration 0x1138 32 read-write 0x00000000 0x00000000 GENCLKCFG_EXCLKSRC EXCLKSRC selects the source for the CLK_OUT external clockoutput block. ULPCLK and MFPCLK require the CLK_OUT divider(EXCLKDIVEN) to be enabled 0x0 0x3 read-write GENCLKCFG_EXCLKDIVVAL EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block. 0x4 0x3 read-write GENCLKCFG_EXCLKDIVEN EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block. 0x7 0x1 read-write GENCLKCFG_FCCSELCLK FCCSELCLK selectes the frequency clock counter (FCC) clock source 0x10 0x4 read-write GENCLKCFG_FCCTRIGSRC FCCTRIGSRC selects the frequency clock counter (FCC) trigger source 0x14 0x1 read-write GENCLKCFG_FCCLVLTRIG FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode 0x15 0x1 read-write GENCLKCFG_ANACPUMPCFG ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method. 0x16 0x2 read-write GENCLKCFG_FCCTRIGCNT FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified. 0x18 0x5 read-write GENCLKEN General clock enable control 0x113C 32 read-write 0x00000000 0x00000011 GENCLKEN_EXCLKEN EXCLKEN enables the CLK_OUT external clock output block. 0x0 0x1 read-write GENCLKEN_EXCLKEN_DISABLE DISABLE 0 GENCLKEN_EXCLKEN_ENABLE ENABLE 1 GENCLKEN_MFPCLKEN MFPCLKEN enables the middle frequency precision clock (MFPCLK). 0x4 0x1 read-write GENCLKEN_MFPCLKEN_DISABLE DISABLE 0 GENCLKEN_MFPCLKEN_ENABLE ENABLE 1 PMODECFG Power mode configuration 0x1140 32 read-write 0x00000000 0x00000023 PMODECFG_SYSSRAMONSTOP SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode. 0x5 0x1 read-write PMODECFG_SYSSRAMONSTOP_DISABLE DISABLE 0 PMODECFG_SYSSRAMONSTOP_ENABLE ENABLE 1 PMODECFG_DSLEEP DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU. 0x0 0x2 read-write PMODECFG_DSLEEP_STOP STOP 0 PMODECFG_DSLEEP_STANDBY STANDBY 1 PMODECFG_DSLEEP_SHUTDOWN SHUTDOWN 2 FCC Frequency clock counter (FCC) count 0x1150 32 read-only 0x00000000 0x003fffff FCC_DATA Frequency clock counter (FCC) count value. 0x0 0x16 read-only SYSOSCTRIMUSER SYSOSC user-specified trim 0x1170 32 read-write 0x00000000 0x1fff3f73 SYSOSCTRIMUSER_RESCOARSE RESCOARSE specifies the resister coarse trim. This value changes with the target frequency. 0x8 0x6 read-write SYSOSCTRIMUSER_RESFINE RESFINE specifies the resister fine trim. This value changes with the target frequency. 0x10 0x4 read-write SYSOSCTRIMUSER_RDIV RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency. 0x14 0x9 read-write SYSOSCTRIMUSER_FREQ FREQ specifies the target user-trimmed frequency for SYSOSC. 0x0 0x2 read-write SYSOSCTRIMUSER_FREQ_SYSOSC16M SYSOSC16M 1 SYSOSCTRIMUSER_FREQ_SYSOSC24M SYSOSC24M 2 SYSOSCTRIMUSER_CAP CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency. 0x4 0x3 read-write SRAMBOUNDARY SRAM Write Boundary 0x1178 32 read-write 0x00000000 0x000fffe0 SRAMBOUNDARY_ADDR SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size. 0x5 0xF read-write SYSTEMCFG System configuration 0x1180 32 read-write 0x00000000 0xff000001 SYSTEMCFG_KEY The key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0 0x18 0x8 write-only SYSTEMCFG_KEY_VALUE VALUE 27 SYSTEMCFG_WWDTLP0RSTDIS WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI. 0x0 0x1 read-write SYSTEMCFG_WWDTLP0RSTDIS_FALSE FALSE 0 SYSTEMCFG_WWDTLP0RSTDIS_TRUE TRUE 1 WRITELOCK SYSCTL register write lockout 0x1200 32 read-write 0x00000000 0x00000001 WRITELOCK_ACTIVE ACTIVE controls whether critical SYSCTL registers are write protected or not. 0x0 0x1 read-write WRITELOCK_ACTIVE_DISABLE DISABLE 0 WRITELOCK_ACTIVE_ENABLE ENABLE 1 RSTCAUSE Reset cause 0x1220 32 read-only 0x00000000 0x0000001f RSTCAUSE_ID ID is a read-to-clear field which indicates the lowest level reset cause since the last read. 0x0 0x5 read-only RSTCAUSE_ID_NORST NORST 0 RSTCAUSE_ID_PORHWFAIL PORHWFAIL 1 RSTCAUSE_ID_POREXNRST POREXNRST 2 RSTCAUSE_ID_PORSW PORSW 3 RSTCAUSE_ID_BORSUPPLY BORSUPPLY 4 RSTCAUSE_ID_BORWAKESHUTDN BORWAKESHUTDN 5 RSTCAUSE_ID_BOOTNONPMUPARITY BOOTNONPMUPARITY 8 RSTCAUSE_ID_BOOTCLKFAIL BOOTCLKFAIL 9 RSTCAUSE_ID_BOOTEXNRST BOOTEXNRST 12 RSTCAUSE_ID_BOOTSW BOOTSW 13 RSTCAUSE_ID_SYSWWDT0 SYSWWDT0 14 RSTCAUSE_ID_SYSBSLEXIT SYSBSLEXIT 16 RSTCAUSE_ID_SYSBSLENTRY SYSBSLENTRY 17 RSTCAUSE_ID_SYSWWDT1 SYSWWDT1 19 RSTCAUSE_ID_SYSFLASHECC SYSFLASHECC 20 RSTCAUSE_ID_SYSCPULOCK SYSCPULOCK 21 RSTCAUSE_ID_SYSDBG SYSDBG 26 RSTCAUSE_ID_SYSSW SYSSW 27 RSTCAUSE_ID_CPUDBG CPUDBG 28 RSTCAUSE_ID_CPUSW CPUSW 29 RESETLEVEL Reset level for application-triggered reset command 0x1300 32 read-write 0x00000000 0x00000007 RESETLEVEL_LEVEL LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset. 0x0 0x3 read-write RESETLEVEL_LEVEL_CPU CPU 0 RESETLEVEL_LEVEL_BOOT BOOT 1 RESETLEVEL_LEVEL_BOOTLOADERENTRY BOOTLOADERENTRY 2 RESETLEVEL_LEVEL_POR POR 3 RESETLEVEL_LEVEL_BOOTLOADEREXIT BOOTLOADEREXIT 4 RESETCMD Execute an application-triggered reset command 0x1304 32 write-only 0x00000000 0xff000001 RESETCMD_KEY The key value of E4h (228) must be written to KEY together with GO to trigger the reset. 0x18 0x8 write-only RESETCMD_KEY_VALUE VALUE 228 RESETCMD_GO Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY. 0x0 0x1 write-only RESETCMD_GO_TRUE TRUE 1 BORTHRESHOLD BOR threshold selection 0x1308 32 read-write 0x00000000 0x00000003 BORTHRESHOLD_LEVEL LEVEL specifies the desired BOR threshold and BOR mode. 0x0 0x2 read-write BORTHRESHOLD_LEVEL_BORMIN BORMIN 0 BORTHRESHOLD_LEVEL_BORLEVEL1 BORLEVEL1 1 BORTHRESHOLD_LEVEL_BORLEVEL2 BORLEVEL2 2 BORTHRESHOLD_LEVEL_BORLEVEL3 BORLEVEL3 3 BORCLRCMD Set the BOR threshold 0x130C 32 write-only 0x00000000 0xff000001 BORCLRCMD_KEY The key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change. 0x18 0x8 write-only BORCLRCMD_KEY_VALUE VALUE 199 BORCLRCMD_GO GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register. 0x0 0x1 write-only BORCLRCMD_GO_TRUE TRUE 1 SYSOSCFCLCTL SYSOSC frequency correction loop (FCL) ROSC enable 0x1310 32 write-only 0x00000000 0xff000001 SYSOSCFCLCTL_KEY The key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL. 0x18 0x8 write-only SYSOSCFCLCTL_KEY_VALUE VALUE 42 SYSOSCFCLCTL_SETUSEFCL Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST. 0x0 0x1 write-only SYSOSCFCLCTL_SETUSEFCL_TRUE TRUE 1 SHDNIOREL SHUTDOWN IO release control 0x131C 32 write-only 0x00000000 0xff000001 SHDNIOREL_KEY The key value 91h must be written to KEY together with RELEASE to set RELEASE. 0x18 0x8 write-only SHDNIOREL_KEY_VALUE VALUE 145 SHDNIOREL_RELEASE Set RELEASE to release the IO after a SHUTDOWN mode exit. 0x0 0x1 write-only SHDNIOREL_RELEASE_TRUE TRUE 1 EXRSTPIN Disable the reset function of the NRST pin 0x1320 32 write-only 0x00000000 0xff000001 EXRSTPIN_KEY The key value 1Eh must be written together with DISABLE to disable the reset function. 0x18 0x8 write-only EXRSTPIN_KEY_VALUE VALUE 30 EXRSTPIN_DISABLE Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR. 0x0 0x1 write-only EXRSTPIN_DISABLE_FALSE FALSE 0 EXRSTPIN_DISABLE_TRUE TRUE 1 SWDCFG Disable the SWD function on the SWD pins 0x1328 32 write-only 0x00000000 0xff000001 SWDCFG_KEY The key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions. 0x18 0x8 write-only SWDCFG_KEY_VALUE VALUE 98 SWDCFG_DISABLE Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO. 0x0 0x1 write-only SWDCFG_DISABLE_TRUE TRUE 1 FCCCMD Frequency clock counter start capture 0x132C 32 write-only 0x00000000 0xff000001 FCCCMD_KEY The key value 0Eh (14) must be written with GO to start a capture. 0x18 0x8 write-only FCCCMD_KEY_VALUE VALUE 14 FCCCMD_GO Set GO to start a capture with the frequency clock counter (FCC). 0x0 0x1 write-only FCCCMD_GO_TRUE TRUE 1 PMUOPAMP GPAMP control 0x1380 32 read-write 0x00000000 0x00000f7f PMUOPAMP_RRI RRI selects the rail-to-rail input mode. 0x4 0x2 read-write PMUOPAMP_RRI_MODE0 MODE0 0 PMUOPAMP_RRI_MODE1 MODE1 1 PMUOPAMP_RRI_MODE2 MODE2 2 PMUOPAMP_RRI_MODE3 MODE3 3 PMUOPAMP_NSEL NSEL selects the GPAMP negative channel input. 0x2 0x2 read-write PMUOPAMP_NSEL_SEL0 SEL0 0 PMUOPAMP_NSEL_SEL1 SEL1 1 PMUOPAMP_NSEL_SEL2 SEL2 2 PMUOPAMP_NSEL_SEL3 SEL3 3 PMUOPAMP_CHOPCLKMODE CHOPCLKMODE selects the GPAMP chopping mode. 0xA 0x2 read-write PMUOPAMP_CHOPCLKMODE_CHOPDISABLED CHOPDISABLED 0 PMUOPAMP_CHOPCLKMODE_REGCHOP REGCHOP 1 PMUOPAMP_CHOPCLKMODE_ADCASSIST ADCASSIST 2 PMUOPAMP_OUTENABLE Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin 0x6 0x1 read-write PMUOPAMP_OUTENABLE_FALSE FALSE 0 PMUOPAMP_OUTENABLE_TRUE TRUE 1 PMUOPAMP_ENABLE Set ENABLE to turn on the GPAMP. 0x0 0x1 read-write PMUOPAMP_ENABLE_FALSE FALSE 0 PMUOPAMP_ENABLE_TRUE TRUE 1 PMUOPAMP_CHOPCLKFREQ CHOPCLKFREQ selects the GPAMP chopping clock frequency 0x8 0x2 read-write PMUOPAMP_CHOPCLKFREQ_CLK16KHZ CLK16KHZ 0 PMUOPAMP_CHOPCLKFREQ_CLK8KHZ CLK8KHZ 1 PMUOPAMP_CHOPCLKFREQ_CLK4KHZ CLK4KHZ 2 PMUOPAMP_CHOPCLKFREQ_CLK2KHZ CLK2KHZ 3 PMUOPAMP_PCHENABLE Set PCHENABLE to enable the positive channel input. 0x1 0x1 read-write PMUOPAMP_PCHENABLE_FALSE FALSE 0 PMUOPAMP_PCHENABLE_TRUE TRUE 1 SHUTDNSTORE0 Shutdown storage memory (byte 0) 0x1400 32 read-write 0x00000000 0x000003ff SHUTDNSTORE0_DATA Shutdown storage byte 0 0x0 0x8 read-write SHUTDNSTORE1 Shutdown storage memory (byte 1) 0x1404 32 read-write 0x00000000 0x000003ff SHUTDNSTORE1_DATA Shutdown storage byte 1 0x0 0x8 read-write SHUTDNSTORE2 Shutdown storage memory (byte 2) 0x1408 32 read-write 0x00000000 0x000003ff SHUTDNSTORE2_DATA Shutdown storage byte 2 0x0 0x8 read-write SHUTDNSTORE3 Shutdown storage memory (byte 3) 0x140C 32 read-write 0x00000000 0x000003ff SHUTDNSTORE3_DATA Shutdown storage byte 3 0x0 0x8 read-write OPA1 1.0 PERIPHERALREGION 0x40022000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 GPRCM_STAT Status Register 0x814 32 read-only GPRCM_STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only GPRCM_STAT_RESETSTKY_NORES NORES 0 GPRCM_STAT_RESETSTKY_RESET RESET 1 CLKOVR Clock Override 0x1010 32 read-write 0x00000000 CLKOVR_OVERRIDE Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request 0x0 0x1 read-write CLKOVR_OVERRIDE_DISABLED DISABLED 0 CLKOVR_OVERRIDE_ENABLED ENABLED 1 CLKOVR_RUN_STOP If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system 0x1 0x1 read-write CLKOVR_RUN_STOP_RUN RUN 0 CLKOVR_RUN_STOP_STOP STOP 1 PWRCTL Power Control 0x101C 32 read-write PWRCTL_AUTO_OFF When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled. 0x0 0x1 read-write PWRCTL_AUTO_OFF_DISABLE DISABLE 0 PWRCTL_AUTO_OFF_ENABLE ENABLE 1 CTL Control Register 0x1100 32 read-write 0x00000000 0x0000ffff CTL_ENABLE OAxn Enable. 0x0 0x1 read-write CTL_ENABLE_OFF OFF 0 CTL_ENABLE_ON ON 1 CFGBASE Configuration Base Register 0x1104 32 read-write 0x00000000 0x0000ffff CFGBASE_GBW Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0. 0x0 0x1 read-write CFGBASE_GBW_LOWGAIN LOWGAIN 0 CFGBASE_GBW_HIGHGAIN HIGHGAIN 1 CFGBASE_RRI Rail-to-rail input enable. Can only be modified when STAT.BUSY=0 0x2 0x1 read-write CFGBASE_RRI_OFF OFF 0 CFGBASE_RRI_ON ON 1 CFG Configuration Register 0x1108 32 read-write 0x00000000 0xffffffff CFG_CHOP Chopping enable. 0x0 0x2 read-write CFG_CHOP_OFF OFF 0 CFG_CHOP_ON ON 1 CFG_CHOP_AVGON AVGON 2 CFG_OUTPIN Enable output pin 0x2 0x1 read-write CFG_OUTPIN_DISABLED DISABLED 0 CFG_OUTPIN_ENABLED ENABLED 1 CFG_PSEL Positive OA input selection. Please refer to the device specific datasheet for exact channels available. 0x3 0x4 read-write CFG_PSEL_NC NC 0 CFG_PSEL_EXTPIN0 EXTPIN0 1 CFG_PSEL_EXTPIN1 EXTPIN1 2 CFG_PSEL_DAC12OUT DAC12OUT 3 CFG_PSEL_DAC8OUT DAC8OUT 4 CFG_PSEL_VREF VREF 5 CFG_PSEL_OANM1RTOP OANM1RTOP 6 CFG_PSEL_GPAMP_OUT_INT GPAMP_OUT_INT 7 CFG_PSEL_VSS VSS 8 CFG_NSEL Negative OA input selection. Please refer to the device specific datasheet for exact channels available. 0x7 0x3 read-write CFG_NSEL_NC NC 0 CFG_NSEL_EXTPIN0 EXTPIN0 1 CFG_NSEL_EXTPIN1 EXTPIN1 2 CFG_NSEL_OANP1RBOT OANP1RBOT 3 CFG_NSEL_OANRTAP OANRTAP 4 CFG_NSEL_OANRTOP OANRTOP 5 CFG_NSEL_SPARE SPARE 6 CFG_MSEL MSEL Mux selection. Please refer to the device specific datasheet for exact channels available. 0xA 0x3 read-write CFG_MSEL_NC NC 0 CFG_MSEL_EXTNPIN1 EXTNPIN1 1 CFG_MSEL_VSS VSS 2 CFG_MSEL_DAC12OUT DAC12OUT 3 CFG_MSEL_OANM1RTOP OANM1RTOP 4 CFG_GAIN Gain setting. Refer to TRM for enumeration information. 0xD 0x3 read-write STAT Status Register 0x1118 32 read-only 0x00000000 0x0000ffff STAT_RDY OA ready status. 0x0 0x1 read-only STAT_RDY_FALSE FALSE 0 STAT_RDY_TRUE TRUE 1 I2C1 1.0 PERIPHERALREGION 0x400F2000 0x0 0x1F00 registers PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG Peripheral Clock Configuration Register 0x808 32 read-write 0x00000000 CLKCFG_KEY KEY to Allow State Change -- 0xA9 0x18 0x8 write-only CLKCFG_KEY_UNLOCK _UNLOCK_W_ 169 CLKCFG_BLOCKASYNC Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0x8 0x1 read-write CLKCFG_BLOCKASYNC_DISABLE DISABLE 0 CLKCFG_BLOCKASYNC_ENABLE ENABLE 1 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1004 32 read-write 0x00000000 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 INT_EVENT0_IIDX Interrupt index 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_MRXDONEFG MRXDONEFG 1 INT_EVENT0_IIDX_STAT_MTXDONEFG MTXDONEFG 2 INT_EVENT0_IIDX_STAT_MRXFIFOTRG MRXFIFOTRG 3 INT_EVENT0_IIDX_STAT_MTXFIFOTRG MTXFIFOTRG 4 INT_EVENT0_IIDX_STAT_MRXFIFOFULL MRXFIFOFULL 5 INT_EVENT0_IIDX_STAT_MTX_EMPTY MTX_EMPTY 6 INT_EVENT0_IIDX_STAT_MNACKFG MNACKFG 8 INT_EVENT0_IIDX_STAT_MSTARTFG MSTARTFG 9 INT_EVENT0_IIDX_STAT_MSTOPFG MSTOPFG 10 INT_EVENT0_IIDX_STAT_MARBLOSTFG MARBLOSTFG 11 INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2 MDMA_DONE1_CH2 12 INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3 MDMA_DONE1_CH3 13 INT_EVENT0_IIDX_STAT_MPEC_RX_ERR MPEC_RX_ERR 14 INT_EVENT0_IIDX_STAT_TIMEOUTA TIMEOUTA 15 INT_EVENT0_IIDX_STAT_TIMEOUTB TIMEOUTB 16 INT_EVENT0_IIDX_STAT_SRXDONEFG SRXDONEFG 17 INT_EVENT0_IIDX_STAT_STXDONEFG STXDONEFG 18 INT_EVENT0_IIDX_STAT_SRXFIFOTRG SRXFIFOTRG 19 INT_EVENT0_IIDX_STAT_STXFIFOTRG STXFIFOTRG 20 INT_EVENT0_IIDX_STAT_SRXFIFOFULL SRXFIFOFULL 21 INT_EVENT0_IIDX_STAT_STXEMPTY STXEMPTY 22 INT_EVENT0_IIDX_STAT_SSTARTFG SSTARTFG 23 INT_EVENT0_IIDX_STAT_SSTOPFG SSTOPFG 24 INT_EVENT0_IIDX_STAT_SGENCALL SGENCALL 25 INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2 SDMA_DONE1_CH2 26 INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3 SDMA_DONE1_CH3 27 INT_EVENT0_IIDX_STAT_SPEC_RX_ERR SPEC_RX_ERR 28 INT_EVENT0_IIDX_STAT_STX_UNFL STX_UNFL 29 INT_EVENT0_IIDX_STAT_SRX_OVFL SRX_OVFL 30 INT_EVENT0_IIDX_STAT_SARBLOST SARBLOST 31 INT_EVENT0_IIDX_STAT_INTR_OVFL INTR_OVFL 32 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_MRXDONE Master Receive Transaction completed Interrupt 0x0 0x1 INT_EVENT0_IMASK_MRXDONE_CLR CLR 0 INT_EVENT0_IMASK_MRXDONE_SET SET 1 INT_EVENT0_IMASK_TIMEOUTA Timeout A Interrupt 0xE 0x1 INT_EVENT0_IMASK_TIMEOUTA_CLR CLR 0 INT_EVENT0_IMASK_TIMEOUTA_SET SET 1 INT_EVENT0_IMASK_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_IMASK_MNACK_CLR CLR 0 INT_EVENT0_IMASK_MNACK_SET SET 1 INT_EVENT0_IMASK_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_IMASK_MSTART_CLR CLR 0 INT_EVENT0_IMASK_MSTART_SET SET 1 INT_EVENT0_IMASK_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_IMASK_MSTOP_CLR CLR 0 INT_EVENT0_IMASK_MSTOP_SET SET 1 INT_EVENT0_IMASK_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_IMASK_MARBLOST_CLR CLR 0 INT_EVENT0_IMASK_MARBLOST_SET SET 1 INT_EVENT0_IMASK_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_IMASK_MTXDONE_CLR CLR 0 INT_EVENT0_IMASK_MTXDONE_SET SET 1 INT_EVENT0_IMASK_MRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 INT_EVENT0_IMASK_MRXFIFOFULL_CLR CLR 0 INT_EVENT0_IMASK_MRXFIFOFULL_SET SET 1 INT_EVENT0_IMASK_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_IMASK_MTXEMPTY_CLR CLR 0 INT_EVENT0_IMASK_MTXEMPTY_SET SET 1 INT_EVENT0_IMASK_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_IMASK_MRXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_MRXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_IMASK_MTXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_MTXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_IMASK_MDMA_DONE1_2_CLR CLR 0 INT_EVENT0_IMASK_MDMA_DONE1_2_SET SET 1 INT_EVENT0_IMASK_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_IMASK_MDMA_DONE1_3_CLR CLR 0 INT_EVENT0_IMASK_MDMA_DONE1_3_SET SET 1 INT_EVENT0_IMASK_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_IMASK_SRXDONE_CLR CLR 0 INT_EVENT0_IMASK_SRXDONE_SET SET 1 INT_EVENT0_IMASK_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_IMASK_STXDONE_CLR CLR 0 INT_EVENT0_IMASK_STXDONE_SET SET 1 INT_EVENT0_IMASK_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_IMASK_SGENCALL_CLR CLR 0 INT_EVENT0_IMASK_SGENCALL_SET SET 1 INT_EVENT0_IMASK_STXEMPTY Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_IMASK_STXEMPTY_CLR CLR 0 INT_EVENT0_IMASK_STXEMPTY_SET SET 1 INT_EVENT0_IMASK_SRXFIFOFULL RXFIFO full event. This interrupt is set if an Slave RX FIFO is full. 0x14 0x1 INT_EVENT0_IMASK_SRXFIFOFULL_CLR CLR 0 INT_EVENT0_IMASK_SRXFIFOFULL_SET SET 1 INT_EVENT0_IMASK_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_IMASK_SRXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_SRXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_IMASK_STXFIFOTRG_CLR CLR 0 INT_EVENT0_IMASK_STXFIFOTRG_SET SET 1 INT_EVENT0_IMASK_SSTART Start Condition Interrupt 0x16 0x1 INT_EVENT0_IMASK_SSTART_CLR CLR 0 INT_EVENT0_IMASK_SSTART_SET SET 1 INT_EVENT0_IMASK_SSTOP Stop Condition Interrupt 0x17 0x1 INT_EVENT0_IMASK_SSTOP_CLR CLR 0 INT_EVENT0_IMASK_SSTOP_SET SET 1 INT_EVENT0_IMASK_SDMA_DONE1_2 Slave DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_IMASK_SDMA_DONE1_2_CLR CLR 0 INT_EVENT0_IMASK_SDMA_DONE1_2_SET SET 1 INT_EVENT0_IMASK_SDMA_DONE1_3 Slave DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_IMASK_SDMA_DONE1_3_CLR CLR 0 INT_EVENT0_IMASK_SDMA_DONE1_3_SET SET 1 INT_EVENT0_IMASK_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_IMASK_MPEC_RX_ERR_CLR CLR 0 INT_EVENT0_IMASK_MPEC_RX_ERR_SET SET 1 INT_EVENT0_IMASK_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_IMASK_TIMEOUTB_CLR CLR 0 INT_EVENT0_IMASK_TIMEOUTB_SET SET 1 INT_EVENT0_IMASK_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_IMASK_SPEC_RX_ERR_CLR CLR 0 INT_EVENT0_IMASK_SPEC_RX_ERR_SET SET 1 INT_EVENT0_IMASK_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_IMASK_STX_UNFL_CLR CLR 0 INT_EVENT0_IMASK_STX_UNFL_SET SET 1 INT_EVENT0_IMASK_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_IMASK_SRX_OVFL_CLR CLR 0 INT_EVENT0_IMASK_SRX_OVFL_SET SET 1 INT_EVENT0_IMASK_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_IMASK_SARBLOST_CLR CLR 0 INT_EVENT0_IMASK_SARBLOST_SET SET 1 INT_EVENT0_IMASK_INTR_OVFL Interrupt Overflow Interrupt Mask 0x1F 0x1 INT_EVENT0_IMASK_INTR_OVFL_CLR CLR 0 INT_EVENT0_IMASK_INTR_OVFL_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only INT_EVENT0_RIS_MRXDONE Master Receive Transaction completed Interrupt 0x0 0x1 INT_EVENT0_RIS_MRXDONE_CLR CLR 0 INT_EVENT0_RIS_MRXDONE_SET SET 1 INT_EVENT0_RIS_TIMEOUTA Timeout A Interrupt 0xE 0x1 INT_EVENT0_RIS_TIMEOUTA_CLR CLR 0 INT_EVENT0_RIS_TIMEOUTA_SET SET 1 INT_EVENT0_RIS_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_RIS_MNACK_CLR CLR 0 INT_EVENT0_RIS_MNACK_SET SET 1 INT_EVENT0_RIS_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_RIS_MSTART_CLR CLR 0 INT_EVENT0_RIS_MSTART_SET SET 1 INT_EVENT0_RIS_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_RIS_MSTOP_CLR CLR 0 INT_EVENT0_RIS_MSTOP_SET SET 1 INT_EVENT0_RIS_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_RIS_MARBLOST_CLR CLR 0 INT_EVENT0_RIS_MARBLOST_SET SET 1 INT_EVENT0_RIS_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_RIS_MTXDONE_CLR CLR 0 INT_EVENT0_RIS_MTXDONE_SET SET 1 INT_EVENT0_RIS_MRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x4 0x1 INT_EVENT0_RIS_MRXFIFOFULL_CLR CLR 0 INT_EVENT0_RIS_MRXFIFOFULL_SET SET 1 INT_EVENT0_RIS_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_RIS_MTXEMPTY_CLR CLR 0 INT_EVENT0_RIS_MTXEMPTY_SET SET 1 INT_EVENT0_RIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_RIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_MRXFIFOTRG_SET SET 1 INT_EVENT0_RIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_RIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_MTXFIFOTRG_SET SET 1 INT_EVENT0_RIS_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_RIS_MDMA_DONE1_2_CLR CLR 0 INT_EVENT0_RIS_MDMA_DONE1_2_SET SET 1 INT_EVENT0_RIS_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_RIS_MDMA_DONE1_3_CLR CLR 0 INT_EVENT0_RIS_MDMA_DONE1_3_SET SET 1 INT_EVENT0_RIS_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_RIS_SRXDONE_CLR CLR 0 INT_EVENT0_RIS_SRXDONE_SET SET 1 INT_EVENT0_RIS_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_RIS_STXDONE_CLR CLR 0 INT_EVENT0_RIS_STXDONE_SET SET 1 INT_EVENT0_RIS_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_RIS_SGENCALL_CLR CLR 0 INT_EVENT0_RIS_SGENCALL_SET SET 1 INT_EVENT0_RIS_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_RIS_STXEMPTY_CLR CLR 0 INT_EVENT0_RIS_STXEMPTY_SET SET 1 INT_EVENT0_RIS_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_RIS_SRXFIFOFULL_CLR CLR 0 INT_EVENT0_RIS_SRXFIFOFULL_SET SET 1 INT_EVENT0_RIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_RIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_SRXFIFOTRG_SET SET 1 INT_EVENT0_RIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_RIS_STXFIFOTRG_CLR CLR 0 INT_EVENT0_RIS_STXFIFOTRG_SET SET 1 INT_EVENT0_RIS_SSTART Start Condition Interrupt 0x16 0x1 INT_EVENT0_RIS_SSTART_CLR CLR 0 INT_EVENT0_RIS_SSTART_SET SET 1 INT_EVENT0_RIS_SSTOP Stop Condition Interrupt 0x17 0x1 INT_EVENT0_RIS_SSTOP_CLR CLR 0 INT_EVENT0_RIS_SSTOP_SET SET 1 INT_EVENT0_RIS_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_RIS_SDMA_DONE1_2_CLR CLR 0 INT_EVENT0_RIS_SDMA_DONE1_2_SET SET 1 INT_EVENT0_RIS_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_RIS_SDMA_DONE1_3_CLR CLR 0 INT_EVENT0_RIS_SDMA_DONE1_3_SET SET 1 INT_EVENT0_RIS_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_RIS_MPEC_RX_ERR_CLR CLR 0 INT_EVENT0_RIS_MPEC_RX_ERR_SET SET 1 INT_EVENT0_RIS_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_RIS_TIMEOUTB_CLR CLR 0 INT_EVENT0_RIS_TIMEOUTB_SET SET 1 INT_EVENT0_RIS_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_RIS_SPEC_RX_ERR_CLR CLR 0 INT_EVENT0_RIS_SPEC_RX_ERR_SET SET 1 INT_EVENT0_RIS_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_RIS_STX_UNFL_CLR CLR 0 INT_EVENT0_RIS_STX_UNFL_SET SET 1 INT_EVENT0_RIS_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_RIS_SRX_OVFL_CLR CLR 0 INT_EVENT0_RIS_SRX_OVFL_SET SET 1 INT_EVENT0_RIS_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_RIS_SARBLOST_CLR CLR 0 INT_EVENT0_RIS_SARBLOST_SET SET 1 INT_EVENT0_RIS_INTR_OVFL Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced 0x1F 0x1 INT_EVENT0_RIS_INTR_OVFL_CLR CLR 0 INT_EVENT0_RIS_INTR_OVFL_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_MRXDONE Master Receive Data Interrupt 0x0 0x1 INT_EVENT0_MIS_MRXDONE_CLR CLR 0 INT_EVENT0_MIS_MRXDONE_SET SET 1 INT_EVENT0_MIS_TIMEOUTA Timeout A Interrupt 0xE 0x1 INT_EVENT0_MIS_TIMEOUTA_CLR CLR 0 INT_EVENT0_MIS_TIMEOUTA_SET SET 1 INT_EVENT0_MIS_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_MIS_MNACK_CLR CLR 0 INT_EVENT0_MIS_MNACK_SET SET 1 INT_EVENT0_MIS_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_MIS_MSTART_CLR CLR 0 INT_EVENT0_MIS_MSTART_SET SET 1 INT_EVENT0_MIS_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_MIS_MSTOP_CLR CLR 0 INT_EVENT0_MIS_MSTOP_SET SET 1 INT_EVENT0_MIS_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_MIS_MARBLOST_CLR CLR 0 INT_EVENT0_MIS_MARBLOST_SET SET 1 INT_EVENT0_MIS_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_MIS_MTXDONE_CLR CLR 0 INT_EVENT0_MIS_MTXDONE_SET SET 1 INT_EVENT0_MIS_MRXFIFOFULL RXFIFO full event. This interrupt is set if the RX FIFO is full. 0x4 0x1 INT_EVENT0_MIS_MRXFIFOFULL_CLR CLR 0 INT_EVENT0_MIS_MRXFIFOFULL_SET SET 1 INT_EVENT0_MIS_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_MIS_MTXEMPTY_CLR CLR 0 INT_EVENT0_MIS_MTXEMPTY_SET SET 1 INT_EVENT0_MIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_MIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_MRXFIFOTRG_SET SET 1 INT_EVENT0_MIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_MIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_MTXFIFOTRG_SET SET 1 INT_EVENT0_MIS_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_MIS_MDMA_DONE1_2_CLR CLR 0 INT_EVENT0_MIS_MDMA_DONE1_2_SET SET 1 INT_EVENT0_MIS_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_MIS_MDMA_DONE1_3_CLR CLR 0 INT_EVENT0_MIS_MDMA_DONE1_3_SET SET 1 INT_EVENT0_MIS_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_MIS_SRXDONE_CLR CLR 0 INT_EVENT0_MIS_SRXDONE_SET SET 1 INT_EVENT0_MIS_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_MIS_STXDONE_CLR CLR 0 INT_EVENT0_MIS_STXDONE_SET SET 1 INT_EVENT0_MIS_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_MIS_SGENCALL_CLR CLR 0 INT_EVENT0_MIS_SGENCALL_SET SET 1 INT_EVENT0_MIS_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_MIS_STXEMPTY_CLR CLR 0 INT_EVENT0_MIS_STXEMPTY_SET SET 1 INT_EVENT0_MIS_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_MIS_SRXFIFOFULL_CLR CLR 0 INT_EVENT0_MIS_SRXFIFOFULL_SET SET 1 INT_EVENT0_MIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_MIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_SRXFIFOTRG_SET SET 1 INT_EVENT0_MIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_MIS_STXFIFOTRG_CLR CLR 0 INT_EVENT0_MIS_STXFIFOTRG_SET SET 1 INT_EVENT0_MIS_SSTART Slave START Detection Interrupt 0x16 0x1 INT_EVENT0_MIS_SSTART_CLR CLR 0 INT_EVENT0_MIS_SSTART_SET SET 1 INT_EVENT0_MIS_SSTOP Slave STOP Detection Interrupt 0x17 0x1 INT_EVENT0_MIS_SSTOP_CLR CLR 0 INT_EVENT0_MIS_SSTOP_SET SET 1 INT_EVENT0_MIS_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_MIS_SDMA_DONE1_2_CLR CLR 0 INT_EVENT0_MIS_SDMA_DONE1_2_SET SET 1 INT_EVENT0_MIS_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_MIS_SDMA_DONE1_3_CLR CLR 0 INT_EVENT0_MIS_SDMA_DONE1_3_SET SET 1 INT_EVENT0_MIS_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_MIS_MPEC_RX_ERR_CLR CLR 0 INT_EVENT0_MIS_MPEC_RX_ERR_SET SET 1 INT_EVENT0_MIS_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_MIS_TIMEOUTB_CLR CLR 0 INT_EVENT0_MIS_TIMEOUTB_SET SET 1 INT_EVENT0_MIS_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_MIS_SPEC_RX_ERR_CLR CLR 0 INT_EVENT0_MIS_SPEC_RX_ERR_SET SET 1 INT_EVENT0_MIS_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_MIS_STX_UNFL_CLR CLR 0 INT_EVENT0_MIS_STX_UNFL_SET SET 1 INT_EVENT0_MIS_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_MIS_SRX_OVFL_CLR CLR 0 INT_EVENT0_MIS_SRX_OVFL_SET SET 1 INT_EVENT0_MIS_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_MIS_SARBLOST_CLR CLR 0 INT_EVENT0_MIS_SARBLOST_SET SET 1 INT_EVENT0_MIS_INTR_OVFL Interrupt overflow 0x1F 0x1 INT_EVENT0_MIS_INTR_OVFL_CLR CLR 0 INT_EVENT0_MIS_INTR_OVFL_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_MRXDONE Master Receive Data Interrupt Signals that a byte has been received 0x0 0x1 INT_EVENT0_ISET_MRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MRXDONE_SET SET 1 INT_EVENT0_ISET_TIMEOUTA Timeout A interrupt 0xE 0x1 INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TIMEOUTA_SET SET 1 INT_EVENT0_ISET_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_ISET_MNACK_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MNACK_SET SET 1 INT_EVENT0_ISET_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_ISET_MSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MSTART_SET SET 1 INT_EVENT0_ISET_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_ISET_MSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MSTOP_SET SET 1 INT_EVENT0_ISET_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_ISET_MARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MARBLOST_SET SET 1 INT_EVENT0_ISET_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_ISET_MTXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MTXDONE_SET SET 1 INT_EVENT0_ISET_MRXFIFOFULL RXFIFO full event. 0x4 0x1 INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MRXFIFOFULL_SET SET 1 INT_EVENT0_ISET_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MTXEMPTY_SET SET 1 INT_EVENT0_ISET_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MRXFIFOTRG_SET SET 1 INT_EVENT0_ISET_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MTXFIFOTRG_SET SET 1 INT_EVENT0_ISET_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MDMA_DONE1_2_SET SET 1 INT_EVENT0_ISET_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MDMA_DONE1_3_SET SET 1 INT_EVENT0_ISET_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_ISET_SRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRXDONE_SET SET 1 INT_EVENT0_ISET_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_ISET_STXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STXDONE_SET SET 1 INT_EVENT0_ISET_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_ISET_SGENCALL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SGENCALL_SET SET 1 INT_EVENT0_ISET_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_ISET_STXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STXEMPTY_SET SET 1 INT_EVENT0_ISET_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRXFIFOFULL_SET SET 1 INT_EVENT0_ISET_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRXFIFOTRG_SET SET 1 INT_EVENT0_ISET_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STXFIFOTRG_SET SET 1 INT_EVENT0_ISET_SSTART Start Condition Interrupt 0x16 0x1 INT_EVENT0_ISET_SSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SSTART_SET SET 1 INT_EVENT0_ISET_SSTOP Stop Condition Interrupt 0x17 0x1 INT_EVENT0_ISET_SSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SSTOP_SET SET 1 INT_EVENT0_ISET_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SDMA_DONE1_2_SET SET 1 INT_EVENT0_ISET_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SDMA_DONE1_3_SET SET 1 INT_EVENT0_ISET_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MPEC_RX_ERR_SET SET 1 INT_EVENT0_ISET_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TIMEOUTB_SET SET 1 INT_EVENT0_ISET_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SPEC_RX_ERR_SET SET 1 INT_EVENT0_ISET_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_ISET_STX_UNFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_STX_UNFL_SET SET 1 INT_EVENT0_ISET_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SRX_OVFL_SET SET 1 INT_EVENT0_ISET_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_ISET_SARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_SARBLOST_SET SET 1 INT_EVENT0_ISET_INTR_OVFL Interrupt overflow 0x1F 0x1 INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_INTR_OVFL_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_MRXDONE Master Receive Data Interrupt Signals that a byte has been received 0x0 0x1 INT_EVENT0_ICLR_MRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MRXDONE_CLR CLR 1 INT_EVENT0_ICLR_TIMEOUTA Timeout A interrupt 0xE 0x1 INT_EVENT0_ICLR_TIMEOUTA_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TIMEOUTA_CLR CLR 1 INT_EVENT0_ICLR_MNACK Address/Data NACK Interrupt 0x7 0x1 INT_EVENT0_ICLR_MNACK_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MNACK_CLR CLR 1 INT_EVENT0_ICLR_MSTART START Detection Interrupt 0x8 0x1 INT_EVENT0_ICLR_MSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MSTART_CLR CLR 1 INT_EVENT0_ICLR_MSTOP STOP Detection Interrupt 0x9 0x1 INT_EVENT0_ICLR_MSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MSTOP_CLR CLR 1 INT_EVENT0_ICLR_MARBLOST Arbitration Lost Interrupt 0xA 0x1 INT_EVENT0_ICLR_MARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MARBLOST_CLR CLR 1 INT_EVENT0_ICLR_MTXDONE Master Transmit Transaction completed Interrupt 0x1 0x1 INT_EVENT0_ICLR_MTXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MTXDONE_CLR CLR 1 INT_EVENT0_ICLR_MRXFIFOFULL RXFIFO full event. 0x4 0x1 INT_EVENT0_ICLR_MRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MRXFIFOFULL_CLR CLR 1 INT_EVENT0_ICLR_MTXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x5 0x1 INT_EVENT0_ICLR_MTXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MTXEMPTY_CLR CLR 1 INT_EVENT0_ICLR_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x2 0x1 INT_EVENT0_ICLR_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MRXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x3 0x1 INT_EVENT0_ICLR_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MTXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_MDMA_DONE1_2 DMA Done 1 on Event Channel 2 0xB 0x1 INT_EVENT0_ICLR_MDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MDMA_DONE1_2_CLR CLR 1 INT_EVENT0_ICLR_MDMA_DONE1_3 DMA Done 1 on Event Channel 3 0xC 0x1 INT_EVENT0_ICLR_MDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MDMA_DONE1_3_CLR CLR 1 INT_EVENT0_ICLR_SRXDONE Slave Receive Data Interrupt Signals that a byte has been received 0x10 0x1 INT_EVENT0_ICLR_SRXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRXDONE_CLR CLR 1 INT_EVENT0_ICLR_STXDONE Slave Transmit Transaction completed Interrupt 0x11 0x1 INT_EVENT0_ICLR_STXDONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STXDONE_CLR CLR 1 INT_EVENT0_ICLR_SGENCALL General Call Interrupt 0x18 0x1 INT_EVENT0_ICLR_SGENCALL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SGENCALL_CLR CLR 1 INT_EVENT0_ICLR_STXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0x15 0x1 INT_EVENT0_ICLR_STXEMPTY_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STXEMPTY_CLR CLR 1 INT_EVENT0_ICLR_SRXFIFOFULL RXFIFO full event. This interrupt is set if an RX FIFO is full. 0x14 0x1 INT_EVENT0_ICLR_SRXFIFOFULL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRXFIFOFULL_CLR CLR 1 INT_EVENT0_ICLR_SRXFIFOTRG Slave Receive FIFO Trigger 0x12 0x1 INT_EVENT0_ICLR_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_STXFIFOTRG Slave Transmit FIFO Trigger 0x13 0x1 INT_EVENT0_ICLR_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STXFIFOTRG_CLR CLR 1 INT_EVENT0_ICLR_SSTART Slave START Detection Interrupt 0x16 0x1 INT_EVENT0_ICLR_SSTART_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SSTART_CLR CLR 1 INT_EVENT0_ICLR_SSTOP Slave STOP Detection Interrupt 0x17 0x1 INT_EVENT0_ICLR_SSTOP_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SSTOP_CLR CLR 1 INT_EVENT0_ICLR_SDMA_DONE1_2 DMA Done 1 on Event Channel 2 0x19 0x1 INT_EVENT0_ICLR_SDMA_DONE1_2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SDMA_DONE1_2_CLR CLR 1 INT_EVENT0_ICLR_SDMA_DONE1_3 DMA Done 1 on Event Channel 3 0x1A 0x1 INT_EVENT0_ICLR_SDMA_DONE1_3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SDMA_DONE1_3_CLR CLR 1 INT_EVENT0_ICLR_MPEC_RX_ERR Master RX Pec Error Interrupt 0xD 0x1 INT_EVENT0_ICLR_MPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MPEC_RX_ERR_CLR CLR 1 INT_EVENT0_ICLR_TIMEOUTB Timeout B Interrupt 0xF 0x1 INT_EVENT0_ICLR_TIMEOUTB_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TIMEOUTB_CLR CLR 1 INT_EVENT0_ICLR_SPEC_RX_ERR Slave RX Pec Error Interrupt 0x1B 0x1 INT_EVENT0_ICLR_SPEC_RX_ERR_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SPEC_RX_ERR_CLR CLR 1 INT_EVENT0_ICLR_STX_UNFL Slave TX FIFO underflow 0x1C 0x1 INT_EVENT0_ICLR_STX_UNFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_STX_UNFL_CLR CLR 1 INT_EVENT0_ICLR_SRX_OVFL Slave RX FIFO overflow 0x1D 0x1 INT_EVENT0_ICLR_SRX_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SRX_OVFL_CLR CLR 1 INT_EVENT0_ICLR_SARBLOST Slave Arbitration Lost 0x1E 0x1 INT_EVENT0_ICLR_SARBLOST_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_SARBLOST_CLR CLR 1 INT_EVENT0_ICLR_INTR_OVFL Interrupt overflow 0x1F 0x1 INT_EVENT0_ICLR_INTR_OVFL_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_INTR_OVFL_CLR CLR 1 INT_EVENT1_IIDX Interrupt index 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_MRXFIFOTRG MRXFIFOTRG 1 INT_EVENT1_IIDX_STAT_MTXFIFOTRG MTXFIFOTRG 2 INT_EVENT1_IIDX_STAT_SRXFIFOTRG SRXFIFOTRG 3 INT_EVENT1_IIDX_STAT_STXFIFOTRG STXFIFOTRG 4 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_IMASK_MRXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_MRXFIFOTRG_SET SET 1 INT_EVENT1_IMASK_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_IMASK_MTXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_MTXFIFOTRG_SET SET 1 INT_EVENT1_IMASK_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_IMASK_SRXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_SRXFIFOTRG_SET SET 1 INT_EVENT1_IMASK_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_IMASK_STXFIFOTRG_CLR CLR 0 INT_EVENT1_IMASK_STXFIFOTRG_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only 0x00000000 INT_EVENT1_RIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_RIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_MRXFIFOTRG_SET SET 1 INT_EVENT1_RIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_RIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_MTXFIFOTRG_SET SET 1 INT_EVENT1_RIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_RIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_SRXFIFOTRG_SET SET 1 INT_EVENT1_RIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_RIS_STXFIFOTRG_CLR CLR 0 INT_EVENT1_RIS_STXFIFOTRG_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_MIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_MRXFIFOTRG_SET SET 1 INT_EVENT1_MIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_MIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_MTXFIFOTRG_SET SET 1 INT_EVENT1_MIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_MIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_SRXFIFOTRG_SET SET 1 INT_EVENT1_MIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_MIS_STXFIFOTRG_CLR CLR 0 INT_EVENT1_MIS_STXFIFOTRG_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_MRXFIFOTRG_SET SET 1 INT_EVENT1_ISET_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_MTXFIFOTRG_SET SET 1 INT_EVENT1_ISET_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_SRXFIFOTRG_SET SET 1 INT_EVENT1_ISET_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_STXFIFOTRG_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_MRXFIFOTRG_CLR CLR 1 INT_EVENT1_ICLR_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_MTXFIFOTRG_CLR CLR 1 INT_EVENT1_ICLR_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_SRXFIFOTRG_CLR CLR 1 INT_EVENT1_ICLR_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_STXFIFOTRG_CLR CLR 1 INT_EVENT2_IIDX Interrupt index 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 0x0 0x8 read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_MRXFIFOTRG MRXFIFOTRG 1 INT_EVENT2_IIDX_STAT_MTXFIFOTRG MTXFIFOTRG 2 INT_EVENT2_IIDX_STAT_SRXFIFOTRG SRXFIFOTRG 3 INT_EVENT2_IIDX_STAT_STXFIFOTRG STXFIFOTRG 4 INT_EVENT2_IMASK Interrupt mask 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_IMASK_MRXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_MRXFIFOTRG_SET SET 1 INT_EVENT2_IMASK_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_IMASK_MTXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_MTXFIFOTRG_SET SET 1 INT_EVENT2_IMASK_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_IMASK_SRXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_SRXFIFOTRG_SET SET 1 INT_EVENT2_IMASK_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_IMASK_STXFIFOTRG_CLR CLR 0 INT_EVENT2_IMASK_STXFIFOTRG_SET SET 1 INT_EVENT2_RIS Raw interrupt status 0x1090 32 read-only 0x00000000 INT_EVENT2_RIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_RIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_MRXFIFOTRG_SET SET 1 INT_EVENT2_RIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_RIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_MTXFIFOTRG_SET SET 1 INT_EVENT2_RIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_RIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_SRXFIFOTRG_SET SET 1 INT_EVENT2_RIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_RIS_STXFIFOTRG_CLR CLR 0 INT_EVENT2_RIS_STXFIFOTRG_SET SET 1 INT_EVENT2_MIS Masked interrupt status 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_MIS_MRXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_MRXFIFOTRG_SET SET 1 INT_EVENT2_MIS_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_MIS_MTXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_MTXFIFOTRG_SET SET 1 INT_EVENT2_MIS_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_MIS_SRXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_SRXFIFOTRG_SET SET 1 INT_EVENT2_MIS_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_MIS_STXFIFOTRG_CLR CLR 0 INT_EVENT2_MIS_STXFIFOTRG_SET SET 1 INT_EVENT2_ISET Interrupt set 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MRXFIFOTRG_SET SET 1 INT_EVENT2_ISET_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MTXFIFOTRG_SET SET 1 INT_EVENT2_ISET_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_SRXFIFOTRG_SET SET 1 INT_EVENT2_ISET_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_STXFIFOTRG_SET SET 1 INT_EVENT2_ICLR Interrupt clear 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_MRXFIFOTRG Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0x0 0x1 INT_EVENT2_ICLR_MRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MRXFIFOTRG_CLR CLR 1 INT_EVENT2_ICLR_MTXFIFOTRG Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0x1 0x1 INT_EVENT2_ICLR_MTXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MTXFIFOTRG_CLR CLR 1 INT_EVENT2_ICLR_SRXFIFOTRG Slave Receive FIFO Trigger 0x2 0x1 INT_EVENT2_ICLR_SRXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_SRXFIFOTRG_CLR CLR 1 INT_EVENT2_ICLR_STXFIFOTRG Slave Transmit FIFO Trigger 0x3 0x1 INT_EVENT2_ICLR_STXFIFOTRG_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_STXFIFOTRG_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write EVT_MODE_INT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0] 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_INT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1] 0x2 0x2 read-only EVT_MODE_INT1_CFG_DISABLE DISABLE 0 EVT_MODE_INT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 GFCTL I2C Glitch Filter Control 0x1200 32 read-write GFCTL_AGFSEL Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0x9 0x2 read-write GFCTL_AGFSEL_AGLIT_5 AGLIT_5 0 GFCTL_AGFSEL_AGLIT_10 AGLIT_10 1 GFCTL_AGFSEL_AGLIT_25 AGLIT_25 2 GFCTL_AGFSEL_AGLIT_50 AGLIT_50 3 GFCTL_DGFSEL Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0x0 0x3 read-write GFCTL_DGFSEL_DISABLED DISABLED 0 GFCTL_DGFSEL_CLK_1 CLK_1 1 GFCTL_DGFSEL_CLK_2 CLK_2 2 GFCTL_DGFSEL_CLK_3 CLK_3 3 GFCTL_DGFSEL_CLK_4 CLK_4 4 GFCTL_DGFSEL_CLK_8 CLK_8 5 GFCTL_DGFSEL_CLK_16 CLK_16 6 GFCTL_DGFSEL_CLK_31 CLK_31 7 GFCTL_AGFEN Analog Glitch Suppression Enable 0x8 0x1 read-write GFCTL_AGFEN_DISABLE DISABLE 0 GFCTL_AGFEN_ENABLE ENABLE 1 GFCTL_CHAIN Analog and digital noise filters chaining enable. 0xB 0x1 GFCTL_CHAIN_DISABLE DISABLE 0 GFCTL_CHAIN_ENABLE ENABLE 1 TIMEOUT_CTL I2C Timeout Count Control Register 0x1204 32 read-write 0x00020002 0xffffffff TIMEOUT_CTL_TCNTLA Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0x0 0x8 read-write TIMEOUT_CTL_TCNTAEN Timeout Counter A Enable 0xF 0x1 read-write TIMEOUT_CTL_TCNTAEN_DISABLE DISABLE 0 TIMEOUT_CTL_TCNTAEN_ENABLE ENABLE 1 TIMEOUT_CTL_TCNTLB Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0x10 0x8 read-write TIMEOUT_CTL_TCNTBEN Timeout Counter B Enable 0x1F 0x1 read-write TIMEOUT_CTL_TCNTBEN_DISABLE DISABLE 0 TIMEOUT_CTL_TCNTBEN_ENABLE ENABLE 1 TIMEOUT_CNT I2C Timeout Count Register 0x1208 32 read-only 0x00020002 0xffffffff TIMEOUT_CNT_TCNTA Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0x0 0x8 read-only TIMEOUT_CNT_TCNTB Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0x10 0x8 MSA I2C Master Slave Address Register 0x1210 32 read-write 0x00000000 MSA_DIR Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0x0 0x1 MSA_DIR_TRANSMIT TRANSMIT 0 MSA_DIR_RECEIVE RECEIVE 1 MSA_SADDR I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0x1 0xA MSA_MMODE This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 MSA_MMODE_MODE7 MODE7 0 MSA_MMODE_MODE10 MODE10 1 MCTR I2C Master Control Register 0x1214 32 read-write 0x00000000 0xffffffff MCTR_BURSTRUN I2C Master Enable and start transaction 0x0 0x1 read-write MCTR_BURSTRUN_DISABLE DISABLE 0 MCTR_BURSTRUN_ENABLE ENABLE 1 MCTR_START Generate START 0x1 0x1 read-write MCTR_START_DISABLE DISABLE 0 MCTR_START_ENABLE ENABLE 1 MCTR_STOP Generate STOP 0x2 0x1 read-write MCTR_STOP_DISABLE DISABLE 0 MCTR_STOP_ENABLE ENABLE 1 MCTR_ACK Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding. 0x3 0x1 read-write MCTR_ACK_DISABLE DISABLE 0 MCTR_ACK_ENABLE ENABLE 1 MCTR_MBLEN I2C transaction length This field contains the programmed length of bytes of the Transaction. 0x10 0xC read-write MCTR_MACKOEN Master ACK overrride Enable 0x4 0x1 MCTR_MACKOEN_DISABLE DISABLE 0 MCTR_MACKOEN_ENABLE ENABLE 1 MCTR_RD_ON_TXEMPTY Read on TX Empty 0x5 0x1 MCTR_RD_ON_TXEMPTY_DISABLE DISABLE 0 MCTR_RD_ON_TXEMPTY_ENABLE ENABLE 1 MSR I2C Master Status Register 0x1218 32 read-only MSR_BUSY I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0x0 0x1 read-only MSR_BUSY_CLEARED CLEARED 0 MSR_BUSY_SET SET 1 MSR_ERR Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0x1 0x1 read-only MSR_ERR_CLEARED CLEARED 0 MSR_ERR_SET SET 1 MSR_ADRACK Acknowledge Address 0x2 0x1 read-only MSR_ADRACK_CLEARED CLEARED 0 MSR_ADRACK_SET SET 1 MSR_DATACK Acknowledge Data 0x3 0x1 read-only MSR_DATACK_CLEARED CLEARED 0 MSR_DATACK_SET SET 1 MSR_ARBLST Arbitration Lost 0x4 0x1 read-only MSR_ARBLST_CLEARED CLEARED 0 MSR_ARBLST_SET SET 1 MSR_IDLE I2C Idle 0x5 0x1 read-only MSR_IDLE_CLEARED CLEARED 0 MSR_IDLE_SET SET 1 MSR_BUSBSY I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0x6 0x1 read-only MSR_BUSBSY_CLEARED CLEARED 0 MSR_BUSBSY_SET SET 1 MSR_MBCNT I2C Master Transaction Count This field contains the current count-down value of the transaction. 0x10 0xC read-only MRXDATA I2C Master RXData 0x121C 32 read-only 0x00000000 0xffffffff MRXDATA_VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only MTXDATA I2C Master TXData 0x1220 32 read-write 0x00000000 0xffffffff MTXDATA_VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write MTPR I2C Master Timer Period 0x1224 32 read-write 0x00000001 0xffffffff MTPR_TPR Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0x0 0x7 read-write MCR I2C Master Configuration 0x1228 32 read-write 0x00000000 0xffffffff MCR_LPBK I2C Loopback 0x8 0x1 read-write MCR_LPBK_DISABLE DISABLE 0 MCR_LPBK_ENABLE ENABLE 1 MCR_MMST Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller. 0x1 0x1 read-write MCR_MMST_DISABLE DISABLE 0 MCR_MMST_ENABLE ENABLE 1 MCR_ACTIVE Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0x0 0x1 read-write MCR_ACTIVE_DISABLE DISABLE 0 MCR_ACTIVE_ENABLE ENABLE 1 MCR_CLKSTRETCH Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0x2 0x1 read-write MCR_CLKSTRETCH_DISABLE DISABLE 0 MCR_CLKSTRETCH_ENABLE ENABLE 1 MBMON I2C Master Bus Monitor 0x1234 32 read-only 0x00000003 0xffffffff MBMON_SCL I2C SCL Status 0x0 0x1 read-only MBMON_SCL_CLEARED CLEARED 0 MBMON_SCL_SET SET 1 MBMON_SDA I2C SDA Status 0x1 0x1 read-only MBMON_SDA_CLEARED CLEARED 0 MBMON_SDA_SET SET 1 MFIFOCTL I2C Master FIFO Control 0x1238 32 read-write 0x00000000 MFIFOCTL_TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 MFIFOCTL_TXTRIG_LEVEL_4 LEVEL_4 4 MFIFOCTL_TXTRIG_LEVEL_5 LEVEL_5 5 MFIFOCTL_TXTRIG_LEVEL_6 LEVEL_6 6 MFIFOCTL_TXTRIG_LEVEL_7 LEVEL_7 7 MFIFOCTL_TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 MFIFOCTL_TXFLUSH_NOFLUSH NOFLUSH 0 MFIFOCTL_TXFLUSH_FLUSH FLUSH 1 MFIFOCTL_RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 MFIFOCTL_RXTRIG_LEVEL_5 LEVEL_5 4 MFIFOCTL_RXTRIG_LEVEL_6 LEVEL_6 5 MFIFOCTL_RXTRIG_LEVEL_7 LEVEL_7 6 MFIFOCTL_RXTRIG_LEVEL_8 LEVEL_8 7 MFIFOCTL_RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 MFIFOCTL_RXFLUSH_NOFLUSH NOFLUSH 0 MFIFOCTL_RXFLUSH_FLUSH FLUSH 1 MFIFOSR I2C Master FIFO Status Register 0x123C 32 read-only 0x00000800 MFIFOSR_RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only MFIFOSR_TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only MFIFOSR_RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 MFIFOSR_RXFLUSH_INACTIVE INACTIVE 0 MFIFOSR_RXFLUSH_ACTIVE ACTIVE 1 MFIFOSR_TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 MFIFOSR_TXFLUSH_INACTIVE INACTIVE 0 MFIFOSR_TXFLUSH_ACTIVE ACTIVE 1 MASTER_I2CPECCTL I2C master PEC control register 0x1240 32 read-write 0x00000000 0xffffffff MASTER_I2CPECCTL_PECCNT PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine. 0x0 0x9 MASTER_I2CPECCTL_PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 MASTER_I2CPECCTL_PECEN_DISABLE DISABLE 0 MASTER_I2CPECCTL_PECEN_ENABLE ENABLE 1 MASTER_PECSR I2C master PEC status register 0x1244 32 read-only 0x00000000 0xffffffff MASTER_PECSR_PECBYTECNT PEC Byte Count This is the current PEC Byte Count of the Master State Machine. 0x0 0x9 MASTER_PECSR_PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 MASTER_PECSR_PECSTS_CHECK_CLEARED CLEARED 0 MASTER_PECSR_PECSTS_CHECK_SET SET 1 MASTER_PECSR_PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 MASTER_PECSR_PECSTS_ERROR_CLEARED CLEARED 0 MASTER_PECSR_PECSTS_ERROR_SET SET 1 SOAR I2C Slave Own Address 0x1250 32 read-write 0x00004000 0xffffffff SOAR_OAR I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0x0 0xA read-write SOAR_OAREN I2C Slave Own Address Enable 0xE 0x1 SOAR_OAREN_DISABLE DISABLE 0 SOAR_OAREN_ENABLE ENABLE 1 SOAR_SMODE This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0xF 0x1 SOAR_SMODE_MODE7 MODE7 0 SOAR_SMODE_MODE10 MODE10 1 SOAR2 I2C Slave Own Address 2 0x1254 32 read-write 0x00000000 0xffffffff SOAR2_OAR2 I2C Slave Own Address 2 This field specifies the alternate OAR2 address. 0x0 0x7 read-write SOAR2_OAR2EN I2C Slave Own Address 2 Enable 0x7 0x1 read-write SOAR2_OAR2EN_DISABLE DISABLE 0 SOAR2_OAR2EN_ENABLE ENABLE 1 SOAR2_OAR2_MASK I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care. 0x10 0x7 SCTR I2C Slave Control Register 0x1258 32 read-write 0x00000404 0xffffffff SCTR_ACTIVE Device Active. Setting this bit enables the slave functionality. 0x0 0x1 read-write SCTR_ACTIVE_DISABLE DISABLE 0 SCTR_ACTIVE_ENABLE ENABLE 1 SCTR_GENCALL General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0x1 0x1 read-write SCTR_GENCALL_DISABLE DISABLE 0 SCTR_GENCALL_ENABLE ENABLE 1 SCTR_SCLKSTRETCH Slave Clock Stretch Enable 0x2 0x1 SCTR_SCLKSTRETCH_DISABLE DISABLE 0 SCTR_SCLKSTRETCH_ENABLE ENABLE 1 SCTR_TXEMPTY_ON_TREQ Tx Empty Interrupt on TREQ 0x3 0x1 SCTR_TXEMPTY_ON_TREQ_DISABLE DISABLE 0 SCTR_TXEMPTY_ON_TREQ_ENABLE ENABLE 1 SCTR_TXTRIG_TXMODE Tx Trigger when slave FSM is in Tx Mode 0x4 0x1 SCTR_TXTRIG_TXMODE_DISABLE DISABLE 0 SCTR_TXTRIG_TXMODE_ENABLE ENABLE 1 SCTR_TXWAIT_STALE_TXFIFO Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0x5 0x1 SCTR_TXWAIT_STALE_TXFIFO_DISABLE DISABLE 0 SCTR_TXWAIT_STALE_TXFIFO_ENABLE ENABLE 1 SCTR_RXFULL_ON_RREQ Rx full interrupt generated on RREQ condition as indicated in SSR 0x6 0x1 SCTR_RXFULL_ON_RREQ_DISABLE DISABLE 0 SCTR_RXFULL_ON_RREQ_ENABLE ENABLE 1 SCTR_EN_DEFHOSTADR Enable Default Host Address 0x7 0x1 SCTR_EN_DEFHOSTADR_DISABLE DISABLE 0 SCTR_EN_DEFHOSTADR_ENABLE ENABLE 1 SCTR_EN_ALRESPADR Enable Alert Response Address 0x8 0x1 SCTR_EN_ALRESPADR_DISABLE DISABLE 0 SCTR_EN_ALRESPADR_ENABLE ENABLE 1 SCTR_EN_DEFDEVADR Enable Deault device address 0x9 0x1 SCTR_EN_DEFDEVADR_DISABLE DISABLE 0 SCTR_EN_DEFDEVADR_ENABLE ENABLE 1 SCTR_SWUEN Slave Wakeup Enable 0xA 0x1 SCTR_SWUEN_DISABLE DISABLE 0 SCTR_SWUEN_ENABLE ENABLE 1 SSR I2C Slave Status Register 0x125C 32 read-only 0x00000000 0xffffffff SSR_RREQ Receive Request 0x0 0x1 read-only SSR_RREQ_CLEARED CLEARED 0 SSR_RREQ_SET SET 1 SSR_TREQ Transmit Request 0x1 0x1 read-only SSR_TREQ_CLEARED CLEARED 0 SSR_TREQ_SET SET 1 SSR_OAR2SEL OAR2 Address Matched This bit gets reevaluated after every address comparison. 0x3 0x1 read-only SSR_OAR2SEL_CLEARED CLEARED 0 SSR_OAR2SEL_SET SET 1 SSR_QCMDST Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0x4 0x1 read-only SSR_QCMDST_CLEARED CLEARED 0 SSR_QCMDST_SET SET 1 SSR_QCMDRW Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0x5 0x1 read-only SSR_QCMDRW_CLEARED CLEARED 0 SSR_QCMDRW_SET SET 1 SSR_RXMODE Slave FSM is in Rx MODE 0x2 0x1 SSR_RXMODE_CLEARED CLEARED 0 SSR_RXMODE_SET SET 1 SSR_BUSBSY I2C bus is busy 0x6 0x1 SSR_BUSBSY_CLEARED CLEARED 0 SSR_BUSBSY_SET SET 1 SSR_TXMODE Slave FSM is in TX MODE 0x7 0x1 SSR_TXMODE_CLEARED CLEARED 0 SSR_TXMODE_SET SET 1 SSR_STALE_TXFIFO Stale Tx FIFO 0x8 0x1 SSR_STALE_TXFIFO_CLEARED CLEARED 0 SSR_STALE_TXFIFO_SET SET 1 SSR_ADDRMATCH Indicates the address for which slave address match happened 0x9 0xA SRXDATA I2C Slave RXData 0x1260 32 read-only 0x00000000 0xffffffff SRXDATA_VALUE Received Data. This field contains the last received data. 0x0 0x8 read-only STXDATA I2C Slave TXData 0x1264 32 read-write 0x00000000 0xffffffff STXDATA_VALUE Transmit Data This byte contains the data to be transferred during the next transaction. 0x0 0x8 read-write SACKCTL I2C Slave ACK Control 0x1268 32 read-write 0x00000000 0xffffffff SACKCTL_ACKOEN I2C Slave ACK Override Enable 0x0 0x1 read-write SACKCTL_ACKOEN_DISABLE DISABLE 0 SACKCTL_ACKOEN_ENABLE ENABLE 1 SACKCTL_ACKOVAL I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data. 0x1 0x1 read-write SACKCTL_ACKOVAL_DISABLE DISABLE 0 SACKCTL_ACKOVAL_ENABLE ENABLE 1 SACKCTL_ACKOEN_ON_START When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition. 0x2 0x1 SACKCTL_ACKOEN_ON_START_DISABLE DISABLE 0 SACKCTL_ACKOEN_ON_START_ENABLE ENABLE 1 SACKCTL_ACKOEN_ON_PECNEXT When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL. 0x3 0x1 SACKCTL_ACKOEN_ON_PECNEXT_DISABLE DISABLE 0 SACKCTL_ACKOEN_ON_PECNEXT_ENABLE ENABLE 1 SACKCTL_ACKOEN_ON_PECDONE When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte. 0x4 0x1 SACKCTL_ACKOEN_ON_PECDONE_DISABLE DISABLE 0 SACKCTL_ACKOEN_ON_PECDONE_ENABLE ENABLE 1 SFIFOCTL I2C Slave FIFO Control 0x126C 32 read-write 0x00000000 SFIFOCTL_TXTRIG TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0x0 0x3 SFIFOCTL_TXTRIG_LEVEL_4 LEVEL_4 4 SFIFOCTL_TXTRIG_LEVEL_5 LEVEL_5 5 SFIFOCTL_TXTRIG_LEVEL_6 LEVEL_6 6 SFIFOCTL_TXTRIG_LEVEL_7 LEVEL_7 7 SFIFOCTL_TXFLUSH TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0x7 0x1 SFIFOCTL_TXFLUSH_NOFLUSH NOFLUSH 0 SFIFOCTL_TXFLUSH_FLUSH FLUSH 1 SFIFOCTL_RXFLUSH RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0xF 0x1 SFIFOCTL_RXFLUSH_NOFLUSH NOFLUSH 0 SFIFOCTL_RXFLUSH_FLUSH FLUSH 1 SFIFOCTL_RXTRIG RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0x8 0x3 SFIFOCTL_RXTRIG_LEVEL_5 LEVEL_5 4 SFIFOCTL_RXTRIG_LEVEL_6 LEVEL_6 5 SFIFOCTL_RXTRIG_LEVEL_7 LEVEL_7 6 SFIFOCTL_RXTRIG_LEVEL_8 LEVEL_8 7 SFIFOSR I2C Slave FIFO Status Register 0x1270 32 read-only 0x00000800 SFIFOSR_RXFIFOCNT Number of Bytes which could be read from the RX FIFO 0x0 0x4 read-only SFIFOSR_TXFIFOCNT Number of Bytes which could be put into the TX FIFO 0x8 0x4 read-only SFIFOSR_TXFLUSH TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0xF 0x1 SFIFOSR_TXFLUSH_INACTIVE INACTIVE 0 SFIFOSR_TXFLUSH_ACTIVE ACTIVE 1 SFIFOSR_RXFLUSH RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0x7 0x1 SFIFOSR_RXFLUSH_INACTIVE INACTIVE 0 SFIFOSR_RXFLUSH_ACTIVE ACTIVE 1 SLAVE_PECCTL I2C Slave PEC control register 0x1274 32 read-write 0x00000000 0xffffffff SLAVE_PECCTL_PECCNT When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction 0x0 0x9 SLAVE_PECCTL_PECEN PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1. 0xC 0x1 SLAVE_PECCTL_PECEN_DISABLE DISABLE 0 SLAVE_PECCTL_PECEN_ENABLE ENABLE 1 SLAVE_PECSR I2C slave PEC status register 0x1278 32 read-only 0x00000000 0xffffffff SLAVE_PECSR_PECBYTECNT This is the current PEC Byte Count of the Slave State Machine. 0x0 0x9 SLAVE_PECSR_PECSTS_CHECK This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop. 0x10 0x1 SLAVE_PECSR_PECSTS_CHECK_CLEARED CLEARED 0 SLAVE_PECSR_PECSTS_CHECK_SET SET 1 SLAVE_PECSR_PECSTS_ERROR This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop. 0x11 0x1 SLAVE_PECSR_PECSTS_ERROR_CLEARED CLEARED 0 SLAVE_PECSR_PECSTS_ERROR_SET SET 1 IOMUX 1.0 PERIPHERALREGION 0x40428000 0x0 0x2000 registers 61 4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60 PINCM[%s] Pin Control Management Register in SECCFG region 0x4 32 read-write 0x00000000 0x7f7fffff PINCM_PF P channel Function selection bits 0x0 0x6 read-write PINCM_PC Peripheral is Connected 0x7 0x1 read-write PINCM_PC_UNCONNECTED UNCONNECTED 0 PINCM_PC_CONNECTED CONNECTED 1 PINCM_WAKESTAT This has the IOPAD WAKEUP signal as status bit. 0xD 0x1 read-only PINCM_WAKESTAT_DISABLE DISABLE 0 PINCM_WAKESTAT_ENABLE ENABLE 1 PINCM_PIPD Pull Down control selection 0x10 0x1 read-write PINCM_PIPD_DISABLE DISABLE 0 PINCM_PIPD_ENABLE ENABLE 1 PINCM_PIPU Pull Up control selection 0x11 0x1 read-write PINCM_PIPU_DISABLE DISABLE 0 PINCM_PIPU_ENABLE ENABLE 1 PINCM_INENA Input Enable Control Selection 0x12 0x1 read-write PINCM_INENA_DISABLE DISABLE 0 PINCM_INENA_ENABLE ENABLE 1 PINCM_HYSTEN Hystersis Enable Control Selection 0x13 0x1 read-write PINCM_HYSTEN_DISABLE DISABLE 0 PINCM_HYSTEN_ENABLE ENABLE 1 PINCM_DRV Drive strength control selection, for HS IOCELL only 0x14 0x1 read-write PINCM_DRV_DRVVAL0 DRVVAL0 0 PINCM_DRV_DRVVAL1 DRVVAL1 1 PINCM_HIZ1 High output value will tri-state the output when this bit is enabled 0x19 0x1 read-write PINCM_HIZ1_DISABLE DISABLE 0 PINCM_HIZ1_ENABLE ENABLE 1 PINCM_WUEN Wakeup Enable bit 0x1B 0x1 read-write PINCM_WUEN_DISABLE DISABLE 0 PINCM_WUEN_ENABLE ENABLE 1 PINCM_WCOMP Wakeup Compare Value bit 0x1C 0x1 read-write PINCM_WCOMP_MATCH0 MATCH0 0 PINCM_WCOMP_MATCH1 MATCH1 1 PINCM_INV Data inversion selection 0x1A 0x1 read-write PINCM_INV_DISABLE DISABLE 0 PINCM_INV_ENABLE ENABLE 1 TIMG2 1.0 PERIPHERALREGION 0x40088000 0x0 0x1F00 registers FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 FPUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x8 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_Z Z 1 IIDX_STAT_L L 2 IIDX_STAT_CCD0 CCD0 5 IIDX_STAT_CCD1 CCD1 6 IIDX_STAT_CCD2 CCD2 7 IIDX_STAT_CCD3 CCD3 8 IIDX_STAT_CCU0 CCU0 9 IIDX_STAT_CCU1 CCU1 10 IIDX_STAT_CCU2 CCU2 11 IIDX_STAT_CCU3 CCU3 12 IIDX_STAT_CCD4 CCD4 13 IIDX_STAT_CCD5 CCD5 14 IIDX_STAT_CCU4 CCU4 15 IIDX_STAT_CCU5 CCU5 16 IIDX_STAT_F F 25 IIDX_STAT_TOV TOV 26 IIDX_STAT_REPC REPC 27 IIDX_STAT_DC DC 28 IIDX_STAT_QEIERR QEIERR 29 IMASK Interrupt mask 0x1028 32 read-write IMASK_Z Zero Event mask 0x0 0x1 IMASK_Z_CLR CLR 0 IMASK_Z_SET SET 1 IMASK_L Load Event mask 0x1 0x1 IMASK_L_CLR CLR 0 IMASK_L_SET SET 1 IMASK_CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 IMASK_CCD0_CLR CLR 0 IMASK_CCD0_SET SET 1 IMASK_CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 IMASK_CCD1_CLR CLR 0 IMASK_CCD1_SET SET 1 IMASK_CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 IMASK_CCU0_CLR CLR 0 IMASK_CCU0_SET SET 1 IMASK_CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 IMASK_CCU1_CLR CLR 0 IMASK_CCU1_SET SET 1 IMASK_TOV Trigger Overflow Event mask 0x19 0x1 IMASK_TOV_CLR CLR 0 IMASK_TOV_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 0xffffffff RIS_Z Zero event generated an interrupt. 0x0 0x1 RIS_Z_CLR CLR 0 RIS_Z_SET SET 1 RIS_L Load event generated an interrupt. 0x1 0x1 RIS_L_CLR CLR 0 RIS_L_SET SET 1 RIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 RIS_CCD0_CLR CLR 0 RIS_CCD0_SET SET 1 RIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 RIS_CCD1_CLR CLR 0 RIS_CCD1_SET SET 1 RIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 RIS_CCU0_CLR CLR 0 RIS_CCU0_SET SET 1 RIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 RIS_CCU1_CLR CLR 0 RIS_CCU1_SET SET 1 RIS_TOV Trigger overflow 0x19 0x1 RIS_TOV_CLR CLR 0 RIS_TOV_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_Z Zero event generated an interrupt. 0x0 0x1 MIS_Z_CLR CLR 0 MIS_Z_SET SET 1 MIS_L Load event generated an interrupt. 0x1 0x1 MIS_L_CLR CLR 0 MIS_L_SET SET 1 MIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 MIS_CCD0_CLR CLR 0 MIS_CCD0_SET SET 1 MIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 MIS_CCD1_CLR CLR 0 MIS_CCD1_SET SET 1 MIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 MIS_CCU0_CLR CLR 0 MIS_CCU0_SET SET 1 MIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 MIS_CCU1_CLR CLR 0 MIS_CCU1_SET SET 1 MIS_TOV Trigger overflow 0x19 0x1 MIS_TOV_CLR CLR 0 MIS_TOV_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_Z Zero event SET 0x0 0x1 ISET_Z_NO_EFFECT NO_EFFECT 0 ISET_Z_SET SET 1 ISET_L Load event SET 0x1 0x1 ISET_L_NO_EFFECT NO_EFFECT 0 ISET_L_SET SET 1 ISET_CCD0 Capture or compare down event SET 0x4 0x1 ISET_CCD0_NO_EFFECT NO_EFFECT 0 ISET_CCD0_SET SET 1 ISET_CCD1 Capture or compare down event SET 0x5 0x1 ISET_CCD1_NO_EFFECT NO_EFFECT 0 ISET_CCD1_SET SET 1 ISET_CCU0 Capture or compare up event SET 0x8 0x1 ISET_CCU0_NO_EFFECT NO_EFFECT 0 ISET_CCU0_SET SET 1 ISET_CCU1 Capture or compare up event SET 0x9 0x1 ISET_CCU1_NO_EFFECT NO_EFFECT 0 ISET_CCU1_SET SET 1 ISET_TOV Trigger Overflow event SET 0x19 0x1 ISET_TOV_NO_EFFECT NO_EFFECT 0 ISET_TOV_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_Z Zero event CLEAR 0x0 0x1 ICLR_Z_NO_EFFECT NO_EFFECT 0 ICLR_Z_CLR CLR 1 ICLR_L Load event CLEAR 0x1 0x1 ICLR_L_NO_EFFECT NO_EFFECT 0 ICLR_L_CLR CLR 1 ICLR_CCD0 Capture or compare down event CLEAR 0x4 0x1 ICLR_CCD0_NO_EFFECT NO_EFFECT 0 ICLR_CCD0_CLR CLR 1 ICLR_CCD1 Capture or compare down event CLEAR 0x5 0x1 ICLR_CCD1_NO_EFFECT NO_EFFECT 0 ICLR_CCD1_CLR CLR 1 ICLR_CCU0 Capture or compare up event CLEAR 0x8 0x1 ICLR_CCU0_NO_EFFECT NO_EFFECT 0 ICLR_CCU0_CLR CLR 1 ICLR_CCU1 Capture or compare up event CLEAR 0x9 0x1 ICLR_CCU1_NO_EFFECT NO_EFFECT 0 ICLR_CCU1_CLR CLR 1 ICLR_TOV Trigger Overflow event CLEAR 0x19 0x1 ICLR_TOV_NO_EFFECT NO_EFFECT 0 ICLR_TOV_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT_MODE_EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only EVT_MODE_EVT0_CFG_DISABLE DISABLE 0 EVT_MODE_EVT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CCPD CCP Direction 0x1100 32 read-write CCPD_C0CCP0 Counter CCP0 0x0 0x1 CCPD_C0CCP0_INPUT INPUT 0 CCPD_C0CCP0_OUTPUT OUTPUT 1 CCPD_C0CCP1 Counter CCP1 0x1 0x1 CCPD_C0CCP1_INPUT INPUT 0 CCPD_C0CCP1_OUTPUT OUTPUT 1 ODIS Output Disable 0x1104 32 read-write ODIS_C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write ODIS_C0CCP0_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP0_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 ODIS_C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write ODIS_C0CCP1_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP1_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 CCLKCTL Counter Clock Control Register 0x1108 32 read-write CCLKCTL_CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write CCLKCTL_CLKEN_DISABLED DISABLED 0 CCLKCTL_CLKEN_ENABLED ENABLED 1 CPS Clock Prescale Register 0x110C 32 read-write CPS_PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write CPSV Clock prescale count status register 0x1110 32 read-only CPSV_CPSVAL Current Prescale Count Value 0x0 0x8 read-only CTTRIGCTL Timer Cross Trigger Control Register 0x1114 32 read-write CTTRIGCTL_CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write CTTRIGCTL_CTEN_DISABLED DISABLED 0 CTTRIGCTL_CTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write CTTRIGCTL_EVTCTEN_DISABLED DISABLED 0 CTTRIGCTL_EVTCTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write CTTRIGCTL_EVTCTTRIGSEL_FSUB0 FSUB0 0 CTTRIGCTL_EVTCTTRIGSEL_FSUB1 FSUB1 1 CTTRIGCTL_EVTCTTRIGSEL_Z Z 2 CTTRIGCTL_EVTCTTRIGSEL_L L 3 CTTRIGCTL_EVTCTTRIGSEL_CCD0 CCD0 4 CTTRIGCTL_EVTCTTRIGSEL_CCD1 CCD1 5 CTTRIGCTL_EVTCTTRIGSEL_CCD2 CCD2 6 CTTRIGCTL_EVTCTTRIGSEL_CCD3 CCD3 7 CTTRIGCTL_EVTCTTRIGSEL_CCU0 CCU0 8 CTTRIGCTL_EVTCTTRIGSEL_CCU1 CCU1 9 CTTRIGCTL_EVTCTTRIGSEL_CCU2 CCU2 10 CTTRIGCTL_EVTCTTRIGSEL_CCU3 CCU3 11 CTTRIG Timer Cross Trigger Register 0x111C 32 write-only CTTRIG_TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only CTTRIG_TRIG_DISABLED DISABLED 0 CTTRIG_TRIG_GENERATE GENERATE 1 CTR Counter Register 0x1800 32 read-write 0x00000000 0xffffffff CTR_CCTR Current Counter value 0x0 0x10 read-write CTRCTL Counter Control Register 0x1804 32 read-write 0x0000ff80 0xffffffff CTRCTL_EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write CTRCTL_EN_DISABLED DISABLED 0 CTRCTL_EN_ENABLED ENABLED 1 CTRCTL_REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write CTRCTL_REPEAT_REPEAT_0 REPEAT_0 0 CTRCTL_REPEAT_REPEAT_1 REPEAT_1 1 CTRCTL_REPEAT_REPEAT_2 REPEAT_2 2 CTRCTL_REPEAT_REPEAT_3 REPEAT_3 3 CTRCTL_REPEAT_REPEAT_4 REPEAT_4 4 CTRCTL_CM Count Mode 0x4 0x2 read-write CTRCTL_CM_DOWN DOWN 0 CTRCTL_CM_UP_DOWN UP_DOWN 1 CTRCTL_CM_UP UP 2 CTRCTL_CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write CTRCTL_CVAE_LDVAL LDVAL 0 CTRCTL_CVAE_NOCHANGE NOCHANGE 1 CTRCTL_CVAE_ZEROVAL ZEROVAL 2 CTRCTL_DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write CTRCTL_DRB_RESUME RESUME 0 CTRCTL_DRB_CVAE_ACTION CVAE_ACTION 1 CTRCTL_CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CTRCTL_CLC_CCCTL0_LCOND CCCTL0_LCOND 0 CTRCTL_CLC_CCCTL1_LCOND CCCTL1_LCOND 1 CTRCTL_CLC_CCCTL2_LCOND CCCTL2_LCOND 2 CTRCTL_CLC_CCCTL3_LCOND CCCTL3_LCOND 3 CTRCTL_CLC_QEI_2INP QEI_2INP 4 CTRCTL_CLC_QEI_3INP QEI_3INP 5 CTRCTL_CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CTRCTL_CAC_CCCTL0_ACOND CCCTL0_ACOND 0 CTRCTL_CAC_CCCTL1_ACOND CCCTL1_ACOND 1 CTRCTL_CAC_CCCTL2_ACOND CCCTL2_ACOND 2 CTRCTL_CAC_CCCTL3_ACOND CCCTL3_ACOND 3 CTRCTL_CAC_QEI_2INP QEI_2INP 4 CTRCTL_CAC_QEI_3INP QEI_3INP 5 CTRCTL_CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CTRCTL_CZC_CCCTL0_ZCOND CCCTL0_ZCOND 0 CTRCTL_CZC_CCCTL1_ZCOND CCCTL1_ZCOND 1 CTRCTL_CZC_CCCTL2_ZCOND CCCTL2_ZCOND 2 CTRCTL_CZC_CCCTL3_ZCOND CCCTL3_ZCOND 3 CTRCTL_CZC_QEI_2INP QEI_2INP 4 CTRCTL_CZC_QEI_3INP QEI_3INP 5 LOAD Load Register 0x1808 32 read-write 0x00000000 0xffffffff LOAD_LD Load Value 0x0 0x10 read-write 2 4 0,1 CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x1810 32 read-write 0x00000000 0xffffffff CC_01_CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 CCCTL_01[%s] Capture or Compare Control Registers 0x1830 32 read-write 0x00000000 0xffffffff CCCTL_01_CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write CCCTL_01_CCOND_NOCAPTURE NOCAPTURE 0 CCCTL_01_CCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_CCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_CCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write CCCTL_01_ACOND_TIMCLK TIMCLK 0 CCCTL_01_ACOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ACOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ACOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND_CC_TRIG_HIGH CC_TRIG_HIGH 5 CCCTL_01_LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CCCTL_01_LCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_LCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_LCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CCCTL_01_ZCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ZCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ZCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write CCCTL_01_COC_COMPARE COMPARE 0 CCCTL_01_COC_CAPTURE CAPTURE 1 CCCTL_01_CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write CCCTL_01_CCACTUPD_IMMEDIATELY IMMEDIATELY 0 CCCTL_01_CCACTUPD_ZERO_EVT ZERO_EVT 1 CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT COMPARE_DOWN_EVT 2 CCCTL_01_CCACTUPD_COMPARE_UP_EVT COMPARE_UP_EVT 3 CCCTL_01_CCACTUPD_ZERO_LOAD_EVT ZERO_LOAD_EVT 4 CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT ZERO_RC_ZERO_EVT 5 CCCTL_01_CCACTUPD_TRIG TRIG 6 CCCTL_01_CC2SELU Selects the source second CCU event. 0x16 0x3 CCCTL_01_CC2SELU_SEL_CCU0 SEL_CCU0 0 CCCTL_01_CC2SELU_SEL_CCU1 SEL_CCU1 1 CCCTL_01_CC2SELU_SEL_CCU2 SEL_CCU2 2 CCCTL_01_CC2SELU_SEL_CCU3 SEL_CCU3 3 CCCTL_01_CC2SELU_SEL_CCU4 SEL_CCU4 4 CCCTL_01_CC2SELU_SEL_CCU5 SEL_CCU5 5 CCCTL_01_CC2SELD Selects the source second CCD event. 0x1D 0x3 CCCTL_01_CC2SELD_SEL_CCD0 SEL_CCD0 0 CCCTL_01_CC2SELD_SEL_CCD1 SEL_CCD1 1 CCCTL_01_CC2SELD_SEL_CCD2 SEL_CCD2 2 CCCTL_01_CC2SELD_SEL_CCD3 SEL_CCD3 3 CCCTL_01_CC2SELD_SEL_CCD4 SEL_CCD4 4 CCCTL_01_CC2SELD_SEL_CCD5 SEL_CCD5 5 2 4 0,1 OCTL_01[%s] CCP Output Control Registers 0x1850 32 read-write 0x00000000 0xffffffff OCTL_01_CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write OCTL_01_CCPOINV_NOINV NOINV 0 OCTL_01_CCPOINV_INV INV 1 OCTL_01_CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write OCTL_01_CCPIV_LOW LOW 0 OCTL_01_CCPIV_HIGH HIGH 1 OCTL_01_CCPO CCP Output Source 0x0 0x4 read-write OCTL_01_CCPO_FUNCVAL FUNCVAL 0 OCTL_01_CCPO_LOAD LOAD 1 OCTL_01_CCPO_CMPVAL CMPVAL 2 OCTL_01_CCPO_ZERO ZERO 4 OCTL_01_CCPO_CAPCOND CAPCOND 5 OCTL_01_CCPO_FAULTCOND FAULTCOND 6 OCTL_01_CCPO_CC0_MIRROR_ALL CC0_MIRROR_ALL 8 OCTL_01_CCPO_CC1_MIRROR_ALL CC1_MIRROR_ALL 9 OCTL_01_CCPO_DEADBAND DEADBAND 12 OCTL_01_CCPO_CNTDIR CNTDIR 13 2 4 0,1 CCACT_01[%s] Capture or Compare Action Registers 0x1870 32 read-write 0x00000000 0xffffffff CCACT_01_ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write CCACT_01_ZACT_DISABLED DISABLED 0 CCACT_01_ZACT_CCP_HIGH CCP_HIGH 1 CCACT_01_ZACT_CCP_LOW CCP_LOW 2 CCACT_01_ZACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write CCACT_01_LACT_DISABLED DISABLED 0 CCACT_01_LACT_CCP_HIGH CCP_HIGH 1 CCACT_01_LACT_CCP_LOW CCP_LOW 2 CCACT_01_LACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write CCACT_01_CDACT_DISABLED DISABLED 0 CCACT_01_CDACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CDACT_CCP_LOW CCP_LOW 2 CCACT_01_CDACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write CCACT_01_CUACT_DISABLED DISABLED 0 CCACT_01_CUACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CUACT_CCP_LOW CCP_LOW 2 CCACT_01_CUACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write CCACT_01_CC2DACT_DISABLED DISABLED 0 CCACT_01_CC2DACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2DACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2DACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write CCACT_01_CC2UACT_DISABLED DISABLED 0 CCACT_01_CC2UACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2UACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2UACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_SWFRCACT CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write CCACT_01_SWFRCACT_DISABLED DISABLED 0 CCACT_01_SWFRCACT_CCP_HIGH CCP_HIGH 1 CCACT_01_SWFRCACT_CCP_LOW CCP_LOW 2 2 4 0,1 IFCTL_01[%s] Input Filter Control Register 0x1880 32 read-write 0x00000000 0xffffffff IFCTL_01_ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write IFCTL_01_ISEL_CCPX_INPUT CCPX_INPUT 0 IFCTL_01_ISEL_CCPX_INPUT_PAIR CCPX_INPUT_PAIR 1 IFCTL_01_ISEL_CCP0_INPUT CCP0_INPUT 2 IFCTL_01_ISEL_TRIG_INPUT TRIG_INPUT 3 IFCTL_01_ISEL_CCP_XOR CCP_XOR 4 IFCTL_01_ISEL_FSUB0 FSUB0 5 IFCTL_01_ISEL_FSUB1 FSUB1 6 IFCTL_01_ISEL_COMP0 COMP0 7 IFCTL_01_ISEL_COMP1 COMP1 8 IFCTL_01_ISEL_COMP2 COMP2 9 IFCTL_01_INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write IFCTL_01_INV_NOINVERT NOINVERT 0 IFCTL_01_INV_INVERT INVERT 1 IFCTL_01_FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write IFCTL_01_FP__3 _3 0 IFCTL_01_FP__5 _5 1 IFCTL_01_FP__8 _8 2 IFCTL_01_CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write IFCTL_01_CPV_CONSECUTIVE CONSECUTIVE 0 IFCTL_01_CPV_VOTING VOTING 1 IFCTL_01_FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write IFCTL_01_FE_DISABLED DISABLED 0 IFCTL_01_FE_ENABLED ENABLED 1 TSEL Trigger Select 0x18B0 32 read-write 0x00000000 0xffffffff TSEL_ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TSEL_ETSEL_TRIG0 TRIG0 0 TSEL_ETSEL_TRIG1 TRIG1 1 TSEL_ETSEL_TRIG2 TRIG2 2 TSEL_ETSEL_TRIG3 TRIG3 3 TSEL_ETSEL_TRIG4 TRIG4 4 TSEL_ETSEL_TRIG5 TRIG5 5 TSEL_ETSEL_TRIG6 TRIG6 6 TSEL_ETSEL_TRIG7 TRIG7 7 TSEL_ETSEL_TRIG8 TRIG8 8 TSEL_ETSEL_TRIG9 TRIG9 9 TSEL_ETSEL_TRIG10 TRIG10 10 TSEL_ETSEL_TRIG11 TRIG11 11 TSEL_ETSEL_TRIG12 TRIG12 12 TSEL_ETSEL_TRIG13 TRIG13 13 TSEL_ETSEL_TRIG14 TRIG14 14 TSEL_ETSEL_TRIG15 TRIG15 15 TSEL_ETSEL_TRIG_SUB0 TRIG_SUB0 16 TSEL_ETSEL_TRIG_SUB1 TRIG_SUB1 17 TSEL_TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write TSEL_TE_DISABLED DISABLED 0 TSEL_TE_ENABLED ENABLED 1 TIMG4 1.0 PERIPHERALREGION 0x4008C000 0x0 0x1F00 registers FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 FPUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x8 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_Z Z 1 IIDX_STAT_L L 2 IIDX_STAT_CCD0 CCD0 5 IIDX_STAT_CCD1 CCD1 6 IIDX_STAT_CCD2 CCD2 7 IIDX_STAT_CCD3 CCD3 8 IIDX_STAT_CCU0 CCU0 9 IIDX_STAT_CCU1 CCU1 10 IIDX_STAT_CCU2 CCU2 11 IIDX_STAT_CCU3 CCU3 12 IIDX_STAT_CCD4 CCD4 13 IIDX_STAT_CCD5 CCD5 14 IIDX_STAT_CCU4 CCU4 15 IIDX_STAT_CCU5 CCU5 16 IIDX_STAT_F F 25 IIDX_STAT_TOV TOV 26 IIDX_STAT_REPC REPC 27 IIDX_STAT_DC DC 28 IIDX_STAT_QEIERR QEIERR 29 IMASK Interrupt mask 0x1028 32 read-write IMASK_Z Zero Event mask 0x0 0x1 IMASK_Z_CLR CLR 0 IMASK_Z_SET SET 1 IMASK_L Load Event mask 0x1 0x1 IMASK_L_CLR CLR 0 IMASK_L_SET SET 1 IMASK_CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 IMASK_CCD0_CLR CLR 0 IMASK_CCD0_SET SET 1 IMASK_CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 IMASK_CCD1_CLR CLR 0 IMASK_CCD1_SET SET 1 IMASK_CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 IMASK_CCU0_CLR CLR 0 IMASK_CCU0_SET SET 1 IMASK_CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 IMASK_CCU1_CLR CLR 0 IMASK_CCU1_SET SET 1 IMASK_TOV Trigger Overflow Event mask 0x19 0x1 IMASK_TOV_CLR CLR 0 IMASK_TOV_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 0xffffffff RIS_Z Zero event generated an interrupt. 0x0 0x1 RIS_Z_CLR CLR 0 RIS_Z_SET SET 1 RIS_L Load event generated an interrupt. 0x1 0x1 RIS_L_CLR CLR 0 RIS_L_SET SET 1 RIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 RIS_CCD0_CLR CLR 0 RIS_CCD0_SET SET 1 RIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 RIS_CCD1_CLR CLR 0 RIS_CCD1_SET SET 1 RIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 RIS_CCU0_CLR CLR 0 RIS_CCU0_SET SET 1 RIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 RIS_CCU1_CLR CLR 0 RIS_CCU1_SET SET 1 RIS_TOV Trigger overflow 0x19 0x1 RIS_TOV_CLR CLR 0 RIS_TOV_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_Z Zero event generated an interrupt. 0x0 0x1 MIS_Z_CLR CLR 0 MIS_Z_SET SET 1 MIS_L Load event generated an interrupt. 0x1 0x1 MIS_L_CLR CLR 0 MIS_L_SET SET 1 MIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 MIS_CCD0_CLR CLR 0 MIS_CCD0_SET SET 1 MIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 MIS_CCD1_CLR CLR 0 MIS_CCD1_SET SET 1 MIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 MIS_CCU0_CLR CLR 0 MIS_CCU0_SET SET 1 MIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 MIS_CCU1_CLR CLR 0 MIS_CCU1_SET SET 1 MIS_TOV Trigger overflow 0x19 0x1 MIS_TOV_CLR CLR 0 MIS_TOV_SET SET 1 MIS_CCD4 Compare down event generated an interrupt CCP4 0xC 0x1 MIS_CCD4_CLR CLR 0 MIS_CCD4_SET SET 1 MIS_CCD5 Compare down event generated an interrupt CCP5 0xD 0x1 MIS_CCD5_CLR CLR 0 MIS_CCD5_SET SET 1 MIS_CCU4 Compare up event generated an interrupt CCP4 0xE 0x1 MIS_CCU4_CLR CLR 0 MIS_CCU4_SET SET 1 MIS_CCU5 Compare up event generated an interrupt CCP5 0xF 0x1 MIS_CCU5_CLR CLR 0 MIS_CCU5_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_Z Zero event SET 0x0 0x1 ISET_Z_NO_EFFECT NO_EFFECT 0 ISET_Z_SET SET 1 ISET_L Load event SET 0x1 0x1 ISET_L_NO_EFFECT NO_EFFECT 0 ISET_L_SET SET 1 ISET_CCD0 Capture or compare down event SET 0x4 0x1 ISET_CCD0_NO_EFFECT NO_EFFECT 0 ISET_CCD0_SET SET 1 ISET_CCD1 Capture or compare down event SET 0x5 0x1 ISET_CCD1_NO_EFFECT NO_EFFECT 0 ISET_CCD1_SET SET 1 ISET_CCU0 Capture or compare up event SET 0x8 0x1 ISET_CCU0_NO_EFFECT NO_EFFECT 0 ISET_CCU0_SET SET 1 ISET_CCU1 Capture or compare up event SET 0x9 0x1 ISET_CCU1_NO_EFFECT NO_EFFECT 0 ISET_CCU1_SET SET 1 ISET_TOV Trigger Overflow event SET 0x19 0x1 ISET_TOV_NO_EFFECT NO_EFFECT 0 ISET_TOV_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_Z Zero event CLEAR 0x0 0x1 ICLR_Z_NO_EFFECT NO_EFFECT 0 ICLR_Z_CLR CLR 1 ICLR_L Load event CLEAR 0x1 0x1 ICLR_L_NO_EFFECT NO_EFFECT 0 ICLR_L_CLR CLR 1 ICLR_CCD0 Capture or compare down event CLEAR 0x4 0x1 ICLR_CCD0_NO_EFFECT NO_EFFECT 0 ICLR_CCD0_CLR CLR 1 ICLR_CCD1 Capture or compare down event CLEAR 0x5 0x1 ICLR_CCD1_NO_EFFECT NO_EFFECT 0 ICLR_CCD1_CLR CLR 1 ICLR_CCU0 Capture or compare up event CLEAR 0x8 0x1 ICLR_CCU0_NO_EFFECT NO_EFFECT 0 ICLR_CCU0_CLR CLR 1 ICLR_CCU1 Capture or compare up event CLEAR 0x9 0x1 ICLR_CCU1_NO_EFFECT NO_EFFECT 0 ICLR_CCU1_CLR CLR 1 ICLR_TOV Trigger Overflow event CLEAR 0x19 0x1 ICLR_TOV_NO_EFFECT NO_EFFECT 0 ICLR_TOV_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT_MODE_EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only EVT_MODE_EVT0_CFG_DISABLE DISABLE 0 EVT_MODE_EVT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CCPD CCP Direction 0x1100 32 read-write CCPD_C0CCP0 Counter CCP0 0x0 0x1 CCPD_C0CCP0_INPUT INPUT 0 CCPD_C0CCP0_OUTPUT OUTPUT 1 CCPD_C0CCP1 Counter CCP1 0x1 0x1 CCPD_C0CCP1_INPUT INPUT 0 CCPD_C0CCP1_OUTPUT OUTPUT 1 ODIS Output Disable 0x1104 32 read-write ODIS_C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write ODIS_C0CCP0_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP0_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 ODIS_C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write ODIS_C0CCP1_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP1_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 CCLKCTL Counter Clock Control Register 0x1108 32 read-write CCLKCTL_CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write CCLKCTL_CLKEN_DISABLED DISABLED 0 CCLKCTL_CLKEN_ENABLED ENABLED 1 CPS Clock Prescale Register 0x110C 32 read-write CPS_PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write CPSV Clock prescale count status register 0x1110 32 read-only CPSV_CPSVAL Current Prescale Count Value 0x0 0x8 read-only CTTRIGCTL Timer Cross Trigger Control Register 0x1114 32 read-write CTTRIGCTL_CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write CTTRIGCTL_CTEN_DISABLED DISABLED 0 CTTRIGCTL_CTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write CTTRIGCTL_EVTCTEN_DISABLED DISABLED 0 CTTRIGCTL_EVTCTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write CTTRIGCTL_EVTCTTRIGSEL_FSUB0 FSUB0 0 CTTRIGCTL_EVTCTTRIGSEL_FSUB1 FSUB1 1 CTTRIGCTL_EVTCTTRIGSEL_Z Z 2 CTTRIGCTL_EVTCTTRIGSEL_L L 3 CTTRIGCTL_EVTCTTRIGSEL_CCD0 CCD0 4 CTTRIGCTL_EVTCTTRIGSEL_CCD1 CCD1 5 CTTRIGCTL_EVTCTTRIGSEL_CCD2 CCD2 6 CTTRIGCTL_EVTCTTRIGSEL_CCD3 CCD3 7 CTTRIGCTL_EVTCTTRIGSEL_CCU0 CCU0 8 CTTRIGCTL_EVTCTTRIGSEL_CCU1 CCU1 9 CTTRIGCTL_EVTCTTRIGSEL_CCU2 CCU2 10 CTTRIGCTL_EVTCTTRIGSEL_CCU3 CCU3 11 CTTRIG Timer Cross Trigger Register 0x111C 32 write-only CTTRIG_TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only CTTRIG_TRIG_DISABLED DISABLED 0 CTTRIG_TRIG_GENERATE GENERATE 1 GCTL Shadow to active load mask 0x1124 32 read-write GCTL_SHDWLDEN Enables shadow to active load of bufferred registers and register fields. 0x0 0x1 read-write GCTL_SHDWLDEN_DISABLE DISABLE 0 GCTL_SHDWLDEN_ENABLE ENABLE 1 CTR Counter Register 0x1800 32 read-write 0x00000000 0xffffffff CTR_CCTR Current Counter value 0x0 0x10 read-write CTRCTL Counter Control Register 0x1804 32 read-write 0x0000ff80 0xffffffff CTRCTL_EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write CTRCTL_EN_DISABLED DISABLED 0 CTRCTL_EN_ENABLED ENABLED 1 CTRCTL_REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write CTRCTL_REPEAT_REPEAT_0 REPEAT_0 0 CTRCTL_REPEAT_REPEAT_1 REPEAT_1 1 CTRCTL_REPEAT_REPEAT_2 REPEAT_2 2 CTRCTL_REPEAT_REPEAT_3 REPEAT_3 3 CTRCTL_REPEAT_REPEAT_4 REPEAT_4 4 CTRCTL_CM Count Mode 0x4 0x2 read-write CTRCTL_CM_DOWN DOWN 0 CTRCTL_CM_UP_DOWN UP_DOWN 1 CTRCTL_CM_UP UP 2 CTRCTL_CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write CTRCTL_CVAE_LDVAL LDVAL 0 CTRCTL_CVAE_NOCHANGE NOCHANGE 1 CTRCTL_CVAE_ZEROVAL ZEROVAL 2 CTRCTL_DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write CTRCTL_DRB_RESUME RESUME 0 CTRCTL_DRB_CVAE_ACTION CVAE_ACTION 1 CTRCTL_CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CTRCTL_CLC_CCCTL0_LCOND CCCTL0_LCOND 0 CTRCTL_CLC_CCCTL1_LCOND CCCTL1_LCOND 1 CTRCTL_CLC_CCCTL2_LCOND CCCTL2_LCOND 2 CTRCTL_CLC_CCCTL3_LCOND CCCTL3_LCOND 3 CTRCTL_CLC_QEI_2INP QEI_2INP 4 CTRCTL_CLC_QEI_3INP QEI_3INP 5 CTRCTL_CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CTRCTL_CAC_CCCTL0_ACOND CCCTL0_ACOND 0 CTRCTL_CAC_CCCTL1_ACOND CCCTL1_ACOND 1 CTRCTL_CAC_CCCTL2_ACOND CCCTL2_ACOND 2 CTRCTL_CAC_CCCTL3_ACOND CCCTL3_ACOND 3 CTRCTL_CAC_QEI_2INP QEI_2INP 4 CTRCTL_CAC_QEI_3INP QEI_3INP 5 CTRCTL_CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CTRCTL_CZC_CCCTL0_ZCOND CCCTL0_ZCOND 0 CTRCTL_CZC_CCCTL1_ZCOND CCCTL1_ZCOND 1 CTRCTL_CZC_CCCTL2_ZCOND CCCTL2_ZCOND 2 CTRCTL_CZC_CCCTL3_ZCOND CCCTL3_ZCOND 3 CTRCTL_CZC_QEI_2INP QEI_2INP 4 CTRCTL_CZC_QEI_3INP QEI_3INP 5 LOAD Load Register 0x1808 32 read-write 0x00000000 0xffffffff LOAD_LD Load Value 0x0 0x10 read-write 2 4 0,1 CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x1810 32 read-write 0x00000000 0xffffffff CC_01_CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 CCCTL_01[%s] Capture or Compare Control Registers 0x1830 32 read-write 0x00000000 0xffffffff CCCTL_01_CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write CCCTL_01_CCOND_NOCAPTURE NOCAPTURE 0 CCCTL_01_CCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_CCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_CCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write CCCTL_01_ACOND_TIMCLK TIMCLK 0 CCCTL_01_ACOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ACOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ACOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND_CC_TRIG_HIGH CC_TRIG_HIGH 5 CCCTL_01_LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CCCTL_01_LCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_LCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_LCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CCCTL_01_ZCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ZCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ZCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write CCCTL_01_COC_COMPARE COMPARE 0 CCCTL_01_COC_CAPTURE CAPTURE 1 CCCTL_01_CCUPD Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0). 0x12 0x3 read-write CCCTL_01_CCUPD_IMMEDIATELY IMMEDIATELY 0 CCCTL_01_CCUPD_ZERO_EVT ZERO_EVT 1 CCCTL_01_CCUPD_COMPARE_DOWN_EVT COMPARE_DOWN_EVT 2 CCCTL_01_CCUPD_COMPARE_UP_EVT COMPARE_UP_EVT 3 CCCTL_01_CCUPD_ZERO_LOAD_EVT ZERO_LOAD_EVT 4 CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT ZERO_RC_ZERO_EVT 5 CCCTL_01_CCUPD_TRIG TRIG 6 CCCTL_01_CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write CCCTL_01_CCACTUPD_IMMEDIATELY IMMEDIATELY 0 CCCTL_01_CCACTUPD_ZERO_EVT ZERO_EVT 1 CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT COMPARE_DOWN_EVT 2 CCCTL_01_CCACTUPD_COMPARE_UP_EVT COMPARE_UP_EVT 3 CCCTL_01_CCACTUPD_ZERO_LOAD_EVT ZERO_LOAD_EVT 4 CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT ZERO_RC_ZERO_EVT 5 CCCTL_01_CCACTUPD_TRIG TRIG 6 CCCTL_01_CC2SELU Selects the source second CCU event. 0x16 0x3 CCCTL_01_CC2SELU_SEL_CCU0 SEL_CCU0 0 CCCTL_01_CC2SELU_SEL_CCU1 SEL_CCU1 1 CCCTL_01_CC2SELU_SEL_CCU2 SEL_CCU2 2 CCCTL_01_CC2SELU_SEL_CCU3 SEL_CCU3 3 CCCTL_01_CC2SELU_SEL_CCU4 SEL_CCU4 4 CCCTL_01_CC2SELU_SEL_CCU5 SEL_CCU5 5 CCCTL_01_CC2SELD Selects the source second CCD event. 0x1D 0x3 CCCTL_01_CC2SELD_SEL_CCD0 SEL_CCD0 0 CCCTL_01_CC2SELD_SEL_CCD1 SEL_CCD1 1 CCCTL_01_CC2SELD_SEL_CCD2 SEL_CCD2 2 CCCTL_01_CC2SELD_SEL_CCD3 SEL_CCD3 3 CCCTL_01_CC2SELD_SEL_CCD4 SEL_CCD4 4 CCCTL_01_CC2SELD_SEL_CCD5 SEL_CCD5 5 2 4 0,1 OCTL_01[%s] CCP Output Control Registers 0x1850 32 read-write 0x00000000 0xffffffff OCTL_01_CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write OCTL_01_CCPOINV_NOINV NOINV 0 OCTL_01_CCPOINV_INV INV 1 OCTL_01_CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write OCTL_01_CCPIV_LOW LOW 0 OCTL_01_CCPIV_HIGH HIGH 1 OCTL_01_CCPO CCP Output Source 0x0 0x4 read-write OCTL_01_CCPO_FUNCVAL FUNCVAL 0 OCTL_01_CCPO_LOAD LOAD 1 OCTL_01_CCPO_CMPVAL CMPVAL 2 OCTL_01_CCPO_ZERO ZERO 4 OCTL_01_CCPO_CAPCOND CAPCOND 5 OCTL_01_CCPO_FAULTCOND FAULTCOND 6 OCTL_01_CCPO_CC0_MIRROR_ALL CC0_MIRROR_ALL 8 OCTL_01_CCPO_CC1_MIRROR_ALL CC1_MIRROR_ALL 9 OCTL_01_CCPO_DEADBAND DEADBAND 12 OCTL_01_CCPO_CNTDIR CNTDIR 13 2 4 0,1 CCACT_01[%s] Capture or Compare Action Registers 0x1870 32 read-write 0x00000000 0xffffffff CCACT_01_ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write CCACT_01_ZACT_DISABLED DISABLED 0 CCACT_01_ZACT_CCP_HIGH CCP_HIGH 1 CCACT_01_ZACT_CCP_LOW CCP_LOW 2 CCACT_01_ZACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write CCACT_01_LACT_DISABLED DISABLED 0 CCACT_01_LACT_CCP_HIGH CCP_HIGH 1 CCACT_01_LACT_CCP_LOW CCP_LOW 2 CCACT_01_LACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write CCACT_01_CDACT_DISABLED DISABLED 0 CCACT_01_CDACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CDACT_CCP_LOW CCP_LOW 2 CCACT_01_CDACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write CCACT_01_CUACT_DISABLED DISABLED 0 CCACT_01_CUACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CUACT_CCP_LOW CCP_LOW 2 CCACT_01_CUACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write CCACT_01_CC2DACT_DISABLED DISABLED 0 CCACT_01_CC2DACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2DACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2DACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write CCACT_01_CC2UACT_DISABLED DISABLED 0 CCACT_01_CC2UACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2UACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2UACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_SWFRCACT CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write CCACT_01_SWFRCACT_DISABLED DISABLED 0 CCACT_01_SWFRCACT_CCP_HIGH CCP_HIGH 1 CCACT_01_SWFRCACT_CCP_LOW CCP_LOW 2 2 4 0,1 IFCTL_01[%s] Input Filter Control Register 0x1880 32 read-write 0x00000000 0xffffffff IFCTL_01_ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write IFCTL_01_ISEL_CCPX_INPUT CCPX_INPUT 0 IFCTL_01_ISEL_CCPX_INPUT_PAIR CCPX_INPUT_PAIR 1 IFCTL_01_ISEL_CCP0_INPUT CCP0_INPUT 2 IFCTL_01_ISEL_TRIG_INPUT TRIG_INPUT 3 IFCTL_01_ISEL_CCP_XOR CCP_XOR 4 IFCTL_01_ISEL_FSUB0 FSUB0 5 IFCTL_01_ISEL_FSUB1 FSUB1 6 IFCTL_01_ISEL_COMP0 COMP0 7 IFCTL_01_ISEL_COMP1 COMP1 8 IFCTL_01_ISEL_COMP2 COMP2 9 IFCTL_01_INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write IFCTL_01_INV_NOINVERT NOINVERT 0 IFCTL_01_INV_INVERT INVERT 1 IFCTL_01_FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write IFCTL_01_FP__3 _3 0 IFCTL_01_FP__5 _5 1 IFCTL_01_FP__8 _8 2 IFCTL_01_CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write IFCTL_01_CPV_CONSECUTIVE CONSECUTIVE 0 IFCTL_01_CPV_VOTING VOTING 1 IFCTL_01_FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write IFCTL_01_FE_DISABLED DISABLED 0 IFCTL_01_FE_ENABLED ENABLED 1 TSEL Trigger Select 0x18B0 32 read-write 0x00000000 0xffffffff TSEL_ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TSEL_ETSEL_TRIG0 TRIG0 0 TSEL_ETSEL_TRIG1 TRIG1 1 TSEL_ETSEL_TRIG2 TRIG2 2 TSEL_ETSEL_TRIG3 TRIG3 3 TSEL_ETSEL_TRIG4 TRIG4 4 TSEL_ETSEL_TRIG5 TRIG5 5 TSEL_ETSEL_TRIG6 TRIG6 6 TSEL_ETSEL_TRIG7 TRIG7 7 TSEL_ETSEL_TRIG8 TRIG8 8 TSEL_ETSEL_TRIG9 TRIG9 9 TSEL_ETSEL_TRIG10 TRIG10 10 TSEL_ETSEL_TRIG11 TRIG11 11 TSEL_ETSEL_TRIG12 TRIG12 12 TSEL_ETSEL_TRIG13 TRIG13 13 TSEL_ETSEL_TRIG14 TRIG14 14 TSEL_ETSEL_TRIG15 TRIG15 15 TSEL_ETSEL_TRIG_SUB0 TRIG_SUB0 16 TSEL_ETSEL_TRIG_SUB1 TRIG_SUB1 17 TSEL_TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write TSEL_TE_DISABLED DISABLED 0 TSEL_TE_ENABLED ENABLED 1 ADC0 1.0 PERIPHERALREGION 0x40004000 0x0 0x2000 registers FSUB_0 Subscriber Configuration Register. 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Configuration Register. 0x444 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 read-write PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 CLKCFG ADC clock configuration Register 0x808 32 read-write 0x00000000 CLKCFG_SAMPCLK ADC sample clock source selection. 0x0 0x2 CLKCFG_SAMPCLK_SYSOSC SYSOSC 0 CLKCFG_SAMPCLK_ULPCLK ULPCLK 1 CLKCFG_SAMPCLK_HFCLK HFCLK 2 CLKCFG_CCONRUN CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source. 0x4 0x1 CLKCFG_CCONRUN_DISABLE DISABLE 0 CLKCFG_CCONRUN_ENABLE ENABLE 1 CLKCFG_CCONSTOP CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source. 0x5 0x1 CLKCFG_CCONSTOP_DISABLE DISABLE 0 CLKCFG_CCONSTOP_ENABLE ENABLE 1 CLKCFG_KEY Unlock key 0x18 0x8 write-only CLKCFG_KEY_UNLOCK_W _TO_UNLOCK_W_ 169 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 INT_EVENT0_IIDX Interrupt index 0x1020 32 read-only 0x00000000 INT_EVENT0_IIDX_STAT Interrupt index status 0x0 0xA read-only INT_EVENT0_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT0_IIDX_STAT_OVIFG OVIFG 1 INT_EVENT0_IIDX_STAT_TOVIFG TOVIFG 2 INT_EVENT0_IIDX_STAT_HIGHIFG HIGHIFG 3 INT_EVENT0_IIDX_STAT_LOWIFG LOWIFG 4 INT_EVENT0_IIDX_STAT_INIFG INIFG 5 INT_EVENT0_IIDX_STAT_DMADONE DMADONE 6 INT_EVENT0_IIDX_STAT_UVIFG UVIFG 7 INT_EVENT0_IIDX_STAT_MEMRESIFG0 MEMRESIFG0 9 INT_EVENT0_IIDX_STAT_MEMRESIFG1 MEMRESIFG1 10 INT_EVENT0_IIDX_STAT_MEMRESIFG2 MEMRESIFG2 11 INT_EVENT0_IIDX_STAT_MEMRESIFG3 MEMRESIFG3 12 INT_EVENT0_IIDX_STAT_MEMRESIFG4 MEMRESIFG4 13 INT_EVENT0_IIDX_STAT_MEMRESIFG5 MEMRESIFG5 14 INT_EVENT0_IIDX_STAT_MEMRESIFG6 MEMRESIFG6 15 INT_EVENT0_IIDX_STAT_MEMRESIFG7 MEMRESIFG7 16 INT_EVENT0_IIDX_STAT_MEMRESIFG8 MEMRESIFG8 17 INT_EVENT0_IIDX_STAT_MEMRESIFG9 MEMRESIFG9 18 INT_EVENT0_IIDX_STAT_MEMRESIFG10 MEMRESIFG10 19 INT_EVENT0_IIDX_STAT_MEMRESIFG11 MEMRESIFG11 20 INT_EVENT0_IIDX_STAT_MEMRESIFG12 MEMRESIFG12 21 INT_EVENT0_IIDX_STAT_MEMRESIFG13 MEMRESIFG13 22 INT_EVENT0_IIDX_STAT_MEMRESIFG14 MEMRESIFG14 23 INT_EVENT0_IIDX_STAT_MEMRESIFG15 MEMRESIFG15 24 INT_EVENT0_IIDX_STAT_MEMRESIFG16 MEMRESIFG16 25 INT_EVENT0_IIDX_STAT_MEMRESIFG17 MEMRESIFG17 26 INT_EVENT0_IIDX_STAT_MEMRESIFG18 MEMRESIFG18 27 INT_EVENT0_IIDX_STAT_MEMRESIFG19 MEMRESIFG19 28 INT_EVENT0_IIDX_STAT_MEMRESIFG20 MEMRESIFG20 29 INT_EVENT0_IIDX_STAT_MEMRESIFG21 MEMRESIFG21 30 INT_EVENT0_IIDX_STAT_MEMRESIFG22 MEMRESIFG22 31 INT_EVENT0_IIDX_STAT_MEMRESIFG23 MEMRESIFG23 32 INT_EVENT0_IMASK Interrupt mask 0x1028 32 read-write 0x00000000 INT_EVENT0_IMASK_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT0_IMASK_INIFG_CLR CLR 0 INT_EVENT0_IMASK_INIFG_SET SET 1 INT_EVENT0_IMASK_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT0_IMASK_LOWIFG_CLR CLR 0 INT_EVENT0_IMASK_LOWIFG_SET SET 1 INT_EVENT0_IMASK_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT0_IMASK_HIGHIFG_CLR CLR 0 INT_EVENT0_IMASK_HIGHIFG_SET SET 1 INT_EVENT0_IMASK_OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 INT_EVENT0_IMASK_OVIFG_CLR CLR 0 INT_EVENT0_IMASK_OVIFG_SET SET 1 INT_EVENT0_IMASK_UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 INT_EVENT0_IMASK_UVIFG_CLR CLR 0 INT_EVENT0_IMASK_UVIFG_SET SET 1 INT_EVENT0_IMASK_TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 INT_EVENT0_IMASK_TOVIFG_CLR CLR 0 INT_EVENT0_IMASK_TOVIFG_SET SET 1 INT_EVENT0_IMASK_DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 INT_EVENT0_IMASK_DMADONE_CLR CLR 0 INT_EVENT0_IMASK_DMADONE_SET SET 1 INT_EVENT0_IMASK_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT0_IMASK_MEMRESIFG0_CLR CLR 0 INT_EVENT0_IMASK_MEMRESIFG0_SET SET 1 INT_EVENT0_IMASK_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT0_IMASK_MEMRESIFG1_CLR CLR 0 INT_EVENT0_IMASK_MEMRESIFG1_SET SET 1 INT_EVENT0_IMASK_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT0_IMASK_MEMRESIFG2_CLR CLR 0 INT_EVENT0_IMASK_MEMRESIFG2_SET SET 1 INT_EVENT0_IMASK_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT0_IMASK_MEMRESIFG3_CLR CLR 0 INT_EVENT0_IMASK_MEMRESIFG3_SET SET 1 INT_EVENT0_RIS Raw interrupt status 0x1030 32 read-only 0x00000000 INT_EVENT0_RIS_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT0_RIS_INIFG_CLR CLR 0 INT_EVENT0_RIS_INIFG_SET SET 1 INT_EVENT0_RIS_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT0_RIS_LOWIFG_CLR CLR 0 INT_EVENT0_RIS_LOWIFG_SET SET 1 INT_EVENT0_RIS_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT0_RIS_HIGHIFG_CLR CLR 0 INT_EVENT0_RIS_HIGHIFG_SET SET 1 INT_EVENT0_RIS_OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 INT_EVENT0_RIS_OVIFG_CLR CLR 0 INT_EVENT0_RIS_OVIFG_SET SET 1 INT_EVENT0_RIS_UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 INT_EVENT0_RIS_UVIFG_CLR CLR 0 INT_EVENT0_RIS_UVIFG_SET SET 1 INT_EVENT0_RIS_TOVIFG Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 INT_EVENT0_RIS_TOVIFG_CLR CLR 0 INT_EVENT0_RIS_TOVIFG_SET SET 1 INT_EVENT0_RIS_DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 INT_EVENT0_RIS_DMADONE_CLR CLR 0 INT_EVENT0_RIS_DMADONE_SET SET 1 INT_EVENT0_RIS_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT0_RIS_MEMRESIFG0_CLR CLR 0 INT_EVENT0_RIS_MEMRESIFG0_SET SET 1 INT_EVENT0_RIS_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT0_RIS_MEMRESIFG1_CLR CLR 0 INT_EVENT0_RIS_MEMRESIFG1_SET SET 1 INT_EVENT0_RIS_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT0_RIS_MEMRESIFG2_CLR CLR 0 INT_EVENT0_RIS_MEMRESIFG2_SET SET 1 INT_EVENT0_RIS_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT0_RIS_MEMRESIFG3_CLR CLR 0 INT_EVENT0_RIS_MEMRESIFG3_SET SET 1 INT_EVENT0_MIS Masked interrupt status 0x1038 32 read-only 0x00000000 INT_EVENT0_MIS_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT0_MIS_INIFG_CLR CLR 0 INT_EVENT0_MIS_INIFG_SET SET 1 INT_EVENT0_MIS_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT0_MIS_LOWIFG_CLR CLR 0 INT_EVENT0_MIS_LOWIFG_SET SET 1 INT_EVENT0_MIS_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT0_MIS_HIGHIFG_CLR CLR 0 INT_EVENT0_MIS_HIGHIFG_SET SET 1 INT_EVENT0_MIS_OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 INT_EVENT0_MIS_OVIFG_CLR CLR 0 INT_EVENT0_MIS_OVIFG_SET SET 1 INT_EVENT0_MIS_UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1. 0x6 0x1 INT_EVENT0_MIS_UVIFG_CLR CLR 0 INT_EVENT0_MIS_UVIFG_SET SET 1 INT_EVENT0_MIS_TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 INT_EVENT0_MIS_TOVIFG_CLR CLR 0 INT_EVENT0_MIS_TOVIFG_SET SET 1 INT_EVENT0_MIS_DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 INT_EVENT0_MIS_DMADONE_CLR CLR 0 INT_EVENT0_MIS_DMADONE_SET SET 1 INT_EVENT0_MIS_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT0_MIS_MEMRESIFG0_CLR CLR 0 INT_EVENT0_MIS_MEMRESIFG0_SET SET 1 INT_EVENT0_MIS_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT0_MIS_MEMRESIFG1_CLR CLR 0 INT_EVENT0_MIS_MEMRESIFG1_SET SET 1 INT_EVENT0_MIS_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT0_MIS_MEMRESIFG2_CLR CLR 0 INT_EVENT0_MIS_MEMRESIFG2_SET SET 1 INT_EVENT0_MIS_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT0_MIS_MEMRESIFG3_CLR CLR 0 INT_EVENT0_MIS_MEMRESIFG3_SET SET 1 INT_EVENT0_ISET Interrupt set 0x1040 32 write-only 0x00000000 INT_EVENT0_ISET_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT0_ISET_INIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_INIFG_SET SET 1 INT_EVENT0_ISET_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT0_ISET_LOWIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_LOWIFG_SET SET 1 INT_EVENT0_ISET_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT0_ISET_HIGHIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_HIGHIFG_SET SET 1 INT_EVENT0_ISET_OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 INT_EVENT0_ISET_OVIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_OVIFG_SET SET 1 INT_EVENT0_ISET_UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x6 0x1 INT_EVENT0_ISET_UVIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_UVIFG_SET SET 1 INT_EVENT0_ISET_TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 INT_EVENT0_ISET_TOVIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_TOVIFG_SET SET 1 INT_EVENT0_ISET_DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 INT_EVENT0_ISET_DMADONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_DMADONE_SET SET 1 INT_EVENT0_ISET_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT0_ISET_MEMRESIFG0_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MEMRESIFG0_SET SET 1 INT_EVENT0_ISET_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT0_ISET_MEMRESIFG1_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MEMRESIFG1_SET SET 1 INT_EVENT0_ISET_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT0_ISET_MEMRESIFG2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MEMRESIFG2_SET SET 1 INT_EVENT0_ISET_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT0_ISET_MEMRESIFG3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ISET_MEMRESIFG3_SET SET 1 INT_EVENT0_ICLR Interrupt clear 0x1048 32 write-only 0x00000000 INT_EVENT0_ICLR_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT0_ICLR_INIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_INIFG_CLR CLR 1 INT_EVENT0_ICLR_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT0_ICLR_LOWIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_LOWIFG_CLR CLR 1 INT_EVENT0_ICLR_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT0_ICLR_HIGHIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_HIGHIFG_CLR CLR 1 INT_EVENT0_ICLR_OVIFG Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x0 0x1 INT_EVENT0_ICLR_OVIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_OVIFG_CLR CLR 1 INT_EVENT0_ICLR_UVIFG Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x6 0x1 INT_EVENT0_ICLR_UVIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_UVIFG_CLR CLR 1 INT_EVENT0_ICLR_TOVIFG Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x1 0x1 INT_EVENT0_ICLR_TOVIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_TOVIFG_CLR CLR 1 INT_EVENT0_ICLR_DMADONE Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x5 0x1 INT_EVENT0_ICLR_DMADONE_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_DMADONE_CLR CLR 1 INT_EVENT0_ICLR_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT0_ICLR_MEMRESIFG0_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MEMRESIFG0_CLR CLR 1 INT_EVENT0_ICLR_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT0_ICLR_MEMRESIFG1_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MEMRESIFG1_CLR CLR 1 INT_EVENT0_ICLR_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT0_ICLR_MEMRESIFG2_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MEMRESIFG2_CLR CLR 1 INT_EVENT0_ICLR_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT0_ICLR_MEMRESIFG3_NO_EFFECT NO_EFFECT 0 INT_EVENT0_ICLR_MEMRESIFG3_CLR CLR 1 INT_EVENT1_IIDX Interrupt index 0x1050 32 read-only 0x00000000 INT_EVENT1_IIDX_STAT Interrupt index status 0x0 0xA read-only INT_EVENT1_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT1_IIDX_STAT_HIGHIFG HIGHIFG 3 INT_EVENT1_IIDX_STAT_LOWIFG LOWIFG 4 INT_EVENT1_IIDX_STAT_INIFG INIFG 5 INT_EVENT1_IIDX_STAT_MEMRESIFG0 MEMRESIFG0 9 INT_EVENT1_IMASK Interrupt mask 0x1058 32 read-write 0x00000000 INT_EVENT1_IMASK_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT1_IMASK_INIFG_CLR CLR 0 INT_EVENT1_IMASK_INIFG_SET SET 1 INT_EVENT1_IMASK_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT1_IMASK_LOWIFG_CLR CLR 0 INT_EVENT1_IMASK_LOWIFG_SET SET 1 INT_EVENT1_IMASK_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT1_IMASK_HIGHIFG_CLR CLR 0 INT_EVENT1_IMASK_HIGHIFG_SET SET 1 INT_EVENT1_IMASK_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT1_IMASK_MEMRESIFG0_CLR CLR 0 INT_EVENT1_IMASK_MEMRESIFG0_SET SET 1 INT_EVENT1_RIS Raw interrupt status 0x1060 32 read-only 0x00000000 INT_EVENT1_RIS_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT1_RIS_INIFG_CLR CLR 0 INT_EVENT1_RIS_INIFG_SET SET 1 INT_EVENT1_RIS_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT1_RIS_LOWIFG_CLR CLR 0 INT_EVENT1_RIS_LOWIFG_SET SET 1 INT_EVENT1_RIS_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT1_RIS_HIGHIFG_CLR CLR 0 INT_EVENT1_RIS_HIGHIFG_SET SET 1 INT_EVENT1_RIS_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT1_RIS_MEMRESIFG0_CLR CLR 0 INT_EVENT1_RIS_MEMRESIFG0_SET SET 1 INT_EVENT1_MIS Masked interrupt status 0x1068 32 read-only 0x00000000 INT_EVENT1_MIS_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT1_MIS_INIFG_CLR CLR 0 INT_EVENT1_MIS_INIFG_SET SET 1 INT_EVENT1_MIS_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT1_MIS_LOWIFG_CLR CLR 0 INT_EVENT1_MIS_LOWIFG_SET SET 1 INT_EVENT1_MIS_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT1_MIS_HIGHIFG_CLR CLR 0 INT_EVENT1_MIS_HIGHIFG_SET SET 1 INT_EVENT1_MIS_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT1_MIS_MEMRESIFG0_CLR CLR 0 INT_EVENT1_MIS_MEMRESIFG0_SET SET 1 INT_EVENT1_ISET Interrupt set 0x1070 32 write-only 0x00000000 INT_EVENT1_ISET_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT1_ISET_INIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_INIFG_SET SET 1 INT_EVENT1_ISET_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT1_ISET_LOWIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_LOWIFG_SET SET 1 INT_EVENT1_ISET_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT1_ISET_HIGHIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_HIGHIFG_SET SET 1 INT_EVENT1_ISET_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT1_ISET_MEMRESIFG0_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ISET_MEMRESIFG0_SET SET 1 INT_EVENT1_ICLR Interrupt clear 0x1078 32 write-only 0x00000000 INT_EVENT1_ICLR_INIFG Mask INIFG in MIS_EX register. 0x4 0x1 INT_EVENT1_ICLR_INIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_INIFG_CLR CLR 1 INT_EVENT1_ICLR_LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x3 0x1 INT_EVENT1_ICLR_LOWIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_LOWIFG_CLR CLR 1 INT_EVENT1_ICLR_HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1. 0x2 0x1 INT_EVENT1_ICLR_HIGHIFG_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_HIGHIFG_CLR CLR 1 INT_EVENT1_ICLR_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT1_ICLR_MEMRESIFG0_NO_EFFECT NO_EFFECT 0 INT_EVENT1_ICLR_MEMRESIFG0_CLR CLR 1 INT_EVENT2_IIDX Interrupt index 0x1080 32 read-only 0x00000000 INT_EVENT2_IIDX_STAT Interrupt index status 0x0 0xA read-only INT_EVENT2_IIDX_STAT_NO_INTR NO_INTR 0 INT_EVENT2_IIDX_STAT_MEMRESIFG0 MEMRESIFG0 9 INT_EVENT2_IIDX_STAT_MEMRESIFG1 MEMRESIFG1 10 INT_EVENT2_IIDX_STAT_MEMRESIFG2 MEMRESIFG2 11 INT_EVENT2_IIDX_STAT_MEMRESIFG3 MEMRESIFG3 12 INT_EVENT2_IIDX_STAT_MEMRESIFG4 MEMRESIFG4 13 INT_EVENT2_IIDX_STAT_MEMRESIFG5 MEMRESIFG5 14 INT_EVENT2_IIDX_STAT_MEMRESIFG6 MEMRESIFG6 15 INT_EVENT2_IIDX_STAT_MEMRESIFG7 MEMRESIFG7 16 INT_EVENT2_IIDX_STAT_MEMRESIFG8 MEMRESIFG8 17 INT_EVENT2_IIDX_STAT_MEMRESIFG9 MEMRESIFG9 18 INT_EVENT2_IIDX_STAT_MEMRESIFG10 MEMRESIFG10 19 INT_EVENT2_IIDX_STAT_MEMRESIFG11 MEMRESIFG11 20 INT_EVENT2_IIDX_STAT_MEMRESIFG12 MEMRESIFG12 21 INT_EVENT2_IIDX_STAT_MEMRESIFG13 MEMRESIFG13 22 INT_EVENT2_IIDX_STAT_MEMRESIFG14 MEMRESIFG14 23 INT_EVENT2_IIDX_STAT_MEMRESIFG15 MEMRESIFG15 24 INT_EVENT2_IIDX_STAT_MEMRESIFG16 MEMRESIFG16 25 INT_EVENT2_IIDX_STAT_MEMRESIFG17 MEMRESIFG17 26 INT_EVENT2_IIDX_STAT_MEMRESIFG18 MEMRESIFG18 27 INT_EVENT2_IIDX_STAT_MEMRESIFG19 MEMRESIFG19 28 INT_EVENT2_IIDX_STAT_MEMRESIFG20 MEMRESIFG20 29 INT_EVENT2_IIDX_STAT_MEMRESIFG21 MEMRESIFG21 30 INT_EVENT2_IIDX_STAT_MEMRESIFG22 MEMRESIFG22 31 INT_EVENT2_IIDX_STAT_MEMRESIFG23 MEMRESIFG23 32 INT_EVENT2_IMASK Interrupt mask extension 0x1088 32 read-write 0x00000000 INT_EVENT2_IMASK_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT2_IMASK_MEMRESIFG0_CLR CLR 0 INT_EVENT2_IMASK_MEMRESIFG0_SET SET 1 INT_EVENT2_IMASK_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT2_IMASK_MEMRESIFG1_CLR CLR 0 INT_EVENT2_IMASK_MEMRESIFG1_SET SET 1 INT_EVENT2_IMASK_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT2_IMASK_MEMRESIFG2_CLR CLR 0 INT_EVENT2_IMASK_MEMRESIFG2_SET SET 1 INT_EVENT2_IMASK_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT2_IMASK_MEMRESIFG3_CLR CLR 0 INT_EVENT2_IMASK_MEMRESIFG3_SET SET 1 INT_EVENT2_RIS Raw interrupt status extension 0x1090 32 read-only 0x00000000 INT_EVENT2_RIS_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT2_RIS_MEMRESIFG0_CLR CLR 0 INT_EVENT2_RIS_MEMRESIFG0_SET SET 1 INT_EVENT2_RIS_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT2_RIS_MEMRESIFG1_CLR CLR 0 INT_EVENT2_RIS_MEMRESIFG1_SET SET 1 INT_EVENT2_RIS_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT2_RIS_MEMRESIFG2_CLR CLR 0 INT_EVENT2_RIS_MEMRESIFG2_SET SET 1 INT_EVENT2_RIS_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT2_RIS_MEMRESIFG3_CLR CLR 0 INT_EVENT2_RIS_MEMRESIFG3_SET SET 1 INT_EVENT2_MIS Masked interrupt status extension 0x1098 32 read-only 0x00000000 INT_EVENT2_MIS_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT2_MIS_MEMRESIFG0_CLR CLR 0 INT_EVENT2_MIS_MEMRESIFG0_SET SET 1 INT_EVENT2_MIS_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT2_MIS_MEMRESIFG1_CLR CLR 0 INT_EVENT2_MIS_MEMRESIFG1_SET SET 1 INT_EVENT2_MIS_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT2_MIS_MEMRESIFG2_CLR CLR 0 INT_EVENT2_MIS_MEMRESIFG2_SET SET 1 INT_EVENT2_MIS_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT2_MIS_MEMRESIFG3_CLR CLR 0 INT_EVENT2_MIS_MEMRESIFG3_SET SET 1 INT_EVENT2_ISET Interrupt set extension 0x10A0 32 write-only 0x00000000 INT_EVENT2_ISET_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT2_ISET_MEMRESIFG0_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MEMRESIFG0_SET SET 1 INT_EVENT2_ISET_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT2_ISET_MEMRESIFG1_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MEMRESIFG1_SET SET 1 INT_EVENT2_ISET_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT2_ISET_MEMRESIFG2_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MEMRESIFG2_SET SET 1 INT_EVENT2_ISET_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT2_ISET_MEMRESIFG3_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ISET_MEMRESIFG3_SET SET 1 INT_EVENT2_ICLR Interrupt clear extension 0x10A8 32 write-only 0x00000000 INT_EVENT2_ICLR_MEMRESIFG0 Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x8 0x1 INT_EVENT2_ICLR_MEMRESIFG0_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MEMRESIFG0_CLR CLR 1 INT_EVENT2_ICLR_MEMRESIFG1 Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0x9 0x1 INT_EVENT2_ICLR_MEMRESIFG1_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MEMRESIFG1_CLR CLR 1 INT_EVENT2_ICLR_MEMRESIFG2 Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xA 0x1 INT_EVENT2_ICLR_MEMRESIFG2_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MEMRESIFG2_CLR CLR 1 INT_EVENT2_ICLR_MEMRESIFG3 Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1 0xB 0x1 INT_EVENT2_ICLR_MEMRESIFG3_NO_EFFECT NO_EFFECT 0 INT_EVENT2_ICLR_MEMRESIFG3_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-only EVT_MODE_INT0_CFG Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0 0x0 0x2 read-only EVT_MODE_INT0_CFG_DISABLE DISABLE 0 EVT_MODE_INT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_INT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 read-only DESC_MAJREV Major rev of the IP 0x4 0x4 read-only DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 read-only DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 read-only DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 read-only CTL0 Control Register 0 0x1100 32 read-write 0x00000000 CTL0_ENC Enable conversion 0x0 0x1 read-write CTL0_ENC_OFF OFF 0 CTL0_ENC_ON ON 1 CTL0_PWRDN Power down policy 0x10 0x1 read-write CTL0_PWRDN_AUTO AUTO 0 CTL0_PWRDN_MANUAL MANUAL 1 CTL0_SCLKDIV Sample clock divider 0x18 0x3 CTL0_SCLKDIV_DIV_BY_1 DIV_BY_1 0 CTL0_SCLKDIV_DIV_BY_2 DIV_BY_2 1 CTL0_SCLKDIV_DIV_BY_4 DIV_BY_4 2 CTL0_SCLKDIV_DIV_BY_8 DIV_BY_8 3 CTL0_SCLKDIV_DIV_BY_16 DIV_BY_16 4 CTL0_SCLKDIV_DIV_BY_24 DIV_BY_24 5 CTL0_SCLKDIV_DIV_BY_32 DIV_BY_32 6 CTL0_SCLKDIV_DIV_BY_48 DIV_BY_48 7 CTL1 Control Register 1 0x1104 32 read-write 0x00000000 CTL1_TRIGSRC Sample trigger source 0x0 0x1 read-write CTL1_TRIGSRC_SOFTWARE SOFTWARE 0 CTL1_TRIGSRC_EVENT EVENT 1 CTL1_SC Start of conversion 0x8 0x1 read-write CTL1_SC_STOP STOP 0 CTL1_SC_START START 1 CTL1_CONSEQ Conversion sequence mode 0x10 0x2 read-write CTL1_CONSEQ_SINGLE SINGLE 0 CTL1_CONSEQ_SEQUENCE SEQUENCE 1 CTL1_CONSEQ_REPEATSINGLE REPEATSINGLE 2 CTL1_CONSEQ_REPEATSEQUENCE REPEATSEQUENCE 3 CTL1_SAMPMODE Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger. 0x14 0x1 read-write CTL1_SAMPMODE_AUTO AUTO 0 CTL1_SAMPMODE_MANUAL MANUAL 1 CTL1_AVGN Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx. 0x18 0x3 read-write CTL1_AVGN_DISABLE DISABLE 0 CTL1_AVGN_AVG_2 AVG_2 1 CTL1_AVGN_AVG_4 AVG_4 2 CTL1_AVGN_AVG_8 AVG_8 3 CTL1_AVGN_AVG_16 AVG_16 4 CTL1_AVGN_AVG_32 AVG_32 5 CTL1_AVGN_AVG_64 AVG_64 6 CTL1_AVGN_AVG_128 AVG_128 7 CTL1_AVGD Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated. 0x1C 0x3 read-write CTL1_AVGD_SHIFT0 SHIFT0 0 CTL1_AVGD_SHIFT1 SHIFT1 1 CTL1_AVGD_SHIFT2 SHIFT2 2 CTL1_AVGD_SHIFT3 SHIFT3 3 CTL1_AVGD_SHIFT4 SHIFT4 4 CTL1_AVGD_SHIFT5 SHIFT5 5 CTL1_AVGD_SHIFT6 SHIFT6 6 CTL1_AVGD_SHIFT7 SHIFT7 7 CTL2 Control Register 2 0x1108 32 read-write 0x00000000 CTL2_DF Data read-back format. Data is always stored in binary unsigned format. 0x0 0x1 read-write CTL2_DF_UNSIGNED UNSIGNED 0 CTL2_DF_SIGNED SIGNED 1 CTL2_RES Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution. 0x1 0x2 read-write CTL2_RES_BIT_12 BIT_12 0 CTL2_RES_BIT_10 BIT_10 1 CTL2_RES_BIT_8 BIT_8 2 CTL2_STARTADD Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 0x10 0x5 read-write CTL2_STARTADD_ADDR_00 ADDR_00 0 CTL2_STARTADD_ADDR_01 ADDR_01 1 CTL2_STARTADD_ADDR_02 ADDR_02 2 CTL2_STARTADD_ADDR_03 ADDR_03 3 CTL2_STARTADD_ADDR_04 ADDR_04 4 CTL2_STARTADD_ADDR_05 ADDR_05 5 CTL2_STARTADD_ADDR_06 ADDR_06 6 CTL2_STARTADD_ADDR_07 ADDR_07 7 CTL2_STARTADD_ADDR_08 ADDR_08 8 CTL2_STARTADD_ADDR_09 ADDR_09 9 CTL2_STARTADD_ADDR_10 ADDR_10 10 CTL2_STARTADD_ADDR_11 ADDR_11 11 CTL2_STARTADD_ADDR_12 ADDR_12 12 CTL2_STARTADD_ADDR_13 ADDR_13 13 CTL2_STARTADD_ADDR_14 ADDR_14 14 CTL2_STARTADD_ADDR_15 ADDR_15 15 CTL2_STARTADD_ADDR_16 ADDR_16 16 CTL2_STARTADD_ADDR_17 ADDR_17 17 CTL2_STARTADD_ADDR_18 ADDR_18 18 CTL2_STARTADD_ADDR_19 ADDR_19 19 CTL2_STARTADD_ADDR_20 ADDR_20 20 CTL2_STARTADD_ADDR_21 ADDR_21 21 CTL2_STARTADD_ADDR_22 ADDR_22 22 CTL2_STARTADD_ADDR_23 ADDR_23 23 CTL2_ENDADD Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 0x18 0x5 read-write CTL2_ENDADD_ADDR_00 ADDR_00 0 CTL2_ENDADD_ADDR_01 ADDR_01 1 CTL2_ENDADD_ADDR_02 ADDR_02 2 CTL2_ENDADD_ADDR_03 ADDR_03 3 CTL2_ENDADD_ADDR_04 ADDR_04 4 CTL2_ENDADD_ADDR_05 ADDR_05 5 CTL2_ENDADD_ADDR_06 ADDR_06 6 CTL2_ENDADD_ADDR_07 ADDR_07 7 CTL2_ENDADD_ADDR_08 ADDR_08 8 CTL2_ENDADD_ADDR_09 ADDR_09 9 CTL2_ENDADD_ADDR_10 ADDR_10 10 CTL2_ENDADD_ADDR_11 ADDR_11 11 CTL2_ENDADD_ADDR_12 ADDR_12 12 CTL2_ENDADD_ADDR_13 ADDR_13 13 CTL2_ENDADD_ADDR_14 ADDR_14 14 CTL2_ENDADD_ADDR_15 ADDR_15 15 CTL2_ENDADD_ADDR_16 ADDR_16 16 CTL2_ENDADD_ADDR_17 ADDR_17 17 CTL2_ENDADD_ADDR_18 ADDR_18 18 CTL2_ENDADD_ADDR_19 ADDR_19 19 CTL2_ENDADD_ADDR_20 ADDR_20 20 CTL2_ENDADD_ADDR_21 ADDR_21 21 CTL2_ENDADD_ADDR_22 ADDR_22 22 CTL2_ENDADD_ADDR_23 ADDR_23 23 CTL2_DMAEN Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers. 0x8 0x1 read-write CTL2_DMAEN_DISABLE DISABLE 0 CTL2_DMAEN_ENABLE ENABLE 1 CTL2_SAMPCNT Number of ADC converted samples to be transferred on a DMA trigger 0xB 0x5 read-write CTL2_SAMPCNT_MIN MIN 0 CTL2_SAMPCNT_MAX MAX 24 CTL2_FIFOEN Enable FIFO based operation 0xA 0x1 CTL2_FIFOEN_DISABLE DISABLE 0 CTL2_FIFOEN_ENABLE ENABLE 1 CLKFREQ Sample Clock Frequency Range Register 0x1110 32 read-write 0x00000000 CLKFREQ_FRANGE Frequency Range. 0x0 0x3 CLKFREQ_FRANGE_RANGE1TO4 RANGE1TO4 0 CLKFREQ_FRANGE_RANGE4TO8 RANGE4TO8 1 CLKFREQ_FRANGE_RANGE8TO16 RANGE8TO16 2 CLKFREQ_FRANGE_RANGE16TO20 RANGE16TO20 3 CLKFREQ_FRANGE_RANGE20TO24 RANGE20TO24 4 CLKFREQ_FRANGE_RANGE24TO32 RANGE24TO32 5 CLKFREQ_FRANGE_RANGE32TO40 RANGE32TO40 6 CLKFREQ_FRANGE_RANGE40TO48 RANGE40TO48 7 CTL3 Control Register 3 0x110C 32 read-write 0x00000000 CTL3_ASCCHSEL ASC channel select. 0x0 0x5 read-write CTL3_ASCSTIME ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation. 0x8 0x1 read-write CTL3_ASCVRSEL Selects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected. 0xC 0x2 read-write SCOMP0 Sample Time Compare 0 Register 0x1114 32 read-write 0x00000000 SCOMP0_VAL Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 0x0 0xA read-write SCOMP1 Sample Time Compare 1 Register 0x1118 32 read-write 0x00000000 SCOMP1_VAL Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 0x0 0xA read-write REFCFG Reference Buffer Configuration Register 0x111C 32 read-write 0x00000000 REFCFG_REFEN Reference buffer enable 0x0 0x1 read-write REFCFG_REFVSEL Configures reference buffer output voltage. 0x1 0x1 read-write REFCFG_IBPROG Configures reference buffer bias current output value. 0x3 0x2 read-write WCLOW Window Comparator Low Threshold Register 0x1148 32 read-write 0x00000000 WCLOW_DATA If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s. 0x0 0x10 read-write WCHIGH Window Comparator High Threshold Register 0x1150 32 read-write 0x00000000 WCHIGH_DATA If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s. 0x0 0x10 read-write 4 4 0,1,2,3 MEMCTL[%s] Conversion Memory Control Register 0x1180 32 read-write 0x00000000 MEMCTL_CHANSEL Input channel select. 0x0 0x5 read-write MEMCTL_CHANSEL_CHAN_0 CHAN_0 0 MEMCTL_CHANSEL_CHAN_1 CHAN_1 1 MEMCTL_CHANSEL_CHAN_2 CHAN_2 2 MEMCTL_CHANSEL_CHAN_3 CHAN_3 3 MEMCTL_CHANSEL_CHAN_4 CHAN_4 4 MEMCTL_CHANSEL_CHAN_5 CHAN_5 5 MEMCTL_CHANSEL_CHAN_6 CHAN_6 6 MEMCTL_CHANSEL_CHAN_7 CHAN_7 7 MEMCTL_CHANSEL_CHAN_8 CHAN_8 8 MEMCTL_CHANSEL_CHAN_9 CHAN_9 9 MEMCTL_CHANSEL_CHAN_10 CHAN_10 10 MEMCTL_CHANSEL_CHAN_11 CHAN_11 11 MEMCTL_CHANSEL_CHAN_12 CHAN_12 12 MEMCTL_CHANSEL_CHAN_13 CHAN_13 13 MEMCTL_CHANSEL_CHAN_14 CHAN_14 14 MEMCTL_CHANSEL_CHAN_15 CHAN_15 15 MEMCTL_CHANSEL_CHAN_16 CHAN_16 16 MEMCTL_CHANSEL_CHAN_17 CHAN_17 17 MEMCTL_CHANSEL_CHAN_18 CHAN_18 18 MEMCTL_CHANSEL_CHAN_19 CHAN_19 19 MEMCTL_CHANSEL_CHAN_20 CHAN_20 20 MEMCTL_CHANSEL_CHAN_21 CHAN_21 21 MEMCTL_CHANSEL_CHAN_22 CHAN_22 22 MEMCTL_CHANSEL_CHAN_23 CHAN_23 23 MEMCTL_CHANSEL_CHAN_24 CHAN_24 24 MEMCTL_CHANSEL_CHAN_25 CHAN_25 25 MEMCTL_CHANSEL_CHAN_26 CHAN_26 26 MEMCTL_CHANSEL_CHAN_27 CHAN_27 27 MEMCTL_CHANSEL_CHAN_28 CHAN_28 28 MEMCTL_CHANSEL_CHAN_29 CHAN_29 29 MEMCTL_CHANSEL_CHAN_30 CHAN_30 30 MEMCTL_CHANSEL_CHAN_31 CHAN_31 31 MEMCTL_TRIG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions. 0x18 0x1 read-write MEMCTL_TRIG_AUTO_NEXT AUTO_NEXT 0 MEMCTL_TRIG_TRIGGER_NEXT TRIGGER_NEXT 1 MEMCTL_VRSEL Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF. 0x8 0x2 read-write MEMCTL_VRSEL_VDDA VDDA 0 MEMCTL_VRSEL_EXTREF EXTREF 1 MEMCTL_VRSEL_INTREF INTREF 2 MEMCTL_WINCOMP Enable window comparator. 0x1C 0x1 read-write MEMCTL_WINCOMP_DISABLE DISABLE 0 MEMCTL_WINCOMP_ENABLE ENABLE 1 MEMCTL_BCSEN Enable burn out current source. 0x14 0x1 read-write MEMCTL_BCSEN_DISABLE DISABLE 0 MEMCTL_BCSEN_ENABLE ENABLE 1 MEMCTL_AVGEN Enable hardware averaging. 0x10 0x1 read-write MEMCTL_AVGEN_DISABLE DISABLE 0 MEMCTL_AVGEN_ENABLE ENABLE 1 MEMCTL_STIME Selects the source of sample timer period between SCOMP0 and SCOMP1. 0xC 0x1 MEMCTL_STIME_SEL_SCOMP0 SEL_SCOMP0 0 MEMCTL_STIME_SEL_SCOMP1 SEL_SCOMP1 1 STATUS Status Register 0x1340 32 read-only 0x00000000 STATUS_BUSY Busy. This bit indicates that an active ADC sample or conversion operation is in progress. 0x0 0x1 read-only STATUS_BUSY_IDLE IDLE 0 STATUS_BUSY_ACTIVE ACTIVE 1 STATUS_REFBUFRDY Indicates reference buffer is powered up and ready. 0x1 0x1 STATUS_REFBUFRDY_NOTREADY NOTREADY 0 STATUS_REFBUFRDY_READY READY 1 ADC0_SVT 1.0 PERIPHERALREGIONSVT 0x4055A000 0x0 0x1000 registers FIFODATA FIFO Data Register 0x160 32 read-only FIFODATA_DATA Read from this data field returns the ADC sample from FIFO. 0x0 0x20 4 4 0,1,2,3 MEMRES[%s] Memory Result Register 0x280 32 read-only MEMRES_DATA MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. 0x0 0x10 WUC 1.0 PERIPHERALREGION 0x40424000 0x0 0x500 registers FSUB_0 Subscriber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 TIMG0 1.0 PERIPHERALREGION 0x40084000 0x0 0x1F00 registers FSUB_0 Subsciber Port 0 0x400 32 read-write 0x00000000 FSUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FSUB_1 Subscriber Port 1 0x404 32 read-write 0x00000000 FSUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FSUB_1_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_0 Publisher Port 0 0x444 32 read-write 0x00000000 FPUB_0_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_0_CHANID_UNCONNECTED UNCONNECTED 0 FPUB_1 Publisher Port 1 0x448 32 read-write 0x00000000 FPUB_1_CHANID 0 = disconnected. 1-15 = connected to channelID = CHANID. 0x0 0x2 FPUB_1_CHANID_UNCONNECTED UNCONNECTED 0 PWREN Power enable 0x800 32 read-write 0x00000000 PWREN_ENABLE Enable the power 0x0 0x1 PWREN_ENABLE_DISABLE DISABLE 0 PWREN_ENABLE_ENABLE ENABLE 1 PWREN_KEY KEY to allow Power State Change 0x18 0x8 write-only PWREN_KEY_UNLOCK_W _TO_UNLOCK_W_ 38 RSTCTL Reset Control 0x804 32 write-only 0x00000000 RSTCTL_RESETSTKYCLR Clear the RESETSTKY bit in the STAT register 0x1 0x1 write-only RSTCTL_RESETSTKYCLR_NOP NOP 0 RSTCTL_RESETSTKYCLR_CLR CLR 1 RSTCTL_RESETASSERT Assert reset to the peripheral 0x0 0x1 write-only RSTCTL_RESETASSERT_NOP NOP 0 RSTCTL_RESETASSERT_ASSERT ASSERT 1 RSTCTL_KEY Unlock key 0x18 0x8 write-only RSTCTL_KEY_UNLOCK_W _TO_UNLOCK_W_ 177 STAT Status Register 0x814 32 read-only STAT_RESETSTKY This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0x10 0x1 read-only STAT_RESETSTKY_NORES NORES 0 STAT_RESETSTKY_RESET RESET 1 CLKDIV Clock Divider 0x1000 32 read-write 0x00000000 CLKDIV_RATIO Selects divide ratio of module clock 0x0 0x3 CLKDIV_RATIO_DIV_BY_1 DIV_BY_1 0 CLKDIV_RATIO_DIV_BY_2 DIV_BY_2 1 CLKDIV_RATIO_DIV_BY_3 DIV_BY_3 2 CLKDIV_RATIO_DIV_BY_4 DIV_BY_4 3 CLKDIV_RATIO_DIV_BY_5 DIV_BY_5 4 CLKDIV_RATIO_DIV_BY_6 DIV_BY_6 5 CLKDIV_RATIO_DIV_BY_7 DIV_BY_7 6 CLKDIV_RATIO_DIV_BY_8 DIV_BY_8 7 CLKSEL Clock Select for Ultra Low Power peripherals 0x1008 32 read-write 0x00000000 CLKSEL_LFCLK_SEL Selects LFCLK as clock source if enabled 0x1 0x1 read-write CLKSEL_LFCLK_SEL_DISABLE DISABLE 0 CLKSEL_LFCLK_SEL_ENABLE ENABLE 1 CLKSEL_MFCLK_SEL Selects MFCLK as clock source if enabled 0x2 0x1 read-write CLKSEL_MFCLK_SEL_DISABLE DISABLE 0 CLKSEL_MFCLK_SEL_ENABLE ENABLE 1 CLKSEL_BUSCLK_SEL Selects BUSCLK as clock source if enabled 0x3 0x1 read-write CLKSEL_BUSCLK_SEL_DISABLE DISABLE 0 CLKSEL_BUSCLK_SEL_ENABLE ENABLE 1 PDBGCTL Peripheral Debug Control 0x1018 32 read-write PDBGCTL_FREE Free run control 0x0 0x1 read-write PDBGCTL_FREE_STOP STOP 0 PDBGCTL_FREE_RUN RUN 1 PDBGCTL_SOFT Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP' 0x1 0x1 read-write PDBGCTL_SOFT_IMMEDIATE IMMEDIATE 0 PDBGCTL_SOFT_DELAYED DELAYED 1 IIDX Interrupt index 0x1020 32 read-only 0x00000000 IIDX_STAT Interrupt index status 0x0 0x8 read-only IIDX_STAT_NO_INTR NO_INTR 0 IIDX_STAT_Z Z 1 IIDX_STAT_L L 2 IIDX_STAT_CCD0 CCD0 5 IIDX_STAT_CCD1 CCD1 6 IIDX_STAT_CCD2 CCD2 7 IIDX_STAT_CCD3 CCD3 8 IIDX_STAT_CCU0 CCU0 9 IIDX_STAT_CCU1 CCU1 10 IIDX_STAT_CCU2 CCU2 11 IIDX_STAT_CCU3 CCU3 12 IIDX_STAT_CCD4 CCD4 13 IIDX_STAT_CCD5 CCD5 14 IIDX_STAT_CCU4 CCU4 15 IIDX_STAT_CCU5 CCU5 16 IIDX_STAT_F F 25 IIDX_STAT_TOV TOV 26 IIDX_STAT_REPC REPC 27 IIDX_STAT_DC DC 28 IIDX_STAT_QEIERR QEIERR 29 IMASK Interrupt mask 0x1028 32 read-write IMASK_Z Zero Event mask 0x0 0x1 IMASK_Z_CLR CLR 0 IMASK_Z_SET SET 1 IMASK_L Load Event mask 0x1 0x1 IMASK_L_CLR CLR 0 IMASK_L_SET SET 1 IMASK_CCD0 Capture or Compare DN event mask CCP0 0x4 0x1 IMASK_CCD0_CLR CLR 0 IMASK_CCD0_SET SET 1 IMASK_CCD1 Capture or Compare DN event mask CCP1 0x5 0x1 IMASK_CCD1_CLR CLR 0 IMASK_CCD1_SET SET 1 IMASK_CCU0 Capture or Compare UP event mask CCP0 0x8 0x1 IMASK_CCU0_CLR CLR 0 IMASK_CCU0_SET SET 1 IMASK_CCU1 Capture or Compare UP event mask CCP1 0x9 0x1 IMASK_CCU1_CLR CLR 0 IMASK_CCU1_SET SET 1 IMASK_TOV Trigger Overflow Event mask 0x19 0x1 IMASK_TOV_CLR CLR 0 IMASK_TOV_SET SET 1 RIS Raw interrupt status 0x1030 32 read-only 0x00000000 0xffffffff RIS_Z Zero event generated an interrupt. 0x0 0x1 RIS_Z_CLR CLR 0 RIS_Z_SET SET 1 RIS_L Load event generated an interrupt. 0x1 0x1 RIS_L_CLR CLR 0 RIS_L_SET SET 1 RIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 RIS_CCD0_CLR CLR 0 RIS_CCD0_SET SET 1 RIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 RIS_CCD1_CLR CLR 0 RIS_CCD1_SET SET 1 RIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 RIS_CCU0_CLR CLR 0 RIS_CCU0_SET SET 1 RIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 RIS_CCU1_CLR CLR 0 RIS_CCU1_SET SET 1 RIS_TOV Trigger overflow 0x19 0x1 RIS_TOV_CLR CLR 0 RIS_TOV_SET SET 1 MIS Masked interrupt status 0x1038 32 read-only 0x00000000 MIS_Z Zero event generated an interrupt. 0x0 0x1 MIS_Z_CLR CLR 0 MIS_Z_SET SET 1 MIS_L Load event generated an interrupt. 0x1 0x1 MIS_L_CLR CLR 0 MIS_L_SET SET 1 MIS_CCD0 Capture or compare down event generated an interrupt CCP0 0x4 0x1 MIS_CCD0_CLR CLR 0 MIS_CCD0_SET SET 1 MIS_CCD1 Capture or compare down event generated an interrupt CCP1 0x5 0x1 MIS_CCD1_CLR CLR 0 MIS_CCD1_SET SET 1 MIS_CCU0 Capture or compare up event generated an interrupt CCP0 0x8 0x1 MIS_CCU0_CLR CLR 0 MIS_CCU0_SET SET 1 MIS_CCU1 Capture or compare up event generated an interrupt CCP1 0x9 0x1 MIS_CCU1_CLR CLR 0 MIS_CCU1_SET SET 1 MIS_TOV Trigger overflow 0x19 0x1 MIS_TOV_CLR CLR 0 MIS_TOV_SET SET 1 ISET Interrupt set 0x1040 32 write-only 0x00000000 ISET_Z Zero event SET 0x0 0x1 ISET_Z_NO_EFFECT NO_EFFECT 0 ISET_Z_SET SET 1 ISET_L Load event SET 0x1 0x1 ISET_L_NO_EFFECT NO_EFFECT 0 ISET_L_SET SET 1 ISET_CCD0 Capture or compare down event SET 0x4 0x1 ISET_CCD0_NO_EFFECT NO_EFFECT 0 ISET_CCD0_SET SET 1 ISET_CCD1 Capture or compare down event SET 0x5 0x1 ISET_CCD1_NO_EFFECT NO_EFFECT 0 ISET_CCD1_SET SET 1 ISET_CCU0 Capture or compare up event SET 0x8 0x1 ISET_CCU0_NO_EFFECT NO_EFFECT 0 ISET_CCU0_SET SET 1 ISET_CCU1 Capture or compare up event SET 0x9 0x1 ISET_CCU1_NO_EFFECT NO_EFFECT 0 ISET_CCU1_SET SET 1 ISET_TOV Trigger Overflow event SET 0x19 0x1 ISET_TOV_NO_EFFECT NO_EFFECT 0 ISET_TOV_SET SET 1 ICLR Interrupt clear 0x1048 32 write-only 0x00000000 ICLR_Z Zero event CLEAR 0x0 0x1 ICLR_Z_NO_EFFECT NO_EFFECT 0 ICLR_Z_CLR CLR 1 ICLR_L Load event CLEAR 0x1 0x1 ICLR_L_NO_EFFECT NO_EFFECT 0 ICLR_L_CLR CLR 1 ICLR_CCD0 Capture or compare down event CLEAR 0x4 0x1 ICLR_CCD0_NO_EFFECT NO_EFFECT 0 ICLR_CCD0_CLR CLR 1 ICLR_CCD1 Capture or compare down event CLEAR 0x5 0x1 ICLR_CCD1_NO_EFFECT NO_EFFECT 0 ICLR_CCD1_CLR CLR 1 ICLR_CCU0 Capture or compare up event CLEAR 0x8 0x1 ICLR_CCU0_NO_EFFECT NO_EFFECT 0 ICLR_CCU0_CLR CLR 1 ICLR_CCU1 Capture or compare up event CLEAR 0x9 0x1 ICLR_CCU1_NO_EFFECT NO_EFFECT 0 ICLR_CCU1_CLR CLR 1 ICLR_TOV Trigger Overflow event CLEAR 0x19 0x1 ICLR_TOV_NO_EFFECT NO_EFFECT 0 ICLR_TOV_CLR CLR 1 EVT_MODE Event Mode 0x10E0 32 read-write 0x00000029 EVT_MODE_EVT0_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0] 0x0 0x2 read-only EVT_MODE_EVT0_CFG_DISABLE DISABLE 0 EVT_MODE_EVT0_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT0_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT1_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x2 0x2 read-only EVT_MODE_EVT1_CFG_DISABLE DISABLE 0 EVT_MODE_EVT1_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT1_CFG_HARDWARE HARDWARE 2 EVT_MODE_EVT2_CFG Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1] 0x4 0x2 read-only EVT_MODE_EVT2_CFG_DISABLE DISABLE 0 EVT_MODE_EVT2_CFG_SOFTWARE SOFTWARE 1 EVT_MODE_EVT2_CFG_HARDWARE HARDWARE 2 DESC Module Description 0x10FC 32 read-only DESC_MINREV Minor rev of the IP 0x0 0x4 DESC_MAJREV Major rev of the IP 0x4 0x4 DESC_INSTNUM Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0x8 0x4 DESC_FEATUREVER Feature Set for the module *instance* 0xC 0x4 DESC_MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0x10 0x10 CCPD CCP Direction 0x1100 32 read-write CCPD_C0CCP0 Counter CCP0 0x0 0x1 CCPD_C0CCP0_INPUT INPUT 0 CCPD_C0CCP0_OUTPUT OUTPUT 1 CCPD_C0CCP1 Counter CCP1 0x1 0x1 CCPD_C0CCP1_INPUT INPUT 0 CCPD_C0CCP1_OUTPUT OUTPUT 1 ODIS Output Disable 0x1104 32 read-write ODIS_C0CCP0 Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x0 0x1 read-write ODIS_C0CCP0_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP0_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 ODIS_C0CCP1 Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0x1 0x1 read-write ODIS_C0CCP1_CCP_OUTPUT_OCTL CCP_OUTPUT_OCTL 0 ODIS_C0CCP1_CCP_OUTPUT_LOW CCP_OUTPUT_LOW 1 CCLKCTL Counter Clock Control Register 0x1108 32 read-write CCLKCTL_CLKEN Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0x0 0x1 read-write CCLKCTL_CLKEN_DISABLED DISABLED 0 CCLKCTL_CLKEN_ENABLED ENABLED 1 CPS Clock Prescale Register 0x110C 32 read-write CPS_PCNT Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0x0 0x8 read-write CPSV Clock prescale count status register 0x1110 32 read-only CPSV_CPSVAL Current Prescale Count Value 0x0 0x8 read-only CTTRIGCTL Timer Cross Trigger Control Register 0x1114 32 read-write CTTRIGCTL_CTEN Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0x0 0x1 read-write CTTRIGCTL_CTEN_DISABLED DISABLED 0 CTTRIGCTL_CTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTEN Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path 0x1 0x1 read-write CTTRIGCTL_EVTCTEN_DISABLED DISABLED 0 CTTRIGCTL_EVTCTEN_ENABLE ENABLE 1 CTTRIGCTL_EVTCTTRIGSEL Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path 0x10 0x4 read-write CTTRIGCTL_EVTCTTRIGSEL_FSUB0 FSUB0 0 CTTRIGCTL_EVTCTTRIGSEL_FSUB1 FSUB1 1 CTTRIGCTL_EVTCTTRIGSEL_Z Z 2 CTTRIGCTL_EVTCTTRIGSEL_L L 3 CTTRIGCTL_EVTCTTRIGSEL_CCD0 CCD0 4 CTTRIGCTL_EVTCTTRIGSEL_CCD1 CCD1 5 CTTRIGCTL_EVTCTTRIGSEL_CCD2 CCD2 6 CTTRIGCTL_EVTCTTRIGSEL_CCD3 CCD3 7 CTTRIGCTL_EVTCTTRIGSEL_CCU0 CCU0 8 CTTRIGCTL_EVTCTTRIGSEL_CCU1 CCU1 9 CTTRIGCTL_EVTCTTRIGSEL_CCU2 CCU2 10 CTTRIGCTL_EVTCTTRIGSEL_CCU3 CCU3 11 CTTRIG Timer Cross Trigger Register 0x111C 32 write-only CTTRIG_TRIG Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0x0 0x1 write-only CTTRIG_TRIG_DISABLED DISABLED 0 CTTRIG_TRIG_GENERATE GENERATE 1 CTR Counter Register 0x1800 32 read-write 0x00000000 0xffffffff CTR_CCTR Current Counter value 0x0 0x10 read-write CTRCTL Counter Control Register 0x1804 32 read-write 0x0000ff80 0xffffffff CTRCTL_EN Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively. 0x0 0x1 read-write CTRCTL_EN_DISABLED DISABLED 0 CTRCTL_EN_ENABLED ENABLED 1 CTRCTL_REPEAT Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended. 0x1 0x3 read-write CTRCTL_REPEAT_REPEAT_0 REPEAT_0 0 CTRCTL_REPEAT_REPEAT_1 REPEAT_1 1 CTRCTL_REPEAT_REPEAT_2 REPEAT_2 2 CTRCTL_REPEAT_REPEAT_3 REPEAT_3 3 CTRCTL_REPEAT_REPEAT_4 REPEAT_4 4 CTRCTL_CM Count Mode 0x4 0x2 read-write CTRCTL_CM_DOWN DOWN 0 CTRCTL_CM_UP_DOWN UP_DOWN 1 CTRCTL_CM_UP UP 2 CTRCTL_CVAE Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active. 0x1C 0x2 read-write CTRCTL_CVAE_LDVAL LDVAL 0 CTRCTL_CVAE_NOCHANGE NOCHANGE 1 CTRCTL_CVAE_ZEROVAL ZEROVAL 2 CTRCTL_DRB Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode. 0x11 0x1 read-write CTRCTL_DRB_RESUME RESUME 0 CTRCTL_DRB_CVAE_ACTION CVAE_ACTION 1 CTRCTL_CLC Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0x7 0x3 read-write CTRCTL_CLC_CCCTL0_LCOND CCCTL0_LCOND 0 CTRCTL_CLC_CCCTL1_LCOND CCCTL1_LCOND 1 CTRCTL_CLC_CCCTL2_LCOND CCCTL2_LCOND 2 CTRCTL_CLC_CCCTL3_LCOND CCCTL3_LCOND 3 CTRCTL_CLC_QEI_2INP QEI_2INP 4 CTRCTL_CLC_QEI_3INP QEI_3INP 5 CTRCTL_CAC Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xA 0x3 read-write CTRCTL_CAC_CCCTL0_ACOND CCCTL0_ACOND 0 CTRCTL_CAC_CCCTL1_ACOND CCCTL1_ACOND 1 CTRCTL_CAC_CCCTL2_ACOND CCCTL2_ACOND 2 CTRCTL_CAC_CCCTL3_ACOND CCCTL3_ACOND 3 CTRCTL_CAC_QEI_2INP QEI_2INP 4 CTRCTL_CAC_QEI_3INP QEI_3INP 5 CTRCTL_CZC Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0xD 0x3 read-write CTRCTL_CZC_CCCTL0_ZCOND CCCTL0_ZCOND 0 CTRCTL_CZC_CCCTL1_ZCOND CCCTL1_ZCOND 1 CTRCTL_CZC_CCCTL2_ZCOND CCCTL2_ZCOND 2 CTRCTL_CZC_CCCTL3_ZCOND CCCTL3_ZCOND 3 CTRCTL_CZC_QEI_2INP QEI_2INP 4 CTRCTL_CZC_QEI_3INP QEI_3INP 5 LOAD Load Register 0x1808 32 read-write 0x00000000 0xffffffff LOAD_LD Load Value 0x0 0x10 read-write 2 4 0,1 CC_01[%s] Capture or Compare Register 0 to Capture or Compare Register 1 0x1810 32 read-write 0x00000000 0xffffffff CC_01_CCVAL Capture or compare value 0x0 0x10 read-write 2 4 0,1 CCCTL_01[%s] Capture or Compare Control Registers 0x1830 32 read-write 0x00000000 0xffffffff CCCTL_01_CCOND Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0x0 0x3 read-write CCCTL_01_CCOND_NOCAPTURE NOCAPTURE 0 CCCTL_01_CCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_CCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_CCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0x4 0x3 read-write CCCTL_01_ACOND_TIMCLK TIMCLK 0 CCCTL_01_ACOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ACOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ACOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ACOND_CC_TRIG_HIGH CC_TRIG_HIGH 5 CCCTL_01_LCOND Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved 0x8 0x3 read-write CCCTL_01_LCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_LCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_LCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_ZCOND Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 0xC 0x3 read-write CCCTL_01_ZCOND_CC_TRIG_RISE CC_TRIG_RISE 1 CCCTL_01_ZCOND_CC_TRIG_FALL CC_TRIG_FALL 2 CCCTL_01_ZCOND_CC_TRIG_EDGE CC_TRIG_EDGE 3 CCCTL_01_COC Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0x11 0x1 read-write CCCTL_01_COC_COMPARE COMPARE 0 CCCTL_01_COC_CAPTURE CAPTURE 1 CCCTL_01_CCACTUPD CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0x1A 0x3 read-write CCCTL_01_CCACTUPD_IMMEDIATELY IMMEDIATELY 0 CCCTL_01_CCACTUPD_ZERO_EVT ZERO_EVT 1 CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT COMPARE_DOWN_EVT 2 CCCTL_01_CCACTUPD_COMPARE_UP_EVT COMPARE_UP_EVT 3 CCCTL_01_CCACTUPD_ZERO_LOAD_EVT ZERO_LOAD_EVT 4 CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT ZERO_RC_ZERO_EVT 5 CCCTL_01_CCACTUPD_TRIG TRIG 6 CCCTL_01_CC2SELU Selects the source second CCU event. 0x16 0x3 CCCTL_01_CC2SELU_SEL_CCU0 SEL_CCU0 0 CCCTL_01_CC2SELU_SEL_CCU1 SEL_CCU1 1 CCCTL_01_CC2SELU_SEL_CCU2 SEL_CCU2 2 CCCTL_01_CC2SELU_SEL_CCU3 SEL_CCU3 3 CCCTL_01_CC2SELU_SEL_CCU4 SEL_CCU4 4 CCCTL_01_CC2SELU_SEL_CCU5 SEL_CCU5 5 CCCTL_01_CC2SELD Selects the source second CCD event. 0x1D 0x3 CCCTL_01_CC2SELD_SEL_CCD0 SEL_CCD0 0 CCCTL_01_CC2SELD_SEL_CCD1 SEL_CCD1 1 CCCTL_01_CC2SELD_SEL_CCD2 SEL_CCD2 2 CCCTL_01_CC2SELD_SEL_CCD3 SEL_CCD3 3 CCCTL_01_CC2SELD_SEL_CCD4 SEL_CCD4 4 CCCTL_01_CC2SELD_SEL_CCD5 SEL_CCD5 5 2 4 0,1 OCTL_01[%s] CCP Output Control Registers 0x1850 32 read-write 0x00000000 0xffffffff OCTL_01_CCPOINV CCP Output Invert The output as selected by CCPO is conditionally inverted. 0x4 0x1 read-write OCTL_01_CCPOINV_NOINV NOINV 0 OCTL_01_CCPOINV_INV INV 1 OCTL_01_CCPIV CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0). 0x5 0x1 read-write OCTL_01_CCPIV_LOW LOW 0 OCTL_01_CCPIV_HIGH HIGH 1 OCTL_01_CCPO CCP Output Source 0x0 0x4 read-write OCTL_01_CCPO_FUNCVAL FUNCVAL 0 OCTL_01_CCPO_LOAD LOAD 1 OCTL_01_CCPO_CMPVAL CMPVAL 2 OCTL_01_CCPO_ZERO ZERO 4 OCTL_01_CCPO_CAPCOND CAPCOND 5 OCTL_01_CCPO_FAULTCOND FAULTCOND 6 OCTL_01_CCPO_CC0_MIRROR_ALL CC0_MIRROR_ALL 8 OCTL_01_CCPO_CC1_MIRROR_ALL CC1_MIRROR_ALL 9 OCTL_01_CCPO_DEADBAND DEADBAND 12 OCTL_01_CCPO_CNTDIR CNTDIR 13 2 4 0,1 CCACT_01[%s] Capture or Compare Action Registers 0x1870 32 read-write 0x00000000 0xffffffff CCACT_01_ZACT CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event. 0x0 0x2 read-write CCACT_01_ZACT_DISABLED DISABLED 0 CCACT_01_ZACT_CCP_HIGH CCP_HIGH 1 CCACT_01_ZACT_CCP_LOW CCP_LOW 2 CCACT_01_ZACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_LACT CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event. 0x3 0x2 read-write CCACT_01_LACT_DISABLED DISABLED 0 CCACT_01_LACT_CCP_HIGH CCP_HIGH 1 CCACT_01_LACT_CCP_LOW CCP_LOW 2 CCACT_01_LACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CDACT CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down. 0x6 0x2 read-write CCACT_01_CDACT_DISABLED DISABLED 0 CCACT_01_CDACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CDACT_CCP_LOW CCP_LOW 2 CCACT_01_CDACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CUACT CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up. 0x9 0x2 read-write CCACT_01_CUACT_DISABLED DISABLED 0 CCACT_01_CUACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CUACT_CCP_LOW CCP_LOW 2 CCACT_01_CUACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2DACT CCP Output Action on CC2D event. 0xC 0x2 read-write CCACT_01_CC2DACT_DISABLED DISABLED 0 CCACT_01_CC2DACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2DACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2DACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_CC2UACT CCP Output Action on CC2U event. 0xF 0x2 read-write CCACT_01_CC2UACT_DISABLED DISABLED 0 CCACT_01_CC2UACT_CCP_HIGH CCP_HIGH 1 CCACT_01_CC2UACT_CCP_LOW CCP_LOW 2 CCACT_01_CC2UACT_CCP_TOGGLE CCP_TOGGLE 3 CCACT_01_SWFRCACT CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0x1C 0x2 read-write CCACT_01_SWFRCACT_DISABLED DISABLED 0 CCACT_01_SWFRCACT_CCP_HIGH CCP_HIGH 1 CCACT_01_SWFRCACT_CCP_LOW CCP_LOW 2 2 4 0,1 IFCTL_01[%s] Input Filter Control Register 0x1880 32 read-write 0x00000000 0xffffffff IFCTL_01_ISEL Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved 0x0 0x4 read-write IFCTL_01_ISEL_CCPX_INPUT CCPX_INPUT 0 IFCTL_01_ISEL_CCPX_INPUT_PAIR CCPX_INPUT_PAIR 1 IFCTL_01_ISEL_CCP0_INPUT CCP0_INPUT 2 IFCTL_01_ISEL_TRIG_INPUT TRIG_INPUT 3 IFCTL_01_ISEL_CCP_XOR CCP_XOR 4 IFCTL_01_ISEL_FSUB0 FSUB0 5 IFCTL_01_ISEL_FSUB1 FSUB1 6 IFCTL_01_ISEL_COMP0 COMP0 7 IFCTL_01_ISEL_COMP1 COMP1 8 IFCTL_01_ISEL_COMP2 COMP2 9 IFCTL_01_INV Input Inversion This bit controls whether the selected input is inverted. 0x7 0x1 read-write IFCTL_01_INV_NOINVERT NOINVERT 0 IFCTL_01_INV_INVERT INVERT 1 IFCTL_01_FP Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0x8 0x2 read-write IFCTL_01_FP__3 _3 0 IFCTL_01_FP__5 _5 1 IFCTL_01_FP__8 _8 2 IFCTL_01_CPV Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0xB 0x1 read-write IFCTL_01_CPV_CONSECUTIVE CONSECUTIVE 0 IFCTL_01_CPV_VOTING VOTING 1 IFCTL_01_FE Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0xC 0x1 read-write IFCTL_01_FE_DISABLED DISABLED 0 IFCTL_01_FE_ENABLED ENABLED 1 TSEL Trigger Select 0x18B0 32 read-write 0x00000000 0xffffffff TSEL_ETSEL External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0x0 0x5 read-write TSEL_ETSEL_TRIG0 TRIG0 0 TSEL_ETSEL_TRIG1 TRIG1 1 TSEL_ETSEL_TRIG2 TRIG2 2 TSEL_ETSEL_TRIG3 TRIG3 3 TSEL_ETSEL_TRIG4 TRIG4 4 TSEL_ETSEL_TRIG5 TRIG5 5 TSEL_ETSEL_TRIG6 TRIG6 6 TSEL_ETSEL_TRIG7 TRIG7 7 TSEL_ETSEL_TRIG8 TRIG8 8 TSEL_ETSEL_TRIG9 TRIG9 9 TSEL_ETSEL_TRIG10 TRIG10 10 TSEL_ETSEL_TRIG11 TRIG11 11 TSEL_ETSEL_TRIG12 TRIG12 12 TSEL_ETSEL_TRIG13 TRIG13 13 TSEL_ETSEL_TRIG14 TRIG14 14 TSEL_ETSEL_TRIG15 TRIG15 15 TSEL_ETSEL_TRIG_SUB0 TRIG_SUB0 16 TSEL_ETSEL_TRIG_SUB1 TRIG_SUB1 17 TSEL_TE Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0x9 0x1 read-write TSEL_TE_DISABLED DISABLED 0 TSEL_TE_ENABLED ENABLED 1 _INTERRUPTS 0x00000000 INT_GROUP0 0x00000040 0 INT_GROUP1 0x00000044 1 TIMG1 0x00000048 2 ADC0 0x00000050 4 SPI0 0x00000064 9 UART1 0x00000074 13 UART0 0x0000007C 15 TIMG0 0x00000080 16 TIMG2 0x00000088 18 TIMG4 0x00000090 20 I2C0 0x000000A0 24 I2C1 0x000000A4 25 DMA 0x000000BC 31